Electronic paper driving circuit and electronic paper display device

Abstract

The application provides an electronic paper driving circuit and an electronic paper display device, wherein the electronic paper driving circuit comprises a driving circuit, an optical detection circuit, a switching circuit, a sampling and locking circuit and a control circuit; the optical detection circuit detects the liquid crystal flipping degree in real time and converts and outputs a first level signal and a second level signal; the sampling and locking circuit counts based on the first level signal and the second level signal transmitted by the switching circuit, accurately records the frame number required by the liquid crystal flipping in a digital quantization form, and adaptively selects a matched driving waveform according to the size of the counting value by the control circuit, so that the accurate matching between the total driving frame number and the actual flipping demand of the liquid crystal is realized; the redundant frame is effectively eliminated in the liquid crystal fast flipping scene, the power consumption is reduced and the refresh period is shortened; in the liquid crystal slow flipping scene, the driving waveform with more total frame numbers is automatically switched to, so that the display quality deterioration problems such as residual image and gray scale jump are eliminated, and the refresh efficiency and the display quality are simultaneously ensured in the whole scene.

Description

Technical Field

[0001] This invention belongs to the field of electronic paper technology, and particularly relates to an electronic paper driving circuit and an electronic paper display device. Background Technology

[0002] Cholesteric liquid crystals are a novel type of bistable display material, which has become a material for electronic paper display devices due to its unique optical and electrical properties. This material has two stable optical states: a high-reflectivity planar state and a low-reflectivity focal conic state. Switching between the two states only requires instantaneous voltage driving, and no continuous power supply is needed during the stable display phase, resulting in extremely low static power consumption. It also has advantages such as natural light visibility, eye-friendly flicker-free display, and excellent color gamut performance, making it widely used in low-power display scenarios such as portable readers, smart tags, automotive displays, and wearable devices.

[0003] Currently, mainstream cholesteric electronic paper driving systems all adopt an open-loop driving architecture. The driving logic relies on a waveform lookup table embedded in the timing controller to achieve screen refresh. During the device manufacturing process, technicians preset a waveform lookup table with fixed parameters according to standard operating conditions. The timing controller calls a driving waveform with a fixed number of frames and a fixed timing sequence, controlling the driving chip to output periodic voltage pulses, driving the cholesteric liquid crystal molecules to complete the flipping and switching, thereby achieving the display of images with different grayscale and color. The entire refresh process is a unidirectional open-loop control. The system can only execute a fixed refresh process according to the preset program and cannot perceive the actual flipping state of the liquid crystal molecules and the stable state of the displayed image in real time.

[0004] The shortcomings of existing technologies are mainly reflected in the two-way performance drawbacks brought about by the fixed refresh mode. On the one hand, to ensure the display integrity of complex images and in harsh environments, most devices default to a slow refresh mode, configuring a large number of refresh frames and a long refresh cycle. When the device displays images with small changes, the resistance to liquid crystal molecule flipping is small, or the environmental conditions are excellent, the liquid crystal molecules can quickly complete the flipping and reach a stable optical state in a short time. However, the fixed waveform lookup table will still execute the complete full-frame refresh process, generating a large number of redundant refresh frames. The redundant refresh operations not only significantly prolong the screen refresh time and reduce the user interaction experience, but also cause unnecessary power consumption, which violates the original intention of low power consumption in e-paper design.

[0005] On the other hand, some devices, in pursuit of the ultimate refresh rate, default to fast refresh mode, which improves refresh efficiency by reducing the total number of refresh frames and compressing the refresh cycle. In this mode, the fixed refresh frame rate cannot meet the liquid crystal flipping requirements under complex working conditions and scenarios with large screen transitions. The refresh process terminates prematurely, causing cholesteric liquid crystal molecules to fail to fully flip to the target optical state. This results in disordered molecular arrangement deviations, ultimately leading to image quality problems such as ghosting, ghost images, grayscale jumps, and contrast degradation, severely affecting the display accuracy and visual effect. Summary of the Invention

[0006] The purpose of this invention is to provide an electronic paper driving circuit that solves the problem of over-refreshing or under-refreshing caused by the fixed refresh mode used in traditional electronic paper driving circuits.

[0007] A first aspect of this invention provides an electronic paper driving circuit, comprising: A driving circuit is used to provide matched multiple driving signals to the display panel within a refresh cycle based on the loaded driving waveform, so as to control the cholesteric liquid crystal flipping of the display panel. An optical detection circuit is used to detect the degree of flipping of the cholesteric liquid crystal during the refresh cycle, and to generate a first level signal representing that the flipping is not in place and a second level signal representing that the flipping is in place. A switching circuit, the control terminal of which is used to input a switch enable signal, the input terminal of which is connected to the output terminal of the optical detection circuit, the switching circuit being triggered to conduct within the refresh cycle by the switch enable signal, the switch enable signal following the change of one of the drive signals; A sampling latch circuit is connected to the switching circuit. The sampling latch circuit is used to count the clock signal during the duration of the first level signal, and latch the count value and output it when the second level signal is received. The control circuit, connected to the sampling latch circuit and the driving circuit, also receives the switch enable signal. The control circuit stores multiple sets of driving waveforms corresponding to different total driving frame numbers. The control circuit is used for: The refresh enable signal selects an initial drive waveform to be applied to the drive circuit within the current refresh cycle; At the end of the current refresh cycle, based on the magnitude of the count value and the state of the switch enable signal, a set of matching drive waveforms is selected and loaded onto the drive circuit in the next refresh cycle to adjust the total number of drive frames for each drive signal in the next refresh cycle.

[0008] Optionally, the optical detection circuit includes: A first photoelectric sensor is integrated on the upper substrate side of the display panel. The first photoelectric sensor is used to collect ambient light signals and generate a first voltage signal. The second photoelectric sensor is integrated on the lower substrate side of the display panel. The second photoelectric sensor is used to collect the transmitted light signal after passing through the cholesteric liquid crystal and generate a second voltage signal. A differential comparison circuit is connected to the first photoelectric sensor and the second photoelectric sensor. The differential comparison circuit is used to compare the first voltage signal and the second voltage signal, and output the first level signal when the cholesteric liquid crystal has not flipped to the target transmittance, and output the second level signal when the cholesteric liquid crystal flips to the target transmittance.

[0009] Optionally, the optical detection circuit further includes: A first signal amplification circuit is connected between the first photoelectric sensor and the differential comparator circuit. The first signal amplification circuit is used to amplify and output the first voltage signal. The second signal amplification circuit is connected between the second photoelectric sensor and the differential comparator circuit. The second signal amplification circuit is used to amplify and output the second voltage signal.

[0010] Optionally, the upper substrate of the display panel is provided with a first driving layer, and the lower substrate of the display panel is provided with a second driving layer; The driving signal includes at least a common electrode voltage signal output to the first driving layer and a data signal output to the second driving layer; The switch enable signal is the common electrode voltage signal or a voltage divider of the common electrode voltage signal.

[0011] Optionally, the sampling latch circuit includes: A multi-stage D flip-flop is cascaded to form a counter chain. The data input of the first-stage D flip-flop in the counter chain is connected to the output of the switching circuit. The clock inputs of all D flip-flops are used to input the clock signal. The counter chain is used for: During the refresh cycle, when the switching circuit transmits the first level signal, the pulse edges of the clock signal are accumulated and counted. When the signal is flipped to the second level, the counting stops and the current count value is latched. An output buffer is disposed between the multiple parallel output terminals of the multi-stage D flip-flop and the control circuit. The output buffer is used for: When the second level signal is received to enable, the count value is output to the control circuit; When the first level signal is received, the control circuit is enabled or disabled, and the output of a valid count value to the control circuit is stopped.

[0012] Optionally, the electronic paper driving circuit further includes: A reset circuit is connected to the switching circuit. The reset circuit is used to output a first reset signal when the first level signal is received and to switch to output a second reset signal when the second level signal is received. The control circuit includes: A timing controller is connected to the drive circuit and the reset circuit. The timing controller is used to load the input corresponding to the drive waveform when it receives a first enable signal and a second reset signal, and to output the drive waveform to the drive circuit when it receives the second enable signal and the first reset signal. The controller is connected to the sampling latch circuit, the reset circuit, and the timing controller. The controller also receives the switch enable signal and stores multiple sets of drive waveforms corresponding to different total drive frame numbers. The control circuit is used for: The refresh enable signal selects an initial drive waveform to be applied to the drive circuit within the current refresh cycle; During the current refresh cycle, when the switch enable signal is valid and the first reset signal is received, the second enable signal is output to the timing controller to control the timing controller to maintain the current drive state; During the current refresh cycle, when the switch enable signal is valid and the second reset signal is received, the count value is acquired, and the count value is compared with the target count range that matches the initial drive waveform. Based on the comparison result, the initial drive waveform is maintained or another target drive waveform is selected and loaded onto the timing controller. The total number of drive frames corresponding to the other target drive waveform is different from that of the initial drive waveform, and the total number of frames of the target drive waveform changes positively with the count value. When the current refresh cycle ends and the switch enable signal is turned off, the second enable signal is output to the timing controller.

[0013] Optionally, the controller maintains the initial drive waveform or selects another target drive waveform to be loaded onto the timing controller based on the comparison result, specifically including: When the count value is within the target count range that matches the initial drive waveform, a second enable signal is output to the timing controller to control the timing controller to maintain the initial drive waveform. When the count value exceeds the target count range matched by the initial drive waveform, another target drive waveform is selected to be loaded and the first enable signal is output to the timing controller. After the loading is completed, the second enable signal is output to the timing controller to control the timing controller to load the target drive waveform and output it to the drive circuit.

[0014] Optionally, the controller is further configured to: When the current refresh cycle ends and the count value is not received before the switch enable signal is turned off, when the switch enable signal is turned off, the first enable signal is output and the initial drive waveform is loaded to the timing controller, and after the loading is completed, the second reset signal is output to reset the timing controller.

[0015] Optionally, the electronic paper driving circuit further includes: The delay circuit is connected to the reset circuit, the timing controller, and the controller respectively. The delay circuit is also used to delay the output of the reset signal from the reset circuit. The delay time of the delay circuit is greater than or equal to the loading time of the timing controller when the controller loads the driving waveform.

[0016] A second aspect of the present invention provides an electronic paper display device, including a display panel and an electronic paper driving circuit as described above. The display panel is connected to the electronic paper driving circuit. The display panel has an upper substrate, a liquid crystal layer and a lower substrate stacked sequentially. The liquid crystal layer is provided with cholesteric liquid crystal.

[0017] The beneficial effects of this invention compared to the prior art are as follows: The above-mentioned electronic paper driving circuit includes a driving circuit, an optical detection circuit, a switching circuit, a sampling latch circuit, and a control circuit. The optical detection circuit detects the degree of liquid crystal flipping in real time and converts and outputs a first-level signal and a second-level signal. The sampling latch circuit counts based on the first-level signal and the second-level signal transmitted by the switching circuit, accurately recording the number of frames required for liquid crystal flipping in digital quantization form. The control circuit adaptively selects the matching driving waveform according to the count value, achieving a precise match between the total number of driving frames and the actual flipping requirements of the liquid crystal. In scenarios with fast liquid crystal flipping, redundant frames are effectively eliminated, power consumption is reduced, and the refresh cycle is shortened. In scenarios with slow liquid crystal flipping, the circuit automatically switches to a driving waveform with a higher total number of frames, eliminating display quality degradation problems such as ghosting and grayscale jumps, thus ensuring both refresh efficiency and display quality in all scenarios. Attached Figure Description

[0018] Figure 1 These are schematic diagrams of the display panels provided in Embodiments 1 and 3 of the present invention; Figure 2 This is a schematic diagram of the electronic paper driving circuit provided in Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of a first structure of the optical detection circuit provided in Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of a second structure of the optical detection circuit provided in Embodiment 1 of the present invention; Figure 5This is a circuit diagram of the optical detection circuit provided in Embodiment 1 of the present invention; Figure 6 The circuit diagram is shown for the switching circuit provided in Embodiment 1 of the present invention; Figure 7 This is a circuit diagram of the sampling latch circuit provided in Embodiment 1 of the present invention; Figure 8 This is a schematic diagram of the first structure of the electronic paper driving circuit provided in Embodiment 2 of the present invention; Figure 9 This is a schematic diagram of a second structure of the electronic paper driving circuit provided in Embodiment 2 of the present invention; Figure 10 The circuit diagram of the switching circuit, reset circuit and delay circuit provided in Embodiment 2 of the present invention is shown below; Figure 11 This is a schematic diagram of the electronic paper display device provided in Embodiment 3 of the present invention.

[0019] The figures in the diagram are labeled as follows: 100. Electronic paper driving circuit; 200. Display panel; 210. Upper substrate; 220. Lower substrate; 230. Liquid crystal layer; 10. Driving circuit; 20. Optical detection circuit; 30. Switching circuit; 40. Sampling latch circuit; 50. Control circuit; 60. Reset circuit; 70. Delay circuit; 21. First photoelectric sensor; 22. Second photoelectric sensor; 23. Differential comparator circuit; 24. First signal amplification circuit; 25. Second signal amplification circuit; 41. Output buffer; 51. Timing controller; 52. Controller; R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; R5, fifth resistor; R6, sixth resistor; R7, seventh resistor; R8, eighth resistor; R9, ninth resistor; R10, tenth resistor; R11, eleventh resistor; C1, first capacitor; C2, second capacitor; C3, third capacitor; LD1, first photodiode; LD2, second photodiode; U1, first operational amplifier; U2, second operational amplifier; U3, comparator; U4, D flip-flop; U5, AND gate; U6, NOT gate; Q1, first electronic switch; Q2, second electronic switch; Ctr1, switch enable signal; Ctr2, refresh enable signal; Vout, level signal output by the optical detection circuit; V1, first voltage signal; V2, second voltage signal; VCC, positive voltage terminal; Vcom, common electrode voltage signal; Clk1, clock signal; RESET, reset signal. Detailed Implementation

[0020] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0021] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0022] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0023] Example 1 A first aspect of this invention provides an electronic paper driving circuit 100, which is connected to a display panel 200, wherein the display panel 200 is a cholesteric liquid crystal display panel, such as... Figure 1 As shown, the display panel 200 is composed of an upper substrate 210, a liquid crystal layer 230, and a lower substrate 220 stacked sequentially from top to bottom. The liquid crystal layer 230 is internally encapsulated and filled with cholesteric liquid crystal material. Relying on the bistable optical properties of cholesteric liquid crystal, it achieves the advantages of zero-power image maintenance and low-power image refresh. The upper and lower substrates of the display panel 200 are respectively provided with driving electrode layers, which are correspondingly connected to the multi-channel signal output terminals of the electronic paper driving circuit 100 to receive the adaptively adjusted driving signals and complete the liquid crystal molecule flipping control and image display.

[0024] like Figure 2 As shown, in this embodiment, the electronic paper driving circuit 100 includes: The driving circuit 10 is used to provide matched multiple driving signals to the display panel 200 within the refresh cycle based on the loaded driving waveform, so as to control the cholesteric liquid crystal flipping of the display panel 200. The optical detection circuit 20 is used to detect the degree of flipping of the cholesteric liquid crystal during the refresh cycle, and to generate a first level signal representing that the flipping is not in place and a second level signal representing that the flipping is in place. The control terminal of the switching circuit 30 is used to input a switch enable signal Ctr1. Its input terminal is connected to the output terminal of the optical detection circuit 20. The switching circuit 30 is used to be triggered to conduct during the refresh cycle by the switch enable signal Ctr1. The switch enable signal Ctr1 follows the change of one of the drive signals. The sampling latch circuit 40 is connected to the switching circuit 30. The sampling latch circuit 40 is used to count the clock signal Clk1 for the duration of the first level signal, and latch the count value and output it when the second level signal is received. Control circuit 50, connected to sampling latch circuit 40 and drive circuit 10, also receives a switch enable signal Ctr1. Control circuit 50 stores multiple sets of drive waveforms corresponding to different total drive frame numbers. Control circuit 50 is used for: The refresh enable signal Ctr2 selects the initial drive waveform to be applied to the drive circuit 10 within the current refresh cycle; At the end of the current refresh cycle, based on the count value and the state of the switch enable signal Ctr1, a set of matching drive waveforms are selected and loaded onto the drive circuit 10 in the next refresh cycle to adjust the total number of drive frames for each drive signal in the next refresh cycle.

[0025] In this embodiment, the driving circuit 10 is the execution driving module of this system. Its function is to receive the driving waveform transmitted by the control circuit 50, and based on the completed driving waveform, output multiple matched driving signals in each refresh cycle, transmit the driving signals to the display panel 200, and drive the cholesteric liquid crystal inside the display panel 200 to complete the flip switching through precise voltage pulse timing control, thereby realizing the adjustment of screen grayscale, color and transmittance, and finally completing the screen refresh update.

[0026] It should be noted that the driving waveform loaded by the driving circuit 10 in each refresh cycle is not a single fixed parameter, but rather waveform data that can contain multiple sets of differentiated parameters. Different driving waveforms correspond to different total driving frames, pulse widths, and voltage amplitudes, which can adapt to different LCD flipping conditions. Each set of driving waveforms has a preset fixed standard frame range, which serves as a benchmark for determining whether there are redundant frames or insufficient frames in the current refresh process, providing data support for subsequent adaptive adjustments.

[0027] The optical detection circuit 20 is the state sensing module of this system, responsible for real-time detection of the liquid crystal flipping state. It works synchronously throughout each refresh cycle, continuously detecting the real-time flipping degree of the cholesteric liquid crystal during the voltage-driven process. Through differential comparison of optical signals, it accurately distinguishes between two states: liquid crystal flipping in place and flipping not in place, and outputs two different level signals accordingly. The first level signal indicates that the liquid crystal molecules have not yet flipped to the target optical state, indicating under-flipping; the second level signal indicates that the liquid crystal molecules have completely flipped to the target transmittance and target optical state, and the flipping process has met the standard.

[0028] Compared to the traditional, undetectable open-loop drive architecture, the optical detection circuit 20 can convert the microscopic arrangement state of liquid crystal molecules and the state of transmittance change, which are invisible to the naked eye, into a level signal that can be recognized and processed by digital circuits in real time. This enables the quantification and visualization of the liquid crystal flip state, providing sensing data for closed-loop feedback regulation.

[0029] The switching circuit 30 is a timing control turn-on module. Its control terminal receives an independent switch enable signal Ctr1, and its input terminal is directly connected to the signal output terminal of the optical detection circuit 20. It can receive the level signal Vout output by the optical detection circuit 20 throughout the entire process. The level signal Vout output by the optical detection circuit 20 includes a first level signal and a second level signal. The turn-on logic of the switching circuit 30 is bound to the electronic paper refresh timing. The switch enable signal Ctr1 changes synchronously with one of the drive signals output by the drive circuit 10, ensuring complete synchronization between the detection timing and the refresh timing, and avoiding detection errors caused by timing misalignment.

[0030] Throughout the entire refresh cycle, the switching circuit 30 remains continuously on, triggered by the effective level of the switch enable signal Ctr1, enabling the level signal output by the optical detection circuit 20 to be transmitted to the back-end sampling latch circuit 40 in real time without delay. When the refresh cycle ends, the switch enable signal Ctr1 synchronously fails, and the switching circuit 30 is turned off, blocking signal transmission and ensuring that the detection data of each refresh cycle is independent and free from crosstalk, thus achieving independent detection, independent judgment, and independent adjustment in a single cycle.

[0031] The sampling latch circuit 40 receives the level signal and clock signal Clk1 transmitted by the switching circuit 30 in real time, and performs the functions of signal counting, state latching, and data output. During the refresh cycle, if the sampling latch circuit 40 continuously receives the first level signal, it means that the liquid crystal is always in the state of not being flipped to the correct position. At this time, the sampling latch circuit 40 continuously accumulates the count on the pulse edge of the clock signal Clk1, and records the duration of the liquid crystal under-flip and the corresponding frame number in real time. When the level signal switches from the first level signal to the second level signal, it means that the liquid crystal has completed the flip. The sampling latch circuit 40 immediately stops counting and latches the currently accumulated count value, completing the single-cycle state data acquisition.

[0032] The control circuit 50, serving as the scheduling and decision-making module of the entire adaptive drive system, establishes bidirectional signal connections with the sampling latch circuit 40 and the drive circuit 10, and simultaneously connects to the switch enable signal Ctr1 to achieve full-process timing control and parameter adjustment. The control circuit 50 internally stores multiple sets of preset drive waveforms, each corresponding to a different total number of drive frames. These include three types of drive waveforms: fast refresh mode, standard mode, and slow refresh mode. The total number of drive frames for these three types increases sequentially, adapting to minor screen changes, regular screen updates, large screen transitions, and harsh operating conditions, respectively.

[0033] The working logic of the control circuit 50 is divided into a dual-cycle linkage control mode, which realizes closed-loop optimization of execution in the current cycle and adaptive adjustment in the next cycle.

[0034] First, during the start-up phase of the current refresh cycle, the control circuit 50 receives the externally input refresh enable signal Ctr2, actively selects a set of initial drive waveforms and loads them onto the drive circuit 10. The drive circuit 10 then performs the current screen refresh operation based on these initial drive waveforms to complete the regular screen update.

[0035] At the same time, the optical detection circuit 20 works synchronously and outputs corresponding first level signal and second level signal. When the ambient light signal is greater than the transmitted light signal penetrating the liquid crystal layer 230, the optical detection circuit 20 outputs the first level signal, indicating that the liquid crystal is still flipping. When the ambient light signal and the transmitted light signal are close to equal, the optical detection circuit 20 switches to output the second level signal, indicating that the liquid crystal flipping is basically completed.

[0036] The switching circuit 30 is controlled by the switch enable signal Ctr1. During the refresh cycle, the switch enable signal Ctr1 is normally output and valid. The switching circuit 30 is turned on and outputs a first level signal to the sampling latch circuit 40. The sampling latch circuit 40 counts the clock signal Clk1 based on the duration of the first level signal. At the end of the refresh cycle, the switch enable signal Ctr1 is turned off along with the drive signal and input to the switching circuit 30. The switching circuit 30 is turned off, triggering the sampling latch circuit 40 to trigger state latching.

[0037] The sampling latch circuit 40 uses clock signal Clk1 as its clock. During the duration of the first level signal, it increments the clock signal Clk1 frame by frame. When the optical detection circuit 20 switches from the first level signal to the second level signal, the sampling latch circuit 40 stops counting, latches the current count value, and outputs it to the control circuit 50 to read the latched data. After receiving the count value, the control circuit 50 compares it with the target count range matched by the initial drive waveform. Based on the comparison result, it identifies whether there is frame redundancy or insufficient frames in the current refresh process, determines whether to switch the drive waveform, and automatically matches and loads the optimal drive waveform in the next refresh cycle based on the determination result. It dynamically adjusts the total number of drive frames in the next refresh cycle to achieve adaptive optimization of the refresh parameters.

[0038] When the count value is within the target count range matching the initial drive waveform, it can be determined that the initial drive waveform has no redundant frames. At this time, the output of the initial drive waveform can be maintained, and the drive circuit 10 can be controlled to maintain the output of the drive signal corresponding to the current initial drive waveform to the display panel 200, and the total number of drive frames of the display panel 200 remains unchanged.

[0039] When the count value exceeds the target count range, the control circuit 50 can determine that there are redundant frames or insufficient frames in the total number of drive frames corresponding to the current initial drive waveform. The control circuit 50 pauses the output of the initial drive waveform, selects another target drive waveform, and loads it into the drive circuit 10. The drive circuit 10 outputs a drive signal with matching frame number to the display panel 200 according to the updated target drive waveform.

[0040] In one optional embodiment, when the count value exceeds the upper limit of the target count range corresponding to the initial drive waveform, it indicates that the current frame count is insufficient. At this time, the target drive waveform corresponding to the slow refresh mode with more frames can be selected. When the count value is lower than the lower limit of the target count range corresponding to the initial drive waveform, it indicates that there are excess frames. At this time, the target drive waveform corresponding to the fast refresh mode with fewer frames can be selected.

[0041] By comparing the count value with the preset standard range, it is determined whether there is a problem of frame redundancy or insufficient frame count in the current refresh process. Based on the determination result, the loading drive waveform is automatically matched in the next refresh cycle, and the total number of drive frames in the next refresh cycle is dynamically adjusted to achieve adaptive optimization of refresh parameters.

[0042] It is understandable that the drive waveform modes stored in the control circuit 50 are not limited to fast refresh, standard, and slow refresh. They can be expanded to N modes (N not less than 2) according to actual applications. The decision logic of the control circuit 50 can be correspondingly expanded to multi-threshold interval comparison to adapt to more refined adaptive refresh control requirements.

[0043] The electronic paper driving circuit 100, through real-time optical detection, timing synchronous sampling, quantitative data analysis, and dynamic waveform matching, can accurately identify the frame number adaptation status of each refresh cycle, automatically reduce redundant refresh frames, and supplement missing refresh frames. While ensuring complete LCD flipping and high-definition, flawless image display, it effectively shortens the refresh time and reduces ineffective power consumption, achieving a dynamic balance between electronic paper refresh speed, display quality, and power consumption performance.

[0044] The optical detection circuit 20 can employ a corresponding optical sensor, photodiode, etc., in an optional embodiment, such as... Figure 1 and Figure 3 As shown, the optical detection circuit 20 includes: The first photoelectric sensor 21 is integrated on the upper substrate 210 side of the display panel 200. The first photoelectric sensor 21 is used to collect ambient light signals and generate a first voltage signal V1. The second photoelectric sensor 22 is integrated on the lower substrate 220 side of the display panel 200. The second photoelectric sensor 22 is used to collect the transmitted light signal after penetrating the cholesteric liquid crystal and generate a second voltage signal V2. The differential comparison circuit 23 is connected to the first photoelectric sensor 21 and the second photoelectric sensor 22. The differential comparison circuit 23 is used to compare the first voltage signal V1 and the second voltage signal V2, and outputs a first level signal when the cholesteric liquid crystal has not flipped to the target transmittance, and outputs a second level signal when the cholesteric liquid crystal flips to the target transmittance.

[0045] In this embodiment, two sets of photoelectric sensors are integrated and arranged on the upper and lower sides of the display panel 200 respectively to realize layered optical signal acquisition. The differential comparison circuit 23 is connected to the output signals of the two sets of photoelectric sensors to complete signal comparison and level output.

[0046] The first photoelectric sensor 21 is integrated on the upper substrate 210 side of the display panel 200 and is exposed to external ambient light throughout the process. It collects ambient light signals of the working scene of the display panel 200 and can capture the dynamic changes of ambient light intensity and color temperature in real time, and convert the collected ambient light optical signals into the corresponding first voltage signal V1.

[0047] The second photoelectric sensor 22 is integrated on the lower substrate 220 side of the display panel 200, located at the end of the backlight transmission path of the liquid crystal layer 230. It collects the transmitted light signal after penetrating the cholesteric liquid crystal layer 230. During liquid crystal flipping, the alignment angle and degree of order of the liquid crystal molecules directly change the transmittance, and the intensity of the transmitted light changes in real time with the progress of liquid crystal flipping. The second photoelectric sensor 22 captures this dynamically changing transmitted light signal and converts it into a corresponding second voltage signal V2, which serves as a detection signal characterizing the liquid crystal flipping state.

[0048] The two signal input terminals of the differential comparator circuit 23 are respectively connected to the signal output terminals of the first photoelectric sensor 21 and the second photoelectric sensor 22, and can receive the first voltage signal V1 and the second voltage signal V2 in real time, and perform differential comparison analysis on the amplitude and fluctuation trend of the two sets of voltage signals. Based on the optical characteristics of cholesteric liquid crystals, when the liquid crystal molecules have not flipped to the target transmittance and target optical state, the transmittance of the liquid crystal layer 230 deviates significantly from the standard state. The intensity of the transmitted light penetrating the liquid crystal layer 230 differs greatly from the ambient light reference intensity. The ambient light signal is greater than the transmitted light signal, and the first voltage signal V1 is greater than the second voltage signal V2. At this time, the differential comparator circuit 23 outputs a first level signal, which accurately characterizes the under-flipping state of the liquid crystal.

[0049] When the liquid crystal molecules continue to flip under the action of the driving signal, gradually approach and finally reach the target alignment state, the transmittance of the liquid crystal layer 230 tends to the standard optimal value, the intensity of transmitted light is basically the same as the ambient light reference intensity, and the difference between the first voltage signal V1 and the second voltage signal V2 is reduced to the preset threshold range. At this time, the differential comparison circuit 23 automatically switches to output the second level signal, accurately indicating that the liquid crystal has completely flipped into place.

[0050] By using the differential detection structure described above, with the ambient light signal as the reference and the transmitted light signal as the liquid crystal flipping state indicator, the influence of ambient light intensity changes and color temperature interference on the decision result is eliminated through differential amplification and comparison. This achieves accurate optical quantization of the liquid crystal flipping completion degree and provides a reliable hardware closed-loop feedback signal for the dynamic selection of the driving waveform of the control circuit 50.

[0051] The voltage signal output by the photoelectric sensor may be too small, leading to inaccurate detection. To improve detection accuracy, in one optional embodiment, such as... Figure 4 As shown, the optical detection circuit 20 also includes: The first signal amplification circuit 24 is connected between the first photoelectric sensor 21 and the differential comparator circuit 23. The first signal amplification circuit 24 is used to amplify and output the first voltage signal V1. The second signal amplification circuit 25 is connected between the second photoelectric sensor 22 and the differential comparator circuit 23. The second signal amplification circuit 25 is used to amplify and output the second voltage signal V2.

[0052] In this embodiment, the two amplifier circuits are symmetrical in structure and matched in parameters, respectively corresponding to the signal output links of the two sets of photoelectric sensors, so as to realize accurate signal amplification and noise reduction processing.

[0053] The first signal amplification circuit 24 is used to receive the first voltage signal V1 output by the first photoelectric sensor 21, amplify and filter the first voltage signal V1 corresponding to the weak original ambient light, remove signal fluctuations caused by circuit noise and transient interference, output the amplified first voltage signal V1 with stable amplitude and smooth waveform, and transmit it to the input terminal of the differential comparator circuit 23.

[0054] The second signal amplification circuit 25 amplifies, filters, and shapes the second voltage signal V2 output by the second photoelectric sensor 22, optimizes the stability of the transmitted light voltage signal, eliminates transmission link noise interference, outputs a standardized amplified second voltage signal V2, and synchronously transmits it to the differential comparator circuit 23.

[0055] Both signal amplification circuits are internally equipped with matched gain resistors and compensation capacitors. The gain resistors are used to precisely control the signal amplification factor, ensuring that the gain parameters of the two amplification circuits are completely consistent. This ensures that the maximum amplitude of the amplified first voltage signal V1 is approximately equal to the maximum amplitude of the second voltage signal V2, providing a unified benchmark for differential comparison. The compensation capacitors are used to compensate for the internal junction capacitance of the photodiode, effectively suppressing oscillations during signal transmission and amplification, avoiding signal distortion and waveform distortion, and ensuring the authenticity and stability of the detected signal.

[0056] In an alternative embodiment, such as Figure 5 As shown, the first photoelectric sensor 21 includes a first photodiode LD1, and the second photoelectric sensor 22 includes a second photodiode LD2.

[0057] The first signal amplification circuit 24 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, and a first operational amplifier U1. The first end of the first resistor R1, the inverting input terminal of the first operational amplifier U1, and the anode of the first photodiode LD1 are connected. The cathode of the first photodiode LD1 is connected to the positive voltage terminal VCC. The second end of the first resistor R1, the first end of the second resistor R2, and the first end of the first capacitor C1 are connected. The second end of the first capacitor C1, the second end of the second resistor R2, and the first end of the third resistor R3 are connected to the output terminal of the first operational amplifier U1. The second end of the third resistor R3 and the first end of the fourth resistor R4 are connected to form the output terminal of the first signal amplification circuit 24. The non-inverting input terminal of the first operational amplifier U1 is connected to the second end of the fourth resistor R4.

[0058] The second signal amplifier circuit 25 includes a fifth resistor R5, a sixth resistor R6, a second operational amplifier U2, and a second capacitor C2. The first end of the fifth resistor R5, the inverting input terminal of the second operational amplifier U2, and the cathode of the second photodiode LD2 are connected. The cathode of the second photodiode LD2 is connected to the positive voltage terminal VCC. The second end of the fifth resistor R5, the first end of the sixth resistor R6, and the first end of the second capacitor C2 are connected. The second end of the sixth resistor R6, the second end of the second capacitor C2, and the output terminal of the second operational amplifier U2 are connected to form the output terminal of the second signal amplifier circuit 25.

[0059] The differential comparator circuit 23 includes a comparator U3. The non-inverting input terminal of the comparator U3 is connected to the output terminal of the first signal amplifier circuit 24, and the inverting input terminal of the comparator U3 is connected to the output terminal of the second signal amplifier circuit 25. The output terminal of the comparator U3 constitutes the output terminal of the comparator U3.

[0060] The ratio of the first resistor R1 to the second resistor R2 constitutes the signal amplification ratio of the first signal amplification circuit 24, and the ratio of the fifth resistor R5 to the sixth resistor R6 constitutes the signal amplification ratio of the second signal amplification circuit 25. The first capacitor C1 and the second capacitor C2 are used to compensate for the internal junction capacitance of the first photodiode LD1 and the second photodiode LD2, effectively suppressing oscillation problems during signal transmission and amplification, avoiding signal distortion and waveform distortion, and ensuring the authenticity and stability of the detection signal.

[0061] The third resistor R3 and the fourth resistor R4 form a voltage divider circuit, which makes the maximum voltage of the first voltage signal V1 output by the first signal amplifier circuit 24 approximately equal to the maximum voltage of the second voltage signal V2 output by the second signal amplifier circuit 25. That is, when the ambient light signal approaches the transmitted light signal, the first voltage signal V1 and the second voltage signal V2 are equal.

[0062] When the ambient light signal is greater than the transmitted light signal, the first voltage signal V1 is greater than the second voltage signal V2, and the comparator U3 outputs a high-level first-level signal. When the ambient light signal approaches the transmitted light signal, the first voltage signal V1 and the second voltage signal V2 are equal, and the comparator U3 outputs a low-level second-level signal.

[0063] The switch enable signal Ctr1 output to the switch circuit 30 can be selected from a corresponding drive signal among the drive signals. In an optional embodiment, the switch enable signal Ctr1 is the common electrode voltage signal Vcom or a voltage divider signal of the common electrode voltage signal Vcom.

[0064] Correspondingly, in an optional embodiment, the upper substrate 210 of the display panel 200 is provided with a first driving layer, and the lower substrate 220 of the display panel 200 is provided with a second driving layer. The driving signal includes at least the common electrode voltage signal Vcom output to the first driving layer and the data signal output to the second driving layer; In this embodiment, the display panel 200 adopts a conventional stacked architecture. The main structure of the display panel 200 includes an upper substrate 210, a liquid crystal layer 230, and a lower substrate 220. The three layers are stacked sequentially from top to bottom. The liquid crystal layer 230 is filled with cholesteric liquid crystal material, and the display function is realized by relying on the bistable optical properties of the cholesteric liquid crystal. A first driving layer is formed on the surface of the upper substrate 210 of the display panel 200, and a second driving layer is formed on the surface of the lower substrate 220. The two driving layers cooperate with each other to receive multiple driving signals output by the driving circuit 10, forming a complete electric field driving loop to control the flipping of liquid crystal molecules.

[0065] The multiple driving signals output by the driving circuit 10 mainly include two types of signals: the common electrode voltage signal Vcom output to the first driving layer of the upper substrate 210, and the data signal output to the second driving layer of the lower substrate 220. The common electrode voltage signal Vcom is the timing reference signal for the entire refresh cycle, which has periodic level change characteristics and covers the entire refresh process; the data signal is a pixel-level driving signal used to precisely control the flipping degree of liquid crystal in each area to achieve grayscale and color adjustment of the image.

[0066] The switch enable signal Ctr1 uses the common electrode voltage signal Vcom, or a voltage divider signal obtained by resistor division of the common electrode voltage signal Vcom. The level change period of the common electrode voltage signal Vcom is synchronized with the electronic paper refresh cycle. When the refresh cycle starts, the common electrode voltage signal Vcom becomes a valid high level; during the refresh cycle, the signal remains valid; at the end of the refresh cycle, the signal returns to zero and becomes invalid. Using this signal as the switch enable signal Ctr1, the on state of the switch circuit 30 can be precisely bound to the refresh process, ensuring that optical detection and signal sampling are only activated during the valid refresh period, and that detection is terminated after the refresh ends, eliminating signal interference during invalid periods and ensuring timing matching accuracy.

[0067] Using the common electrode voltage signal Vcom as the timing reference, there is no need to add an additional timing generation module. The original driving timing resources of the display panel 200 can be reused. While ensuring timing synchronization accuracy, the overall circuit architecture is simplified, hardware costs and circuit layout difficulty are reduced, and the stability and consistency of system timing control are improved.

[0068] Corresponding to the level state of the common electrode voltage signal Vcom, in an optional embodiment, such as Figure 6 As shown, the switching circuit 30 includes a seventh resistor R7, an eighth resistor R8, and a first electronic switch Q1. The first terminal of the first electronic switch Q1 is connected to the input terminal of the differential comparator circuit 23, and the second terminal of the first electronic switch Q1 is connected to the input terminal of the sampling latch circuit 40. The control terminal of the first electronic switch Q1, the second terminal of the seventh resistor R7, and the first terminal of the eighth resistor R8 are connected. The first terminal of the seventh resistor R7 is used to input the common electrode voltage signal Vcom, and the second terminal of the eighth resistor R8 is grounded. The seventh resistor R7 and the eighth resistor R8 form a voltage divider circuit and output the common electrode voltage signal Vcom. When in the refresh cycle, the common electrode voltage signal Vcom or its divided voltage signal is in a high-level active state, the first electronic switch Q1 is turned on, and the level signal output by the differential comparator circuit 23 is transmitted to the sampling latch circuit 40. When the refresh cycle ends, the common electrode voltage signal Vcom or its divided voltage signal switches to a low level, the first electronic switch Q1 is turned off, and the signal path is closed.

[0069] The sampling latch circuit 40 can be composed of latches, counters, etc., as shown in an optional embodiment. Figure 7 As shown, the sampling latch circuit 40 includes: A multi-stage D flip-flop U4 is cascaded to form a counter chain. The data input of the first-stage D flip-flop U4 in the counter chain is connected to the output of the switching circuit 30. The clock inputs of all D flip-flops U4 are used to input the clock signal Clk1. The counter chain is used for: During the refresh cycle, when the switching circuit 30 transmits the first level signal, the pulse edges of the clock signal Clk1 are accumulated and counted. When the signal is flipped to the second level, the counting stops and the current count value is latched. Output buffer 41 is located between the multi-channel parallel output of the multi-stage D flip-flop U4 and the control circuit 50. Output buffer 41 is used for: When the second-level signal is received to enable, the count value is output to the control circuit 50; When the first level signal is received, the function is enabled or disabled, and the output of a valid count value to the control circuit 50 is cut off.

[0070] In this embodiment, the sampling latch circuit 40 mainly consists of two parts: a multi-level D flip-flop U4 and an output buffer 41. The multi-level D flip-flops U4 are cascaded to form a complete counter chain, realizing clock pulse accumulation and counting and state latching. The output buffer 41 is set between the flip-flop output terminal and the control circuit 50 to realize the controllable on / off of signal output.

[0071] A counter chain is constructed by cascading multiple D flip-flops U4. The data input terminal of the first-stage D flip-flop U4 in the counter chain is directly connected to the signal output terminal of the switching circuit 30, and receives the level signal transmitted through the switching circuit 30 in real time. The clock input terminals of all D flip-flops U4 are uniformly connected to the clock signal Clk1 to ensure that the counting timing of each stage of the flip-flops is completely synchronized, and to achieve accurate pulse edge counting.

[0072] The working logic of the counter chain is deeply integrated with the refresh process and the level signal status. During a complete refresh cycle, the switching circuit 30 is continuously turned on. If the optical detection circuit 20 continuously outputs the first level signal, it means that the liquid crystal is always in a state of incomplete flipping. At this time, the counter chain continuously detects the rising or falling edge of the clock signal Clk1 pulse, and continuously accumulates and counts the pulse edges to record the number of frames and duration of under-flipping of the liquid crystal in real time.

[0073] When the output signal of the optical detection circuit 20 switches from the first level signal to the second level signal, it means that the liquid crystal molecules have completely flipped to the target optical state. At this time, the counter chain immediately stops pulse counting and latches the current accumulated count value to complete the status data acquisition of this refresh cycle. The latched count value can accurately characterize the degree of under-flipping and the number of effective refresh frames in this refresh cycle.

[0074] The output buffer 41 is an independent signal controllable output module, which is arranged between the multi-channel parallel output terminal of the multi-level D flip-flop U4 and the back-end control circuit 50. It undertakes the signal output enable control function to avoid invalid signals and interference signals from being transmitted to the control circuit 50 and causing judgment errors.

[0075] The enable logic of the output buffer 41 is linked and matched with the level signal of the optical detection circuit 20. When the detection circuit outputs the second level signal, the output buffer 41 receives a valid enable command, automatically turns on the output path, and transmits the accurate count value latched by the D flip-flop U4 to the control circuit 50 completely, providing data support for subsequent waveform adjustment; when the detection circuit continuously outputs the first level signal, the output buffer 41 is in the disabled output state, automatically cuts off the output path, and prevents incomplete or invalid count values ​​from being transmitted to the control circuit 50, ensuring that each data transmitted to the control circuit 50 is complete and valid single-cycle detection data.

[0076] By using a multi-level D flip-flop U4 cascaded counting and latching architecture, combined with an output buffer 41 for controllable output, the quantitative acquisition and accurate recording of the LCD flip state are realized. The data acquisition accuracy is high and the stability is good. It can accurately distinguish different states such as complete flip, slight under-flip, and severe under-flip, providing accurate data support for the fine waveform adjustment of the control circuit 50.

[0077] The output buffer 41 can adopt a corresponding logic gate or other structure. In an optional embodiment, such as... Figure 7 As shown, the output buffer 41 includes a NOT gate U6 and multiple AND gates U5; The first input of each AND gate U5 is connected to the output of a D flip-flop U4, and the second input of each AND gate U5 is connected in parallel to the output of an NOT gate U6. The input of the NOT gate U6 is connected to the output of the switching circuit 30.

[0078] When the switching circuit 30 transmits the first level signal, the NOT gate U6 outputs a low level signal to each AND gate U5, and each AND gate U5 outputs a low level to the control circuit 50. The control circuit 50 has no count value input. When the switching circuit 30 transmits the second level signal, the NOT gate U6 outputs a high level to the control circuit 50, and the count value latched by each D flip-flop U4 can be output to the control circuit 50 through the AND gate U5.

[0079] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: The above-mentioned electronic paper driving circuit 100 includes a driving circuit 10, an optical detection circuit 20, a switching circuit 30, a sampling latch circuit 40, and a control circuit 50. The optical detection circuit 20 detects the degree of liquid crystal flipping in real time and converts and outputs a first level signal and a second level signal. The sampling latch circuit 40 counts based on the first level signal and the second level signal transmitted by the switching circuit 30, accurately records the number of frames required for liquid crystal flipping in digital quantization form, and the control circuit 50 adaptively selects the matching driving waveform according to the size of the count value, thereby achieving a precise match between the total number of driving frames and the actual flipping requirements of the liquid crystal. In the scenario of fast liquid crystal flipping, redundant frames are effectively eliminated, power consumption is reduced, and the refresh cycle is shortened. In the scenario of slow liquid crystal flipping, the drive waveform with a larger total number of frames is automatically switched to eliminate display quality degradation problems such as ghosting and grayscale jumps, thus ensuring refresh efficiency and display quality in all scenarios.

[0080] Example 2 The control circuit 50 can be composed of a corresponding timing controller or similar structure. In an optional embodiment, such as... Figure 8 As shown, the electronic paper driving circuit 100 also includes: The reset circuit 60 is connected to the switching circuit 30. The reset circuit 60 is used to output a first reset signal when a first level signal is received and to switch to output a second reset signal when a second level signal is received. The control circuit 50 includes: The timing controller 51 is connected to the drive circuit 10 and the reset circuit 60. The timing controller 51 is used to load the corresponding drive waveform when it receives the first enable signal and the second reset signal, and to output the drive waveform to the drive circuit 10 when it receives the second enable signal and the first reset signal. Controller 52 is connected to sampling latch circuit 40, reset circuit 60, and timing controller 51. Controller 52 also receives a switch enable signal Ctr1. Controller 52 stores multiple sets of drive waveforms corresponding to different total drive frame numbers. Control circuit 50 is used for: The refresh enable signal Ctr2 selects the initial drive waveform to be applied to the drive circuit 10 within the current refresh cycle; During the current refresh cycle, when the switch enable signal Ctr1 is valid and the first reset signal is received, the second enable signal is output to the timing controller 51 to control the timing controller 51 to maintain the current drive state. During the current refresh cycle, when the switch enable signal Ctr1 is valid and the second reset signal is received, the count value is acquired and compared with the target count range that matches the initial drive waveform. Based on the comparison result, the initial drive waveform is maintained or another target drive waveform is selected and loaded into the timing controller 51. The total number of drive frames corresponding to the other target drive waveform is different from that of the initial drive waveform, and the total number of frames of the target drive waveform changes positively with the count value. When the current refresh cycle ends and the switch enable signal Ctr1 is turned off, the second enable signal is output to the timing controller 51.

[0081] In this embodiment, the electronic paper driving circuit 100 is further provided with a reset circuit 60. The reset circuit 60 establishes a signal connection with the output terminal of the switch circuit 30, and can receive the level signal transmitted from the optical detection circuit 20 by the switch circuit 30 in real time, and output different reset signals RESET according to the state of the level signal.

[0082] The specific working logic is as follows: when the reset circuit 60 receives the first level signal, it outputs the first reset signal; when the reset circuit 60 receives the second level signal, it automatically switches to output the second reset signal, thereby realizing the dynamic linkage between the reset signal RESET and the LCD flip state.

[0083] The corresponding control circuit 50 is specifically divided into two independent functional units: timing controller 51 and controller 52. The two units work together to perform waveform loading and execution and logic decision scheduling functions, respectively, so as to realize hierarchical control of functions and improve the stability of system operation.

[0084] The timing controller 51, acting as a waveform execution unit, establishes signal connections with the drive circuit 10, the reset circuit 60, and the controller 52. Its function is to receive the enable signal transmitted by the controller 52 and the reset signal RESET transmitted by the reset circuit 60, thereby completing the loading, updating, and output control of the drive waveform. When the timing controller 51 receives a combined instruction of the first enable signal and the second reset signal, it executes the drive waveform loading operation, completing the writing and configuration of new waveform data. When it receives a combined instruction of the second enable signal and the first reset signal, it stably outputs the currently loaded drive waveform to the drive circuit 10, maintaining a normal refresh drive state.

[0085] The controller 52, acting as a decision-making and scheduling unit, is connected to the sampling latch circuit 40, the reset circuit 60, and the timing controller 51, and is also connected to the switch enable signal Ctr1. Internally, it stores multiple sets of drive waveforms corresponding to different total drive frames and is responsible for the entire process logic judgment, parameter adjustment, and instruction output. The complete workflow of the controller 52 is divided into four stages, accurately adapting to the entire refresh cycle conditions.

[0086] The first stage is the initial waveform loading stage. When the system receives the external refresh enable signal Ctr2 to start the refresh process, the controller 52 retrieves a set of initial drive waveforms, loads them to the timing controller 51, and then loads them to the drive circuit 10 through the timing controller 51. The drive circuit 10 outputs a drive signal based on the initial drive waveform and performs the current round of screen refresh operation to complete the initial drive configuration.

[0087] The second stage is the normal refresh maintenance stage. During the current refresh cycle, the switch enable signal Ctr1 remains valid, and the timing controller 51 outputs the drive waveform normally. If the controller 52 continues to receive the first reset signal, that is, the switch circuit 30 outputs the first level signal, it means that the liquid crystal has not yet flipped to the correct position, and there is a risk of under-flipping. At this time, the controller 52 continuously outputs the second enable signal to the timing controller 51, controlling the timing controller 51 to maintain the current initial drive waveform unchanged and continue to execute the refresh drive process to ensure that the liquid crystal has sufficient time to complete the flipping.

[0088] The third stage is the adaptive waveform adjustment stage. During the current refresh cycle, the switch enable signal Ctr1 remains valid. If the controller 52 receives the second reset signal, i.e., the switch circuit 30 outputs the second level signal, it indicates that the liquid crystal has completed its flip-flop in the current refresh cycle. The controller 52 immediately reads the count value latched by the sampling latch circuit 40 and compares this count value with the target count range corresponding to the initial drive waveform. Based on the comparison result, the controller 52 determines whether there are redundant frames in the current refresh cycle and performs waveform adjustment accordingly, maintaining the original waveform or switching to a new target drive waveform. The total number of frames of each drive waveform is positively correlated with the latched count value. The larger the count value, the longer the liquid crystal flip-flop takes and the more frames are required, and the system automatically matches a slower refresh waveform with a higher frame rate. The smaller the count value, the faster the liquid crystal flip-flop and the more redundant frames are, and the system automatically matches a faster refresh waveform with a lower frame rate, achieving precise adaptation.

[0089] By comparing the count value with the preset standard range, it is determined whether there is a problem of frame redundancy or insufficient frame count in the current refresh process. Based on the determination result, the loading drive waveform is automatically matched in the next refresh cycle, and the total number of drive frames in the next refresh cycle is dynamically adjusted to achieve adaptive optimization of refresh parameters.

[0090] It is understandable that the drive waveform modes stored in the controller 52 are not limited to fast refresh, standard, and slow refresh. They can be expanded to N modes (N not less than 2) according to actual applications. The decision logic of the controller 52 can be expanded to multi-threshold interval comparison to adapt to more refined adaptive refresh control requirements.

[0091] The fourth stage is the cycle completion control stage. When the current refresh cycle ends, the switch enable signal Ctr1 automatically turns off and becomes ineffective. The controller 52 outputs a second enable signal to the timing controller 51 to lock the current drive waveform configuration, completing the end of this round of refresh process and waiting for the next refresh cycle to start and execute the optimized drive waveform.

[0092] Through the collaborative design of the reset circuit 60 and the dual-unit control circuit 50, the entire process logic of signal linkage, state determination, and waveform switching is improved, realizing a complete closed-loop control from state detection, data latching, logic determination to parameter adaptive adjustment. It can accurately adapt to different flipping conditions and fundamentally solve the performance drawbacks of the traditional fixed refresh mode.

[0093] In an optional embodiment, the controller 52 maintains the initial drive waveform or selects another target drive waveform to be loaded onto the timing controller 51 based on the comparison result, specifically including: When the count value is within the target count range that matches the initial drive waveform, a second enable signal is output to the timing controller 51 to control the timing controller 51 to maintain the initial drive waveform. When the count value exceeds the target count range matched by the initial drive waveform, another target drive waveform is selected to be loaded and the first enable signal is output to the timing controller 51. After the loading is completed, the second enable signal is output to the timing controller 51 to control the timing controller 51 to load the target drive waveform and output it to the drive circuit 10.

[0094] In this embodiment, the controller 52 performs differentiated waveform control operations based on the comparison results of the count values. Specifically, it is divided into two working modes: precise adaptation to two working conditions: no redundant refresh and redundant refresh.

[0095] The first mode is waveform maintenance mode. When the latch count value read by the controller 52 falls within the target count range corresponding to the initial drive waveform, it means that the number of drive frames in this refresh cycle matches the LCD flipping requirements, with no redundant frames or under-flipping issues caused by insufficient frame count. The current initial drive waveform parameters are adapted to the current operating conditions. At this time, the controller 52 continuously outputs a second enable signal to the timing controller 51, controlling the timing controller 51 to maintain the current initial drive waveform unchanged. The next refresh cycle continues to use this waveform to perform the refresh operation without parameter adjustment.

[0096] The second mode is waveform update mode. When the latch count value read by controller 52 exceeds the target count range corresponding to the initial drive waveform, it indicates that the current refresh condition does not match the initial waveform parameters, resulting in significant frame redundancy or insufficient frame count, requiring adaptive update of the drive parameters. In this case, controller 52 first retrieves the target drive waveform matching the current count value, then outputs the first enable signal to timing controller 51, triggering the waveform loading mechanism of timing controller 51. This completely writes the new target drive waveform into the internal configuration register of timing controller 51, completing the waveform parameter update. After the waveform loading process is fully completed, controller 52 switches to outputting the second enable signal, locking the new waveform configuration, and controlling timing controller 51 to output the updated target drive waveform to drive circuit 10, performing an adaptive refresh operation in the next refresh cycle.

[0097] In an optional embodiment, when the count value exceeds the upper limit of the target count range corresponding to the initial drive waveform, it indicates that the current frame count is insufficient. At this time, the controller 52 can select the target drive waveform corresponding to the slow refresh mode with more frames. When the count value is lower than the lower limit of the target count range corresponding to the initial drive waveform, it indicates that there are excess frames. At this time, the controller 52 can select the target drive waveform corresponding to the fast refresh mode with fewer frames.

[0098] The controller 52 determines whether there is frame redundancy or insufficient frame count in the current refresh process by comparing the count value with the preset standard range. Based on the determination result, it automatically matches the loading drive waveform in the next refresh cycle and dynamically adjusts the total number of drive frames in the next refresh cycle to achieve adaptive optimization of refresh parameters.

[0099] It is understandable that the drive waveform modes stored in the controller 52 are not limited to fast refresh, standard, and slow refresh. They can be expanded to N modes (N not less than 2) according to actual applications. The decision logic of the controller 52 can be expanded to multi-threshold interval comparison to adapt to more refined adaptive refresh control requirements.

[0100] Through the logical design of graded judgment and differentiated control, the working condition adaptation state can be accurately distinguished, and adaptive control can be achieved to maintain stability without adjustment and update accurately when adjustment is required. This ensures the system's operational stability under normal working conditions and realizes dynamic parameter optimization under special working conditions, taking into account both system stability and adaptability flexibility.

[0101] In an alternative embodiment, the controller 52 is further configured to: When the current refresh cycle ends and no count value is received before the switch enable signal Ctr1 is turned off, the first enable signal and the initial drive waveform are output to the timing controller 51 when the switch enable signal Ctr1 is turned off, and the second reset signal is output to reset the timing controller 51 after the loading is completed.

[0102] In this embodiment, in actual working scenarios, due to factors such as transient circuit interference, signal fluctuations, and transient hardware anomalies, an abnormal situation may occur where the refresh cycle has ended, but the controller 52 has not received a valid count value transmitted by the sampling latch circuit 40, thus failing to complete the operating condition determination and waveform adjustment. To address this abnormal operating condition, this embodiment sets up dedicated fault-tolerant processing logic.

[0103] At the point when the current refresh cycle ends and the switch enable signal Ctr1 is about to turn off, if the controller 52 fails to acquire a valid latch count value, it determines that the refresh detection in this round is abnormal and cannot obtain valid operating data. At this time, the controller 52 outputs the first enable signal, forcibly triggering the timing controller 51 to reload the initial drive waveform, restoring the device's factory default standard refresh parameters, and avoiding the retention of abnormal parameters that may affect subsequent display effects.

[0104] After the initial drive waveform is fully loaded, the controller 52 outputs a second reset signal to reset the timing controller 51, clearing the residual state and incorrect configuration of the abnormal refresh in this round, allowing the timing controller 51 to fully restore to the initial stable working state, completely eliminating the parameter disorder and display abnormality caused by abnormal working conditions, ensuring the normal and stable execution of subsequent refresh processes, and greatly improving the anti-interference capability and operational reliability of the electronic paper drive circuit 100.

[0105] In an alternative embodiment, such as Figure 9 As shown, the electronic paper driving circuit 100 also includes: The delay circuit 70 is connected to the reset circuit 60, the timing controller 51 and the controller 52 respectively. The delay circuit 70 is also used to delay the output of the reset signal RESET from the reset circuit 60. The delay time of the delay circuit 70 is greater than or equal to the loading time of the timing controller 51 from the loading of the drive waveform by the controller 52.

[0106] In this embodiment, the electronic paper driving circuit 100 is equipped with an independent delay circuit 70. The delay circuit 70 establishes signal connections with the reset circuit 60, the timing controller 51, and the controller 52 respectively. Its function is to perform delay processing on all reset signals RESET output by the reset circuit 60, accurately control the output timing of the reset signal RESET, and match the running time of the waveform loading.

[0107] The delay time of the delay circuit 70 is precisely calibrated, and the delay threshold is greater than or equal to the complete loading time of the controller 52 transmitting and loading the drive waveform to the timing controller 51, ensuring that the timing logic is completely reasonable. When the system performs waveform update and parameter reset operations, the controller 52 first completes the transmission and loading of the new drive waveform. Only after the waveform data is completely written to the timing controller 51 and the configuration parameters are fully effective, does the delay circuit 70 release the reset signal RESET and execute the reset operation of the timing controller 51.

[0108] This timing design completely avoids problems such as waveform loading interruption, incomplete parameter writing, and configuration failure caused by premature triggering of the RESET signal. It ensures that every waveform update and parameter restoration operation is executed completely, ensuring that adaptive parameter adjustment takes effect, further improving the rigor and operational stability of the drive logic, and eliminating display abnormalities and adjustment failures caused by timing misalignment.

[0109] The reset circuit 60 can be composed of corresponding switching devices, and the delay circuit 70 can be composed of corresponding capacitors and resistors. In an optional embodiment, such as... Figure 10 As shown, the reset circuit 60 includes a ninth resistor R9, a tenth resistor R10, and a second electronic switch Q2. The first end of the ninth resistor R9 is connected to the positive voltage terminal VCC, and the second end of the ninth resistor R9 is connected to the first end of the second electronic switch Q2. The control terminal of the second electronic switch Q2 is connected to the output terminal of the switch circuit 30, and the second end of the second electronic switch Q2 is connected to the first end of the tenth resistor R10. The second end of the tenth resistor R10 constitutes the output terminal of the reset circuit 60.

[0110] When the switching circuit 30 outputs a high-level first-level signal, the second electronic switch Q2 of the reset circuit 60 is turned off and outputs a low-level first-level reset signal. When the switching circuit 30 outputs a low-level second-level signal, the reset circuit 60 outputs a high-level second-level reset signal. The timing controller 51 receives the high-level second-level reset signal and performs a reset.

[0111] like Figure 10 As shown, the delay circuit 70 includes an eleventh resistor R11 and a third capacitor C3. The first end of the eleventh resistor R11, the first end of the third capacitor C3, and the output terminal of the reset circuit 60 are connected to form the output terminal of the delay circuit 70. The second end of the eleventh resistor R11 and the second end of the third capacitor C3 are grounded. The eleventh resistor R11 and the third capacitor C3 form an RC delay unit and delay the output of the reset signal RESET from the reset circuit 60. The eleventh resistor R11 and the third capacitor C3 with corresponding resistance values ​​can be selected according to the relationship between the loading time of the controller 52 and the delay time.

[0112] Example 3 A second aspect of the present invention provides an electronic paper display device, such as... Figure 11 As shown, the electronic paper display device includes a display panel 200 and an electronic paper driving circuit 100. The specific structure of the electronic paper driving circuit 100 is as described in the above embodiments. Since this electronic paper display device adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be described in detail here. The display panel 200 is connected to the electronic paper driving circuit 100. The display panel 200 is provided with an upper substrate 210, a liquid crystal layer 230, and a lower substrate 220 stacked sequentially. The liquid crystal layer 230 is provided with cholesteric liquid crystal.

[0113] In this embodiment, as Figure 1 As shown, the display panel 200 adopts a stacked structure, consisting of an upper substrate 210, a liquid crystal layer 230, and a lower substrate 220 stacked sequentially from top to bottom. The liquid crystal layer 230 is encapsulated and filled with cholesteric liquid crystal material. Relying on the bistable optical properties of cholesteric liquid crystal, it achieves the advantages of zero-power image maintenance and low-power image refresh. The upper and lower substrates of the display panel 200 are respectively provided with driving electrode layers, which are correspondingly connected to the multi-channel driving signal output terminals of the driving circuit 10. They receive the adaptively adjusted driving waveform signals to complete the liquid crystal molecule flipping control and image display.

[0114] This electronic paper display device is equipped with an adaptive closed-loop driven electronic paper driving circuit 100, which can sense the liquid crystal flipping state and environmental conditions in real time, and dynamically adjust the refresh rate and driving waveform. It solves the problems of power consumption waste, image quality degradation and poor scene adaptability caused by the fixed refresh of traditional electronic paper. It has the advantages of low power consumption, high image quality and high adaptability, and can be widely used in various low power consumption display scenarios such as smart wearables, e-readers, smart supermarket labels, and vehicle auxiliary displays.

[0115] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. An electronic paper driving circuit, characterized in that, include: A driving circuit is used to provide matched multiple driving signals to the display panel within a refresh cycle based on the loaded driving waveform, so as to control the cholesteric liquid crystal flipping of the display panel. An optical detection circuit is used to detect the degree of flipping of the cholesteric liquid crystal during the refresh cycle, and to generate a first level signal representing that the flipping is not in place and a second level signal representing that the flipping is in place. A switching circuit, the control terminal of which is used to input a switch enable signal, the input terminal of which is connected to the output terminal of the optical detection circuit, the switching circuit being triggered to conduct within the refresh cycle by the switch enable signal, the switch enable signal following the change of one of the drive signals; A sampling latch circuit is connected to the switching circuit. The sampling latch circuit is used to count the clock signal during the duration of the first level signal, and latch the count value and output it when the second level signal is received. The control circuit, connected to the sampling latch circuit and the driving circuit, also receives the switch enable signal. The control circuit stores multiple sets of driving waveforms corresponding to different total driving frame numbers. The control circuit is used for: The refresh enable signal selects an initial drive waveform to be applied to the drive circuit within the current refresh cycle; At the end of the current refresh cycle, based on the magnitude of the count value and the state of the switch enable signal, a set of matching drive waveforms is selected and loaded onto the drive circuit in the next refresh cycle to adjust the total number of drive frames for each drive signal in the next refresh cycle.

2. The electronic paper driving circuit as described in claim 1, characterized in that, The optical detection circuit includes: A first photoelectric sensor is integrated on the upper substrate side of the display panel. The first photoelectric sensor is used to collect ambient light signals and generate a first voltage signal. The second photoelectric sensor is integrated on the lower substrate side of the display panel. The second photoelectric sensor is used to collect the transmitted light signal after penetrating the cholesteric liquid crystal and generate a second voltage signal. A differential comparison circuit is connected to the first photoelectric sensor and the second photoelectric sensor. The differential comparison circuit is used to compare the first voltage signal and the second voltage signal, and output the first level signal when the cholesteric liquid crystal has not flipped to the target transmittance, and output the second level signal when the cholesteric liquid crystal flips to the target transmittance.

3. The electronic paper driving circuit as described in claim 2, characterized in that, The optical detection circuit further includes: A first signal amplification circuit is connected between the first photoelectric sensor and the differential comparator circuit. The first signal amplification circuit is used to amplify and output the first voltage signal. The second signal amplification circuit is connected between the second photoelectric sensor and the differential comparator circuit. The second signal amplification circuit is used to amplify and output the second voltage signal.

4. The electronic paper driving circuit as described in claim 2, characterized in that, The upper substrate of the display panel is provided with a first driving layer, and the lower substrate of the display panel is provided with a second driving layer. The driving signal includes at least a common electrode voltage signal output to the first driving layer and a data signal output to the second driving layer; The switch enable signal is the common electrode voltage signal or a voltage divider of the common electrode voltage signal.

5. The electronic paper driving circuit as described in claim 1, characterized in that, The sampling latch circuit includes: A multi-stage D flip-flop is cascaded to form a counter chain. The data input of the first-stage D flip-flop in the counter chain is connected to the output of the switching circuit. The clock inputs of all D flip-flops are used to input the clock signal. The counter chain is used for: During the refresh cycle, when the switching circuit transmits the first level signal, the pulse edges of the clock signal are accumulated and counted. When the signal is flipped to the second level, the counting stops and the current count value is latched. An output buffer is disposed between the multi-channel parallel output terminals of the multi-stage D flip-flop and the control circuit. The output buffer is used for: When the second level signal is received to enable, the count value is output to the control circuit; When the first level signal is received, the control circuit is enabled or disabled, and the output of a valid count value to the control circuit is stopped.

6. The electronic paper driving circuit according to any one of claims 1 to 5, characterized in that, The electronic paper driving circuit also includes: A reset circuit is connected to the switching circuit. The reset circuit is used to output a first reset signal when the first level signal is received and to switch to output a second reset signal when the second level signal is received. The control circuit includes: A timing controller is connected to the drive circuit and the reset circuit. The timing controller is used to load the input corresponding to the drive waveform when it receives a first enable signal and a second reset signal, and to output the drive waveform to the drive circuit when it receives the second enable signal and the first reset signal. The controller is connected to the sampling latch circuit, the reset circuit, and the timing controller. The controller also receives the switch enable signal and stores multiple sets of drive waveforms corresponding to different total drive frame numbers. The control circuit is used for: The refresh enable signal selects an initial drive waveform to be applied to the drive circuit within the current refresh cycle; During the current refresh cycle, when the switch enable signal is valid and the first reset signal is received, the second enable signal is output to the timing controller to control the timing controller to maintain the current drive state; During the current refresh cycle, when the switch enable signal is valid and the second reset signal is received, the count value is acquired, and the count value is compared with the target count range that matches the initial drive waveform. Based on the comparison result, the initial drive waveform is maintained or another target drive waveform is selected and loaded onto the timing controller. The total number of drive frames corresponding to the other target drive waveform is different from that of the initial drive waveform, and the total number of frames of the target drive waveform changes positively with the count value. When the current refresh cycle ends and the switch enable signal is turned off, the second enable signal is output to the timing controller.

7. The electronic paper driving circuit as described in claim 6, characterized in that, The controller maintains the initial drive waveform or selects another target drive waveform to be loaded onto the timing controller based on the comparison result, specifically including: When the count value is within the target count range that matches the initial drive waveform, a second enable signal is output to the timing controller to control the timing controller to maintain the initial drive waveform. When the count value exceeds the target count range matched by the initial drive waveform, another target drive waveform is selected to be loaded and the first enable signal is output to the timing controller. After the loading is completed, the second enable signal is output to the timing controller to control the timing controller to load the target drive waveform and output it to the drive circuit.

8. The electronic paper driving circuit as described in claim 6, characterized in that, The controller is also used for: When the current refresh cycle ends and the count value is not received before the switch enable signal is turned off, when the switch enable signal is turned off, the first enable signal is output and the initial drive waveform is loaded to the timing controller, and after the loading is completed, the second reset signal is output to reset the timing controller.

9. The electronic paper driving circuit as described in claim 8, characterized in that, The electronic paper driving circuit also includes: The delay circuit is connected to the reset circuit, the timing controller, and the controller respectively. The delay circuit is also used to delay the output of the reset signal from the reset circuit. The delay time of the delay circuit is greater than or equal to the loading time of the timing controller when the controller loads the driving waveform.

10. An electronic paper display device, characterized in that, The device includes a display panel and an electronic paper driving circuit as described in any one of claims 1 to 9, wherein the display panel is connected to the electronic paper driving circuit, and the display panel has an upper substrate, a liquid crystal layer and a lower substrate stacked sequentially, wherein the liquid crystal layer is provided with cholesteric liquid crystal.

Images