Memory access control method, cache method and corresponding apparatus, data processing device

Abstract

The present disclosure provides a memory access control method, a cache method, and corresponding devices and data processing equipment, and belongs to the technical field of computers. The memory access control method comprises: judging whether a cache module meets a preset target memory access condition; in response to the cache module meeting any target memory access condition, determining a first sub-block information code corresponding to the met target memory access condition; and sending the first sub-block information code and a received memory access request to the cache module, so as to control the cache module to execute a memory access operation corresponding to the memory access request based on the first sub-block information code. The embodiments of the present disclosure can take into account the bandwidth use efficiency and memory hit rate between cache levels.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a memory access control method, a caching method, a memory access control device, a caching device, and a data processing device. Background Technology

[0002] In the caching module, a cache line can be divided into sectors, with each sector serving as the smallest unit of data transfer. While using sectors as the data transfer unit can improve bandwidth utilization between cache levels in some scenarios, it can also lead to frequent cache misses and performance degradation in others. Summary of the Invention

[0003] This disclosure provides a memory access control method, a caching method, a memory access control device, a caching device, and a data processing device.

[0004] In a first aspect, this disclosure provides a memory access control method, which includes: determining whether the cache module meets a preset target memory access condition, the target memory access condition being used to characterize whether the memory access behavior of the cache module conforms to a preset target memory access mode; in response to the cache module meeting any of the target memory access conditions, determining a first sub-block information code corresponding to the met target memory access condition; sending the first sub-block information code and a received memory access request to the cache module to control the cache module to perform a memory access operation corresponding to the memory access request based on the first sub-block information code; wherein, the first sub-block information code is used to characterize information of a first target sub-block that the target cache unit hit by the memory access request backfills to the cache unit at the next higher level, the first target sub-block including a first sub-block indicated by the memory access request and at least one second sub-block predicted based on the target memory access condition that is adjacent to the first sub-block.

[0005] Secondly, this disclosure provides a caching method, which includes: receiving a first sub-block information encoding and a memory access request; determining a target cache unit hit by the memory access request; decoding the first sub-block information encoding to obtain information of a first target sub-block; determining cache filling data in the target cache unit based on the information of the first target sub-block; and filling the cache filling data back into a cache unit at the upper level of the target cache unit; wherein the first sub-block information encoding is issued by the control module of the cache module when the cache module meets the target memory access conditions, the target memory access conditions are used to characterize whether the memory access behavior of the cache module conforms to a preset target memory access mode, and the first target sub-block includes a first sub-block indicated by the memory access request and at least one second sub-block predicted based on the target memory access conditions met by the cache module and adjacent to the first sub-block.

[0006] Thirdly, this disclosure provides a memory access control device, which includes: a judgment module, configured to judge whether the cache module meets a preset target memory access condition, the target memory access condition being used to characterize whether the memory access behavior of the cache module conforms to a preset target memory access mode; a first determination module, configured to determine a first sub-block information code corresponding to the met target memory access condition in response to the cache module meeting any of the target memory access conditions; and a sending module, configured to send the first sub-block information code and a received memory access request to the cache module to control the cache module to perform a memory access operation corresponding to the memory access request based on the first sub-block information code; wherein, the first sub-block information code is used to characterize information of a first target sub-block that the target cache unit hit by the memory access request fills back to the cache unit at the next higher level, the first target sub-block including the first sub-block indicated by the memory access request and at least one second sub-block predicted based on the target memory access condition and adjacent to the first sub-block.

[0007] Fourthly, this disclosure provides a caching device, comprising: a receiving module for receiving a first sub-block information encoding and a memory access request; a hit module for determining a target cache unit hit by the memory access request; a decoding module for decoding the first sub-block information encoding to obtain information of a first target sub-block; a second determining module for determining cache filling data in the target cache unit based on the information of the first target sub-block; and a filling module for filling the cache filling data back into a cache unit at the upper level of the target cache unit; wherein the first sub-block information encoding is issued by the control module of the cache module when the cache module meets the target memory access conditions, the target memory access conditions are used to characterize whether the memory access behavior of the cache module conforms to a preset target memory access mode, and the first target sub-block includes a first sub-block indicated by the memory access request and at least one second sub-block predicted to be adjacent to the first sub-block based on the target memory access conditions met by the cache module.

[0008] Fifthly, this disclosure provides a data processing device, which includes: at least one processing unit, at least one memory access control device, and at least one cache device; wherein the processing unit is used to perform data processing corresponding to a target task, the memory access control device is the aforementioned memory access control device, and the cache device is the aforementioned cache device.

[0009] In a sixth aspect, this disclosure provides an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores one or more computer programs executable by the at least one processor, the one or more computer programs being executed by the at least one processor to enable the at least one processor to perform the memory access control method described above.

[0010] In a seventh aspect, this disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the memory access control method described above.

[0011] Eighthly, this disclosure provides a computer program product including computer-readable code. When the computer-readable code is executed in a processor of an electronic device, the processor in the electronic device executes the memory access control method described above. The memory access control method provided in this disclosure can determine whether a cache module meets preset target memory access conditions, thereby determining whether the memory access behavior of the cache module conforms to a preset target memory access mode. In response to the cache module meeting any target memory access condition, a first sub-block information encoding corresponding to the met target memory access condition is determined. The first sub-block information encoding and the received memory access request are sent to the cache module, thereby controlling the cache module to execute the memory access operation corresponding to the memory access request based on the first sub-block information encoding. The first sub-block information encoding is used to characterize information about the first target sub-block that the target cache unit hit by the memory access request fills back to the upper-level cache unit. The first target sub-block includes the first sub-block indicated by the memory access request and at least one second sub-block predicted based on the target memory access conditions and adjacent to the first sub-block.

[0012] Therefore, by setting a control module to control the cache module, it is possible to determine whether the cache module meets the preset target memory access conditions. When it is determined that the cache module meets any target memory access condition, the first sub-block information code corresponding to the target memory access condition is determined and sent to the cache module along with the memory access request. This allows the cache module to determine the first target sub-block based on the first sub-block information code and fill the data in it back into the upper-level cache unit of the hit target cache unit. Since the first target sub-block includes not only the first sub-block indicated by the memory access request itself, but also at least one second sub-block that is adjacent to the first sub-block and predicted according to the target memory access conditions, the probability of subsequent memory access requests corresponding to the second sub-block is higher. Therefore, the hit rate can be improved, and the number of sub-block transmissions between different levels of cache units can be reduced, the bandwidth consumption between different levels of cache units can be reduced, and the utilization efficiency of cached data can be increased. In other words, the embodiments of this disclosure can dynamically adjust the number, position, and other contents of the sub-blocks returned by the lower-level cache unit to the upper-level cache unit through the encoding of the first sub-block information, thereby enabling adaptive matching of appropriate cache backfilling methods for different memory access modes, taking into account both bandwidth utilization efficiency and memory hit rate between cache levels.

[0013] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0014] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the embodiments of the present disclosure to explain the disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0015] Figure 1 This is a flowchart of a memory access control method provided in an embodiment of the present disclosure.

[0016] Figure 2 This is a schematic diagram of another memory access control method provided in an embodiment of this disclosure.

[0017] Figure 3 A flowchart of a caching method provided in an embodiment of this disclosure.

[0018] Figure 4 This is a block diagram of a memory access control device provided in an embodiment of the present disclosure.

[0019] Figure 5 This is a block diagram of a caching device provided in an embodiment of the present disclosure.

[0020] Figure 6 This is a block diagram of a data processing device provided in an embodiment of the present disclosure.

[0021] Figure 7 This is a block diagram of an electronic device provided in an embodiment of the present disclosure.

[0022] Figure 8 A block diagram of another electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0023] To enable those skilled in the art to better understand the technical solutions of this disclosure, exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments of this disclosure to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0024] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0025] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0026] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded. Words such as “connected” or “linked” are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.

[0027] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0028] The collection, storage, use, processing, transmission, provision, and disclosure of user personal information in this technical solution comply with relevant laws and regulations and do not violate public order and good morals. The use of user data in this technical solution follows relevant national laws and regulations. For example, appropriate measures are taken for personal information access control; restrictions are imposed on the display of personal information; the purpose of using personal information does not exceed the scope of direct or reasonable association; and explicit identification is eliminated when using personal information to avoid precisely targeting specific individuals.

[0029] In the field of digital information, memory access performance is often the bottleneck of chip performance. To reduce the high latency caused by frequent memory access, multi-level cache structures are usually introduced in chip design. A cache unit can consist of multiple cache lines, and a cache line can be divided into multiple sub-blocks. For example, a 128-byte cache line can consist of four 32-byte sub-blocks.

[0030] For example, if a memory access request misses an L1 cache unit, the L2 cache unit needs to return the corresponding data to the L1 cache unit. The L1 cache unit sends information such as the location of the required data within a specific sub-block of the cache line to the L2 cache unit. The L2 cache unit then returns the cached data for the corresponding sub-block based on this location information. Cached data within other unnecessary sub-blocks within the same cache line is not returned. Compared to directly returning the entire cache line, this sub-block-level data transfer reduces bandwidth usage between cache levels and increases the efficiency of using valid data. However, in some scenarios, this approach, using a single sub-block as the smallest unit of data transfer, may lead to frequent misses, resulting in performance degradation.

[0031] In view of this, the present disclosure provides a memory access control method, a caching method, a memory access control device, a caching device, and a data processing device, which can effectively balance bandwidth utilization efficiency and memory access hit rate between cache levels.

[0032] In a first aspect, embodiments of this disclosure provide a memory access control method.

[0033] Figure 1 The flowchart illustrates a memory access control method provided in this embodiment. This method can be applied to a control module for controlling a cache module. The cache module includes multiple levels of cache units, each cache unit includes multiple cache lines, and each cache line includes multiple sub-blocks. (Refer to...) Figure 1 The memory access control method may include the following steps:

[0034] Step S11: Determine whether the cache module meets the preset target memory access conditions. The target memory access conditions are used to characterize whether the memory access behavior of the cache module conforms to the preset target memory access mode.

[0035] Step S12: In response to the cache module satisfying any target memory access condition, determine the first sub-block information encoding corresponding to the satisfied target memory access condition;

[0036] Step S13: The first sub-block information encoding and the received memory access request are sent to the cache module to control the cache module to execute the memory access operation corresponding to the memory access request based on the first sub-block information encoding;

[0037] The first sub-block information encoding is used to characterize the information of the first target sub-block that the target cache unit hit by the memory access request fills back to the cache unit at the next higher level. The first target sub-block includes the first sub-block indicated by the memory access request and at least one second sub-block that is adjacent to the first sub-block based on the target memory access conditions.

[0038] In some optional embodiments, a control module may be added upstream of the cache module, and the memory access control method of the present disclosure embodiments may be executed based on the control module.

[0039] Furthermore, the control module can determine whether the cache module meets any target memory access condition. As long as it is determined that the cache module meets a certain target memory access condition, it can determine the first sub-block information code corresponding to the met target memory access condition and send it to the cache module, controlling the cache module to perform the corresponding memory access operation based on the first sub-block information code.

[0040] In some optional embodiments, the target memory access condition refers to the memory access behavior of the cache module conforming to a preset target memory access pattern. The target memory access pattern has a certain predictable regularity, which is in contrast to memory access patterns that have no clear predictable regularity or cannot predict memory access patterns. In other words, considering that the memory access behavior of the cache module has specific regularities for different target memory access conditions, these regularities can be used to predict the memory access operations for the cache module, thereby indicating how to perform cache backfilling.

[0041] In some optional embodiments, the cache module is performing a memory access operation based on the second sub-block information code previously issued by the control module. During this process, the control module can continuously or intermittently determine whether the cache module meets a certain target memory access condition. If it is determined that the cache module meets a certain target memory access condition, the control module can determine the first sub-block information code corresponding to the newly determined target memory access condition and issue it to the cache module, controlling the cache module to switch from using the second sub-block information code to using the first sub-block information code to perform the corresponding memory access operation.

[0042] It should be noted that the second sub-block information encoding can be either the sub-block information encoding used when the cache module does not meet any target memory access condition, or the sub-block information encoding used when the cache module meets a target memory access condition. Therefore, when the control module detects that the cache module changes from not meeting any target memory access condition to meeting a target memory access condition, or when it detects that the cache module switches from one target memory access condition to another, it can determine new sub-block encoding information (such as the first sub-block information encoding) based on the currently met target memory access condition and send this new sub-block encoding information to the cache module. In other words, if it detects that the cache module consistently meets a target memory access condition, there is no need to adjust the sub-block information encoding currently used by the cache module, and therefore no need to send a new sub-block information encoding to the cache module.

[0043] It should also be noted that the first sub-block information encoding determined when the target memory access condition is met can characterize the information of the first target sub-block to be backfilled to the upper-level cache unit by the target cache unit hit by the memory access request. Cache backfilling or cache filling refers to the operation of moving and loading cache data from the lower-level cache unit hit by the memory access request to the upper-level cache unit when the memory access request does not hit the highest-level cache unit of the cache module. The first sub-block information encoding can indicate the first target sub-block to be backfilled with cache data. Furthermore, the first target sub-block includes two sub-blocks: the first sub-block and the second sub-block. The first sub-block is the sub-block indicated by the memory access request that should have been returned, and the second sub-block is one or more sub-blocks adjacent to the first sub-block, predicted according to the target memory access condition. In other words, through a single memory access operation, not only is the cached data data1 corresponding to the first sub-block that should have been returned already filled in, but the cached data data2 corresponding to the second sub-block is also filled in. The reason for pre-filling the extra cached data data2 is mainly because, under the target memory access mode corresponding to the target memory access condition, the cache module is more likely to access the cached data data2 corresponding to the second sub-block in the short term. Therefore, returning this part of the cached data in advance can improve the subsequent hit rate and also improve the bandwidth utilization efficiency between cache levels.

[0044] For example, the cache module includes N levels of cache units (N>1). When the control module detects that the cache module meets a certain target memory access condition, it determines the first sub-block information code corresponding to the target memory access condition and sends it to the cache module. During the memory access operation based on the first sub-block information code, if the memory access request hits the cache unit of the k-th level (1<k≤N), then when backfilling the cached data hit in the cache unit of the k-th level to the cache units of the 1st to the (k-1)th levels, the cache module can use the first sub-block information code sent by the control module. The first sub-block information code can indicate the number of sub-blocks and / or the position of the first target sub-block corresponding to the cached data that needs to be backfilled in the cache unit of the k-th level.

[0045] In contrast, related technologies do not include a control module for implementing the memory access control method of this disclosure, nor do they determine whether the cache module meets the target memory access conditions, nor do they issue first sub-block information codes to dynamically adjust or control the cache backfilling operation of the cache module during the memory access operation. Instead, they perform the cache backfilling operation according to fixed configuration information.

[0046] Taking a cache line containing four sub-blocks as an example, if an application accesses the four sub-blocks of a cache line sequentially through memory access requests, and assumes that the L1 cache unit of the cache module is not hit, if related technologies are used, four misses will occur for the L1 cache unit. Each time a miss occurs, a corresponding sub-block needs to be returned from the L2 cache unit. However, if the memory access control method of this embodiment is used, when it is identified that the cache module meets the target access condition of sequential access, the cache data of the four sub-blocks in the entire cache line can be returned from the L2 cache unit when the first miss occurs by sending the first sub-block information encoding to the cache module. Then, the subsequent three memory access requests will directly hit the L1 cache unit, thereby improving the memory access hit rate, improving the bandwidth utilization efficiency between cache levels, and thus improving memory access efficiency.

[0047] In summary, in this embodiment of the present disclosure, by setting a control module for controlling the cache module, it is possible to determine whether the cache module meets the preset target memory access conditions. When it is determined that the cache module meets any target memory access condition, the first sub-block information code corresponding to the target memory access condition is determined and sent to the cache module along with the memory access request. This allows the cache module to determine the first target sub-block based on the first sub-block information code and backfill the data within it to the upper-level cache unit of the hit target cache unit. Since the first target sub-block includes not only the first sub-block indicated by the memory access request itself, but also at least one second sub-block that is adjacent to the first sub-block and predicted according to the target memory access conditions, the probability of subsequent memory access requests corresponding to the second sub-block is high. Therefore, the subsequent hit rate can be improved. At the same time, the number of sub-block transmissions between different levels of cache units can be reduced, the bandwidth consumption between different levels of cache units can be reduced, and the utilization efficiency of cached data can be increased. In other words, the embodiments of this disclosure can dynamically adjust the number, position, and other contents of the sub-blocks returned by the lower-level cache unit to the upper-level cache unit through the encoding of the first sub-block information, thereby enabling adaptive matching of appropriate cache backfilling methods for different memory access modes, taking into account both bandwidth utilization efficiency and memory hit rate between cache levels.

[0048] The data exchange and storage method of the present disclosure embodiments will be described in detail below.

[0049] In some optional embodiments, the cache module is a hardware functional module that integrates multi-level cache units and supporting control logic. It can be deployed between the processor core and main memory to cache frequently accessed data, reduce memory access latency, and reduce main memory bandwidth pressure.

[0050] For example, the caching module includes multiple levels of caching units, each caching unit includes multiple cache lines, and each cache line includes multiple sub-blocks.

[0051] Furthermore, each cache unit can independently maintain status information such as cache lines, tags, valid bits, and dirty bits. After receiving a memory access request from an upstream module, tag comparison and hit detection can be performed layer by layer from near to far. The memory access request may hit any cache unit at any level, and if not all cache units are hit, further access can be initiated to the downstream storage module (such as main memory).

[0052] In some optional embodiments, the cache module may employ multiple memory access modes to perform memory access operations. A memory access mode refers to the behavioral paradigm, such as the distribution pattern of the target memory address, access timing characteristics, data read / write organization, and access granularity, when a functional entity such as a processor, computing core, or main control unit initiates a memory access request. In other words, each memory access mode is an abstract generalization of a type of memory access behavior, and the address distribution characteristics and read / write behavior characteristics corresponding to different memory access modes differ significantly.

[0053] It should be noted that memory access operations refer to a series of specific read and write operations performed in response to a single access request initiated by the Central Processing Unit (CPU), bus, etc. Memory access behavior, on the other hand, is the behavior exhibited by aggregating a large number of memory access operations, which can be characterized by certain patterns. By statistically analyzing a series of memory access operations performed by the cache module, statistical features such as address change sequences, access time intervals, read / write direction ratios, and space coverage granularity can be extracted. This allows for the summarization of reproducible and predictable memory access behavior patterns, and the target memory access pattern belongs to this type of memory access behavior pattern.

[0054] In other words, a single memory access operation is a concept at the micro-execution level, while memory access behavior and memory access patterns are macro-abstracts of batch memory access operations. They are not limited to the execution details of a single request, but focus on finding the evolution patterns of address sequences, the strength of spatial and temporal locality, the periodicity of access, and other overall characteristics.

[0055] By using this analytical logic of extracting memory access patterns from the underlying memory access operations, we can extract patterns from scattered and irregular memory access operations and transform them into corresponding target memory access patterns and their corresponding target memory access conditions, providing an important foundation for controlling the cache module.

[0056] In some optional embodiments, memory access modes may include sequential memory access mode, step memory access mode, clustered memory access mode, random memory access mode, etc. Among them, the memory access addresses corresponding to the sequential memory access mode are usually continuously increasing or decreasing, the step memory access mode refers to accessing memory in a jump manner according to a preset step size, the clustered memory access mode refers to multiple memory access requests concentrating on accessing a small interval, and the memory access addresses of the random memory access mode are irregularly and discretely distributed, with extremely poor spatial locality.

[0057] Furthermore, the target memory access pattern includes memory access patterns with good spatial locality; in other words, if the cache module corresponds to the target memory access pattern, it means that the memory access behavior of the cache module is concentrated in a local area and will not be randomly and discretely distributed in a large range of areas.

[0058] In some alternative embodiments, the target memory access mode includes at least one of continuous memory access mode and step memory access mode.

[0059] It should be noted that the above examples of target memory access modes are merely illustrative and are not intended to limit the scope of this disclosure.

[0060] Considering the characteristics of the memory access behavior of the target memory access mode, the cache module can be controlled to adjust the number and / or position of the returned sub-blocks by sending the corresponding first sub-block information encoding to the cache module, thereby maximizing the hit rate of memory access requests.

[0061] As mentioned above, the control module can continuously or intermittently determine whether the cache module meets the target memory access conditions. If it is determined that the cache module meets any target memory access condition, it can determine the first sub-block information code corresponding to the target memory access condition and send the first sub-block information code and the memory access request to the cache module, so that the cache module can perform the memory access operation corresponding to the memory access request based on the first sub-block information code. For example, when the memory access request hits the k-th level cache unit (1 < k ≤ N), the cache filling data that the k-th level cache unit needs to return to the cache units of the 1st to k-1st levels is determined according to the first sub-block information code, and these cache filling data are backfilled into the cache units of the 1st to k-1st levels, where N is the total number of levels of the cache module. Furthermore, the backfilled cache data corresponds to the first target sub-block, which includes not only the first sub-block indicated by the memory access request, but also the second sub-block that is predicted based on the target memory access conditions and has a higher probability of being accessed later.

[0062] Furthermore, when it is detected that the cache module no longer meets any of the target memory access conditions, it indicates that the first sub-block information encoding currently in use does not match the current memory access mode of the cache module. Therefore, the first sub-block information encoding can be adjusted or updated to obtain a new sub-block information encoding, and the new sub-block information encoding can be sent to the cache module to reduce bandwidth waste between cache levels and improve bandwidth utilization efficiency between cache levels.

[0063] In some optional embodiments, after sending the first sub-block information encoding and the received memory access request to the cache module, the memory access control method further includes: in response to detecting that the cache module does not meet the target memory access condition, sending the second sub-block information encoding and the received memory access request to the cache module to control the cache module to perform the memory access operation corresponding to the memory access request based on the second sub-block information encoding; wherein, the second sub-block information encoding is used to characterize the information of the second target sub-block backfilled by the target cache unit hit by the memory access request to the upper-level cache unit, and the second target sub-block includes the sub-block indicated by the memory access request. In other words, when the cache module does not meet any target memory access condition, the backfilling of the sub-block data indicated by the memory access request can be controlled through the second sub-block information encoding, possibly without the need to return other cache data.

[0064] For example, the second sub-block information encoding indicates that the number of the second target sub-block is 1. Therefore, it is only necessary to return the data in the sub-block indicated by the memory access request.

[0065] Therefore, the memory access behavior of the cache module has two cases: satisfying the target memory access conditions and not satisfying the target memory access conditions. A first sub-block information code Code1 and a second sub-block information code Code2 are set for each case, and a corresponding first sub-block information code Code1i (where i represents the sequence number of the target memory access condition) is set for each target memory access condition ACon(i). Based on this, when it is detected that the cache module does not satisfy all target memory access conditions, the matching sub-block information code is determined as the second sub-block information code Code2, and this second sub-block information code Code2 is sent to the cache module. When it is detected that the cache module satisfies a certain target memory access condition ACon(j), the sub-block information code corresponding to this target memory access condition ACon(j) is determined as the first sub-block information code Code2j, and this first sub-block information code Code2j is sent to the cache module. Here, j represents the sequence number of the satisfied target memory access condition, 1≤i≤M, 1≤j≤M, and M represents the total number of target memory access conditions.

[0066] This approach allows for adaptive adjustment of the number and / or position of sub-blocks returned from lower-level cache units to upper-level cache units within cache lines, based on the memory access scenarios of the cache modules. This balances bandwidth utilization efficiency and memory hit rate between cache levels.

[0067] In some optional embodiments, it can be determined whether the cache module meets the target memory access conditions based on the memory access context information of the cache module. The cache context information includes historical memory access information about the cache module and / or pending memory access information (i.e., information related to unprocessed memory access requests), and may include attribute information and status information regarding the memory access behavior of the cache module. This allows the cache module's memory access pattern to be determined or predicted based on the cache context information, thereby determining whether the cache module meets the target memory access conditions.

[0068] In some optional embodiments, determining whether a cache module meets preset target memory access conditions includes: obtaining the memory access context information of the cache module; determining memory access attribute information based on the memory access context information; and determining whether the cache module meets any target memory access condition based on the memory access attribute information. The memory access context information may include historical memory access behavior information and / or pending memory access behavior information, which is a relatively raw form of data. The memory access attribute information is information extracted, processed, and refined from the memory access context information to reflect historical memory access attributes and / or pending memory access attributes.

[0069] In other words, on the one hand, considering that the memory access behavior of the cache module may have a certain consistency, the historical memory access behavior information of the cache module can be used to predict whether the memory access operation to be executed by the cache module meets the target memory access conditions. For example, if the cache module corresponds to memory access mode Mode1 in the time period (t0, t1), it is highly likely that the cache module will still correspond to memory access mode Mode1 at time t1 or in the time period (t1, t2). On the other hand, considering that the memory access behavior of the cache module may change, the pending memory access behavior information of the cache module can also be used to predict whether the memory access operation to be executed by the cache module meets the target memory access conditions. For example, if the cache module receives a pending memory access request, it can predict what kind of memory access operation the cache module will execute and whether the memory access operation meets a certain target memory access condition based on the relevant information of the memory access request. Furthermore, the historical memory access behavior information and pending memory access behavior information of the cache module can be combined to more comprehensively predict whether the memory access operation to be executed by the cache module meets the target memory access conditions.

[0070] Therefore, in this embodiment, it can be seen that whether the memory access behavior to be executed by the cache module conforms to the target memory access mode can be determined directly based on historical memory access behavior, or based on the relevant information of currently received but not yet executed memory access requests. Alternatively, it can be determined by combining the relevant information of historical memory access behavior and currently received but not yet executed memory access requests. Based on this, when determining whether the cache module meets the target memory access conditions, various types and combinations of information can be used, thus enabling determination of whether the target memory access conditions are met for various application scenarios, resulting in a high degree of application scope and processing flexibility.

[0071] In some optional embodiments, the cache context information includes historical memory access records of the cache module and / or memory access request information received by the cache module and awaiting processing. The memory access request information includes a resource type identifier and / or address space attribute of the memory access request. The memory access attribute information includes at least one of the following: historical memory access address information, a first memory access resource type, and a second memory access resource type. Accordingly, determining the memory access attribute information based on the memory access context information includes at least one of the following: obtaining historical memory access address information based on the historical memory access records of the cache module; obtaining the resource type identifier and / or address space attribute corresponding to the historical memory access request based on the historical memory access records of the cache module; determining the first memory access resource type corresponding to the historical memory access request based on the resource type identifier and / or address space attribute corresponding to the historical memory access request, wherein the address space attribute is used to indicate the memory access resource type of the cached data within the memory access address corresponding to the memory access request; and determining the second memory access resource type corresponding to the memory access request awaiting processing based on the resource type identifier and / or address space attribute corresponding to the received memory access request awaiting processing.

[0072] In some optional embodiments, the historical memory access record includes a record of multiple historical memory access behaviors of the cache module. For each historical memory access behavior record, it may include the corresponding historical memory access address, resource type identifier, address space attributes, etc., which are not limited in this embodiment of the present disclosure.

[0073] The resource type identifier identifies the type of memory resource corresponding to the accessed data. Furthermore, for the caching module, its storage space can be divided into multiple storage subspaces, each corresponding to a specific address space attribute, used to store cached data of that resource type. For example, the caching module includes P types of storage subspaces, each corresponding to a specific resource type, used to store data of that resource type. In other words, the memory resource type of the corresponding cached data can be determined based on the resource type identifier and / or address space attribute.

[0074] Furthermore, cached data of different memory access resource types differ in data organization and business access attributes, resulting in each memory access resource type corresponding to its own mainstream and typical memory access mode. Therefore, memory access resource type can serve as the basis for determining the memory access mode of a cache module.

[0075] In some optional embodiments, the first memory access resource type or the second memory access resource type includes at least a portion of streaming linear buffer type, control type, scalar type, tensor type, index type, and instruction type; wherein, the cached data corresponding to the streaming linear buffer type is usually arranged contiguously and consumed in a pipelined manner, therefore, its mainstream and typical memory access mode is the contiguous memory access mode; the cached data corresponding to the tensor type includes matrix data, tensor data, etc., which are usually involved in operations such as convolution, therefore, its mainstream and typical memory access mode is the strafing memory access mode; the cached data corresponding to the scalar type... The cached data for index types typically consists of single-variable, small-granularity, independent data that may be accessed centrally. Therefore, its mainstream and typical memory access mode is the clustered memory access mode. The cached data for index types usually involves jump addressing, discrete mapping, and other processing types. Therefore, its mainstream and typical memory access mode is the random memory access mode. The cached data for control types typically consists of configuration parameters and global parameters that may be accessed centrally. Therefore, its mainstream and typical memory access mode is the clustered memory access mode. The cached data for instruction types typically includes sequentially arranged instructions. Therefore, its mainstream and typical memory access mode is the contiguous memory access mode.

[0076] In some optional embodiments, the memory access attribute information includes at least one of the following: historical memory access address information, a first memory access resource type, and a second memory access resource type. Accordingly, determining whether the cache module meets any target memory access condition based on the memory access attribute information includes: when the memory access attribute information includes historical memory access address information, determining a historical memory access pattern based on the historical memory access address information, predicting a first predicted memory access pattern based on the historical memory access pattern, and determining that the cache module meets the target memory access condition if the first predicted memory access pattern is the same as any target memory access pattern; when the memory access attribute information includes a first memory access resource type or a second memory access resource type, predicting a second predicted memory access pattern based on the first memory access resource type or the second memory access resource type, and determining that the cache module meets the target memory access condition if the second predicted memory access pattern is the same as any target memory access pattern; when the memory access attribute information includes a first memory access resource type and a second memory access resource type, predicting a third predicted memory access pattern based on the second memory access resource type, and determining that the cache module meets the target memory access condition if the third predicted memory access pattern is the same as any target memory access pattern.

[0077] For example, if the memory access attribute information only includes historical memory access address information, the distribution of historical memory access addresses can be analyzed based on the historical memory access address information to determine the historical memory access pattern. Considering the characteristic that memory access behavior has a certain degree of continuity, the first predicted memory access pattern is likely to be the same as the memory access pattern that the cache module is about to execute. Therefore, the historical memory access pattern is used as the first predicted memory access pattern. Based on this, if the first predicted memory access pattern is the same as any target memory access pattern, it is determined that the cache module meets the target memory access condition, and the target memory access pattern corresponding to the target memory access condition is the first predicted memory access pattern. If the first predicted memory access pattern is different from all target memory access patterns, it is determined that the cache module does not meet the target memory access condition.

[0078] For example, if the memory access attribute information includes a first memory access resource type or a second memory access resource type, a second predicted memory access mode can be predicted based on the first memory access resource type or the second memory access resource type. If the second predicted memory access mode is the same as a certain target memory access mode, it can be determined that the cache module meets the target memory access condition, and the target memory access mode corresponding to the target memory access condition is the second predicted memory access mode. If the second predicted memory access mode is different from all target memory access modes, it can be determined that the cache module does not meet the target memory access condition.

[0079] For example, assuming that the target memory access modes are predetermined to include three types, namely mode1, mode2, and mode3, if the second predicted memory access mode determined according to the first or second memory access resource type is mode4, then it can be determined that the second predicted memory access mode is different from any of the target memory access modes, and therefore it can be confirmed that the cache module does not meet the target memory access conditions. Furthermore, if the determined second predicted memory access mode is mode2, then it can be determined that the second predicted memory access mode mode2 is the same as mode2 in the target memory access mode, and therefore it can be confirmed that the cache module meets the target memory access conditions.

[0080] For example, if the memory access attribute information includes a first memory access resource type and a second memory access resource type, then considering that the second memory access resource type is more reflective of the memory access behavior that the cache module is currently performing compared to the first memory access resource type, a third predicted memory access mode can be determined based on the second memory access resource type. If the third predicted memory access mode is the same as any target memory access mode, then it is determined that the cache module meets the target memory access condition, and the target memory access mode corresponding to the target memory access condition is the third predicted memory access mode. If the third predicted memory access mode is different from all target memory access modes, then it is determined that the cache module does not meet the target memory access condition.

[0081] Therefore, the embodiments of this disclosure can set differentiated memory access mode prediction and matching logic according to different composition forms of memory access attribute information: for scenarios that only contain historical memory access address information, the memory access mode that the cache module will execute can be deduced and predicted through historical memory access behavior; for scenarios that contain a single type of memory access resource, the memory access mode that the cache module will execute can be deduced and predicted through resource type mapping; for scenarios that contain two types of memory access resource, the memory access mode that the cache module will execute can be deduced and predicted based on the second type of resource. On this basis, by comparing the predicted memory access mode with the target memory access mode, it can be determined whether the cache module meets the target memory access conditions.

[0082] In some optional embodiments, determining whether a cache module meets any target memory access condition based on memory access attribute information further includes: when the memory access attribute information includes historical memory access address information and a first memory access resource type, fusing a first predicted memory access mode corresponding to the historical memory access address information and a second predicted memory access mode corresponding to the first memory access resource type to obtain a first fused predicted memory access mode; if the first fused predicted memory access mode is the same as any target memory access mode, determining that the cache module meets the target memory access condition; when the memory access attribute information includes historical memory access address information and a second memory access resource type, fusing the first predicted memory access mode corresponding to the historical memory access address information and the second predicted memory access mode corresponding to the first memory access resource type to obtain a first fused predicted memory access mode; and if the first fused predicted memory access mode is the same as any target memory access mode, determining that the cache module meets the target memory access condition; and if the memory access attribute information includes historical memory access address information and a second memory access resource type, fusing the first predicted memory access mode corresponding to the historical memory access address information and the second predicted memory access mode corresponding to the first memory access resource type to obtain a first fused predicted memory access mode. The second predicted memory access mode corresponding to the memory access resource type is fused to obtain a second fused predicted memory access mode. If the second fused predicted memory access mode is the same as any target memory access mode, it is determined that the cache module meets the target memory access condition. If the memory access attribute information includes historical memory access address information, the first memory access resource type and the second memory access resource type, the first fused predicted memory access mode corresponding to the first predicted memory access mode and the first memory access resource type and the second predicted memory access mode corresponding to the second memory access resource type are fused to obtain a third fused predicted memory access mode. If the third fused predicted memory access mode is the same as any target memory access mode, it is determined that the cache module meets the target memory access condition.

[0083] For example, if the memory access attribute information includes historical memory access address information and a first memory access resource type, the distribution of historical memory access addresses can be analyzed based on the historical memory access address information to determine the historical memory access pattern, and this historical memory access pattern can be used as the first predicted memory access pattern. Simultaneously, a second predicted memory access pattern can be determined based on the first memory access resource type. The first and second predicted memory access patterns are then used together to make a prediction, thereby determining a more comprehensive, accurate, and complete first fused predicted memory access pattern. Considering the coherent nature of memory access behavior, this first fused predicted memory access pattern is highly likely to be the same as the memory access pattern that the cache module is about to execute. Based on this, if the first fused predicted memory access pattern is the same as any target memory access pattern, it is determined that the cache module meets the target memory access condition, and the target memory access pattern corresponding to this target memory access condition is the first fused predicted memory access pattern. If the first fused predicted memory access pattern is different from all target memory access patterns, it is determined that the cache module does not meet the target memory access condition.

[0084] When determining the first converged predicted memory access mode based on the first predicted memory access mode corresponding to the historical memory access address information and the second predicted memory access mode corresponding to the first memory access resource type, two situations may arise: In the first case, the first predicted memory access mode and the second predicted memory access mode are the same, in which case either the first predicted memory access mode or the second predicted memory access mode can be directly used as the first converged predicted memory access mode; In the second case, the first predicted memory access mode and the second predicted memory access mode are different. Considering that the first predicted memory access mode actually reflects the historical memory access mode, its accuracy is relatively higher than that of the second predicted memory access mode. Therefore, the first predicted memory access mode can be used as the first converged predicted memory access mode.

[0085] For example, if the memory access attribute information includes historical memory access address information and a second memory access resource type, the distribution of historical memory access addresses can be analyzed based on the historical memory access address information to determine the historical memory access pattern. This historical memory access pattern is then used as the first predicted memory access pattern. Simultaneously, a second predicted memory access pattern can be determined based on the second memory access resource type. The first and second predicted memory access patterns are then used together to make a prediction, thereby determining a more comprehensive, accurate, and complete second fused predicted memory access pattern. This second fused predicted memory access pattern is then used as the memory access pattern that the cache module will execute. Based on this, if the second fused predicted memory access pattern is the same as any target memory access pattern, the cache module is determined to meet the target memory access condition, and the target memory access pattern corresponding to this target memory access condition is the second fused predicted memory pattern. If the second fused predicted memory access pattern is different from all target memory access patterns, the cache module is determined not to meet the target memory access condition.

[0086] When jointly predicting and determining the second fused memory access mode based on the first predicted memory access mode corresponding to the historical memory access address information and the second predicted memory access mode corresponding to the second memory access resource type, two situations may arise: In the first case, the first predicted memory access mode and the second predicted memory access mode are the same, in which case either the first predicted memory access mode or the second predicted memory access mode can be directly used as the second fused memory access mode; In the second case, the first predicted memory access mode and the second predicted memory access mode are different. Considering that the first predicted memory access mode reflects the historical memory access mode, while the second predicted memory access mode is more able to reflect the memory access behavior that the cache module is currently going to perform, the accuracy of the second predicted memory access mode may be relatively higher. Therefore, the second predicted memory access mode can be used as the second fused memory access mode.

[0087] Furthermore, for cases where the first predicted memory access mode and the second predicted memory access mode are different, historical first memory access parameters such as the first spatial span, first access interval, and first access frequency of the historical memory access address can be determined based on historical memory access address information. Predictive second memory access parameters such as the second spatial span, second access interval, and second access frequency can be predicted based on the second memory access resource type and / or the second predicted memory access mode. Then, based on the first and second memory access parameters, fused memory access parameters are determined using methods such as weighted fusion. For example, the fused spatial span is determined based on the first and second spatial spans, the fused access interval is determined based on the first and second access intervals, and the fused access frequency is determined based on the first and second access frequencies. Finally, the memory access mode matching the aforementioned fused memory access parameters is inferred as the second fused predicted memory access mode. The weighting coefficients used in the weighted fusion can be determined based on experience, statistical data, and simulation data, and this embodiment does not impose any limitations on this.

[0088] For example, if the memory access attribute information includes historical memory access address information, a first memory access resource type, and a second memory access resource type, then a first fusion predicted memory access mode can be determined first based on the historical memory access address information and the first memory access resource type. At the same time, a corresponding second predicted memory access mode can be determined based on the second memory access resource type. On this basis, a third fusion predicted memory access mode can be determined by jointly predicting based on the first fusion predicted memory access mode and the second predicted memory access mode. If the third fusion predicted memory access mode is the same as any target memory access mode, then it is determined that the cache module meets the target memory access condition, and the target memory access mode corresponding to the target memory access condition is the third fusion predicted memory access mode. If the third fusion predicted memory access mode is different from all target memory access modes, then it is determined that the cache module does not meet the target memory access condition.

[0089] When determining the third fusion predictive memory access mode based on the first fusion predictive memory access mode and the second predictive memory access mode corresponding to the second memory access resource type, two situations may arise: In the first case, the first fusion predictive memory access mode and the second predictive memory access mode are the same, in which case either the first fusion predictive memory access mode or the second predictive memory access mode can be directly used as the third fusion predictive memory access mode; In the second case, the first fusion predictive memory access mode and the second predictive memory access mode are different. Considering that the first fusion predictive memory access mode reflects the historical memory access mode, while the second predictive memory access mode is more able to reflect the memory access behavior that the cache module is currently going to perform, the accuracy of the second predictive memory access mode may be relatively higher. Therefore, the second predictive memory access mode can be used as the third fusion predictive memory access mode.

[0090] Furthermore, in cases where the first fusion prediction memory access mode and the second prediction memory access mode are different, historical first memory access parameters such as the first spatial span, first access interval, and first access frequency of the historical memory access address can be determined based on historical memory access address information. Historical third memory access parameters such as the third spatial span, third access interval, and third access frequency of the historical memory access address can be determined based on the first memory access resource type. Predictive second memory access parameters such as the second spatial span, second access interval, and second access frequency can be predicted based on the second memory access resource type and / or the second prediction memory access mode. Based on the first, second, and third memory access parameters, fusion memory access parameters can be determined using methods such as weighted fusion. For example, the fusion spatial span can be determined based on the first, third, and second spatial spans; the fusion access interval can be determined based on the first, third, and second access intervals; and the fusion access frequency can be determined based on the first, third, and second access frequencies. Then, the memory access mode that matches the aforementioned fusion memory access parameters can be inferred as the third fusion prediction memory access mode.

[0091] It should be noted that the above examples of memory access attribute information are merely illustrative. Similarly, determining whether a cache module meets the target memory access conditions based on memory access attribute information is also an illustrative example, and this disclosure does not impose any limitations on it.

[0092] Therefore, it can be seen that there are multiple combinations of obtainable memory access attribute information. For each combination, it is possible to accurately determine whether the cache module meets any target memory access condition based on the memory access attribute information. In this way, memory access detection of the cache module can be performed for various application scenarios, effectively expanding the application scope of the memory access control method of this disclosure embodiment.

[0093] In some optional embodiments, the first memory access resource type or the second memory access resource type includes at least a portion of streaming linear buffer type, control type, scalar type, tensor type, index type, and instruction type; accordingly, predicting a second predicted memory access mode based on the first memory access resource type or the second memory access resource type includes: determining the second predicted memory access mode as a continuous memory access mode when the first memory access resource type corresponds to a streaming linear buffer type or an instruction type, or when the second memory access resource type corresponds to a streaming linear buffer type or an instruction type; determining the second predicted memory access mode as a clustered memory access mode when the first memory access resource type corresponds to a control type or a scalar type, or when the second memory access resource type corresponds to a control type or a scalar type; determining the second predicted memory access mode as a strafing memory access mode when the first memory access resource type or the second memory access resource type corresponds to a tensor type; and determining the second predicted memory access mode as a random memory access mode when the first memory access resource type or the second memory access resource type corresponds to an index type.

[0094] Therefore, for each type of memory access resource, there exists a corresponding most common and typical memory access pattern. Thus, this prior information can be fully utilized as the basis for determining the second predicted memory access pattern. When the first or second memory access resource type is clearly defined, the most likely memory access pattern can be quickly and efficiently determined and used as the second predicted memory access pattern.

[0095] In some optional embodiments, the first sub-block information encoding and the second sub-block information encoding can respectively reflect the number of the first target sub-block and the second target sub-block. The cached data in the first target sub-block and the second target sub-block is the cache filling data.

[0096] For example, the second sub-block information is encoded as "00", which indicates that the number of the second target sub-block is 1; for example, when the first sub-block information is encoded as "01", it indicates that the number of the first target sub-block is 2; for example, when the first sub-block information is encoded as "10", it indicates that the number of the first target sub-block is 3; for example, when the first sub-block information is encoded as "11", it indicates that the number of the first target sub-block is 4.

[0097] In some optional embodiments, the first sub-block information encoding and the second sub-block information encoding can respectively reflect the number and position of the first target sub-block and the second target sub-block.

[0098] For example, the information encoding of the first sub-block can be in the form of a mask.

[0099] For example, when the second sub-block information is encoded as "0001", it is used to represent the fourth sub-block in the cache line corresponding to the second target sub-block; for example, when the first sub-block information is encoded as "0011", it is used to represent the third and fourth sub-blocks in the cache line corresponding to the first target sub-block; for example, when the first sub-block information is encoded as "0111", it is used to represent the second to fourth sub-blocks in the cache line corresponding to the first target sub-block.

[0100] In some optional embodiments, determining the first sub-block information code corresponding to the satisfied target memory access condition includes: determining the number of target sub-blocks and / or the location of target sub-blocks based on the satisfied target memory access condition; and determining the first sub-block information code based on the number of target sub-blocks and / or the location of target sub-blocks.

[0101] For example, based on the target memory access mode corresponding to the target memory access conditions, it can predict which addresses the subsequent memory access requests may access, determine the number and / or location of the sub-blocks corresponding to these addresses, thereby obtaining the target number and / or target sub-block location, and then encode the target number and / or target sub-block location according to a pre-set encoding method to obtain the first sub-block information encoding.

[0102] In some optional embodiments, conditional encoding mapping information can be pre-set, which is a mapping table between target memory access conditions and first sub-block information codes, including each target memory access condition and its corresponding first sub-block information code; based on this, after determining the target memory access conditions that are met, the corresponding first sub-block information code can be determined according to the conditional encoding mapping information.

[0103] It should be noted that using encoding instead of directly transmitting information such as the number and location of target sub-blocks allows for the standardized and unified expression of this information. Furthermore, a reasonable encoding method can enable the encoding of the first and second sub-blocks to carry more information. Additionally, when determining the number of encoding bits, several redundant bits can be reserved. This allows for the use of these redundant bits in encoding when new or modified requirements arise, effectively improving overall maintainability and scalability.

[0104] In some optional embodiments, the target memory access conditions include a first target memory access condition where the memory access behavior conforms to a continuous memory access pattern and a second target memory access condition where the memory access behavior conforms to a stepping memory access pattern; accordingly, determining the target sub-block quantity and / or target sub-block location based on the satisfied target memory access conditions includes: if the first target memory access condition is satisfied, determining the first target sub-block quantity and / or first target sub-block location, wherein the first target sub-block quantity is greater than one and the first target sub-block location represents multiple consecutive sub-block locations; if the second target memory access condition is satisfied, determining the second target sub-block quantity and / or second target sub-block location, wherein the second target sub-block quantity is greater than one and the second target sub-block location represents multiple sub-block locations with intervals.

[0105] For example, assuming that the first sub-block information encoding corresponding to the first target memory access condition represents the number of first target sub-blocks as q1 (q1≥2), then if the memory access request hits the r1th sub-block in the cache line when the first target memory access condition is met, then the r1th sub-block to the r1+q1-1th sub-blocks can be identified as the first target sub-blocks, where the r1th sub-block is the first sub-block, and the r1+1th sub-block to the r1+q1-1th sub-blocks are the second sub-blocks.

[0106] For example, suppose that the first sub-block information encoding corresponding to the second target memory access condition represents the number of the first target sub-blocks as q2 (q2≥2), and the corresponding step size is w (w≥1). Then, if the memory access request hits the r2th sub-block in the cache line when the second target memory access condition is met, the r2th sub-block and the r2+w+1th to r2+w+q2th sub-blocks can be identified as the first target sub-blocks. Among them, the r2th sub-block is the first sub-block, and the r2+w+1th to r2+w+q2th sub-blocks are the second sub-blocks.

[0107] It should be noted that the above description of the number and position of the first target sub-blocks is merely illustrative and is not intended to limit the scope of this disclosure.

[0108] Therefore, in this embodiment of the present disclosure, personalized first sub-block information encoding can be set for different target memory access conditions, thereby effectively improving the accuracy of control and thus effectively improving the hit rate.

[0109] Figure 2 This is a schematic diagram of another memory access control method provided in an embodiment of this disclosure. (Refer to...) Figure 2 A control module is added upstream of the cache module, so that the address calculation module, control module and cache module are connected in sequence. The control module can obtain memory access context information from the address calculation module, and based on this, determine whether the cache module meets the target memory access conditions, and then determine the encoding of the sub-block information to be sent to the cache module.

[0110] In some optional embodiments, the control module can determine whether the current situation is likely to involve multiple short-term accesses to different sub-blocks of the same cache line, or other memory access scenarios with good locality, based on the target memory access conditions. The information used to make this determination may come from the memory address information of the previous one or several accesses, or from the type of memory resource being accessed, etc., and this disclosure does not limit this. Figure 2 As shown, the aforementioned information can originate from the memory access context information obtained by the control module from the address calculation module. The control module can determine the sub-block information encoding and send the address and sub-block information encoding to the cache module.

[0111] Furthermore, when the control module determines that the cache module does not meet the target memory access conditions, it can determine the current sub-block information encoding as the second sub-block information encoding based on the default configuration information, and send the second sub-block information encoding to the cache module to control the cache module's memory access operation. When the control module determines that the cache module meets a certain target memory access condition, it can generate or obtain the first sub-block information encoding that matches the target memory access condition. The first sub-block information encoding is used to represent the number and / or position of sub-blocks in the cache line that the lower-level cache unit needs to return to the upper-level cache unit. The first sub-block information encoding is then sent to the cache module to control its memory access operation.

[0112] like Figure 2 As shown, the caching module includes L1 cache unit, L2 cache unit, ..., LN cache unit. If the memory access request misses the L1 cache unit, the first sub-block information encoding will be sent to the L2 cache unit along with the inter-caching transaction request. The processing unit in the L2 cache unit can decode the first sub-block information encoding according to the agreed decoding method, determine the number and / or position of the first target sub-block to be returned, and return the cached data in the corresponding first target sub-block of the specified cache line based on this. Similarly, if the L2 cache unit also misses the cache, the L3 cache unit can return the cached data in a similar way, which will not be described in detail here.

[0113] In summary, the embodiments of this disclosure can flexibly configure the number and / or position of sub-blocks to be returned by sub-block information encoding (such as first sub-block information encoding and second sub-block information encoding), thereby improving the bandwidth utilization between cache levels based on sub-block transmission technology and reducing the miss rate in scenarios with good locality, thus improving memory access efficiency.

[0114] It should be noted that the reason for placing the control module upstream of the cache module is mainly because more comprehensive and richer memory access context information can be obtained upstream of the cache module. This allows for a more accurate determination of whether the cache module meets the target memory access conditions, and enables timely adjustment of the sub-block information encoding to match the current memory access behavior. This effectively balances bandwidth utilization efficiency and memory hit rate between cache levels.

[0115] Secondly, embodiments of this disclosure provide a caching method.

[0116] Figure 3 A flowchart illustrating a caching method provided in an embodiment of this disclosure. (Refer to...) Figure 3 The caching method may include the following steps:

[0117] Step S31: Receive the first sub-block information encoding and memory access request;

[0118] Step S32: Determine the target cache unit hit by the memory access request;

[0119] Step S33: Decode the encoded information of the first sub-block to obtain the information of the first target sub-block;

[0120] Step S34: Based on the information of the first target sub-block, determine the cache filling data in the target cache unit;

[0121] Step S35: Fill the cache with the cache filling data back into the cache unit above the target cache unit;

[0122] The first sub-block information is encoded by the control module of the cache module when the cache module meets the target memory access conditions. The target memory access conditions are used to characterize whether the memory access behavior of the cache module conforms to the preset target memory access mode. The first target sub-block includes the first sub-block indicated by the memory access request and at least one second sub-block that is adjacent to the first sub-block based on the target memory access conditions met by the cache module.

[0123] For details on how to detect whether the cache module meets the target memory access conditions, and how to determine the corresponding sub-block information encoding for different situations, please refer to the memory access control method in the embodiments of this disclosure, which will not be described in detail here.

[0124] In some alternative embodiments, the caching module includes multiple levels of caching units, each caching unit including multiple cache lines, and each cache line including multiple sub-blocks.

[0125] In some optional embodiments, decoding the encoding of the first sub-block information to obtain the information of the first target sub-block includes: decoding the encoding of the first sub-block information according to a preset decoding method to obtain the information of the first target sub-block; wherein, the information of the first target sub-block includes the number of target sub-blocks and / or the position of target sub-blocks, specifically corresponding to the number of first target sub-blocks and / or the position of the first target sub-blocks.

[0126] In some optional embodiments, if the cache module receives the second sub-block information encoding, it can also decode the second sub-block information encoding to obtain the information of the second target sub-block, specifically the number of the second target sub-blocks and / or the position of the second target sub-blocks.

[0127] Therefore, the caching module can correctly decode the sub-block information encoding, thereby determining the information of the corresponding target sub-block based on the decoding result. Then, it can determine the cache filling data based on the information of the target sub-block, and fill the cache filling data back into the higher-level cache unit located above the target cache unit. The target cache unit is the cache unit hit by the memory access request.

[0128] In some optional embodiments, the caching module includes L1 cache unit, L2 cache unit, ..., LN cache unit, where N > 1. If the caching module meets the target memory access condition, and the memory access request does not hit the L1 cache unit, the L1 cache unit will send the inter-caching level transaction request and the first sub-block information encoding together to the L2 cache unit. After receiving the inter-caching level transaction request, if the L2 cache unit determines that it has hit the target memory access, it can decode the first sub-block information encoding according to the preset processing unit therein, determine the number and / or position of the first target sub-block according to the decoding result, and then fill the cache data of the first target sub-block back into the L1 cache unit. Each level of the cache unit can be equipped with a preset processing unit, which can perform decoding processing. The preset processing unit can be a newly added functional unit, or it can be implemented by adding corresponding processing logic (such as decoding logic) to the original controller of the cache unit. This disclosure embodiment does not limit this.

[0129] In summary, in this embodiment of the present disclosure, the cache module can receive sub-block information encoding (such as first sub-block information encoding and second sub-block information encoding), and dynamically adjust the number, position and other information of sub-blocks returned by the lower-level cache unit to the upper-level cache unit according to the sub-block information encoding. This enables it to adaptively match appropriate cache backfilling methods for different memory access modes, taking into account both bandwidth utilization efficiency and memory hit rate between cache levels.

[0130] It is understood that the various method embodiments mentioned above in this disclosure can be combined with each other to form combined embodiments without violating the principle and logic. Due to space limitations, this disclosure will not elaborate further. Those skilled in the art will understand that in the above methods of specific implementation, the specific execution order of each step should be determined by its function and possible internal logic.

[0131] In addition, this disclosure also provides memory access control devices, caching devices, data processing devices, electronic devices, and computer-readable storage media, all of which can be used to implement any of the caching methods or caching approaches provided in this disclosure. The corresponding technical solutions and descriptions are described in the relevant sections of the method section and will not be repeated here.

[0132] Thirdly, embodiments of this disclosure provide a memory access control device.

[0133] Figure 4 This is a block diagram of a memory access control device provided in an embodiment of the present disclosure.

[0134] Reference Figure 4 This disclosure provides a memory access control device for controlling a cache module. The cache module includes multiple levels of cache units, each cache unit includes multiple cache lines, and each cache line includes multiple sub-blocks. The memory access control device 400 includes:

[0135] The judgment module 401 is used to determine whether the cache module meets the preset target memory access conditions. The target memory access conditions are used to characterize whether the memory access behavior of the cache module conforms to the preset target memory access mode.

[0136] The first determining module 402 is used to determine the first sub-block information encoding corresponding to the satisfied target memory access condition in response to the cache module satisfying any target memory access condition.

[0137] The sending module 403 is used to send the first sub-block information encoding and the received memory access request to the cache module, so as to control the cache module to perform the memory access operation corresponding to the memory access request based on the first sub-block information encoding;

[0138] The first sub-block information encoding is used to characterize the information of the first target sub-block that the target cache unit hit by the memory access request fills back to the cache unit at the next higher level. The first target sub-block includes the first sub-block indicated by the memory access request and at least one second sub-block that is adjacent to the first sub-block based on the target memory access conditions.

[0139] In this embodiment of the disclosure, by setting a control module for controlling the cache module, it is possible to determine whether the cache module meets the preset target memory access conditions. When it is determined that the cache module meets any target memory access condition, the first sub-block information code corresponding to the target memory access condition is determined and sent to the cache module along with the memory access request. This allows the cache module to determine the first target sub-block based on the first sub-block information code and backfill the data in it to the upper-level cache unit of the hit target cache unit. Since the first target sub-block includes not only the first sub-block indicated by the memory access request itself, but also at least one second sub-block that is adjacent to the first sub-block and predicted according to the target memory access conditions, the probability of subsequent memory access requests corresponding to the second sub-block is high. Therefore, the subsequent hit rate can be improved. At the same time, the number of sub-block transmissions between different levels of cache units can be reduced, the bandwidth consumption between different levels of cache units can be reduced, and the utilization efficiency of cached data can be increased. In other words, the embodiments of this disclosure can dynamically adjust the number, position, and other contents of the sub-blocks returned by the lower-level cache unit to the upper-level cache unit through the encoding of the first sub-block information, thereby enabling adaptive matching of appropriate cache backfilling methods for different memory access modes, taking into account both bandwidth utilization efficiency and memory hit rate between cache levels.

[0140] Fourthly, embodiments of this disclosure provide a caching device.

[0141] Figure 5 This is a block diagram of a caching device provided in an embodiment of the present disclosure.

[0142] Reference Figure 5 This disclosure provides a caching device 500, which includes:

[0143] The receiving module 501 is used to receive the first sub-block information encoding and memory access request;

[0144] Hit module 502 is used to determine the target cache unit hit by the memory access request;

[0145] Decoding module 503 is used to decode the information encoding of the first sub-block to obtain the information of the first target sub-block;

[0146] The second determining module 504 is used to determine the cache filling data in the target cache unit based on the information of the first target sub-block;

[0147] The filling module 505 is used to fill cached data back into the upper-level cache unit of the target cache unit;

[0148] The sub-block information encoding includes the first sub-block information encoding when the cache module meets the target memory access conditions or the second sub-block information encoding when the cache module does not meet the target memory access conditions. The target memory access conditions are used to characterize whether the memory access behavior of the cache module conforms to the preset target memory access mode.

[0149] In this embodiment of the disclosure, the cache module can receive sub-block information encoding (such as first sub-block information encoding and second sub-block information encoding), and dynamically adjust the number, position and other information of sub-blocks returned by the lower-level cache unit to the upper-level cache unit according to the sub-block information encoding, so as to adaptively match the appropriate cache backfilling method for different memory access modes, taking into account the bandwidth utilization efficiency and memory access hit rate between cache levels.

[0150] Fifthly, embodiments of this disclosure provide a data processing device.

[0151] Figure 6 This is a block diagram of a data processing device provided in an embodiment of the present disclosure.

[0152] Reference Figure 6 This disclosure provides a data processing device 600, which includes at least one processing unit 610, at least one memory access control device 620, and at least one cache device 630.

[0153] The processing unit 610 is used to perform data processing corresponding to the target task, the memory access control device 620 adopts the memory access control device described in any one of the embodiments of this disclosure, and the cache device 630 adopts the cache device described in any one of the embodiments of this disclosure.

[0154] In this embodiment, the memory access control module can detect whether the cache module meets the target cache conditions, adjust the sub-block information encoding, and send it to the cache module. The cache module can receive the sub-block information encoding and dynamically adjust the number, position, and other information of the sub-blocks returned by the lower-level cache unit to the upper-level cache unit according to the sub-block information encoding. Based on this, it can adaptively match the appropriate cache backfill method for different memory access modes, taking into account both the bandwidth utilization efficiency and memory hit rate between cache levels.

[0155] Each module in the aforementioned memory access control device, cache device, and data processing device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in the computer device in hardware form, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0156] Figure 7 This is a block diagram of an electronic device provided in an embodiment of the present disclosure.

[0157] Reference Figure 7 This disclosure provides an electronic device, which includes: at least one processor 701, at least one memory 702, and one or more I / O interfaces 703; wherein the memory 702 stores one or more computer programs that can be executed by at least one processor 701, and the one or more computer programs are executed by at least one processor 701 to enable at least one processor 701 to perform the memory access control method described above.

[0158] Figure 8 A block diagram of another electronic device provided in an embodiment of this disclosure.

[0159] Reference Figure 8 This disclosure provides another electronic device, which includes a plurality of processing cores 801 and an on-chip network 802, wherein the plurality of processing cores 801 are all connected to the on-chip network 802, and the on-chip network 802 is used to interact with data between the plurality of processing cores and external data.

[0160] One or more processing cores 801 store one or more instructions, and the one or more instructions are executed by one or more processing cores 801 to enable one or more processing cores 801 to execute the memory access control method described above.

[0161] The modules in the aforementioned electronic devices can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0162] This disclosure also provides a computer-readable storage medium storing a computer program thereon, wherein the computer program, when executed by a processor, implements the memory access control method described above. The computer-readable storage medium may be volatile or non-volatile.

[0163] This disclosure also provides a computer program product including computer-readable code. When the computer-readable code is run in a processor of an electronic device, the processor in the electronic device executes the memory access control method described above. Those skilled in the art will understand that all or some steps, systems, or devices disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be executed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software can be distributed on a computer-readable storage medium, which may include computer storage media (or non-transitory media) and communication media (or transient media).

[0164] As is known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable program instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), static random access memory (SRAM), flash memory or other memory technologies, portable compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, it is known to those skilled in the art that communication media typically contain computer-readable program instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0165] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0166] Computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing state information from the computer-readable program instructions to implement various aspects of this disclosure.

[0167] The computer program product described herein can be implemented specifically through hardware, software, or a combination thereof. In one alternative embodiment, the computer program product is specifically embodied in a computer storage medium; in another alternative embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0168] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0169] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0170] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0171] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0172] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A memory access control method, characterized in that, An application to a control module for controlling a cache module, the cache module comprising multiple levels of cache units, each cache unit comprising multiple cache lines, and each cache line comprising multiple sub-blocks, the method comprising: Determine whether the cache module meets the preset target memory access conditions. The target memory access conditions are used to characterize whether the memory access behavior of the cache module conforms to the preset target memory access mode. In response to the cache module satisfying any of the target memory access conditions, a first sub-block information encoding corresponding to the satisfied target memory access condition is determined; The first sub-block information encoding and the received memory access request are sent to the cache module to control the cache module to execute the memory access operation corresponding to the memory access request based on the first sub-block information encoding; The first sub-block information encoding is used to characterize the information of the first target sub-block that the target cache unit hit by the memory access request fills back to the cache unit at the next higher level. The first target sub-block includes the first sub-block indicated by the memory access request and at least one second sub-block that is adjacent to the first sub-block based on the target memory access conditions.

2. The method according to claim 1, characterized in that, After encoding the first sub-block information and sending the received memory access request to the cache module, the method further includes: In response to the detection that the cache module does not meet the target memory access condition, the second sub-block information encoding and the received memory access request are sent to the cache module to control the cache module to perform the memory access operation corresponding to the memory access request based on the second sub-block information encoding; The second sub-block information encoding is used to characterize the information of the second target sub-block that the target cache unit hit by the memory access request fills back to the cache unit at the next higher level. The second target sub-block includes the sub-block indicated by the memory access request.

3. The method according to claim 1 or 2, characterized in that, The step of determining whether the cache module meets the preset target memory access conditions includes: Obtain the memory access context information of the cache module; Determine memory access attribute information based on the memory access context information; Based on the memory access attribute information, determine whether the cache module meets any of the target memory access conditions.

4. The method according to claim 3, characterized in that, The memory access context information includes the historical memory access records of the cache module and / or the memory access request information received by the cache module and pending processing. The memory access request information includes the resource type identifier and / or address space attribute of the memory access request. The memory access attribute information includes at least one of the following: historical memory access address information, a first memory access resource type, and a second memory access resource type. The step of determining the memory access attribute information based on the memory access context information includes at least one of the following: Based on the historical memory access records of the cache module, the historical memory access address information is obtained; Based on the historical memory access records of the cache module, obtain the resource type identifier and / or address space attribute corresponding to the historical memory access request; based on the resource type identifier and / or address space attribute corresponding to the historical memory access request, determine the first memory access resource type corresponding to the historical memory access request, wherein the address space attribute is used to indicate the memory access resource type of the cached data in the memory access address corresponding to the memory access request; Based on the resource type identifier and / or address space attribute corresponding to the received, pending memory access request, determine the second memory access resource type corresponding to the pending memory access request.

5. The method according to claim 3, characterized in that, The memory access attribute information includes at least one of the following: historical memory access address information, first memory access resource type, and second memory access resource type; The step of determining whether the cache module meets any of the target memory access conditions based on the memory access attribute information includes: When the memory access attribute information includes the historical memory access address information, the historical memory access mode is determined according to the historical memory access address information, and a first predicted memory access mode is predicted based on the historical memory access mode. When the first predicted memory access mode is the same as any of the target memory access modes, it is determined that the cache module satisfies the target memory access condition. When the memory access attribute information includes the first memory access resource type or the second memory access resource type, a second predicted memory access mode is predicted based on the first memory access resource type or the second memory access resource type. When the second predicted memory access mode is the same as any of the target memory access modes, it is determined that the cache module satisfies the target memory access condition. When the memory access attribute information includes the first memory access resource type and the second memory access resource type, a third predicted memory access mode is predicted based on the second memory access resource type. If the third predicted memory access mode is the same as any of the target memory access modes, it is determined that the cache module satisfies the target memory access condition.

6. The method according to claim 5, characterized in that, The step of determining whether the cache module meets any of the target memory access conditions based on the memory access attribute information further includes: When the memory access attribute information includes the historical memory access address information and the first memory access resource type, the first predicted memory access mode corresponding to the historical memory access address information and the second predicted memory access mode corresponding to the first memory access resource type are fused to obtain a first fused predicted memory access mode. When the first fused predicted memory access mode is the same as any of the target memory access modes, it is determined that the cache module satisfies the target memory access condition. When the memory access attribute information includes the historical memory access address information and the second memory access resource type, the first predicted memory access mode corresponding to the historical memory access address information and the second predicted memory access mode corresponding to the second memory access resource type are fused to obtain a second fused predicted memory access mode. When the second fused predicted memory access mode is the same as any of the target memory access modes, it is determined that the cache module satisfies the target memory access condition. When the memory access attribute information includes the historical memory access address information, the first memory access resource type, and the second memory access resource type, the first fused memory access mode corresponding to the first predicted memory access mode and the first memory access resource type, and the second predicted memory access mode corresponding to the second memory access resource type are fused to obtain a third fused memory access mode. If the third fused memory access mode is the same as any of the target memory access modes, it is determined that the cache module satisfies the target memory access condition.

7. The method according to claim 5, characterized in that, The first memory access resource type or the second memory access resource type includes at least a portion of streaming linear buffer type, control type, scalar type, tensor type, index type, and instruction type; The step of predicting the second memory access pattern based on the first memory access resource type or the second memory access resource type includes: If the first memory access resource type corresponds to the streaming linear buffer type or the instruction type, or if the second memory access resource type corresponds to the streaming linear buffer type or the instruction type, the second predicted memory access mode is determined to be a continuous memory access mode. If the first memory access resource type corresponds to the control type or the scalar type, or if the second memory access resource type corresponds to the control type or the scalar type, the second predicted memory access mode is determined to be the clustered memory access mode. When the first memory access resource type or the second memory access resource type corresponds to the tensor type, the second predicted memory access mode is determined to be the step memory access mode; If the first memory access resource type or the second memory access resource type corresponds to the index type, the second predicted memory access mode is determined to be a random memory access mode.

8. The method according to claim 1, characterized in that, The encoding of the first sub-block information corresponding to the determined and satisfied target memory access condition includes: Based on the target memory access conditions that are met, determine the number of target sub-blocks and / or the location of target sub-blocks; The first sub-block information encoding is determined based on the number of target sub-blocks and / or the location of the target sub-blocks.

9. The method according to claim 8, characterized in that, The target memory access conditions include a first target memory access condition where the memory access behavior conforms to the continuous memory access mode and a second target memory access condition where the memory access behavior conforms to the step memory access mode. The step of determining the number of target sub-blocks and / or the location of target sub-blocks based on the satisfied target memory access conditions includes: If the first target memory access condition is met, determine the number of first target sub-blocks and / or the location of the first target sub-blocks. The number of first target sub-blocks is greater than one, and the location of the first target sub-block represents multiple consecutive sub-block locations. If the second target memory access condition is met, determine the number of second target sub-blocks and / or the location of the second target sub-blocks. The number of second target sub-blocks is greater than one, and the location of the second target sub-blocks represents multiple sub-block locations with intervals.

10. The method according to claim 1, characterized in that, The target memory access mode includes at least one of continuous memory access mode and step memory access mode.

11. A caching method, characterized in that, include: Receive the first sub-block information encoding and memory access request; Determine the target cache unit hit by the memory access request; The information of the first sub-block is encoded and then decoded to obtain the information of the first target sub-block. Based on the information of the first target sub-block, determine the cache filling data in the target cache unit; The cache filling data is then backfilled into the upper-level cache unit of the target cache unit; The first sub-block information is encoded by the control module of the cache module when the cache module meets the target memory access conditions. The target memory access conditions are used to characterize whether the memory access behavior of the cache module conforms to the preset target memory access mode. The first target sub-block includes the first sub-block indicated by the memory access request and at least one second sub-block that is adjacent to the first sub-block based on the target memory access conditions met by the cache module.

12. The method according to claim 11, characterized in that, The step of decoding the encoded information of the first sub-block to obtain the information of the first target sub-block includes: The information of the first sub-block is decoded according to a preset decoding method to obtain the information of the first target sub-block. The information of the first target sub-block includes the number of target sub-blocks and / or the location of the target sub-blocks.

13. A memory access control device, characterized in that, For controlling a caching module, the caching module comprising multiple levels of caching units, each caching unit comprising multiple cache lines, each cache line comprising multiple sub-blocks, the device comprising: The judgment module is used to determine whether the cache module meets the preset target memory access conditions. The target memory access conditions are used to characterize whether the memory access behavior of the cache module conforms to the preset target memory access mode. The first determining module is configured to determine the first sub-block information encoding corresponding to the satisfied target memory access condition in response to the cache module satisfying any of the target memory access conditions. The sending module is used to send the first sub-block information encoding and the received memory access request to the cache module, so as to control the cache module to perform the memory access operation corresponding to the memory access request based on the first sub-block information encoding; The first sub-block information encoding is used to characterize the information of the first target sub-block that the target cache unit hit by the memory access request fills back to the cache unit at the next higher level. The first target sub-block includes the first sub-block indicated by the memory access request and at least one second sub-block that is adjacent to the first sub-block based on the target memory access conditions.

14. A buffer device, characterized in that, include: The receiving module is used to receive the first sub-block information encoding and memory access request; The hit module is used to determine the target cache unit hit by the memory access request; The decoding module is used to decode the information encoding of the first sub-block to obtain the information of the first target sub-block; The second determining module is used to determine the cache filling data in the target cache unit based on the information of the first target sub-block; A filling module is used to fill the cache filling data back into the upper-level cache unit of the target cache unit; The first sub-block information is encoded by the control module of the cache module when the cache module meets the target memory access conditions. The target memory access conditions are used to characterize whether the memory access behavior of the cache module conforms to the preset target memory access mode. The first target sub-block includes the first sub-block indicated by the memory access request and at least one second sub-block that is adjacent to the first sub-block based on the target memory access conditions met by the cache module.

15. A data processing device, characterized in that, include: At least one processing unit, at least one memory access control device, and at least one cache device; The processing unit is used to perform data processing corresponding to the target task, the memory access control device is the memory access control device as described in claim 13, and the cache device is the cache device as described in claim 14.

16. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores one or more computer programs that can be executed by the at least one processor, the one or more computer programs being executed by the at least one processor to enable the at least one processor to perform the memory access control method as described in any one of claims 1-10.

17. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the memory access control method as described in any one of claims 1-10.

18. A computer program product, characterized in that, It includes computer-readable code, which, when executed in a processor of an electronic device, causes the processor in the electronic device to perform the memory access control method as described in any one of claims 1-10.

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