A self-test structure and a self-test method of a ternary content addressable memory

Abstract

The application discloses a self-test structure and a self-test method of a ternary content addressable memory (TCAM), and belongs to the technical field of integrated circuit testability design. The self-test structure comprises peripheral selection logic connected to the input and output ends of the TCAM array, a control end of the peripheral selection logic being connected to a test start signal, and being used for switching the TCAM array to a test mode under the control of the test start signal; a controller electrically connected with the peripheral selection logic, the controller comprising a test vector generator and a comparator; the test vector generator is used for generating a test vector in the test mode, the test vector comprising an address signal, a data signal and a mode control signal, the test vector being loaded into the TCAM array via the peripheral selection logic; and a first input end of the comparator being connected to the output end of the TCAM array via the peripheral selection logic, and a second input end of the comparator being connected to an expected value output end of the test vector generator.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design testability technology, and relates to a self-test structure and self-test method for a three-state content-addressable memory. Background Technology

[0002] Ternary Content Addressable Memory (TCAM), as a content-addressable hardware search engine, has the core advantage of being able to perform parallel searches of stored data within a single clock cycle. Compared to traditional memories (such as SRAM and DRAM) that rely on address indexes or search systems based on software algorithms, TCAM directly reduces the search complexity from O(logN) or O(N) at the software level to O(1) at the hardware level, making it irreplaceable in high-speed network search applications such as routing table lookups, packet classification, and access control lists (ACLs). In particular, TCAM's unique "X" (Don't Care, wildcard) state encoding mechanism allows for flexible mask matching of stored entries, further significantly reducing the number of rule entries and greatly improving search efficiency. As a special type of memory, TCAM's core functions can be divided into two categories: storage function and matching query function. Correspondingly, its working modes also cover three types: read operation, write operation, and data matching operation. In the TCAM storage array, the data access and control logic in read / write mode is similar to that of traditional general-purpose memory, with cell access performed through address decoding; however, the matching operation is completely different from that of traditional memory—the matching operation requires comparing the input search data with all storage cells in the storage array in parallel, and outputting the match address (MatchAddress) and match indication signal (MatchHit) via a priority encoder.

[0003] With the exponential growth of network bandwidth, the capacity and bit width of on-chip integrated TCAMs are constantly increasing, and their manufacturing processes are becoming more complex, making their testing far more difficult than that of conventional memories. Traditional testing methods for memory arrays can only cover internal faults in read / write memory cells (such as fixed faults and transition faults), and cannot activate and observe the comparison logic and hit output logic on the matching line. Currently, Memory Built-in Self-Test (MBIST) technology has become the mainstream solution for Design for Testability (DFT) of large-capacity embedded memories. However, the standard MBIST controllers and algorithm libraries provided by existing mature commercial EDA tools are all developed for traditional read / write memories (RAM / ROM), and their test vector generation logic lacks the ability to time-drive and respond to the "matching mode" control signal. Overall, since TCAMs introduce matching search modes and wildcard mask functions compared to traditional memories, directly using the traditional MBIST structure will face the following significant drawbacks: (1) Lack of functional coverage: Traditional MBIST cannot generate the search control signal and mask signal required for TCAM matching mode, resulting in the TCAM-specific matching comparison logic circuit, hit priority encoder and wildcard (X) comparison path being in an untested "blind zone" for a long time, and dynamic faults and delay faults on the matching path cannot be detected.

[0004] (2) Poor algorithm compatibility: Conventional memory testing algorithms only verify the consistency between written data and read data, while the core value of TCAM lies in "searching". Its fault model not only includes physical damage to the storage unit, but also includes two types of matching logic errors: "Miss-Hit" and "False-Hit". Traditional algorithms cannot define and quantify such faults.

[0005] (3) Testing depends on external ATE equipment: If you try to verify the matching function of TCAM directly through external automatic test equipment (ATE), it is difficult to achieve matching delay test at full speed due to the difference between the ATE channel rate and the chip's internal operating frequency. At the same time, it will greatly increase the test vector storage capacity and test application time (TAT), resulting in a sharp increase in test cost, which does not meet the needs of large-scale mass production.

[0006] In summary, given that the existing standard MBIST architecture and EDA tool processes are incompatible with TCAM's hybrid functional (storage + matching) testing requirements, and that external testing solutions suffer from technical bottlenecks such as high cost and low fault coverage, Summary of the Invention

[0007] The purpose of this invention is to solve the technical problems in the prior art where the MBIST architecture cannot cover the TCAM matching query function test and the reliance on external ATE leads to high testing costs. This invention provides a self-test structure and self-test method for a tri-state content-addressable memory.

[0008] To achieve the above objectives, the present invention employs the following technical solution: In a first aspect, the present invention discloses a self-test structure for a tri-state content-addressable memory, wherein the tri-state content-addressable memory includes a TCAM array; the self-test structure includes: The peripheral selection logic is connected to the input and output terminals of the TCAM array. The control terminal of the peripheral selection logic is connected to the test start signal, which is used to switch the TCAM array to test mode under the control of the test start signal. A controller, electrically connected to the peripheral selection logic, the controller including a test vector generator and a comparator; The test vector generator is used to generate test vectors in the test mode. The test vectors include address signals, data signals, and mode control signals. The test vectors are loaded into the TCAM array via the peripheral selection logic. The first input of the comparator is connected to the output of the TCAM array via the peripheral selection logic, and the second input of the comparator is connected to the expected value output of the test vector generator. The comparator is used to compare the response output of the TCAM array with the expected value and output a test result indication signal.

[0009] Further improvements are made in the following aspects: The peripheral selection logic includes: The input selection logic is connected between the output of the test vector generator and the input of the TCAM array, and is used to select the test vector output by the test vector generator to the TCAM array in the test mode. The output selection logic is connected between the output terminal of the TCAM array and the first input terminal of the comparator, and is used to select the response output of the TCAM array to the comparator in the test mode.

[0010] The test vector generator includes a stored fault test vector generation unit and a matched fault test vector generation unit. The storage-type fault test vector generation unit is used to generate read / write test sequences covering the positive and negative data of the TCAM array storage unit; The matching fault test vector generation unit is used to generate matching search test sequences.

[0011] The storage-type fault test vector generation unit generates the read-write test sequence based on the March algorithm or the Checkboard algorithm. Each read operation step in the read-write test sequence is followed by a reverse read operation step to achieve full coverage testing of the forward and reverse data of the TCAM array storage unit.

[0012] The matching fault test vector generation unit generates the matching search test sequence based on the improved March-like algorithm. The matching search test sequence includes an erase operation sequence, a write operation sequence, and a search operation sequence.

[0013] In the matching search test sequence, the erase operation sequence contains 5N erase operations, the write operation sequence contains 6N write operations, and the search operation sequence contains 4N+2B search operations, where N is the address depth of the TCAM array and B is the data bit width of the TCAM array.

[0014] The matching search test sequence includes an exact matching test sequence and a mask matching test sequence; The precise matching test sequence is used to perform precise data matching tests on each storage cell of the TCAM array. The mask matching test sequence is used to perform fuzzy matching tests after masking the bits that are not of interest using a mask signal.

[0015] The mode control signals include chip select signal, read / write enable signal, mode selection signal, inverted read enable signal, refresh signal, and mask signal; The test vector generator is also used to generate the chip select signal, read / write enable signal, mode select signal, inverted read enable signal, refresh signal, and mask signal, and loads them to the corresponding control terminal of the TCAM array via the peripheral selection logic.

[0016] When the mode selection signal is at the first level, the TCAM array operates in read / write mode; when the mode selection signal is at the second level, the TCAM array operates in match query mode.

[0017] Secondly, this invention discloses a self-testing method for a tri-state content-addressable memory, based on the aforementioned self-testing structure for a tri-state content-addressable memory, comprising: Test start-up steps: The peripheral selection logic is controlled by the test start-up signal to switch the TCAM array to test mode; Test vector generation step: The test vector generator generates a test vector, which includes an address signal, a data signal, and a mode control signal. The mode control signal includes at least a mode selection signal for controlling the TCAM array to work in read / write mode or match query mode. Test loading step: The test vector is loaded into the TCAM array via the peripheral selection logic, so that the TCAM array performs storage-type fault tests and / or matching-type fault tests; Comparison output step: The comparator receives the response output of the TCAM array, compares the response output with the expected value provided by the test vector generator, and outputs a test result indication signal.

[0018] Compared with the prior art, the present invention has the following beneficial effects: This invention discloses a self-test structure for a tri-state content-addressable memory (TCAM). By adding peripheral selection logic controlled by a test initiation signal around the TCAM array, the invention independently switches the TCAM array to test mode. This allows the address signals, data signals, and mode control signals generated by the test vector generator to be fully applied to the TCAM array, overcoming the limitation of existing MBIST architectures that can only cover read / write paths and cannot activate matching query paths. Combined with an on-chip comparator that compares the response output with the expected value in real time, this achieves traversal detection and 100% coverage of internal faults, delay faults, inter-cell coupling faults, and matching comparison circuit faults within the TCAM memory cells, effectively improving fault coverage. Simultaneously, the test vector generator... The success, loading, and response discrimination are all integrated into the on-chip controller. Only the final pass / fail signal needs to be output to the external device, which fundamentally eliminates the dependence on external ATE equipment, avoids the test bottleneck caused by channel rate mismatch, significantly reduces the difficulty of test program development and the size of test vector storage, and significantly saves test time and mass production test costs. In addition, the self-test structure consists of two main parts: peripheral selection logic and controller. The circuit overhead is small, and the test mode and normal operation mode are cleanly isolated by the test start signal, which does not affect the performance of TCAM during normal chip operation. Moreover, it does not depend on a specific process technology and can be widely used for TCAM array testing with different capacities and bit widths. It has good engineering practical value and portability.

[0019] This invention discloses a self-testing method for a three-state content-addressable memory (TCAM). The method uses a test start signal to control peripheral selection logic, switching the TCAM array to test mode. An on-chip test vector generator autonomously generates a complete test vector covering address signals, data signals, and mode control signals. This vector is then loaded onto the TCAM array via the peripheral selection logic to perform memory-type fault tests and matching fault tests. This achieves full coverage stimulation of the TCAM read / write path and matching query path, overcoming the limitation of traditional MBIST, which can only test memory functions. Simultaneously, an on-chip comparator compares the TCAM array's response output with the expected value provided by the test vector generator in real time and outputs the test result indication. The entire process of generating, loading, executing, and judging test vectors is completed in a closed loop within the chip, eliminating the need for external ATE equipment to participate in cycle-by-cycle vector application and response acquisition. This avoids test bottlenecks caused by mismatch between ATE channel rates and chip internal frequencies, significantly reduces the storage size of test vectors and the development difficulty of test programs, and substantially shortens test time and mass production test costs. Furthermore, this method uses a test start signal to uniformly control the start of the test process and mode switching, with a clear boundary between the test mode and the normal working mode. After the test process ends, the TCAM array returns to normal working state without affecting the original functions and performance of the chip, exhibiting high process simplicity and broad process applicability. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of a self-test structure for a three-state content-addressable memory according to an embodiment of the present invention; Figure 2 This is a timing diagram of the read operation of a self-test structure for a tri-state content-addressable memory according to an embodiment of the present invention; Figure 3 This is a timing diagram of the write operation of a self-test structure for a tri-state content-addressable memory according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the matching operation of a self-test structure for a tri-state content-addressable memory in an embodiment of the present invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0023] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0024] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0025] The present invention will now be described in further detail with reference to the accompanying drawings: See Figure 1 This invention discloses a self-test structure for a tri-state content-addressable memory, wherein the tri-state content-addressable memory includes a TCAM array; the self-test structure includes: The peripheral selection logic is connected to the input and output terminals of the TCAM array. The control terminal of the peripheral selection logic is connected to the test start signal, which is used to switch the TCAM array to test mode under the control of the test start signal. A controller, electrically connected to the peripheral selection logic, the controller including a test vector generator and a comparator; The test vector generator is used to generate test vectors in the test mode. The test vectors include address signals, data signals, and mode control signals. The test vectors are loaded into the TCAM array via the peripheral selection logic. The first input of the comparator is connected to the output of the TCAM array via the peripheral selection logic, and the second input of the comparator is connected to the expected value output of the test vector generator. The comparator is used to compare the response output of the TCAM array with the expected value and output a test result indication signal.

[0026] This invention discloses a self-test structure for a tri-state content-addressable memory (TCAM). By adding peripheral selection logic controlled by a test initiation signal around the TCAM array, the invention independently switches the TCAM array to test mode. This allows the address signals, data signals, and mode control signals generated by the test vector generator to be fully applied to the TCAM array, overcoming the limitation of existing MBIST architectures that can only cover read / write paths and cannot activate matching query paths. Combined with an on-chip comparator that compares the response output with the expected value in real time, this achieves traversal detection and 100% coverage of internal faults, delay faults, inter-cell coupling faults, and matching comparison circuit faults within the TCAM memory cells, effectively improving fault coverage. Simultaneously, the test vector generator... The success, loading, and response discrimination are all integrated into the on-chip controller. Only the final pass / fail signal needs to be output to the external device, which fundamentally eliminates the dependence on external ATE equipment, avoids the test bottleneck caused by channel rate mismatch, significantly reduces the difficulty of test program development and the size of test vector storage, and significantly saves test time and mass production test costs. In addition, the self-test structure consists of two main parts: peripheral selection logic and controller. The circuit overhead is small, and the test mode and normal operation mode are cleanly isolated by the test start signal, which does not affect the performance of TCAM during normal chip operation. Moreover, it does not depend on a specific process technology and can be widely used for TCAM array testing with different capacities and bit widths. It has good engineering practical value and portability.

[0027] The present invention will be described in detail below with reference to specific embodiments: Example 1 This embodiment discloses a self-test structure for a tri-state content-addressable memory, wherein the tri-state content-addressable memory includes a TCAM array; the self-test structure includes: A peripheral selection logic is connected to the input / output terminals of the TCAM array. The control terminal of the peripheral selection logic is connected to a test start signal, used to switch the TCAM array to test mode under the control of the test start signal. The peripheral selection logic includes: The input selection logic is connected between the output of the test vector generator and the input of the TCAM array, and is used to select the test vector output by the test vector generator to the TCAM array in the test mode. The output selection logic is connected between the output terminal of the TCAM array and the first input terminal of the comparator, and is used to select the response output of the TCAM array to the comparator in the test mode.

[0028] A controller, electrically connected to the peripheral selection logic, the controller including a test vector generator and a comparator; The test vector generator is used to generate test vectors in the test mode. The test vectors include address signals, data signals, and mode control signals. The test vectors are loaded onto the TCAM array via the peripheral selection logic. The test vector generator includes a storage-type fault test vector generation unit and a matching-type fault test vector generation unit. The mode control signals include a chip select signal, a read / write enable signal, a mode selection signal, an inverted read enable signal, a refresh signal, and a mask signal. The test vector generator is also used to generate the chip select signal, read / write enable signal, mode selection signal, inverted read enable signal, refresh signal, and mask signal, and loads them to the corresponding control terminals of the TCAM array via the peripheral selection logic. When the mode selection signal is at the first level, the TCAM array operates in read / write mode; when the mode selection signal is at the second level, the TCAM array operates in match query mode.

[0029] The storage-type fault test vector generation unit is used to generate read / write test sequences covering the positive and negative data of the TCAM array storage units; the matching fault test vector generation unit is used to generate matching search test sequences.

[0030] See Figure 2 , Figure 3 and Figure 4 The storage-type fault test vector generation unit generates the read-write test sequence based on the March algorithm or the Checkboard algorithm. Each read operation step in the read-write test sequence is followed by a reverse read operation step to achieve full coverage testing of the forward and reverse data of the TCAM array storage unit. The matching fault test vector generation unit generates the matching lookup test sequence based on the improved March-like algorithm. The matching lookup test sequence includes an erase operation sequence, a write operation sequence, and a lookup operation sequence.

[0031] In the matching search test sequence, the erase operation sequence contains 5N erase operations, the write operation sequence contains 6N write operations, and the search operation sequence contains 4N+2B search operations, where N is the address depth of the TCAM array and B is the data bit width of the TCAM array.

[0032] The matching search test sequence includes an exact matching test sequence and a mask matching test sequence; The precise matching test sequence is used to perform precise data matching tests on each storage cell of the TCAM array; the mask matching test sequence is used to perform fuzzy matching tests after masking the bits that are not of interest using a mask signal.

[0033] The first input of the comparator is connected to the output of the TCAM array via the peripheral selection logic, and the second input of the comparator is connected to the expected value output of the test vector generator. The comparator is used to compare the response output of the TCAM array with the expected value and output a test result indication signal.

[0034] This invention also discloses a self-testing method for a tri-state content-addressable memory, based on the aforementioned self-testing structure for a tri-state content-addressable memory, comprising: Test start-up steps: The peripheral selection logic is controlled by the test start-up signal to switch the TCAM array to test mode; Test vector generation step: The test vector generator generates a test vector, which includes an address signal, a data signal, and a mode control signal. The mode control signal includes at least a mode selection signal for controlling the TCAM array to work in read / write mode or match query mode. Test loading step: The test vector is loaded into the TCAM array via the peripheral selection logic, so that the TCAM array performs storage-type fault tests and / or matching-type fault tests; Comparison output step: The comparator receives the response output of the TCAM array, compares the response output with the expected value provided by the test vector generator, and outputs a test result indication signal.

[0035] This invention discloses a self-testing method for a three-state content-addressable memory (TCAM). The method uses a test start signal to control peripheral selection logic, switching the TCAM array to test mode. An on-chip test vector generator autonomously generates a complete test vector covering address signals, data signals, and mode control signals. This vector is then loaded onto the TCAM array via the peripheral selection logic to perform memory-type fault tests and matching fault tests. This achieves full coverage stimulation of the TCAM read / write path and matching query path, overcoming the limitation of traditional MBIST, which can only test memory functions. Simultaneously, an on-chip comparator compares the TCAM array's response output with the expected value provided by the test vector generator in real time and outputs the test result indication. The entire process of generating, loading, executing, and judging test vectors is completed in a closed loop within the chip, eliminating the need for external ATE equipment to participate in cycle-by-cycle vector application and response acquisition. This avoids test bottlenecks caused by mismatch between ATE channel rates and chip internal frequencies, significantly reduces the storage size of test vectors and the development difficulty of test programs, and substantially shortens test time and mass production test costs. Furthermore, this method uses a test start signal to uniformly control the start of the test process and mode switching, with a clear boundary between the test mode and the normal working mode. After the test process ends, the TCAM array returns to normal working state without affecting the original functions and performance of the chip, exhibiting high process simplicity and broad process applicability.

[0036] Example 2 The self-test structure of this invention has been successfully applied to a large-scale 65nm process SOC chip. This SOC circuit integrates a 256x232 TCAM (Test Module Assembly), and the design incorporates a set of control circuitry around the TCAM to enable automatic testing and response discrimination. The operation of the controller is described from the perspectives of both memory-related faults and matching faults.

[0037] 1. Storage-type faults The MBIST circuit generates test vectors according to the algorithm steps and writes them into the TCAM. The test vectors include address, data, chip select, and read / write enable signals. It iterates through all address read / write operations, repeating this process until all algorithm steps are completed. During this process, a comparison error in any loop indicates a memory fault; no test failures indicate the memory has passed the test. For the TCAM's unique inverted data read operation, the enable signal rd_t_f is controlled so that after each read operation in the algorithm steps, an inverted read operation is performed to test the TCAM's inverted read logic.

[0038] 2. Matching-related faults (1) Exact match The match-0 operation first uses the flush signal to erase all addresses, writing 0 to address 0, pulling the mode_sel enable signal high to enter match mode. After matching 0, the m_hit output is pulled high, A_o outputs the address, and then flush is pulled high to erase the data at address 0. This process is repeated sequentially in ascending address order. The m_hit signal is compared with the expected value in the comparator, outputting fail / pass. Matching 1 follows the same procedure.

[0039] (2) Mask matching During the matching search, if there are values ​​that are not of interest, they can be written using a mask. Setting the mask value of the uninterested bits to 1 allows for fuzzy matching tests (X-0, X-1).

[0040] 3. Matching logic test A faulty matching circuit can be detected by writing one-hot data to each address and matching it against all 0s or all 1s.

[0041] The addition of this self-test structure solves the current design testability problem of TCAM, can completely cover 100% of the fault detection within TCAM, automatically generate test vectors, and save test time and test costs. Table 1 is the TCAM truth table.

[0042] Table 1

[0043] The working principle of this invention is as follows: The TCAM test circuit mainly consists of two parts.

[0044] The selection logic of the TCAM's periphery is controlled by the test start signal to ensure that the test vector given by the controller is loaded during the test.

[0045] The controller circuit mainly includes a test vector generator, comparators, and other logic. The test vector generator provides the address data and various mode control signals required by the TCAM, and compares the TCAM output with the expected value, outputting pass / fail signals to an external device for observation.

[0046] Testing TCAM needs to cover both storage-related and matching-related faults. For storage-related fault testing, the traditional March and Checkboard algorithms are used. However, due to the differences in TCAM storage cell structure, these algorithms cannot effectively cover all storage faults in TCAM. Therefore, the March and Checkboard algorithms are improved by adding a test sequence of inverse data, achieving full coverage testing of both positive and negative data of TCAM storage cells.

[0047] For matching fault testing, an improved March-like matching fault testing algorithm was implemented, which can complete the matching fault testing of N faults with only 5N erase operations, 6N write operations, and 4N+2B lookup operations. Matching fault detection of B-bit TCAM memory cells.

[0048] This invention implements traversal single-cycle read / write and match lookup testing for TCAM storage faults and matching faults, achieving 100% coverage detection of faults within TCAM cells, latency faults, and inter-cell faults. By utilizing an on-chip controller to automatically control and determine read / write and matching tests, it eliminates dependence on test equipment, significantly reduces the development difficulty of test programs and test vectors, and saves testing time and costs.

[0049] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A self-test structure for a tri-state content-addressable memory, characterized in that, The tri-state content-addressable memory includes a TCAM array; The self-test structure includes: The peripheral selection logic is connected to the input and output terminals of the TCAM array. The control terminal of the peripheral selection logic is connected to the test start signal, which is used to switch the TCAM array to test mode under the control of the test start signal. A controller, electrically connected to the peripheral selection logic, the controller including a test vector generator and a comparator; The test vector generator is used to generate test vectors in the test mode. The test vectors include address signals, data signals, and mode control signals. The test vectors are loaded into the TCAM array via the peripheral selection logic. The first input of the comparator is connected to the output of the TCAM array via the peripheral selection logic, and the second input of the comparator is connected to the expected value output of the test vector generator. The comparator is used to compare the response output of the TCAM array with the expected value and output a test result indication signal.

2. The self-test structure of the tri-state content-addressable memory according to claim 1, characterized in that, The peripheral selection logic includes: The input selection logic is connected between the output of the test vector generator and the input of the TCAM array, and is used to select the test vector output by the test vector generator to the TCAM array in the test mode. The output selection logic is connected between the output terminal of the TCAM array and the first input terminal of the comparator, and is used to select the response output of the TCAM array to the comparator in the test mode.

3. The self-test structure of the tri-state content-addressable memory according to claim 1, characterized in that, The test vector generator includes a stored fault test vector generation unit and a matched fault test vector generation unit. The storage-type fault test vector generation unit is used to generate read / write test sequences covering the positive and negative data of the TCAM array storage unit; The matching fault test vector generation unit is used to generate matching search test sequences.

4. The self-test structure of the tri-state content-addressable memory according to claim 3, characterized in that, The storage-type fault test vector generation unit generates the read-write test sequence based on the March algorithm or the Checkboard algorithm. Each read operation step in the read-write test sequence is followed by a reverse read operation step to achieve full coverage testing of the forward and reverse data of the TCAM array storage unit.

5. The self-test structure of the tri-state content-addressable memory according to claim 3, characterized in that, The matching fault test vector generation unit generates the matching search test sequence based on the improved March-like algorithm. The matching search test sequence includes an erase operation sequence, a write operation sequence, and a search operation sequence.

6. The self-test structure of the tri-state content-addressable memory according to claim 5, characterized in that, In the matching search test sequence, the erase operation sequence contains 5N erase operations, the write operation sequence contains 6N write operations, and the search operation sequence contains 4N+2B search operations, where N is the address depth of the TCAM array and B is the data bit width of the TCAM array.

7. The self-test structure of the tri-state content-addressable memory according to claim 3, characterized in that, The matching search test sequence includes an exact matching test sequence and a mask matching test sequence; The precise matching test sequence is used to perform precise data matching tests on each storage cell of the TCAM array. The mask matching test sequence is used to perform fuzzy matching tests after masking the bits that are not of interest using a mask signal.

8. The self-test structure of the tri-state content-addressable memory according to claim 1, characterized in that, The mode control signals include chip select signal, read / write enable signal, mode selection signal, inverted read enable signal, refresh signal, and mask signal; The test vector generator is also used to generate the chip select signal, read / write enable signal, mode select signal, inverted read enable signal, refresh signal, and mask signal, and loads them to the corresponding control terminal of the TCAM array via the peripheral selection logic.

9. The self-test structure of the tri-state content-addressable memory according to claim 8, characterized in that, When the mode selection signal is at the first level, the TCAM array operates in read / write mode; when the mode selection signal is at the second level, the TCAM array operates in match query mode.

10. A self-testing method for a tri-state content-addressable memory, based on the self-testing structure of the tri-state content-addressable memory according to any one of claims 1-9, characterized in that, include: Test start-up steps: The peripheral selection logic is controlled by the test start-up signal to switch the TCAM array to test mode; Test vector generation step: The test vector generator generates a test vector, which includes an address signal, a data signal, and a mode control signal. The mode control signal includes at least a mode selection signal for controlling the TCAM array to work in read / write mode or match query mode. Test loading step: The test vector is loaded into the TCAM array via the peripheral selection logic, so that the TCAM array performs storage-type fault tests and / or matching-type fault tests; Comparison output step: The comparator receives the response output of the TCAM array, compares the response output with the expected value provided by the test vector generator, and outputs a test result indication signal.

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