A chip defect nondestructive detection method based on thermoelectric response characteristics

Abstract

The application relates to a chip defect nondestructive detection method based on a thermoelectric response feature, and belongs to the technical field of radio frequency chip detection.The method comprises the following steps: a preset electric excitation signal is applied to a radio frequency chip to be detected, so that the radio frequency chip to be detected generates a nondestructive temperature rise; during the application of the electric excitation signal, time sequence data and spatial distribution data of a temperature field of a surface of the radio frequency chip to be detected changing over time are collected; according to the time sequence data and the spatial distribution data, multi-dimensional feature parameters for characterizing a chip thermal response feature are extracted; the multi-dimensional feature parameters are input into a preset clustering discriminant model for pattern recognition, so as to automatically judge whether the radio frequency chip to be detected has an internal defect, and output the type and / or severity grade of the internal defect when the internal defect exists.The application has the effects of realizing detailed detection of radio frequency chip defects and automatically judging the defect type.

Description

Technical Field

[0001] This application relates to the field of radio frequency chip inspection technology, and in particular to a non-destructive testing method for chip defects based on thermoelectric response characteristics. Background Technology

[0002] Radio frequency (RF) chips (such as power amplifiers, low-noise amplifiers, and RF switches) are widely used in aerospace, 5G communication, and IoT devices, and their reliability directly affects the performance and lifespan of the entire system. Currently, for non-destructive testing of internal defects in RF chips, the industry mainly uses methods such as DC electrical parameter testing, functional logic testing, and infrared thermal imaging temperature screening. In some scenarios, RF performance indicators such as S-parameters are also used for comprehensive judgment.

[0003] In actual production line applications, the above-mentioned detection methods generally have the following shortcomings: Firstly, DC parameter testing and functional logic testing are mainly based on the electrical behavior of the chip to determine its passability. For structural defects such as bond detachment, poor soldering, microcracks and electrostatic discharge (ESD) latent damage, they do not significantly affect the DC operating point or logic function in the early stages. Such methods are difficult to detect effectively and have detection blind spots.

[0004] Secondly, infrared thermal imaging screening solutions typically image the temperature field on the chip surface and use a preset temperature threshold as a criterion to identify the presence of abnormal heating areas. While this type of solution can identify chips with abnormal temperatures to some extent, its output is limited to a binary judgment of "qualified / suspected abnormal," and it cannot further distinguish the specific defect type causing the abnormality. That is, it cannot answer whether the abnormality originates from bond detachment, poor soldering, microcracks, or ESD latent damage. This lack of identification capability leaves subsequent failure analysis and process improvement without a clear direction.

[0005] Third, while comprehensive judgment based on S-parameters and other RF indicators can reflect changes in chip RF performance to some extent, this type of testing relies on precision equipment such as vector network analyzers, resulting in high system costs, low testing efficiency, and test results easily affected by test fixtures and calibration status. More importantly, this type of solution also primarily provides a conclusion on whether performance meets standards, lacking the ability to automatically classify defect types.

[0006] In summary, existing RF chip internal defect detection technologies, after determining the existence of anomalies, cannot automatically output defect type information, making it difficult to meet the actual needs of production lines for rapid location and classification of defect root causes. Summary of the Invention

[0007] To achieve detailed detection of defects in radio frequency chips and automatic identification of defect types, this application provides a non-destructive testing method for chip defects based on thermoelectric response characteristics.

[0008] In a first aspect, this application provides a non-destructive testing method for chip defects based on thermoelectric response characteristics, including: A preset electrical excitation signal is applied to the radio frequency chip under test to induce a non-destructive temperature rise in the chip. During the application of the electrical excitation signal, time-series data and spatial distribution data of the temperature field on the surface of the radio frequency chip under test are collected. Based on the time-series data and spatial distribution data, multidimensional feature parameters are extracted to characterize the thermal response of the chip. The multidimensional feature parameters are input into a preset clustering discrimination model for pattern recognition to automatically determine whether the radio frequency chip under test has internal defects, and output the type and / or severity level of the internal defects when they exist.

[0009] By adopting the above technical solution, an electrical excitation is applied to the RF chip under test to generate a non-destructive temperature rise. The time-series data and spatial distribution data of the chip surface temperature field are collected, multi-dimensional feature parameters for characterizing the thermal response of the chip are extracted, and a clustering discrimination model is used for pattern recognition. This enables the automatic determination of whether the chip has internal defects, as well as the type and severity of the defects, without testing RF indicators such as S-parameters. This achieves non-contact non-destructive testing, reducing the cost and complexity of testing equipment.

[0010] Optionally, the method further includes: Based on the multidimensional feature parameters, the relative thermal impedance change between different regions of the radio frequency chip under test is calculated by inversion. Based on the relative thermal resistance change, the longitudinal distribution depth and / or lateral distribution area of ​​the internal defects in the chip package are determined and output.

[0011] By adopting the above technical solution, the relative thermal impedance change between different regions of the chip is further calculated through inversion, and the longitudinal distribution depth and / or lateral distribution area of ​​defects in the chip package are determined, thereby providing spatial location information of defects and providing specific location basis for subsequent failure analysis.

[0012] Optionally, during the continuous application of the electrical excitation signal, the method further includes: Collect steady-state temperature distribution data of the surface temperature field of the radio frequency chip under test after it reaches thermal equilibrium. Extract the temperature uniformity index and / or thermal field symmetry index of the surface of the radio frequency chip under test from the steady-state temperature analysis data; The step of inputting the multidimensional feature parameters into a preset clustering discriminant model for pattern recognition includes: inputting the temperature uniformity index and / or thermal field symmetry index as part of the multidimensional feature parameters into the clustering discriminant model for pattern recognition.

[0013] By employing the above technical solution, steady-state temperature distribution data of the chip surface after reaching thermal equilibrium is collected, and temperature uniformity and / or thermal field symmetry indices are extracted. These indices are then incorporated into multi-dimensional feature parameters for clustering discrimination. Temperature uniformity reflects the dispersion of the overall temperature distribution of the chip, while thermal field symmetry reflects the symmetry of the temperature field about its geometric center. These two indices supplement the information of the multi-dimensional feature parameters from the spatial distribution dimension under thermal equilibrium, thereby improving the clustering discrimination model's accuracy in distinguishing defect types.

[0014] Optionally, the extraction of multidimensional feature parameters for characterizing the thermal response of the chip includes: Based on the time series data and spatial distribution data, a full-field thermal gradient vector field is constructed on the surface of the radio frequency chip under test; Calculate the anisotropy index of the full-field thermal gradient vector field, and use the anisotropy index as one of the multidimensional feature parameters.

[0015] By employing the above technical solution, a full-field thermal gradient vector field on the chip surface is constructed, and its anisotropy index is calculated. This index is then used as one of the multidimensional feature parameters. The anisotropy index quantifies the uniformity of the thermal gradient vector field distribution in different directions. The thermal gradient vector field of a defect-free chip is isotropic. When defects (especially bond detachment or microcracks) are present, heat flow deflection leads to an increase in the anisotropy index. This provides a feature dimension reflecting the abnormality of heat conduction direction for the clustering discrimination model, thereby improving the sensitivity of identifying defects such as bond detachment and microcracks.

[0016] Optionally, determining and outputting the longitudinal distribution depth and / or lateral distribution region of the internal defects in the chip package includes: Determine the longitudinal distribution depth and / or lateral distribution area of ​​the internal defect in the chip package, and based on the gradient rate of change of the relative thermal resistance at the longitudinal distribution depth and / or the spatial distribution variance in the lateral distribution area, determine whether the physical property of the internal defect is an interface defect or a bulk material defect. When the defect is determined to be an interface type, the output defect type is either a poor weld or a bond detachment; when the defect is determined to be a bulk material type, the output defect type is a microcrack.

[0017] By adopting the above technical solution, the physical properties of the defect are further determined as interface-type or bulk material-type defects based on the gradient rate of change of relative thermal resistance in the depth direction or the spatial distribution variance in the transverse region. The specific defect type (cold weld or bond detachment, microcrack) is then output accordingly. Interface-type defects (with a step-like abrupt change in gradient rate and a large spatial distribution variance) correspond to cold welds or bond detachment, while bulk material-type defects (with a continuous and gradual change in gradient rate and a small spatial distribution variance) correspond to microcracks, thus achieving refined differentiation of defect types.

[0018] Optionally, the method further includes: Perform streamline tracing on the full field of view thermal gradient vector field to extract the positions of the confluence points and / or bifurcation points in the thermal gradient vector field; Based on the location of the confluence point and / or bifurcation point, determine the boundary contour of the heat flow obstruction region of the internal defect in the chip package; Based on the boundary profile, determine the lateral dimension of the internal defect; Based on the spatial correspondence between the boundary contour and the longitudinal distribution depth and / or the lateral distribution area, the determined longitudinal distribution depth and / or lateral distribution area are processed. The processing operation specifically includes: determining the longitudinal depth layer of the internal defect, and / or correcting the boundary of the lateral distribution area. The processing result of the aforementioned processing operation is output as the quantitative basis for the severity level.

[0019] By employing the above technical solution, streamline tracing of the vector field and extraction of confluence and / or bifurcation points determine the boundary contour of the heat flow blockage region, thereby determining the lateral dimensions of the defect. Using the spatial correspondence between the boundary contour and the determined longitudinal distribution depth and / or lateral distribution area, the longitudinal depth layer is determined or the boundary of the lateral distribution area is corrected. The results of this processing serve as the quantitative basis for severity level assessment. The physical mechanism of heat flow confluence and bifurcation points is as follows: when heat flow encounters a defect, it bifurcates upstream of the defect and converges downstream, with the connecting lines forming the defect boundary. Based on this physical mechanism, the lateral dimensions of the defect and the precision of the longitudinal depth layer are achieved, providing a quantitative geometric dimension and depth layer basis for severity level assessment.

[0020] Optionally, the method further includes: In the full field of view thermal gradient vector field, with the center of the heat source as the reference point, the first temperature rise time series curve of the reference point is obtained; Obtain the second temperature rise time series curves of multiple sampling points other than the reference point in the full field of view thermal gradient vector field; Calculate the cross-correlation function of each of the second temperature rise time series curves relative to the first temperature rise time series curve, and extract the peak delay of each of the second temperature rise time series curves; Based on the distribution of each peak delay on the surface of the RF chip under test, a delay distribution map is constructed; The location and / or range of the time delay anomaly region are extracted from the time delay distribution map as the location information of the internal defect.

[0021] By employing the above technical solution, using the heat source center as a reference point, the temperature rise time series curves of each sampling point are obtained. The cross-correlation function of each sampling point relative to the reference point is calculated, and the peak time delay is extracted to construct a time delay distribution map. The location and / or range of time delay anomaly regions are extracted as auxiliary defect location information. Impaired heat conduction in the defect area leads to a delay in heat arrival time, which is manifested in the time delay distribution map as an area with an abnormally high peak time delay. Utilizing the heat propagation time delay—a physical dimension independent of thermal impedance amplitude—for defect location can be mutually verified with the thermal impedance inversion location results described above. When the two locations are consistent, the reliability of the location is enhanced; when they are inconsistent, manual verification is prompted.

[0022] Secondly, this application provides a chip defect non-destructive testing system based on thermoelectric response characteristics, comprising: An electrical excitation module is used to apply a preset electrical excitation signal to the radio frequency chip under test, so as to cause the radio frequency chip under test to generate a non-destructive temperature rise. The temperature acquisition module is used to acquire time-series data and spatial distribution data of the temperature field change over time on the surface of the radio frequency chip under test during the application of the electrical excitation signal. The feature extraction module is used to extract multidimensional feature parameters to characterize the thermal response of the chip based on the time-series data and spatial distribution data. The clustering discrimination module is used to input the multidimensional feature parameters into a preset clustering discrimination model for pattern recognition, so as to automatically determine whether the radio frequency chip under test has internal defects, and output the type and / or severity level of the internal defects when the internal defects exist.

[0023] Thirdly, this application provides a chip defect non-destructive testing device based on thermoelectric response characteristics, including a memory and a processor, wherein the memory stores a computer program that can be loaded by the processor and executed as described in any of the first aspects.

[0024] Fourthly, this application provides a computer-readable storage medium storing a computer program that can be loaded by a processor and executed as described in any of the first aspects.

[0025] In summary, this application includes the following beneficial technical effects: In this application, by applying electrical excitation to the RF chip under test to generate a non-destructive temperature rise, the time-series data and spatial distribution data of the chip surface temperature field are collected, multi-dimensional feature parameters for characterizing the thermal response characteristics of the chip are extracted, and a clustering discrimination model is used for pattern recognition. This enables the automatic determination of whether the chip has internal defects, as well as the defect type and severity level, without testing RF indicators such as S-parameters. This achieves non-contact non-destructive testing, reducing the cost and complexity of testing equipment. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic flowchart of a chip defect non-destructive testing method based on thermoelectric response characteristics disclosed in an embodiment of this application.

[0028] Figure 2 This is a structural block diagram of a chip defect non-destructive testing system based on thermoelectric response characteristics disclosed in an embodiment of this application.

[0029] Explanation of reference numerals in the attached figures: 201, Electrical excitation module; 202, Temperature acquisition module; 203, Feature extraction module; 204, Clustering discrimination module. Detailed Implementation

[0030] The following is in conjunction with the appendix Figure 1-2 This application will be described in further detail.

[0031] This application discloses a non-destructive testing method for chip defects based on thermoelectric response characteristics (hereinafter referred to as the testing method). The main body executing the testing method is a non-destructive testing system for chip defects based on thermoelectric response characteristics (hereinafter referred to as the testing system). The following will be described in conjunction with the attached... Figure 1 The detailed execution process of the detection system for the detection method is described in detail.

[0032] S101 applies a preset electrical excitation signal to the RF chip under test to induce a non-destructive temperature rise in the RF chip under test.

[0033] S102, during the application of the electrical excitation signal, acquires the time-series data and spatial distribution data of the temperature field change over time on the surface of the radio frequency chip under test.

[0034] S103, based on time-series data and spatial distribution data, extracts multidimensional feature parameters to characterize the thermal response of the chip.

[0035] S103 inputs multi-dimensional feature parameters into a preset clustering discrimination model for pattern recognition to automatically determine whether the RF chip under test has internal defects, and outputs the type and / or severity level of the internal defects when internal defects exist.

[0036] In implementation, step S101 is first executed to apply a preset electrical excitation signal to the RF chip under test. The electrical excitation signal is a constant, low-power DC signal generated by the electrical excitation module of the detection system, used to drive the RF chip under test into its operating state and generate a controllable, non-destructive temperature rise. The electrical excitation module is preferably a programmable DC power supply, connected to the power supply port of the RF chip under test via a power cable. Its output voltage and current parameters are set according to the rated operating power consumption of the RF chip under test to ensure that the applied electrical power does not cause thermal damage to the chip.

[0037] Before applying the electrical excitation signal, the operator sets the voltage and current values ​​of the electrical excitation signal in the host computer software of the testing system according to the model and specifications of the RF chip under test. The host computer sends the set parameters to the programmable DC power supply via Ethernet or RS232 serial port. After receiving the setting command, the programmable DC power supply outputs a constant DC current to the RF chip under test according to the set voltage and current values. After the electrical excitation signal is applied, the internal circuit structure of the RF chip under test begins to work and consumes electrical energy, which is converted into Joule heat, causing the chip temperature to gradually rise. To avoid damage to the chip due to overheating, the power of the electrical excitation signal is limited to a range that keeps the chip junction temperature from exceeding 70% to 80% of the rated maximum junction temperature. This power level is sufficient to generate a temperature rise of several degrees Celsius to more than ten degrees Celsius on the chip surface. This temperature rise will not cause any irreversible physical or electrical damage to the chip, thus achieving a non-destructive temperature rise. In actual operation, the host computer software of the detection system has a pre-stored table of recommended excitation parameters for different chip models. After the operator selects the chip model, the host computer automatically retrieves the corresponding excitation parameters and sends them to the programmable DC power supply through the communication cable.

[0038] While step S101 is being executed, step S102 is initiated. During the application of the electrical excitation signal, time-series data and spatial distribution data of the temperature field change over time on the surface of the RF chip under test are acquired. The temperature field acquisition is performed by the temperature acquisition module of the detection system, preferably an infrared thermal imager. An infrared thermal imager is a non-contact optical temperature measurement device that inverts the temperature by detecting the infrared radiation energy emitted from the chip surface, without affecting the chip's heat dissipation state or RF impedance characteristics. The infrared thermal imager is connected to the data acquisition computer of the detection system via a signal cable (such as a Camera Link cable or Ethernet cable). Its lens is placed perpendicular to the surface of the RF chip under test, typically 10 cm to 30 cm away, and the field of view should completely cover the entire chip surface.

[0039] Simultaneously with the application of the electrical excitation signal, the host computer sends a synchronous acquisition trigger command to the infrared thermal imager via the trigger signal line. Upon receiving the trigger command, the infrared thermal imager begins to continuously acquire a sequence of thermal images of the chip surface at a preset acquisition frame rate. The acquisition frame rate is set according to the thermal time constant of the chip under test, typically between 25 and 100 frames per second, to ensure that transient changes during the temperature rise process can be captured.

[0040] Each frame of thermal image captured by an infrared thermal imager is a two-dimensional temperature field distribution map. Each pixel in the image corresponds to the temperature value of a tiny area on the chip surface. The spatial resolution of the pixels depends on the number of pixels in the infrared thermal imager's detector (e.g., 640×512 pixels) and the lens magnification. As the electrical excitation signal is continuously applied, the chip surface temperature gradually rises. The infrared thermal imager continuously records the temperature field distribution map at each moment, thus forming a set of thermal image sequences arranged in chronological order. Each frame of thermal image provides spatial distribution data, while all frames arranged in chronological order constitute temporal data. The acquisition process continues until the chip surface temperature field reaches thermal equilibrium (i.e., the temperature value of each pixel fluctuates less than a set threshold within a preset time period), typically ranging from 30 to 120 seconds, depending on the chip's packaging structure and heat dissipation conditions. During the acquisition process, the detection system also needs to perform emissivity correction on the infrared thermal imager (because the emissivity of different material surfaces is different). If the chip surface is polished metal (emissivity is less than 0.05), the measurement error is large. In this case, a thin layer of high emissivity coating needs to be sprayed evenly on the chip surface or the chip needs to be placed next to a blackbody with known emissivity for comparison and correction to ensure that the temperature measurement accuracy is within ±1°C.

[0041] After acquiring the time-series and spatial distribution data of the temperature field in step S102, the process proceeds to step S103, where multidimensional feature parameters characterizing the chip's thermal response are extracted based on the time-series and spatial distribution data. This step is executed by the feature extraction module of the detection system, which is a software function module running on the data acquisition computer.

[0042] First, temporal features are extracted from the time-series data. For the temperature value of each pixel in each frame of the thermal image acquired by the infrared thermal imager, a temperature rise curve of that pixel over time can be plotted. The feature extraction module performs linear fitting on the initial segment of the temperature rise curve (e.g., data points within the first 5 to 10 seconds), and uses the slope obtained from the fitting as the initial temperature rise rate. This parameter reflects the rate at which the chip surface temperature rises at the instant of electrical excitation. Based on this, the feature extraction module obtains the time point corresponding to when the temperature rise curve reaches 63.2% of the steady-state temperature rise value as the thermal time constant. This parameter is an inherent characterization of the chip's thermal response speed; different types and severity of defects will cause different degrees of shift in the thermal time constant.

[0043] Next, spatial dimension features are extracted from the spatial distribution data. The feature extraction module selects a thermal image frame when the temperature field reaches thermal equilibrium. The thermal equilibrium state is defined as follows: the feature extraction module continuously monitors the temperature values ​​of multiple preset monitoring points in the temperature field (including the geometric center point of the surface area of ​​the RF chip under test, and the pixels at the four corners of the surface area: upper left, upper right, lower left, and lower right). When the rate of temperature change at each monitoring point does not exceed 0.1°C / min within 30 consecutive seconds, the temperature field is considered to have reached thermal equilibrium. Alternatively, the thermal equilibrium time of the chip under test at a preset excitation power can be pre-determined experimentally and stored in the detection system. During actual detection, maintaining the electrical excitation signal for the preset duration is considered to have reached thermal equilibrium. After reaching thermal equilibrium, the feature extraction module calculates the standard deviation of the temperature values ​​of all pixels in the entire chip surface area from the thermal image at the corresponding moment. This standard deviation serves as a temperature uniformity index, quantifying the uniformity of the overall temperature distribution of the chip.

[0044] Meanwhile, the thermal image frame is rotated 180° around the geometric center of the chip, and the mean square error of the temperature difference between each pixel between the original image and the rotated image is calculated as a thermal field symmetry index, which reflects the symmetry of the chip's temperature field distribution.

[0045] In addition, the feature extraction module performs local threshold analysis on the thermal image under thermal equilibrium: First, using the global temperature mean plus twice the standard deviation as the judgment threshold, each pixel in the thermal image is scanned one by one to determine whether its temperature value is higher than the threshold; then, using the 8-connectivity criterion (i.e., a pixel is adjacent to pixels in eight directions: above, below, left, right, upper left, upper right, lower left, and lower right), connectivity analysis is performed on pixels that meet the threshold condition. A connected region is defined as the set of all pixels that meet the condition, extending the search through adjacent relationships from any pixel that meets the condition. The extension in that direction terminates when a pixel that does not meet the threshold condition is encountered. The total number of all connected regions that meet the condition is counted as the number of abnormal hot spots. This indicator reflects whether there are local abnormal heat points on the chip surface. To eliminate noise interference, an area threshold can be preset (e.g., the total number of pixels in a connected region is not less than 3). Only connected regions with an area reaching this threshold are counted as abnormal hot spots.

[0046] Finally, the fitting residual is extracted from the complete global average temperature rise curve: For each frame of thermal image, the feature extraction module first calculates the arithmetic mean of the temperature values ​​of all pixels in the entire chip surface area of ​​the image frame, and concatenates the global average temperature values ​​of all frames in chronological order to form the measured global average temperature rise curve; then, the measured global average temperature rise curve is compared point by point with the preset defect-free standard global average temperature rise curve, and the sum of squared errors between the two is calculated as the curve fitting residual. This index comprehensively reflects the overall deviation between the chip's actual thermal response and the ideal state.

[0047] The four parameters mentioned above—initial temperature rise rate, thermal time constant, number of anomalous hot spots, and curve fitting residual—along with the temperature uniformity index and thermal field symmetry index, which will be elaborated in detail below (see the extraction process of steady-state temperature distribution data in step S103), together constitute the complete multidimensional feature parameters used in this application to characterize the thermal response of the chip. For ease of description, the initial temperature rise rate, thermal time constant, number of anomalous hot spots, and curve fitting residual will be referred to as the basic feature parameters below.

[0048] After extracting the multidimensional feature parameters, the process proceeds to step S104, where the multidimensional feature parameters are input into a preset clustering discrimination model for pattern recognition to automatically determine whether the RF chip under test has internal defects. If internal defects are found, the type and / or severity level of the internal defects are output.

[0049] The clustering discrimination model is a classification model built based on the fuzzy C-means clustering algorithm. It is pre-built and stored in the clustering discrimination module of the detection system through an offline training phase. The training process of this model is as follows: First, multiple sample chips with known defect types are acquired. These sample chips include defect-free chips and chips known to have different types of defects such as bond detachment, cold solder joints, microcracks, and electrostatic discharge latent damage. The number of samples for each state is no less than 30. For each sample chip, the same operation process as described in steps S101 to S103 is performed to extract its multi-dimensional feature parameters, forming a labeled feature vector sample set. Then, the fuzzy C-means clustering algorithm is used to perform cluster analysis on this sample set. The algorithm divides the sample set into multiple clusters corresponding to the number of defect types. Each cluster corresponds to a defect state (including the defect-free state), and the cluster center and feature value distribution range of each cluster are determined. The core of the fuzzy C-means clustering algorithm lies in the introduction of the membership degree concept. Each sample belongs to different clusters with different membership degrees. This allows the algorithm to handle the blurred boundaries between defects and normal states with fine detail, making it particularly suitable for detection methods such as infrared thermal imaging, which inherently possess a certain degree of fuzziness. After training, the cluster center and the distribution range of eigenvalues ​​for each cluster constitute the core parameters of the clustering discriminant model.

[0050] In the actual online detection phase, after the feature extraction module inputs the multidimensional feature parameters of the chip under test into the clustering and discrimination module, the clustering and discrimination module first normalizes the feature vector, and then calculates the weighted Euclidean distance from the feature vector to the cluster centers of each cluster. Based on this, the clustering and discrimination module calls the standard membership function in the fuzzy C-means clustering algorithm to calculate the membership value of the feature vector to each cluster. The expression for the membership function is the standard fuzzy C-means clustering algorithm's membership calculation formula:

[0051] Among them, u ij x represents the membership value of the j-th sample to be tested to the i-th cluster center. j Let v be the feature vector of the sample to be tested. i and v k Let c be the cluster center vectors of the i-th and k-th clusters, c be the total number of clusters, and m be the fuzzy weighting index (which is 2 in this embodiment). Represents the eigenvector x j To the corresponding cluster center v i The weighted Euclidean distance is calculated using the following formula:

[0052] Where d is the total dimension of the feature vector (d=6 in this embodiment), r is the dimension index, and x jr and v irwhere are the feature values ​​of the sample to be tested and the cluster center in the r-th dimension, respectively. The weight coefficient w r The principle for determining the value of w is as follows: During the offline training phase, calculate the reciprocal of the variance of the feature values ​​of all training samples in the r-th dimension, i.e., w r =1 / σ r 2 This eliminates the influence of different feature dimensions on distance calculation. Using the weighted Euclidean distance formula described above, the distance term in the membership function can be accurately calculated, thus reproducing the entire clustering process.

[0053] After obtaining the membership values ​​of the test sample to each cluster, the clustering discrimination module takes the cluster corresponding to the maximum membership value as the preliminary judgment result. If the maximum membership value is greater than or equal to the preset confidence threshold (this threshold is set by the operator between 0.8 and 0.95 according to the actual detection accuracy requirements, and is preferably set to 0.85 in this embodiment), the preliminary judgment result is accepted: when the cluster corresponding to the maximum membership value is a "defect-free" cluster, it is determined that the RF chip under test does not have internal defects, and the "qualified" result is output; when the cluster corresponding to the maximum membership value is a cluster of a certain defect type, it is determined that the RF chip under test has an internal defect corresponding to that cluster, and the type of the defect is output. The defect type includes, but is not limited to, bond detachment, cold solder joint, microcracks, and electrostatic discharge latent damage. If the maximum membership value is less than the preset confidence threshold, it indicates that the feature vector of the test chip does not match the cluster center of any known category. At this time, the clustering discrimination module determines the result as "unknown" and prompts the operator to manually review the chip through the host computer interface of the detection system.

[0054] While outputting the defect type, the clustering discrimination module also quantifies the severity level of the output defect based on the distance of the feature vector from the cluster center of the corresponding defect type cluster. Specifically, during the offline training phase, the clustering discrimination module statistically analyzes the feature vectors of all training samples under each defect type, calculates the weighted Euclidean distance from the feature vector of each training sample in that category to its cluster center, and calculates the mean and standard deviation of this distance. Based on this, the deviation distance is divided into three continuous numerical intervals: the first interval is greater than or equal to zero and ≤ "mean plus one standard deviation", corresponding to a mild level; the second interval is greater than "mean plus one standard deviation" and ≤ "mean plus two standard deviations", corresponding to a moderate level; and the third interval is greater than "mean plus two standard deviations", corresponding to a severe level. In actual online testing, the clustering discrimination module calculates the weighted Euclidean distance from the feature vector of the chip under test to the cluster center of its defect type cluster. It then determines which of the three intervals this distance falls into, outputting the corresponding severity level. The closer the deviation, the closer the chip's defect behavior is to the typical state of that type of defect, and the lower the severity level; the farther the deviation, the more severe the chip's defect behavior, and the higher the severity level. Through this process, the clustering discrimination module ultimately outputs a binary conclusion: whether the RF chip under test has internal defects, and if so, the type and severity level of the defect.

[0055] Optionally, the detection method may also include the following steps: S301, based on multi-dimensional characteristic parameters, inversely calculates the relative thermal impedance change between different regions of the RF chip under test; S302 determines and outputs the longitudinal distribution depth and / or lateral distribution area of ​​internal defects in the chip package based on the relative thermal resistance change.

[0056] The "extraction of multidimensional feature parameters for characterizing chip thermal response" in S103 includes the following sub-steps: Based on time-series data and spatial distribution data, a full-field thermal gradient vector field is constructed on the surface of the RF chip under test. Calculate the anisotropy index of the thermal gradient vector field across the entire field of view, and use the anisotropy index as one of the multidimensional characteristic parameters.

[0057] The step S302, "Determine and output the vertical distribution depth and / or lateral distribution area of ​​internal defects in the chip package," includes the following sub-steps: Determine the longitudinal distribution depth and / or lateral distribution area of ​​internal defects in the chip package. Based on the gradient rate of change of relative thermal resistance at the longitudinal distribution depth and / or the spatial distribution variance in the lateral distribution area, determine whether the physical properties of the internal defects are interface defects or bulk material defects. When the defect is determined to be an interface type, the output defect type is either a poor weld or a bond detachment; when the defect is determined to be a bulk material type, the output defect type is a microcrack.

[0058] S401 performs streamline tracing on the full field of view thermal gradient vector field to extract the positions of the confluence and / or bifurcation points in the thermal gradient vector field. Based on the location of the confluence and / or bifurcation points, determine the boundary profile of the heat flow blockage region of the internal defect in the chip package; Determine the lateral dimensions of the internal defects based on the boundary profile; Based on the spatial correspondence between the boundary contour and the longitudinal distribution depth and / or the lateral distribution area, the longitudinal distribution depth and / or the lateral distribution area determined in S302 are processed. The processing operation specifically includes: determining the longitudinal depth layer of the internal defect, and / or correcting the boundary of the lateral distribution area. The processing results of the processing operation will be output as the quantitative basis for the severity level.

[0059] In implementation, after extracting the multidimensional feature parameters in S103, the detection system proceeds to S201, where it calculates the relative thermal impedance changes between different regions of the RF chip under test based on the multidimensional feature parameters. This step is executed by the thermal impedance inversion module of the detection system. The basic principle of thermal impedance inversion is that differences in thermal impedance between different regions inside the chip lead to corresponding differences in the surface temperature field distribution: regions with higher thermal impedance (such as defective areas) experience impeded heat conduction and relatively higher surface temperatures; regions with lower thermal impedance (such as intact areas) experience smooth heat conduction and relatively lower surface temperatures. Based on this physical correspondence, the detection system uses the spatial distribution data extracted in step S103 (i.e., the temperature values ​​of each pixel in the thermal image under thermal equilibrium) as input. Based on a one-dimensional or two-dimensional thermal conduction model, it employs a regularized inversion algorithm (such as the Tikhonov regularization method or the conjugate gradient method) to solve the inverse problem of thermal conduction, thus inferring the surface temperature distribution of the chip into the thermal impedance distribution at various locations inside the chip package.

[0060] To complete the aforementioned inversion calculation, the detection system first needs to perform three-dimensional discretization of the internal space of the chip package. Specifically, the thermal impedance inversion module establishes a three-dimensional spatial coordinate system with the overall dimensions of the chip package under test as the boundary. The x and y axes are defined in the chip plane direction, and the z axis is defined in the chip thickness direction. During modeling, the thermal impedance inversion module divides the chip package into several tiny cubic or cuboid units in three-dimensional space, each unit being called a voxel. A voxel is the basic spatial unit constituting the three-dimensional thermal impedance distribution matrix. Each voxel has unique spatial coordinates (x, y, z), where the x and y coordinates correspond to the pixel position on the chip plane, and the z coordinate corresponds to the depth layer position in the chip thickness direction. The principle for setting the voxel size is: the voxel size in the planar direction should be consistent with or in an integer ratio to the pixel size in the thermal image acquired by the infrared thermal imager; an integer ratio means that the ratio of the voxel size to the pixel size is a positive integer greater than or equal to 1. When the scaling factor is 1, each voxel corresponds one-to-one with a pixel in the planar direction, meaning each pixel position independently constitutes a voxel. When the scaling factor is greater than 1 (e.g., 2), adjacent 2×2 pixels are merged into one voxel, and the temperature value of this voxel is the average temperature of these four pixels, in order to reduce data dimensionality and subsequent inversion calculations. In this embodiment, a scaling factor of 1 is preferably used, that is, maintaining consistency with the pixel size, to obtain the highest spatial resolution.

[0061] For example, if each pixel of an infrared thermal imager corresponds to a 5-micrometer × 5-micrometer physical area on the chip surface, then the dimensions of each voxel in the x and y directions are also set to 5 micrometers. The voxel dimensions in the thickness direction are set according to the total thickness and layered structure of the chip package. For example, if the total thickness of the chip is 300 micrometers and contains three layers of different materials, each layer can be further subdivided into several sub-layers along the thickness direction. The thickness of each sub-layer is the voxel dimension in the z direction, which is usually set to 10 to 20 micrometers to ensure that the thermal impedance differences of different depth layers can be distinguished. Through the above discretization, the entire chip package is divided into several voxels. The thermal impedance inversion module calculates the thermal impedance value at the location of each voxel, thereby obtaining the three-dimensional thermal impedance distribution matrix of the entire chip package.

[0062] After obtaining the three-dimensional thermal impedance distribution matrix, the thermal impedance inversion module uses the thermal impedance value of the defect-free region as a benchmark to calculate the relative difference between each voxel and the benchmark value, i.e., the relative thermal impedance change at that voxel location. The relative thermal impedance change is usually expressed as a percentage. For example, if the thermal impedance value of a voxel is 15% higher than the benchmark value, then the relative thermal impedance change of that voxel is +15%. The relative thermal impedance changes of each voxel are arranged according to their spatial coordinates to form a three-dimensional thermal impedance change distribution matrix. The spatial set of all voxels whose relative thermal impedance changes are significantly greater than zero in this matrix represents the regions with thermal impedance anomalies inside the chip. The distribution location and range of these regions are the direct data source for determining the longitudinal and lateral distribution areas of defects in the subsequent step S202.

[0063] After calculating the relative thermal impedance changes in each region in S201, the detection system proceeds to S202. Based on the relative thermal impedance changes, it determines and outputs the longitudinal distribution depth and / or lateral distribution area of ​​internal defects within the chip package. This step is still performed by the thermal impedance inversion module. The detection system arranges the relative thermal impedance changes of all voxels in three-dimensional space according to their spatial coordinates, forming a three-dimensional thermal impedance change distribution matrix. Subsequently, the detection system analyzes this three-dimensional distribution matrix: along the thickness direction of the chip package (i.e., longitudinally, scanning layer by layer from the chip surface to the bottom of the chip), it averages the relative thermal impedance changes of all voxels in each plane, obtaining an average thermal impedance change rate curve that varies along the depth direction. The depth layer where the peak value of the curve is located is the possible longitudinal distribution depth of the defect.

[0064] It should be noted that during the three-dimensional discretization process in step S201, the thermal impedance inversion module has divided the chip package into multiple discrete depth layers along the chip thickness direction (z-axis). The number of depth layers depends on the total thickness of the chip package and the preset vertical resolution requirement. Specifically, the thermal impedance inversion module divides the total thickness of the chip package by a preset layer thickness step size (e.g., 10 micrometers), and the integer part obtained is the total number of depth layers. The principle for setting the layer thickness step size is: while ensuring that the interfaces of each material layer of the chip can be distinguished, the layer thickness step size should not be greater than half the thickness of the thinnest material layer in the chip package to be tested, so as to avoid missing defects located at the thin layer interface due to excessive sampling interval. Taking a typical RF chip package as an example, its total thickness is usually 200 micrometers to 500 micrometers, including multiple materials such as chip substrate layer, solder layer, and substrate layer. If the preset layer thickness step size is 10 micrometers and the total thickness is 300 micrometers, then the total number of depth layers is 30, where the first layer corresponds to the chip surface position and the 30th layer corresponds to the chip bottom position. Each layer occupies a voxel height (i.e., 10 micrometers) along the z-axis, and all voxels within that layer have the same z-coordinate index. During layer-by-layer scanning, the detection system starts from layer 1 and sequentially calculates the arithmetic mean of the relative thermal resistance changes of all voxels in each layer until layer 30 is scanned, thus obtaining the average thermal resistance change rate curve along the depth direction. In this way, the meaning of layer-by-layer is clearly defined as follows: the chip package is divided into several discrete depth layers along the chip thickness direction with a fixed layer thickness step, and then each layer is analyzed sequentially according to its z-coordinate index from smallest to largest.

[0065] Meanwhile, within each plane, voxels whose relative thermal impedance changes exceed a preset threshold (this threshold is set by the operator between 5% and 15% based on the required detection accuracy; in this embodiment, it is preferably set to 10%) undergo spatial clustering analysis. A density clustering algorithm (such as the DBSCAN algorithm) is used to group spatially adjacent voxels whose changes all exceed the preset threshold into the same anomalous region. Then, the circumscribed rectangle or convex hull profile of this anomalous region on the plane is extracted as the lateral distribution area of ​​the defect on that plane. When using the DBSCAN algorithm for density clustering, the neighborhood radius Eps is set to the distance between the centers of two adjacent voxels (i.e., the voxel size), and the minimum sample size MinPts is set to 4. That is, when a voxel's neighborhood contains at least 4 voxels, the voxel is identified as a core point. All voxels reachable by density through the core point are grouped into the same cluster, and each cluster corresponds to an anomalous region.

[0066] If a defect appears only in a certain depth layer and the abnormal area in that layer is relatively concentrated, the detection system will only output the vertical distribution depth of that layer and the corresponding horizontal distribution area. If the defect spans multiple depth layers, the detection system will output the vertical distribution depth of each layer and its corresponding horizontal distribution area. If the defect has no horizontal distribution in a certain depth layer (i.e., there are no voxels exceeding the threshold in a certain layer plane), the detection system will only output the vertical distribution depth and will not output the horizontal distribution area of ​​that layer.

[0067] Through the above process, the detection system finally determines and outputs the vertical distribution depth and / or horizontal distribution area of ​​internal defects in the chip package, providing a spatial positioning reference for the physical property judgment in the subsequent step S302 and the boundary correction in the step S401.

[0068] In the process of extracting multidimensional feature parameters for characterizing the thermal response of the chip in S103, the detection system further extracts feature parameters related to the thermal gradient vector field from the spatial distribution data. Specifically, S103 includes the following sub-steps S301 and S302.

[0069] First, sub-step S301 is executed to construct the full-field thermal gradient vector field of the surface of the RF chip under test based on the time-series data and spatial distribution data. This step is performed by the vector field construction module of the detection system. The vector field construction module selects a frame of thermal image when the temperature field reaches thermal equilibrium as input. Each pixel in the thermal image contains the temperature value at that location. For each pixel in the thermal image, the vector field construction module calculates the spatial temperature derivative of that pixel in the horizontal direction (x direction) and the vertical direction (y direction), denoted as dT / dX and dT / dY, respectively. The spatial temperature derivative is calculated using the central difference method. That is, for a pixel located at coordinates (i,j), its horizontal derivative is the temperature value of the right adjacent pixel (i+1,j) minus the temperature value of the left adjacent pixel (i−1,j), divided by twice the pixel spacing. The vertical derivative is calculated similarly. The horizontal and vertical derivatives are combined into a two-dimensional vector (dT / dX, dT / dY), which is the thermal gradient vector of that pixel. Its direction points towards the direction of the fastest temperature increase, and its magnitude reflects the drastic degree of temperature change. This calculation is performed on each pixel in the thermal image to obtain the thermal gradient vector of each pixel within the entire field of view. The collection of all these vectors constitutes the full-field-of-view thermal gradient vector field of the surface of the RF chip under test.

[0070] After constructing the full-field thermal gradient vector field in S301, the detection system proceeds to S302 to calculate the anisotropy index of the full-field thermal gradient vector field and uses the anisotropy index as one of the multidimensional feature parameters. This step is still performed by the vector field construction module. The anisotropy index is used to quantify whether the distribution of the thermal gradient vector field in different directions is uniform. Its physical meaning is as follows: In a defect-free uniform chip, heat diffuses uniformly from the center of the heat source to the surroundings, and the thermal gradient amplitudes in each direction are roughly the same, so the thermal gradient vector field is isotropic. When there are defects inside the chip (especially bond detachment or microcracks), the thermal conductivity of the defect region decreases, and the heat is forced to travel along a specific path, resulting in a significant increase in the thermal gradient amplitude in some directions and a corresponding decrease in the thermal gradient amplitude in other directions, so the thermal gradient vector field is anisotropic.

[0071] The specific calculation method for the anisotropy index is as follows: First, count the thermal gradient directions of all pixels in the full field of view thermal gradient vector field, and divide the 0° to 360° directional range into multiple directional intervals according to a preset number of intervals (e.g., 36 intervals, each interval width is 10°); then, count the sum of the thermal gradient magnitudes of all pixels in each directional interval to obtain the heat flow intensity distribution in each direction; next, normalize the distribution so that its sum is 1, to obtain a directional probability distribution function; finally, calculate the Kullback-Leibler divergence between the directional probability distribution function and the uniform distribution (i.e., the probability in each direction is 1 / 36), and this divergence value is the anisotropy index.

[0072] The specific formula for calculating the Kullback-Leibler divergence is: KL(P||Q)=Σ_{θ=1}^{36} P(θ)·log2(P(θ) / Q(θ)), where P(θ) is the normalized probability value of the heat flux intensity in the θ-th directional interval, and Q(θ) is the probability value of uniform distribution in the θ-th directional interval (i.e., 1 / 36). When P(θ)=0, this contribution is directly set to 0 (i.e., 0·log2(0)=0). The calculation direction is from the directional distribution P to the uniform distribution Q. The larger the value, the greater the degree of deviation of the directional distribution from the uniform distribution, that is, the more significant the anisotropy.

[0073] The anisotropy index is a real number greater than or equal to 0. The closer the value is to 0, the closer the thermal gradient vector field is to isotropy, and the more uniform the internal structure of the chip. The larger the value, the more significant the anisotropy of the thermal gradient vector field, and the greater the possibility that defects inside the chip cause heat flow deflection. The calculated anisotropy index, as one of the multidimensional feature parameters, is input into the clustering discrimination model along with other features extracted in step S103 (such as the initial temperature rise rate, thermal time constant, etc.) for pattern recognition, providing an additional field feature dimension for subsequent defect discrimination. It should be noted that the number of direction intervals, normalization processing, and Kullback-Leibler divergence calculation mentioned above are all well-known mathematical operations in the field, and the detection system can directly call the corresponding numerical calculation library functions to complete them.

[0074] After determining and outputting the longitudinal distribution depth and / or lateral distribution area of ​​internal defects within the chip package in step S202, the detection system proceeds to step S302 to further analyze the determined defect location information to determine whether the physical properties of the defect are interface-type or bulk material-type defects. This step is performed by the physical property discrimination module of the detection system. The physical property discrimination module determines the physical properties of the defect based on the relative thermal impedance change obtained in step S202, the gradient rate of change in the longitudinal distribution depth direction, and / or the spatial distribution variance in the lateral distribution area.

[0075] Specifically, if vertical depth information is determined in S202, the physical property discrimination module extracts the relative thermal resistance change values ​​of each depth layer along the thickness direction of the chip package, forming a relative thermal resistance change rate curve that varies along the depth direction. Then, the first derivative of this curve is calculated to obtain the gradient rate of change of relative thermal resistance along the depth direction. The physical property discrimination module analyzes the shape of this gradient rate curve: if the gradient rate shows a significant step change at a certain depth interface (i.e., a sharp jump in the relative thermal resistance change between adjacent depth layers, for example, from 5% to 25%), it indicates that the defect is located at the interface between two different material layers, meaning the defect is an interface-type defect; if the gradient rate shows a continuous gradual change within the bulk material (i.e., the relative thermal resistance change changes slowly with increasing depth, without a step change), it indicates that the defect is located within the bulk material, meaning the defect is a bulk material-type defect.

[0076] Simultaneously or alternatively, if information about a lateral distribution area is determined in S202, the physical property discrimination module extracts the relative thermal impedance changes of all voxels within the lateral distribution area and calculates the spatial distribution variance of these changes. The physical property discrimination module compares this variance with a preset variance threshold: if the spatial distribution variance is greater than the preset variance threshold, it indicates that the thermal impedance change of the defect within the lateral area is relatively discrete and locally drastic. This distribution pattern usually corresponds to interface defects (such as clear boundaries of bond detachment areas and significant differences in thermal impedance between detached and intact areas); if the spatial distribution variance is less than or equal to the preset variance threshold, it indicates that the thermal impedance change of the defect within the lateral area is relatively uniform and changes gradually. This distribution pattern usually corresponds to bulk material defects (such as microcracks dispersed within the material, and relatively uniform thermal impedance changes throughout the entire area). The preset variance threshold is determined by the following statistical calibration method: During the offline training phase, multiple sets (e.g., no less than 30 sets) of sample chips known to be bulk material defects (i.e., microcracks) are acquired. The spatial distribution variance of the relative thermal resistance change in the lateral distribution area is extracted according to the same process as online detection. The arithmetic mean and standard deviation of these variance values ​​are calculated. Then, the preset variance threshold is calculated as arithmetic mean + 2 × standard deviation. As an optional implementation example, during the offline calibration of a batch of RF chips (model XXPA-001, infrared thermal imager pixel size 5μm), the variance values ​​of 30 bulk material defect samples were obtained. The calculated arithmetic mean was 2.3, and the standard deviation was 0.45. Therefore, the preset variance threshold calculated using the above formula is 2.3 + 2 × 0.45 = 3.2. In actual online testing, if the spatial distribution variance of the lateral distribution area of ​​a chip under test is greater than 3.2, the spatial distribution dispersion of the defect is determined to be significantly higher than that of typical bulk material defects, belonging to the interface type defect; if it is less than or equal to 3.2, it is determined to be a bulk material defect. It should be noted that this value of 3.2 is only valid for this specific chip model and testing environment. In actual operation, the threshold needs to be recalculated and determined based on the calibration samples under the current testing conditions (including chip model, infrared thermal imager spatial resolution, ambient temperature, etc.).

[0077] After completing the above judgment, the physical attribute discrimination module outputs the physical attribute discrimination result of the defect: when it is determined to be an interface type defect, it further outputs the defect type as poor solder joint or bond detachment: since both poor solder joint and bond detachment occur at the welding interface or bonding interface between the chip and the substrate, both belong to interface type defects, but whether it is poor solder joint or bond detachment needs to be further distinguished in combination with the lateral distribution area position determined in step S202 (poor solder joint usually manifests as local incomplete fusion inside the solder layer, and its lateral area is usually located directly below the pad; bond detachment manifests as the bonding wire separating from the pad, and its lateral area is usually located at the edge of the bonding pad or the bonding point. In actual implementation, the coordinate positions of each pad and bonding point in the chip layout and their corresponding spatial range (stored in polygon or polygon combination form) can be pre-stored in the knowledge base of the detection system. The specific method for determining overlap analysis is as follows: Calculate the percentage of overlap between the lateral distribution area determined in step S202 and the spatial range of each pad in the knowledge base, i.e., the overlap area divided by the total area of ​​the lateral distribution area. If the percentage of overlap is greater than a preset first threshold (e.g., 50%), and the distance between the geometric center of the lateral distribution area and the center of the pad is less than the pad radius, then the defect is determined to be a cold solder joint. If the percentage of overlap is greater than a preset second threshold (e.g., 50%), and the geometric center of the lateral distribution area is located in the edge region of the bonding point (i.e., more than 70% of the bonding point radius from the center of the bonding point but still within the bounded rectangle of the bonding point), then the defect is determined to be a bond detachment. The first and second thresholds are set by the operator within the same numerical range according to the actual detection accuracy requirements; in this embodiment, both are preferably set to 50%. When a bulk material defect is determined, the output defect type is a microcrack, because microcracks occur inside the chip bulk material and belong to bulk material defects. Through the above process, accurate identification of defect physical properties and refined output of defect types are achieved.

[0078] After outputting the anisotropy index as one of the multidimensional feature parameters in step S302, the detection system further utilizes the full-field thermal gradient vector field constructed in step S301 to perform in-depth thermal flow path analysis. This part is executed by the thermal flow topology analysis module of the detection system, specifically including the following sub-steps S401 to S405.

[0079] First, sub-step S401 is executed to perform streamline tracing on the full-field thermal gradient vector field, extracting the positions of confluence points and / or bifurcation points. The specific streamline tracing process is as follows: starting from several seed points in the central region of the heat source in the thermal image, the streamline extends step-by-step along the direction of the thermal gradient vector field (i.e., the direction of temperature increase). At each step, the streamline moves forward by a preset step size (e.g., one pixel spacing) along the thermal gradient vector direction of the current point. This process is repeated after reaching a new position until the chip edge is reached or the temperature gradient amplitude falls below a preset threshold, thus forming a streamline extending outward from the heat source. Repeating this tracing process for multiple seed points yields multiple heat flow paths covering the entire chip surface area.

[0080] The seed points mentioned above refer to the starting point for flow tracing. Their selection method is as follows: The thermal topology analysis module of the detection system first performs a global scan of the thermal image in thermal equilibrium to determine the highest temperature point within the entire field of view. This point corresponds to the center of the heat source inside the chip. Then, using this highest temperature point as the center, multiple pixels within a preset neighborhood range are selected as seed points. The principle for setting the neighborhood range is to cover all high-temperature pixels in the central region of the heat source. Typically, all pixels within a square window centered on the highest temperature point and with an odd number of pixels on each side (such as 5×5 or 7×7, the specific value can be adjusted according to the chip size and the spatial resolution adaptability of the infrared thermal imager) are selected as seed points. The number of seed points is the total number of pixels within this window; for example, a 5×5 window corresponds to 25 seed points, and a 7×7 window corresponds to 49 seed points. It should be noted that the more seed points there are, the denser the generated streamlines, and the higher the accuracy of subsequent extraction of confluence and bifurcation points. However, the computational load will also increase accordingly. In this embodiment, a 5×5 window is preferred, ensuring both accuracy and computational efficiency.

[0081] Based on the multiple heat flow paths obtained, the heat flow topology analysis module performs topology analysis on all heat flow paths: A heat flow path convergence point is defined as a point where multiple heat flow paths converge in space at the same location or within a very small region. This is characterized by the spacing between adjacent streamlines (i.e., heat flow paths; heat flow path and streamline are synonymous, both referring to a complete heat propagation trajectory curve traced from the seed point along the direction of the thermal gradient vector field) gradually decreasing to zero (i.e., less than one pixel spacing). A heat flow path bifurcation point is defined as a point where a single heat flow path splits into two or more branches. This is characterized by a sharp bifurcation of the streamline in the direction at that location, i.e., the angle of change of the streamline in the direction before and after the bifurcation point is greater than a preset angle threshold. This preset angle threshold is set by the operator according to the actual detection accuracy requirements, and is usually set between 45° and 90°. When the angle of change of the streamline in the direction before and after a certain location is greater than this threshold, it is determined that a sharp bifurcation occurs in the direction at that location. In this embodiment, the preset angle threshold is preferably set to 60°.

[0082] The extraction of the locations of the aforementioned confluence and bifurcation points employs a calculation method based on streamline geometry. For each streamline, the thermal-fluid topology analysis module calculates the following two quantitative indicators point-by-point along the streamline's extension direction: First, the curvature value at that point, i.e., the rate of change of the streamline direction along the arc length, reflecting the degree of curvature at that location; second, the distance between that point and other streamlines adjacent to it, i.e., the shortest Euclidean distance from that point to the adjacent streamline. After completing the above calculations, the thermal-fluid topology analysis module compares the curvature value at each point with the average curvature value of the streamline. When the curvature value at a point exceeds a preset multiple (e.g., twice) of the average curvature value of the streamline, it is determined that the curvature at that point has an "abnormal peak value." The value of the preset multiple directly affects the sensitivity of identifying confluence and bifurcation points: a multiple that is too low (e.g., less than 1.5 times) will cause a large number of normal curvature points to be misjudged as abnormal peak values, generating a large number of false alarms; a multiple that is too high (e.g., greater than 3 times) will miss confluence or bifurcation points with relatively gentle curvature changes that actually exist. Therefore, the preset multiplier is preferably set between 1.8 and 2.2 times, and in this embodiment, it is set to 2 times.

[0083] Simultaneously, the distance between adjacent streamlines at each point is compared with the average distance between adjacent streamlines. When the distance between adjacent streamlines at a point is less than half of the average, the point is determined to have a "minimum distance between adjacent streamlines". When both conditions are met at the same location (i.e., the point has both an abnormal curvature peak and a minimum distance between adjacent streamlines), the thermal flux topology analysis module determines the point as a convergence point or a bifurcation point. Further distinguishing between convergence and bifurcation points involves examining the streamline trends before and after the point. If multiple streamlines gradually converge before the point and gradually diverge after passing it, the point is a convergence point; if a single streamline splits into multiple branches at the point, the point is a bifurcation point.

[0084] After extracting the positions of the confluence points and / or bifurcation points in sub-step S401, the detection system proceeds to sub-step S402. Based on the positions of the confluence points and / or bifurcation points, the boundary contour of the heat flow obstruction region of the internal defect within the chip package is determined. The physical meaning of confluence points and bifurcation points is as follows: when the heat flow path encounters a defect region with increased thermal resistance during propagation, the heat flow cannot directly pass through this region and can only detour around the defect edge, thus forming a bifurcation point upstream of the defect (the heat flow is forced to divert and detour), and a confluence point downstream of the defect (the detoured heat flow re-converges). Therefore, the line connecting the spatial positions of the confluence points and bifurcation points constitutes the boundary contour of the defect region on a two-dimensional plane. The heat flow topology analysis module connects all confluence points and bifurcation points according to their spatial adjacency to form a closed curve, which is the boundary contour of the heat flow obstruction region.

[0085] After determining the boundary contour in sub-step S402, the detection system proceeds to sub-step S403 to determine the lateral dimensions of the internal defects based on the boundary contour. Specifically, after determining the defect boundary contour, the thermal flow topology analysis module calculates the maximum span of the contour in the horizontal direction (X direction) as the lateral width, the maximum span in the vertical direction (Y direction) as the lateral length, and simultaneously calculates the area enclosed by the boundary contour as a comprehensive quantitative value of the lateral dimension. These three indicators describe the lateral extent of the defect from different dimensions: lateral width and lateral length reflect the extent of the defect's extension in two orthogonal directions, suitable for assessing whether the defect extends along a specific direction (e.g., microcracks typically extend linearly along a certain direction); area reflects the overall coverage of the defect, suitable for comprehensively assessing the severity of the defect. The three indicators are calculated in parallel and output together for operators to select according to actual needs, with area serving as the primary basis for quantifying severity. This lateral dimension is output in units of pixels or calibrated physical dimensions (micrometers). A larger lateral dimension indicates a larger extent of the defect's distribution on the chip plane, and a higher degree of severity.

[0086] Simultaneously or after determining the lateral dimension in sub-step S403, the detection system proceeds to sub-step S404, whereby the longitudinal distribution depth and / or lateral distribution area determined in step S202 are processed based on the spatial correspondence between the boundary contour and the longitudinal distribution depth and / or lateral distribution area determined in step S202. It is important to emphasize that the output of step S202 may have three scenarios: only longitudinal distribution depth (the defect appears only in one depth layer), only lateral distribution area (the defect has a lateral distribution within a certain plane, but its longitudinal depth cannot be determined), and both. Sub-step S404 performs different processing for each of these three scenarios: If step S202 determines that there is a longitudinal distribution depth, the thermal flux topology analysis module projects the boundary contour determined in S402 in the depth direction. That is, it projects the planar region enclosed by the boundary contour downwards along the thickness direction to each depth layer, determines which depth layers the boundary contour covers, and thus determines the longitudinal depth layer of the defect. Specifically, the coordinates of all voxels within the boundary contour are spatially aligned with the three-dimensional thermal impedance variation distribution matrix obtained by inversion in step S202. The number of voxels covered by the boundary contour in each depth layer is counted, and one or more depth layers with the largest number of covered voxels are determined as the longitudinal depth layer of the defect. The "coarse depth" given in this processing operation S302 is refined into a "precise depth layer with boundary constraints".

[0087] If a lateral distribution area is determined in step S202, the heat flow topology analysis module spatially overlays and compares the boundary contour determined in S402 with the lateral distribution area determined in step S202. The boundary contour is the defect boundary directly depicted based on the geometric features of the heat flow path, with pixel-level accuracy. The lateral distribution area in step S202, however, is obtained based on thermal impedance threshold clustering, and its boundary is significantly affected by the threshold setting, resulting in relatively lower accuracy. The heat flow topology analysis module uses the boundary contour as a reference to correct the original boundary of the lateral distribution area: if the original boundary is inconsistent with the boundary contour, the boundary contour is used as the standard, and the boundary of the lateral distribution area is updated to the range defined by the boundary contour. This processing operation improves the lateral positioning accuracy of the defect from "threshold-dependent coarse positioning" to "geometrically precise pixel-level positioning."

[0088] If S202 determines both the longitudinal distribution depth and the lateral distribution area, the heat flow topology analysis module will perform both processing operations simultaneously, determining the longitudinal depth layer and correcting the boundary of the lateral distribution area.

[0089] After the above processing is completed in sub-step S404, the detection system proceeds to sub-step S405, outputting the processing results of the operations in sub-step S404 as the quantitative basis for the severity level. Specifically, the thermal flow topology analysis module uses the lateral dimensions (i.e., the lateral width, length, and / or area of ​​the defect) determined in sub-step S403, and the vertical depth layers (the number of depth layers covered by the defect and the specific location of each layer) and / or the boundary-corrected lateral distribution area (the corrected boundary range) determined in sub-step S404 as the quantitative basis for the severity level. These, along with the defect type output in step S104, are output to the detection system's host computer interface or database for reference by operators or the production line quality management system. A larger lateral dimension and more vertical depth layers crossed by the defect indicate a larger impact range of the defect within the chip package, and a higher severity level. These quantitative parameters, together with the severity level determined based on clustering distance in step S104, form a double confirmation, constituting a complete assessment of the defect severity. When forming double verification, the detection system processes the following logic: if the severity level determined based on cluster distance matches the severity level determined based on lateral size / vertical depth, then that level is output as the final severity level; if the two do not match (e.g., the cluster distance indicates mild severity but the lateral size is large), then the higher level is output as the final severity level to ensure the reliability of chip screening. Simultaneously, the host computer interface specially marks chips with inconsistent severity levels, prompting operators to manually verify those chips.

[0090] Optionally, the detection method may also include the following steps: S401, in the full field of view thermal gradient vector field, with the center of the heat source as the reference point, obtain the first temperature rise time series curve of the reference point; S402, obtain the second temperature rise time series curves of multiple sampling points other than the reference point in the full field of view thermal gradient vector field; S403, calculate the cross-correlation function of each second temperature rise time series curve relative to the first temperature rise time series curve, and extract the peak delay of each second temperature rise time series curve; S404, construct a delay distribution map based on the distribution of each peak delay on the surface of the RF chip under test; S405, extract the location and / or range of time delay anomaly areas from the time delay distribution map as location information for internal defects.

[0091] In implementation, after outputting the anisotropy index as one of the multidimensional feature parameters in step S302, the detection system further utilizes the full-field thermal gradient vector field constructed in step S301 to perform auxiliary localization analysis of internal defects in the chip based on heat propagation time delay. This part is executed by the time delay analysis module of the detection system, specifically including the following sub-steps S401 to S405.

[0092] First, sub-step S401 is executed. In the full-field thermal gradient vector field, with the center of the heat source as the reference point, the first temperature rise time-series curve of the reference point is acquired. This step is performed by the time delay analysis module of the detection system. The time delay analysis module first determines the location of the heat source center, performs a global scan of the thermal image in thermal equilibrium, and locates the highest temperature point in the full field of view, which corresponds to the center of the heat source inside the chip. The pixel location of this highest temperature point is determined as the reference point. Then, the time delay analysis module extracts the temperature value sequence of the reference point during the entire period of electrical excitation signal application from the temperature field time-series data acquired in step S102, and uses this sequence as the first temperature rise time-series curve. The first temperature rise time-series curve reflects the temperature rise process at the center of the heat source over time after heat is generated from the center of the heat source, and this curve serves as the reference benchmark for subsequent time delay analysis.

[0093] After obtaining the first temperature rise timing curve of the reference point in sub-step S401, the detection system proceeds to sub-step S402 to obtain the second temperature rise timing curves of multiple sampling points other than the reference point in the full-field thermal gradient vector field. This step is still executed by the time delay analysis module. The sampling points are selected as follows: in the full-field thermal gradient vector field, with the reference point as the center, multiple sampling points are selected along multiple directions (e.g., horizontal, vertical, and two diagonal directions, i.e., 0°, 45°, 90°, and 135°) according to a preset sampling interval (e.g., selecting one sampling point every 10 pixels); the number of sampling points in each direction depends on the chip size and the sampling interval. With the reference point as the center, starting from the reference point, the sampling points extend outwards along a certain direction at preset sampling intervals until the chip edge is reached; the total number of sampling points traversed is the number of sampling points in that direction. For example, if the chip surface has a horizontal pixel width of 640 pixels, the reference point is located at the center (i.e., at the 320th pixel), and the sampling interval is 10 pixels, then 32 sampling points can be collected from the reference point to the left edge and 32 sampling points to the right edge in the horizontal direction, for a total of 64 sampling points in the horizontal direction. The number of sampling points in the four directions may be different, and each direction is calculated independently.

[0094] Alternatively, all pixels within the entire field of view can be used as sampling points. The latter involves greater computational cost but yields a complete time delay distribution map. In this embodiment, it is preferable to select sampling points at equal intervals along multiple directions, centered on a reference point, to control computational load while ensuring analysis accuracy. For each sampling point, the time delay analysis module extracts the temperature value sequence of that sampling point from the temperature field time-series data acquired in step S102 during the entire period of electrical excitation signal application, and uses this sequence as the second temperature rise time-series curve for that sampling point. The second temperature rise time-series curve reflects the temperature rise process at that sampling point over time after heat propagates from the heat source center to the sampling point.

[0095] After obtaining the second temperature rise time-series curves for each sampling point in sub-step S402, the detection system proceeds to sub-step S403 to calculate the cross-correlation function of each second temperature rise time-series curve with respect to the first temperature rise time-series curve, and extract the peak time delay of each second temperature rise time-series curve. This step is still performed by the time delay analysis module. The physical meaning of the cross-correlation function is: to estimate the time delay of one signal relative to another by calculating the similarity between two signals at different time offsets. In this step, the cross-correlation function is used to calculate the propagation time required for heat to spread from the center of the heat source (reference point) to each sampling point. Specifically, the time delay analysis module denotes the first temperature rise time-series curve as T_ref(t) and the second temperature rise time-series curve of a certain sampling point as T_sample(t), and the cross-correlation function between the two is defined as: R(τ)=Σ_t[T_ref(t)×T_sample(t+τ)]; In this expression, τ is the time offset, representing the amount of translation of the second temperature rise time series curve relative to the first temperature rise time series curve on the time axis, and its value range is -τ. max to +τ max , where τ max This is the preset maximum time delay value (usually set to half of the total duration of the entire temperature rise process). R(τ) is the cross-correlation function value, reflecting the degree of similarity between the second temperature rise time series curve and the first temperature rise time series curve after shifting by τ.

[0096] After calculating the entire cross-correlation function curve, the time delay analysis module searches for the τ value corresponding to the maximum value on the curve. Before searching for the maximum value, the time delay analysis module first smooths the cross-correlation function curve (e.g., using moving average filtering or Gaussian filtering) to eliminate noise-induced glitches. When searching for the maximum value on the smoothed curve, if multiple highly similar peaks appear (i.e., the difference between peaks is less than a preset peak difference threshold, such as 5% of the maximum peak), the τ value corresponding to the first peak reached is taken as the peak delay to eliminate ambiguity caused by signal oscillation. This τ value is the peak delay of the temperature rise time series curve at the sampling point relative to the temperature rise time series curve at the reference point. The physical meaning of this peak delay is: the time required for heat to travel from the center of the heat source to the sampling point. The larger the peak delay, the longer the time required for heat to travel to that location, and the greater the possibility of anomalies in thermal resistance on the heat conduction path between that location and the center of the heat source.

[0097] After extracting the peak delay of each sampling point in sub-step S403, the detection system proceeds to sub-step S404 to construct a delay distribution map based on the distribution of each peak delay on the surface of the RF chip under test. This step is still performed by the delay analysis module. The delay analysis module associates the spatial coordinates (x, y) of each sampling point with its corresponding peak delay value, forming a discrete data point set on the chip plane. Then, spatial interpolation is performed on this discrete data point set to estimate the peak delay value at the location of the unsampled point. The spatial interpolation method can be inverse distance weighted interpolation or kriging interpolation: inverse distance weighted interpolation is suitable for cases where the sampling point distribution is relatively uniform and the interpolation region has no obvious anisotropy; it is simple to calculate and fast. Kriging interpolation is suitable for cases where the sampling point distribution is uneven and the data has spatial autocorrelation; it has higher interpolation accuracy but a larger computational load. In this embodiment, inverse distance weighted interpolation is preferably used. The weighting coefficient is the reciprocal of the square of the distance from the sampling point to the interpolation point. This means that when calculating the peak time delay value of the interpolation point, sampling points closer to that point have a greater influence. After interpolation, the time delay analysis module arranges the peak time delay values ​​of all locations within the entire field of view according to their spatial coordinates, forming a two-dimensional image, which is the time delay distribution map. In the time delay distribution map, the grayscale value or pseudo-color value of each pixel represents the peak time delay value at that location; higher brightness or darker color indicates a greater peak time delay at that location.

[0098] After constructing the time delay distribution map in sub-step S404, the detection system proceeds to sub-step S405 to extract the location and / or range of time delay anomaly regions from the time delay distribution map as location information for internal defects. This step is still performed by the time delay analysis module. The method for extracting time delay anomaly regions is as follows: First, the time delay analysis module calculates the mean (μ) and standard deviation (σ) of the peak time delay values ​​of all pixels in the time delay distribution map. Then, pixels with peak time delay values ​​greater than μ + k⋅σ are identified as time delay anomaly pixels, where k is a preset multiplier coefficient, set by the operator according to the actual detection sensitivity requirements, usually set between 2 and 3, and preferably set to 2 in this embodiment. The theoretical basis of this determination method is that the existence of defective regions (such as cold solder joints or microcracks) hinders the normal conduction of heat, causing the heat to arrive in the region significantly later than in the surrounding normal regions. Therefore, in the time delay distribution map, the peak time delay value is significantly higher than that of the surrounding regions. After identifying all delay-abnormal pixels, the delay analysis module uses a connected component labeling algorithm (e.g., using the 8-connectivity criterion, where a pixel is adjacent to pixels in its eight directions: top, bottom, left, right, upper left, upper right, lower left, and lower right) to cluster all delay-abnormal pixels, grouping adjacent pixels into a single delay-abnormal region. After clustering, the delay analysis module calculates the bounding rectangle or convex hull contour of each delay-abnormal region, serving as its location and extent description. The location information refers to the center coordinates or coordinate range of the region on the chip plane, while the extent information refers to the size of the bounding rectangle or the number of pixels. The delay analysis module outputs the location and / or extent of these delay-abnormal regions as auxiliary location information for internal defects. The auxiliary positioning information can be spatially compared and verified with the longitudinal distribution depth and lateral distribution area of ​​the defect determined based on thermal impedance inversion in step S202. If the two are basically consistent in spatial position (for example, the distance between the center position of the time delay anomaly area and the center position of the lateral distribution area determined in S202 is less than a preset distance threshold), they corroborate each other, enhancing the confidence of the defect positioning result. If there is a significant difference, the detection system marks the chip as "positioning result inconsistent, manual verification required" in the host computer interface, prompting the operator to further inspect the chip. The aforementioned preset distance threshold is set by the operator according to the chip size and detection accuracy requirements, and is usually set to 5% to 10% of the pixel width in the chip's planar direction. For example, when the pixel width of the chip surface in the horizontal direction is 640 pixels, the preset distance threshold can be set to 32 to 64 pixels. In this embodiment, it is preferred to set it to 5% of the pixel width in the chip's planar direction, i.e., 32 pixels.

[0099] Optionally, during the continuous application of the electrical excitation signal, the detection method further includes: Collect steady-state temperature distribution data of the surface temperature field of the radio frequency chip under test after it reaches thermal equilibrium. Extract temperature uniformity and / or thermal field symmetry indices from the surface of the radio frequency chip under test from steady-state temperature analysis data; Multidimensional feature parameters are input into a preset clustering discriminant model for pattern recognition, including: temperature uniformity index and / or thermal field symmetry index as part of the multi-feature parameters and input into the clustering discriminant model for pattern recognition.

[0100] In implementation, during step S102, while acquiring time-series and spatial distribution data of the temperature field, the detection system further acquires steady-state temperature distribution data of the surface of the RF chip under test after it reaches thermal equilibrium, and extracts temperature uniformity and / or thermal field symmetry indices as supplementary dimensions of multidimensional feature parameters. This part is executed by the feature extraction module of the detection system and specifically includes the following sub-steps.

[0101] First, during the continuous application of the electrical excitation signal, the feature extraction module determines in real time whether the temperature field has reached thermal equilibrium. The feature extraction module continuously monitors the temperature values ​​at multiple preset monitoring points in the temperature field (including the chip's geometric center and four corner points). When the temperature change rate at each monitoring point does not exceed 0.1°C / min within 30 consecutive seconds, the temperature field is determined to have reached thermal equilibrium. The aforementioned 30-second monitoring duration and the 0.1°C / min rate of change threshold are preferred parameters in this embodiment. These parameters can be adaptively adjusted by the operator according to the packaging form, size, and thermal capacity of the chip under test. For chips with larger package sizes or higher thermal capacities, the temperature change rate is slower, so the rate of change threshold can be appropriately relaxed (e.g., 0.2°C / min) or the monitoring duration extended (e.g., 60 seconds). For chips with smaller package sizes or lower thermal capacities, the temperature change rate is faster, so the rate of change threshold can be appropriately tightened (e.g., 0.05°C / min) or the monitoring duration shortened (e.g., 15 seconds). The operator can set these parameters within the above range according to actual testing requirements. As an alternative, the thermal equilibrium time of the chip under test at a preset excitation power can be determined experimentally in advance and stored in the detection system. During actual testing, maintaining the electrical excitation signal for the preset duration is considered to have reached thermal equilibrium. Once thermal equilibrium is determined, the feature extraction module obtains steady-state temperature distribution data from the most recently acquired frame of the infrared thermal imager, i.e., the temperature value matrix of each pixel in the entire field of view under thermal equilibrium conditions.

[0102] After acquiring steady-state temperature distribution data, the feature extraction module extracts the temperature uniformity index and / or thermal field symmetry index of the RF chip surface from the steady-state temperature distribution data.

[0103] The specific method for extracting the temperature uniformity index is as follows: The feature extraction module selects all pixels corresponding to the surface area of ​​the RF chip under test from the steady-state temperature distribution data, and forms a one-dimensional array with the temperature values ​​of these pixels. The arithmetic mean and standard deviation of all elements in this array are then calculated. The arithmetic mean reflects the overall temperature level of the chip surface, while the standard deviation reflects the dispersion of the temperature at various locations on the chip surface relative to the overall average. A smaller standard deviation indicates a more uniform temperature distribution on the chip surface; a larger standard deviation indicates the presence of localized areas with excessively high or low temperatures on the chip surface, resulting in poorer temperature uniformity. The feature extraction module outputs this standard deviation as the temperature uniformity index.

[0104] The specific extraction method for the thermal field symmetry index is as follows: The feature extraction module selects a frame of thermal image corresponding to the surface region of the RF chip under test from the steady-state temperature distribution data. Using the geometric center of this thermal image as the rotation center, the entire frame of thermal image is rotated 180° around this center in the plane. After rotation, the feature extraction module aligns the original thermal image and the rotated thermal image pixel by pixel, calculates the square of the temperature difference at each corresponding pixel position in the two images, and then sums the squared differences of all pixel positions and divides by the total number of pixels to obtain the mean square error (MSE) value. The smaller the MSE, the better the symmetry of the chip surface temperature field about the geometric center; the larger the MSE, the more asymmetrical the chip surface temperature field, which may indicate the presence of asymmetrical structural defects inside the chip (such as unilateral bond detachment). The feature extraction module outputs this MSE as the thermal field symmetry index.

[0105] After extracting the temperature uniformity index and / or thermal field symmetry index, the feature extraction module incorporates these indices as components of the multidimensional feature parameters. Specifically, based on the six feature parameters originally extracted in step S103 (i.e., initial temperature rise rate, thermal time constant, temperature uniformity, thermal field symmetry, number of anomalous hot spots, and curve fitting residual), the temperature uniformity index and / or thermal field symmetry index extracted in this step are added as supplementary features and incorporated into the multidimensional feature parameters.

[0106] It should be noted that the temperature uniformity and thermal field symmetry indices extracted here refer to the same features extracted in step S103. Step S103 has already mentioned extracting temperature uniformity and thermal field symmetry as one of the multidimensional feature parameters. This step elaborates on the specific extraction methods for these two features to more fully disclose their implementation details. The extraction operation performed in step S103 based on the same steady-state temperature distribution data is the extraction method described in this step (i.e., standard deviation and mean square error). The two are not mutually corroborating each other after extraction, but rather a detailed description of the same extraction operation in this step.

[0107] Finally, the detection system incorporates multi-dimensional feature parameters, including temperature uniformity and thermal field symmetry indices, into a pre-defined clustering discriminant model for pattern recognition. Specifically, the input feature vector of the clustering discriminant model contains six dimensions: initial temperature rise rate, thermal time constant, number of anomalous hot spots, curve fitting residual, temperature uniformity index extracted in this step, and thermal field symmetry index extracted in this step. These six dimensions together constitute the complete input feature vector.

[0108] This application also discloses a chip defect non-destructive testing system based on thermoelectric response characteristics. (Refer to...) Figure 2 ,include: The electrical excitation module 201 is used to apply a preset electrical excitation signal to the radio frequency chip under test so as to cause a non-destructive temperature rise in the radio frequency chip under test. Temperature acquisition module 202 is used to acquire time-series data and spatial distribution data of the temperature field change over time on the surface of the radio frequency chip under test during the application of the electrical excitation signal. Feature extraction module 203 is used to extract multidimensional feature parameters to characterize the thermal response characteristics of the chip based on the time series data and spatial distribution data; The clustering discrimination module 204 is used to input the multidimensional feature parameters into a preset clustering discrimination model for pattern recognition, so as to automatically determine whether the radio frequency chip under test has internal defects, and output the type and / or severity level of the internal defects when the internal defects exist.

[0109] This application also discloses a chip defect non-destructive testing device based on thermoelectric response characteristics. The chip defect non-destructive testing device based on thermoelectric response characteristics includes a memory and a processor. The memory stores a computer program that can be loaded by the processor and executed as described above for a chip defect non-destructive testing method based on thermoelectric response characteristics.

[0110] This application also discloses a computer-readable storage medium that stores a computer program that can be loaded by a processor and executed as described above for a non-destructive testing method for chip defects based on thermoelectric response characteristics. The computer-readable storage medium includes, for example, various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0111] It should be noted that in this paper, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0112] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit the scope of protection of the application. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on these embodiments, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

Claims

1. A non-destructive testing method for chip defects based on thermoelectric response characteristics, characterized in that, include: A preset electrical excitation signal is applied to the radio frequency chip under test to induce a non-destructive temperature rise in the chip. During the application of the electrical excitation signal, time-series data and spatial distribution data of the temperature field on the surface of the radio frequency chip under test are collected. Based on the time-series data and spatial distribution data, multidimensional feature parameters are extracted to characterize the thermal response of the chip. The multidimensional feature parameters are input into a preset clustering discrimination model for pattern recognition to automatically determine whether the radio frequency chip under test has internal defects, and output the type and / or severity level of the internal defects when they exist.

2. The chip defect non-destructive testing method based on thermoelectric response characteristics according to claim 1, characterized in that, The method further includes: Based on the multidimensional feature parameters, the relative thermal impedance change between different regions of the radio frequency chip under test is calculated by inversion. Based on the relative thermal resistance change, the longitudinal distribution depth and / or lateral distribution area of ​​the internal defects in the chip package are determined and output.

3. The non-destructive testing method for chip defects based on thermoelectric response characteristics according to claim 1, characterized in that, During the continuous application of the electrical excitation signal, the method further includes: Collect steady-state temperature distribution data of the surface temperature field of the radio frequency chip under test after it reaches thermal equilibrium. Extract the temperature uniformity index and / or thermal field symmetry index of the surface of the radio frequency chip under test from the steady-state temperature analysis data; The step of inputting the multidimensional feature parameters into a preset clustering discriminant model for pattern recognition includes: inputting the temperature uniformity index and / or thermal field symmetry index as part of the multidimensional feature parameters into the clustering discriminant model for pattern recognition.

4. The chip defect non-destructive testing method based on thermoelectric response characteristics according to claim 2, characterized in that, The extraction of multidimensional feature parameters for characterizing the thermal response of the chip includes: Based on the time series data and spatial distribution data, a full-field thermal gradient vector field is constructed on the surface of the radio frequency chip under test; Calculate the anisotropy index of the full-field thermal gradient vector field, and use the anisotropy index as one of the multidimensional feature parameters.

5. The non-destructive testing method for chip defects based on thermoelectric response characteristics according to claim 2, characterized in that, The process of determining and outputting the longitudinal distribution depth and / or lateral distribution region of the internal defects in the chip package includes: Determine the longitudinal distribution depth and / or lateral distribution area of ​​the internal defect in the chip package, and based on the gradient rate of change of the relative thermal resistance at the longitudinal distribution depth and / or the spatial distribution variance in the lateral distribution area, determine whether the physical property of the internal defect is an interface defect or a bulk material defect. When the defect is determined to be an interface type, the output defect type is either a poor weld or a bond detachment; when the defect is determined to be a bulk material type, the output defect type is a microcrack.

6. The chip defect nondestructive testing method based on thermoelectric response characteristics according to claim 4, characterized in that, The method further includes: Perform streamline tracing on the full field of view thermal gradient vector field to extract the positions of the confluence points and / or bifurcation points in the thermal gradient vector field; Based on the location of the confluence point and / or bifurcation point, determine the boundary contour of the heat flow obstruction region of the internal defect in the chip package; Based on the boundary profile, determine the lateral dimension of the internal defect; Based on the spatial correspondence between the boundary contour and the longitudinal distribution depth and / or the lateral distribution area, the longitudinal distribution depth and / or the lateral distribution area determined in claim 2 are processed. The processing operation specifically includes: determining the longitudinal depth layer of the internal defect, and / or correcting the boundary of the lateral distribution area. The processing result of the aforementioned processing operation is output as the quantitative basis for the severity level.

7. The chip defect nondestructive testing method based on thermoelectric response characteristics according to claim 4, characterized in that, The method further includes: In the full field of view thermal gradient vector field, with the center of the heat source as the reference point, the first temperature rise time series curve of the reference point is obtained; Obtain the second temperature rise time series curves of multiple sampling points other than the reference point in the full field of view thermal gradient vector field; Calculate the cross-correlation function of each of the second temperature rise time series curves relative to the first temperature rise time series curve, and extract the peak delay of each of the second temperature rise time series curves; Based on the distribution of each peak delay on the surface of the RF chip under test, a delay distribution map is constructed; The location and / or range of the time delay anomaly region are extracted from the time delay distribution map as the location information of the internal defect.

8. A chip defect nondestructive testing system based on thermoelectric response characteristics, characterized in that, include: The electrical excitation module (201) is used to apply a preset electrical excitation signal to the radio frequency chip under test so as to cause the radio frequency chip under test to generate a non-destructive temperature rise; The temperature acquisition module (202) is used to acquire time-series data and spatial distribution data of the temperature field on the surface of the radio frequency chip under test during the application of the electrical excitation signal. The feature extraction module (203) is used to extract multidimensional feature parameters to characterize the thermal response features of the chip based on the time-series data and spatial distribution data; The clustering discrimination module (204) is used to input the multidimensional feature parameters into a preset clustering discrimination model for pattern recognition, so as to automatically determine whether the radio frequency chip under test has internal defects, and output the type and / or severity level of the internal defects when the internal defects exist.

9. A non-destructive testing device for chip defects based on thermoelectric response characteristics, characterized in that, It includes a memory and a processor, wherein the memory stores a computer program that can be loaded by the processor and executed as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer program is stored that can be loaded by a processor and executed as described in any one of claims 1 to 7.

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