A spaceborne navigation signal fast continuation broadcasting method, device, equipment and medium

Abstract

The application relates to the technical field of satellite navigation payload design, and provides a satellite-borne navigation signal fast continuation playing method, device, equipment and medium. Through the characteristics that the anti-fuse type FPGA and the DSP have stronger anti-radiation capacity than the SRAM type FPGA, the anti-fuse type FPGA is used for local time calibration and the local time is maintained through period counting, the reliability of the local time is greatly improved, and the problem that the local time is recovered after a few seconds of reloading due to the influence of single particles after the traditional scheme adopts the SRAM type FPGA to maintain the local time is solved. The application combines the satellite navigation signal pseudo-code period characteristics and the hierarchical time maintenance mechanism, sets the time information sent by the anti-fuse type FPGA to the SRAM type FPGA to synchronize the satellite navigation signal pseudo-code period, and after the SRAM type FPGA is reset and reloaded due to single particle flip, the continuation playing of the navigation signal can be completed in a very short time.

Description

Technical Field

[0001] This application relates to the field of satellite navigation payload design technology, and in particular to a method, apparatus, equipment and medium for rapid rebroadcasting of satellite navigation signals. Background Technology

[0002] The navigation signal generation payload is a core component of a satellite navigation system. Based on an externally input 1PPS and 122.76MHz clock signal, it generates high-precision navigation signals and broadcasts them to the ground. It is the direct carrier for the satellite navigation system to provide services to a wide range of users, and its service continuity is directly related to the service performance of the satellite navigation system.

[0003] When navigation signal generation payloads are in orbit, they are susceptible to space radiation, resulting in single-event upsets (SEE). This can cause flips in the digital logic of SRAM-based FPGAs within the payload, leading to malfunctions. To address SEE, radiation hardening techniques such as triple-mode redundancy (TMR) and timed refresh are commonly employed. However, due to their hardware characteristics, SRAM-based FPGAs cannot be completely immune to radiation: TMR cannot harden resources such as IOI, IOB, GCLK, and BRAM interconnects within the SRAM-based FPGA, only CLB resources, and single points of failure often exist at the convergence points of the three modes; timed refresh has a certain time interval, which cannot eliminate the impact of SEE between refreshes. Once a critical module in an SRAM-based FPGA experiences a SEE, a reset and reload may be required to restore normal operation.

[0004] After the SRAM-type FPGA is reloaded, it restores the local time based on the externally input 1PPS and time synchronization information, and starts broadcasting the signal at the moment when the entire message is broadcast. This process often lasts for several seconds or even more than ten seconds, which seriously affects the continuity of satellite services. Summary of the Invention

[0005] Therefore, it is necessary to provide a method, apparatus, device, and medium for rapid re-broadcasting of spaceborne navigation signals that can significantly shorten the re-broadcasting time of navigation signals after reloading due to single-event upsets in SRAM-type FPGAs.

[0006] A method for rapid rebroadcast of spaceborne navigation signals, the method comprising: A navigation signal fast replay device based on a hierarchical time maintenance mechanism was constructed using an SRAM-type FPGA, a DSP, and an antifuse-type FPGA. The DSP receives external time synchronization commands and obtains local time information from the SRAM-type FPGA to obtain time synchronization information, and then sends the time synchronization information to the antifuse-type FPGA. The antifuse FPGA performs local time calibration based on the time synchronization information and maintains the local time through cycle counting; When the antifuse FPGA detects an anomaly in the SRAM FPGA, the antifuse FPGA sends a reset signal, load data, and time information to the SRAM FPGA to reset and reload the SRAM FPGA; the time information includes a millisecond pulse signal, a millisecond count, a second count, and a week count. The SRAM-type FPGA, based on the received time information and using a millisecond pulse signal as a time reference, determines the starting point for generating pseudocode for each signal component based on the millisecond count. Pseudocode is generated starting at each starting point. The DSP writes the navigation message into the SRAM-type FPGA and configures the message broadcast start position determined by the second and millisecond counts to the SRAM-type FPGA. At the message transmission time, the SRAM-type FPGA reads the navigation message from the message broadcast start position, modulates the message into pseudocode, and then performs carrier modulation to generate a satellite navigation signal.

[0007] In one embodiment, the time synchronization information includes a week count and a week-in-seconds count.

[0008] In one embodiment, the antifuse FPGA is configured with a 122.76MHz counter register, a millisecond counter register, a second counter register, a week counter register, a second counter configuration register, a week counter configuration register, and a time synchronization control register.

[0009] In one embodiment, the antifuse FPGA performs local time calibration based on the time synchronization information and maintains the local time through cycle counting, including: The antifuse FPGA synchronizes the week count and second count in the local time information with the week count and intra-week second count in the time synchronization information according to the time synchronization information; Each time a 122.76MHz clock signal arrives, the 122.76MHz counter register is incremented by 1. After the 122.76MHz counter register has counted for 1ms, it is cleared to zero, and the millisecond counter register is incremented by 1. After the millisecond counter register has counted for 1s, it is cleared to zero, and the second counter register is incremented by 1. After the second counter register has counted for one cycle, it is cleared to zero, and the cycle counter register is incremented by 1.

[0010] In one embodiment, the antifuse FPGA synchronizes the week count and second count in the local time information with the week count and intra-week second count in the time synchronization information according to the time synchronization information, including: The DSP delays the week-inclusive seconds count in the time synchronization information by 1 second, writes the week count and week-inclusive seconds count into the second count configuration register and week count configuration register of the antifuse FPGA, respectively, and enables the time synchronization control register of the antifuse FPGA, thereby controlling the antifuse FPGA to synchronize the values ​​of the second count register and week count register with the values ​​of the second count configuration register and week count configuration register.

[0011] In one embodiment, the SRAM-type FPGA, based on received time information and using a millisecond pulse signal as a time reference, determines the starting point for generating pseudocode for each signal component based on millisecond counts. Pseudocode generation begins at each starting point. The DSP writes the navigation message into the SRAM-type FPGA and configures the message broadcast start position determined by the second and millisecond counts to the SRAM-type FPGA. At the message transmission time, the SRAM-type FPGA reads the navigation message from the message broadcast start position, modulates the message into pseudocode, and then performs carrier modulation to generate a satellite navigation signal, including: The SRAM-type FPGA determines the periodicity type of the pseudocode based on the satellite navigation signal format; For pseudocode with a period of 1 millisecond, the SRAM-type FPGA detects the rising edge of the millisecond pulse and starts generating pseudocode through the code generation module to complete the rapid recovery of pseudocode. For pseudocode with a period greater than 1 millisecond, the SRAM-type FPGA pre-stores the pseudocode sequence in ROM. After detecting the rising edge of the millisecond pulse, the SRAM-type FPGA reads the millisecond count transmitted by the antifuse-type FPGA, and then calculates the code offset address of the pseudocode stored in ROM based on the millisecond count, the period of the pseudocode, and the code length of the pseudocode. The pseudocode sequence in ROM is read according to the code offset address until all the pseudocode in the current pseudocode period has been read, thus completing the rapid recovery of pseudocode. The DSP enables the signal generation channel of the SRAM-type FPGA and writes a message frame into the storage RAM of the SRAM-type FPGA via the EMIF bus. The DSP calculates the RAM read start address of the message based on the second count, millisecond count, message frame length, and symbol period, and configures the RAM read start address of the message to the SRAM-type FPGA via the EMIF bus. The SRAM-type FPGA reads the navigation message from the RAM starting address of the message at the time of message transmission and modulates the read navigation message into pseudocode. The SRAM-type FPGA performs carrier modulation on the modulated pseudo-code to generate satellite navigation signals.

[0012] In one embodiment, the pseudocode is modulated with subcodes, which are generated by pre-storing them in ROM.

[0013] A device for rapid replay of spaceborne navigation signals, the device comprising: The continuous wave device construction module is used to build a navigation signal rapid continuous wave device based on a hierarchical time maintenance mechanism, which is constructed from SRAM-type FPGA, DSP and antifuse-type FPGA. The time synchronization information acquisition module is used to receive external time synchronization instructions through the DSP and obtain local time information from the SRAM-type FPGA to obtain time synchronization information, and send the time synchronization information to the antifuse-type FPGA; A time correction and maintenance module is used for the antifuse FPGA to perform local time calibration based on the time calibration information and to maintain the local time through cycle counting; An anomaly calibration module is used to send a reset signal, load data, and time information to the SRAM-type FPGA when the antifuse-type FPGA detects an anomaly in the SRAM-type FPGA, so as to reset and reload the SRAM-type FPGA; the time information includes a millisecond pulse signal, a millisecond count, a second count, and a week count; The signal generation module is used by the SRAM-type FPGA to determine the starting point for generating pseudocode for each signal component based on the received time information and the millisecond pulse signal as the time reference. The DSP writes the navigation message into the SRAM-type FPGA and configures the message broadcast start position determined by the second count and millisecond count to the SRAM-type FPGA. At the message transmission time, the SRAM-type FPGA reads the navigation message from the message broadcast start position, modulates the message into pseudocode, and then performs carrier modulation to generate a satellite navigation signal.

[0014] A computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program performing the following steps: A navigation signal fast replay device based on a hierarchical time maintenance mechanism was constructed using an SRAM-type FPGA, a DSP, and an antifuse-type FPGA. The DSP receives external time synchronization commands and obtains local time information from the SRAM-type FPGA to obtain time synchronization information, and then sends the time synchronization information to the antifuse-type FPGA. The antifuse FPGA performs local time calibration based on the time synchronization information and maintains the local time through cycle counting; When the antifuse FPGA detects an anomaly in the SRAM FPGA, the antifuse FPGA sends a reset signal, load data, and time information to the SRAM FPGA to reset and reload the SRAM FPGA; the time information includes a millisecond pulse signal, a millisecond count, a second count, and a week count. The SRAM-type FPGA, based on the received time information and using a millisecond pulse signal as a time reference, determines the starting point for generating pseudocode for each signal component based on the millisecond count. Pseudocode is generated starting at each starting point. The DSP writes the navigation message into the SRAM-type FPGA and configures the message broadcast start position determined by the second and millisecond counts to the SRAM-type FPGA. At the message transmission time, the SRAM-type FPGA reads the navigation message from the message broadcast start position, modulates the message into pseudocode, and then performs carrier modulation to generate a satellite navigation signal.

[0015] A computer-readable storage medium having a computer program stored thereon, the computer program performing the following steps when executed by a processor: A navigation signal fast replay device based on a hierarchical time maintenance mechanism was constructed using an SRAM-type FPGA, a DSP, and an antifuse-type FPGA. The DSP receives external time synchronization commands and obtains local time information from the SRAM-type FPGA to obtain time synchronization information, and then sends the time synchronization information to the antifuse-type FPGA. The antifuse FPGA performs local time calibration based on the time synchronization information and maintains the local time through cycle counting; When the antifuse FPGA detects an anomaly in the SRAM FPGA, the antifuse FPGA sends a reset signal, load data, and time information to the SRAM FPGA to reset and reload the SRAM FPGA; the time information includes a millisecond pulse signal, a millisecond count, a second count, and a week count. The SRAM-type FPGA, based on the received time information and using a millisecond pulse signal as a time reference, determines the starting point for generating pseudocode for each signal component based on the millisecond count. Pseudocode is generated starting at each starting point. The DSP writes the navigation message into the SRAM-type FPGA and configures the message broadcast start position determined by the second and millisecond counts to the SRAM-type FPGA. At the message transmission time, the SRAM-type FPGA reads the navigation message from the message broadcast start position, modulates the message into pseudocode, and then performs carrier modulation to generate a satellite navigation signal.

[0016] The aforementioned method, apparatus, equipment, and medium for rapid replay of satellite navigation signals leverage the superior radiation resistance of antifuse FPGAs and DSPs compared to SRAM FPGAs. By employing an antifuse FPGA for local time calibration and maintaining the local time through period counting, the reliability of the local time is significantly improved. This solves the problem of traditional solutions using SRAM FPGAs for local time maintenance, where reloading after a single-event event requires several seconds to restore the local time. This invention combines the pseudo-code periodicity of satellite navigation signals with a hierarchical time maintenance mechanism. The time information sent from the antifuse FPGA to the SRAM FPGA includes millisecond pulse signals and millisecond counts to synchronize the pseudo-code period of the satellite navigation signal. Therefore, even after the SRAM FPGA experiences a reset and reload due to a single-event event, the navigation signal can be replayed in a very short time. Attached Figure Description

[0017] Figure 1 This is an application scenario diagram of a method for rapid rebroadcasting of spaceborne navigation signals in one embodiment; Figure 2 This is a flowchart illustrating a method for rapid rebroadcasting of satellite navigation signals in one embodiment; Figure 3 This is a schematic diagram of the structure of a navigation signal fast replay device in one embodiment; Figure 4 This is a schematic diagram of the process for maintaining the cycle count time in one embodiment; Figure 5 This is a structural block diagram of a satellite navigation signal rapid replay device in one embodiment; Figure 6 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0019] The rapid replay method for spaceborne navigation signals provided in this application can be applied to, for example... Figure 1 In the application environment shown, the satellite navigation system 104 broadcasts navigation signals to the user terminal 102. The terminal 102 can be, but is not limited to, various personal computers, laptops, smartphones, tablets, and portable wearable devices.

[0020] In one embodiment, such as Figure 2 As shown, a method for rapid replay of spaceborne navigation signals is provided, which can be applied to... Figure 1Taking the navigation signal generation payload of a satellite navigation system as an example, the following steps are included: Step 201: Construct a navigation signal fast replay device based on a hierarchical time maintenance mechanism, which is constructed from an SRAM-type FPGA, a DSP, and an antifuse-type FPGA.

[0021] A DSP (Digital Signal Processor) is a microprocessor specifically designed for digital signal processing.

[0022] Step 202: Receive the time synchronization command from the external input via the DSP and obtain the local time information from the SRAM-type FPGA to obtain the time synchronization information, and send the time synchronization information to the antifuse-type FPGA.

[0023] Step 203: The antifuse FPGA performs local time calibration based on the time synchronization information and maintains the local time through cycle counting.

[0024] Step 204: When the antifuse FPGA detects an abnormality in the SRAM FPGA, the antifuse FPGA sends a reset signal, load data, and time information to the SRAM FPGA to reset and reload the SRAM FPGA; the time information includes millisecond pulse signals, millisecond counts, second counts, and week counts.

[0025] Step 205: Based on the received time information, the SRAM-type FPGA uses the millisecond pulse signal as the time reference and determines the starting point for generating pseudocode for each signal component according to the millisecond count. Pseudocode is generated starting at each starting point. The DSP writes the navigation message into the SRAM-type FPGA and configures the message broadcast start position determined by the second count and millisecond count to the SRAM-type FPGA. At the message transmission time, the SRAM-type FPGA reads the navigation message from the message broadcast start position, modulates the message into pseudocode, and then performs carrier modulation to generate a satellite navigation signal.

[0026] In the aforementioned rapid replay method for satellite navigation signals, the superior radiation resistance of antifuse FPGAs and DSPs compared to SRAM FPGAs is utilized. An antifuse FPGA is used for local time calibration, and period counting is used to maintain the local time, significantly improving the reliability of the local time. This solves the problem of traditional solutions using SRAM FPGAs for local time maintenance, where reloading after a single-event event requires several seconds to restore the local time. This invention combines the pseudo-code periodicity of satellite navigation signals with a hierarchical time maintenance mechanism. The time information sent from the antifuse FPGA to the SRAM FPGA includes millisecond pulse signals and millisecond counts to synchronize the pseudo-code period of the satellite navigation signal. Therefore, even after the SRAM FPGA experiences a reset and reload due to a single-event event, the navigation signal can be replayed in a very short time.

[0027] In one embodiment, a navigation signal fast replay device based on a hierarchical time-maintenance mechanism, constructed from an SRAM-type FPGA, a DSP, and an antifuse-type FPGA, is described as follows: Figure 3 As shown.

[0028] In one embodiment, the time synchronization information includes a week count and a week-in-seconds count.

[0029] In this embodiment, the time synchronization information includes week count and second count within the week, so that the antifuse FPGA can synchronize a clock more than one second when performing local time calibration based on the time synchronization information.

[0030] In one embodiment, the antifuse FPGA is configured with a 122.76MHz counter register, a millisecond counter register, a second counter register, a week counter register, a second counter configuration register, a week counter configuration register, and a time synchronization control register.

[0031] In one embodiment, reference Figure 4 In step 203, the antifuse FPGA performs local time calibration based on the time synchronization information and maintains the local time through cycle counting, including: Step 2031: The antifuse FPGA synchronizes the week count and second count in the local time information with the week count and intra-week second count in the time synchronization information according to the time synchronization information; Step 2032: After each arrival of the 122.76MHz clock signal, the 122.76MHz counter register is incremented by 1. After the 122.76MHz counter register has counted for 1ms, it is cleared to zero, and the millisecond counter register is incremented by 1. After the millisecond counter register has counted for 1s, it is cleared to zero, and the second counter register is incremented by 1. After the second counter register has counted for 1 cycle, it is cleared to zero, and the week counter register is incremented by 1.

[0032] In one embodiment, in step 2031, the antifuse FPGA synchronizes the week count and second count in the local time information with the week count and intra-week second count in the time synchronization information according to the time synchronization information, including: The DSP delays the week-inclusive seconds count in the time synchronization information by 1 second, writes the week count and week-inclusive seconds count into the second count configuration register and week count configuration register of the antifuse FPGA, respectively, and enables the time synchronization control register of the antifuse FPGA, controlling the antifuse FPGA to synchronize the values ​​of the second count register and week count register with the values ​​of the second count configuration register and week count configuration register.

[0033] When the week count in the time synchronization information is 604799, the week count in the time synchronization information output by the DSP is incremented by 1, and the week count is cleared to zero.

[0034] In one embodiment, the antifuse-type FPGA performs local time calibration based on time synchronization information and maintains the local time through cycle counting, and further includes: When a 1PPS signal is input, the millisecond count register is cleared.

[0035] In this embodiment, when a 1PPS signal is input, the antifuse FPGA uses the input 122.76MHz clock signal to generate a local 1PPS signal and a millisecond pulse signal, and synchronizes the locally generated 1PPS signal with the input 1PPS signal. At the same time, the millisecond count register is cleared to synchronize the clock for seconds.

[0036] In one embodiment, the timing information also includes a 1PPS signal.

[0037] In one embodiment, in step 205, the SRAM-type FPGA, based on the received time information and using a millisecond pulse signal as a time reference, determines the starting point for generating pseudocode for each signal component according to the millisecond count. Pseudocode generation begins at each starting point. The DSP writes the navigation message into the SRAM-type FPGA and configures the message broadcast start position determined by the second and millisecond counts to the SRAM-type FPGA. At the message transmission time, the SRAM-type FPGA reads the navigation message from the message broadcast start position, modulates the message into pseudocode, and then performs carrier modulation to generate a satellite navigation signal, including: Step 2051: The SRAM-type FPGA determines the period type of the pseudocode based on the satellite navigation signal format.

[0038] Step 2052: For pseudo-code with a period of 1 millisecond, after the SRAM-type FPGA detects the rising edge of the millisecond pulse, it starts generating pseudo-code through the code generation module to complete the rapid recovery of pseudo-code. For pseudo-code with a period greater than 1 millisecond, the SRAM-type FPGA pre-stores the pseudo-code sequence in ROM. After the SRAM-type FPGA detects the rising edge of the millisecond pulse, it reads the millisecond count transmitted from the antifuse-type FPGA. Then, based on the millisecond count, the period of the pseudo-code, and the code length of the pseudo-code, it calculates the code offset address of the pseudo-code stored in ROM. Based on the code offset address, it reads the pseudo-code sequence in ROM until all the pseudo-code within the current pseudo-code period has been read, thus completing the rapid recovery of pseudo-code.

[0039] The SRAM-based FPGA incorporates a chip read address offset register.

[0040] Step 2053: The DSP enables the signal generation channel of the SRAM-type FPGA and writes a message frame into the storage RAM of the SRAM-type FPGA via the EMIF bus.

[0041] Step 2054: The DSP calculates the RAM read start address of the message based on the second count, millisecond count, message frame length and symbol period, and configures the RAM read start address of the message to the SRAM type FPGA through the EMIF bus.

[0042] Step 2055: At the time of message transmission, the SRAM-type FPGA reads the navigation message from the RAM starting address of the message and modulates the read navigation message into pseudocode.

[0043] Step 2056: The SRAM-type FPGA performs carrier modulation on the modulated pseudo-code to generate a satellite navigation signal.

[0044] In one embodiment, in a B1C signal message with a frame length of 1800 symbol bits, a symbol period of 10 milliseconds, and a broadcast period of 18 seconds, after the signal generation channel of the SRAM-type FPGA is activated, the DSP writes 1800 bits of message into the RAM of the SRAM-type FPGA. At this time, the second count is 34 and the millisecond count is 782. First, the second count is modulo 18 according to the message broadcast period, the integer period is removed, leaving 16 seconds, and then 782 milliseconds are added to calculate the message offset duration as 16782 milliseconds. According to the symbol period, the message read start address is calculated as 16782 / 10 = 1678.2, which is rounded to obtain the message read start address as 1678. After the SRAM-type FPGA detects the rising edge of the millisecond pulse, the SRAM-type FPGA reads the message from the RAM at the 1678th message symbol, completing the rapid recovery of the message.

[0045] In one embodiment, the SRAM-type FPGA pre-stores a pseudo-code sequence in the ROM. The pseudo-code sequence is a B1C code with a period of 10 milliseconds and a code length of 10230. 10ms contains 10230 code chips, therefore there are 1023 pseudo-code sequences per millisecond. After detecting the rising edge of the millisecond pulse, the SRAM-type FPGA reads a millisecond count value of 236. It modulo-10 the millisecond count value according to the period, removes the integer period, and calculates the code offset duration as 6 milliseconds. Then, based on the period and code length of the B1C code, it calculates the code offset address corresponding to the 6-millisecond offset duration as 10230 / 10×6 = 6138. The SRAM-type FPGA reads the ROM from the 6138th bit until it reaches 10230, completing the rapid recovery of the pseudo-code. In the next 10ms, it starts reading again from 0.

[0046] In one embodiment, the pseudocode is modulated with subcodes, which are generated by pre-storing them in ROM, and the recovery method is the same as the processing method for pseudocode periods exceeding 1ms.

[0047] The subcode is also a periodically repeating code, with each code typically having a width of 10ms. Since the specific content of the subcode is known, it can be pre-stored in the ROM of an SRAM-type FPGA and then read. Based on the current millisecond count, the code offset address of the subcode at the current moment is calculated, and the subcode is read from the ROM according to the code offset address.

[0048] It should be understood that, although Figure 2 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 2 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0049] In one embodiment, such as Figure 5 As shown, a device for rapid replay of spaceborne navigation signals is provided, comprising: The re-wave device construction module 901 is used to build a navigation signal rapid re-play device based on a hierarchical time maintenance mechanism, which is constructed from SRAM-type FPGA, DSP and antifuse-type FPGA.

[0050] The time synchronization information acquisition module 902 is used to receive external time synchronization instructions through the DSP and obtain local time information from the SRAM-type FPGA to obtain time synchronization information, and then send the time synchronization information to the antifuse-type FPGA.

[0051] The time correction and maintenance module 903 is used by the antifuse FPGA to perform local time calibration based on the time calibration information and maintain the local time through cycle counting.

[0052] The anomaly calibration module 904 is used to send a reset signal, load data and time information to the SRAM FPGA when the antifuse FPGA detects an anomaly in the SRAM FPGA in order to reset and reload the SRAM FPGA; the time information includes millisecond pulse signal, millisecond count, second count and week count.

[0053] The signal generation module 905 uses the received time information and the millisecond pulse signal as the time reference. It determines the starting point for generating pseudocode for each signal component based on the millisecond count. The DSP writes the navigation message into the SRAM FPGA and configures the message broadcast start position determined by the second and millisecond counts to the SRAM FPGA. At the message transmission time, the SRAM FPGA reads the navigation message from the message broadcast start position, modulates the message into pseudocode, and then performs carrier modulation to generate the satellite navigation signal.

[0054] In one embodiment, the time synchronization information includes a week count and a week-in-seconds count.

[0055] In one embodiment, the antifuse FPGA is configured with a 122.76MHz counter register, a millisecond counter register, a second counter register, a week counter register, a second counter configuration register, a week counter configuration register, and a time synchronization control register.

[0056] In one embodiment, the antifuse FPGA performs local time calibration based on time synchronization information and maintains the local time through cycle counting, including: The antifuse type FPGA synchronizes the week count and second count in the local time information with the week count and second count within the week in the time synchronization information based on the time synchronization information; Each time the 122.76MHz clock signal arrives, the 122.76MHz counter register is incremented by 1. After the 122.76MHz counter register has counted for 1ms, it is cleared to zero, and the millisecond counter register is incremented by 1. After the millisecond counter register has counted for 1s, it is cleared to zero, and the second counter register is incremented by 1. After the second counter register has counted for one cycle, it is cleared to zero, and the week counter register is incremented by 1.

[0057] In one embodiment, the antifuse FPGA synchronizes the week count and second count in the local time information with the week count and intra-week second count in the time synchronization information based on the time synchronization information, including: The DSP delays the week-inclusive seconds count in the time synchronization information by 1 second, writes the week count and week-inclusive seconds count into the second count configuration register and week count configuration register of the antifuse FPGA, respectively, and enables the time synchronization control register of the antifuse FPGA, controlling the antifuse FPGA to synchronize the values ​​of the second count register and week count register with the values ​​of the second count configuration register and week count configuration register.

[0058] In one embodiment, the antifuse-type FPGA performs local time calibration based on time synchronization information and maintains the local time through cycle counting, and further includes: When a 1PPS signal is input, the millisecond count register is cleared.

[0059] In one embodiment, the timing information also includes a 1PPS signal.

[0060] In one embodiment, the SRAM-type FPGA, based on received time information and using a millisecond pulse signal as a time reference, determines the starting point for generating pseudocode for each signal component based on millisecond counts. Pseudocode generation begins at each starting point. The DSP writes the navigation message into the SRAM-type FPGA and configures the message broadcast start position determined by the second and millisecond counts to the SRAM-type FPGA. At the message transmission time, the SRAM-type FPGA reads the navigation message from the message broadcast start position, modulates the message into pseudocode, and then performs carrier modulation to generate a satellite navigation signal, including: SRAM-based FPGAs determine the period type of pseudocode based on the satellite navigation signal format.

[0061] For pseudocode with a period of 1 millisecond, the SRAM-type FPGA detects the rising edge of the millisecond pulse and starts generating pseudocode through the code generation module to complete the rapid recovery of pseudocode. For pseudocode with a period greater than 1 millisecond, the SRAM-type FPGA pre-stores the pseudocode sequence in ROM. After detecting the rising edge of the millisecond pulse, the SRAM-type FPGA reads the millisecond count transmitted from the antifuse FPGA, and then calculates the code offset address of the pseudocode stored in ROM based on the millisecond count, the period of the pseudocode, and the code length of the pseudocode. The pseudocode sequence in ROM is then read according to the code offset address until all the pseudocode in the current pseudocode period has been read, thus completing the rapid recovery of pseudocode.

[0062] The SRAM-based FPGA incorporates a chip read address offset register.

[0063] The DSP enables the signal generation channel of the SRAM-type FPGA and writes a message frame into the storage RAM of the SRAM-type FPGA via the EMIF bus.

[0064] The DSP calculates the RAM read start address of the message based on the second count, millisecond count, message frame length, and symbol period, and configures the RAM read start address of the message to the SRAM-type FPGA via the EMIF bus.

[0065] SRAM-type FPGAs read the navigation message from the starting address of the message's RAM at the time of message transmission and modulate the read navigation message into pseudocode.

[0066] The SRAM-based FPGA performs carrier modulation on the modulated pseudo-code to generate satellite navigation signals.

[0067] In one embodiment, the pseudocode is modulated with subcodes, which are generated by pre-storing them in ROM, and the recovery method is the same as the processing method for pseudocode periods exceeding 1ms.

[0068] Specific limitations regarding the rapid re-broadcast device for spaceborne navigation signals can be found in the limitations of the rapid re-broadcast method for spaceborne navigation signals described above, and will not be repeated here. Each module in the aforementioned rapid re-broadcast device for spaceborne navigation signals can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the corresponding operations of each module.

[0069] In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 6 As shown, the computer device includes a processor, memory, network interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The network interface is used to communicate with external terminals via a network connection. When the computer program is executed by the processor, it implements a method for rapid replay of satellite navigation signals. The display screen can be an LCD screen or an e-ink screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad mounted on the computer device casing, or an external keyboard, touchpad, or mouse.

[0070] Those skilled in the art will understand that Figure 6 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0071] In one embodiment, a computer device is provided, including a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement the steps of the method described above.

[0072] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, the computer program performing the following steps when executed by a processor: Step 201: Construct a navigation signal fast replay device based on a hierarchical time maintenance mechanism, which is constructed from an SRAM-type FPGA, a DSP, and an antifuse-type FPGA.

[0073] Step 202: Receive the time synchronization command from the external input via the DSP and obtain the local time information from the SRAM-type FPGA to obtain the time synchronization information, and send the time synchronization information to the antifuse-type FPGA.

[0074] Step 203: The antifuse FPGA performs local time calibration based on the time synchronization information and maintains the local time through cycle counting.

[0075] Step 204: When the antifuse FPGA detects an abnormality in the SRAM FPGA, the antifuse FPGA sends a reset signal, load data, and time information to the SRAM FPGA to reset and reload the SRAM FPGA; the time information includes millisecond pulse signals, millisecond counts, second counts, and week counts.

[0076] Step 205: Based on the received time information, the SRAM-type FPGA uses the millisecond pulse signal as the time reference and determines the starting point for generating pseudocode for each signal component according to the millisecond count. Pseudocode is generated starting at each starting point. The DSP writes the navigation message into the SRAM-type FPGA and configures the message broadcast start position determined by the second count and millisecond count to the SRAM-type FPGA. At the message transmission time, the SRAM-type FPGA reads the navigation message from the message broadcast start position, modulates the message into pseudocode, and then performs carrier modulation to generate a satellite navigation signal.

[0077] In one embodiment, the time synchronization information includes a week count and a week-in-seconds count.

[0078] In one embodiment, the antifuse FPGA is configured with a 122.76MHz counter register, a millisecond counter register, a second counter register, a week counter register, a second counter configuration register, a week counter configuration register, and a time synchronization control register.

[0079] In one embodiment, the antifuse FPGA performs local time calibration based on time synchronization information and maintains the local time through cycle counting, including: The antifuse type FPGA synchronizes the week count and second count in the local time information with the week count and second count within the week in the time synchronization information based on the time synchronization information; Each time the 122.76MHz clock signal arrives, the 122.76MHz counter register is incremented by 1. After the 122.76MHz counter register has counted for 1ms, it is cleared to zero, and the millisecond counter register is incremented by 1. After the millisecond counter register has counted for 1s, it is cleared to zero, and the second counter register is incremented by 1. After the second counter register has counted for one cycle, it is cleared to zero, and the week counter register is incremented by 1.

[0080] In one embodiment, in step 2031, the antifuse FPGA synchronizes the week count and second count in the local time information with the week count and intra-week second count in the time synchronization information according to the time synchronization information, including: The DSP delays the week-inclusive seconds count in the time synchronization information by 1 second, writes the week count and week-inclusive seconds count into the second count configuration register and week count configuration register of the antifuse FPGA, respectively, and enables the time synchronization control register of the antifuse FPGA, controlling the antifuse FPGA to synchronize the values ​​of the second count register and week count register with the values ​​of the second count configuration register and week count configuration register.

[0081] In one embodiment, the antifuse-type FPGA performs local time calibration based on time synchronization information and maintains the local time through cycle counting, and further includes: When a 1PPS signal is input, the millisecond count register is cleared.

[0082] In one embodiment, the timing information also includes a 1PPS signal.

[0083] In one embodiment, in step 205, the SRAM-type FPGA, based on the received time information and using a millisecond pulse signal as a time reference, determines the starting point for generating pseudocode for each signal component according to the millisecond count. Pseudocode generation begins at each starting point. The DSP writes the navigation message into the SRAM-type FPGA and configures the message broadcast start position determined by the second and millisecond counts to the SRAM-type FPGA. At the message transmission time, the SRAM-type FPGA reads the navigation message from the message broadcast start position, modulates the message into pseudocode, and then performs carrier modulation to generate a satellite navigation signal, including: Step 2051: The SRAM-type FPGA determines the period type of the pseudocode based on the satellite navigation signal format.

[0084] Step 2052: For pseudo-code with a period of 1 millisecond, after the SRAM-type FPGA detects the rising edge of the millisecond pulse, it starts generating pseudo-code through the code generation module to complete the rapid recovery of pseudo-code. For pseudo-code with a period greater than 1 millisecond, the SRAM-type FPGA pre-stores the pseudo-code sequence in ROM. After the SRAM-type FPGA detects the rising edge of the millisecond pulse, it reads the millisecond count transmitted from the antifuse-type FPGA. Then, based on the millisecond count, the period of the pseudo-code, and the code length of the pseudo-code, it calculates the code offset address of the pseudo-code stored in ROM. Based on the code offset address, it reads the pseudo-code sequence in ROM until all the pseudo-code within the current pseudo-code period has been read, thus completing the rapid recovery of pseudo-code.

[0085] The SRAM-based FPGA incorporates a chip read address offset register.

[0086] Step 2053: The DSP enables the signal generation channel of the SRAM-type FPGA and writes a message frame into the storage RAM of the SRAM-type FPGA via the EMIF bus.

[0087] Step 2054: The DSP calculates the RAM read start address of the message based on the second count, millisecond count, message frame length and symbol period, and configures the RAM read start address of the message to the SRAM type FPGA through the EMIF bus.

[0088] Step 2055: At the time of message transmission, the SRAM-type FPGA reads the navigation message from the RAM starting address of the message and modulates the read navigation message into pseudocode.

[0089] Step 2056: The SRAM-type FPGA performs carrier modulation on the modulated pseudo-code to generate a satellite navigation signal.

[0090] In one embodiment, the pseudocode is modulated with subcodes, which are generated by pre-storing them in ROM, and the recovery method is the same as the processing method for pseudocode periods exceeding 1ms.

[0091] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0092] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0093] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for rapid rebroadcasting of spaceborne navigation signals, characterized in that, The method includes: A navigation signal fast replay device based on a hierarchical time maintenance mechanism was constructed using an SRAM-type FPGA, a DSP, and an antifuse-type FPGA. The DSP receives external time synchronization commands and obtains local time information from the SRAM-type FPGA to obtain time synchronization information, and then sends the time synchronization information to the antifuse-type FPGA. The antifuse FPGA performs local time calibration based on the time synchronization information and maintains the local time through cycle counting; When the antifuse FPGA detects an anomaly in the SRAM FPGA, the antifuse FPGA sends a reset signal, load data, and time information to the SRAM FPGA to reset and reload the SRAM FPGA; the time information includes a millisecond pulse signal, a millisecond count, a second count, and a week count. The SRAM-type FPGA, based on the received time information and using a millisecond pulse signal as a time reference, determines the starting point for generating pseudocode for each signal component based on the millisecond count. Pseudocode is generated starting at each starting point. The DSP writes the navigation message into the SRAM-type FPGA and configures the message broadcast start position determined by the second and millisecond counts to the SRAM-type FPGA. At the message transmission time, the SRAM-type FPGA reads the navigation message from the message broadcast start position, modulates the message into pseudocode, and then performs carrier modulation to generate a satellite navigation signal.

2. The method according to claim 1, characterized in that, The time synchronization information includes week count and week-in-second count.

3. The method according to claim 2, characterized in that, The antifuse FPGA is configured with a 122.76MHz counter register, a millisecond counter register, a second counter register, a week counter register, a second counter configuration register, a week counter configuration register, and a time synchronization control register.

4. The method according to claim 3, characterized in that, The antifuse FPGA performs local time calibration based on the time synchronization information and maintains the local time through cycle counting, including: The antifuse FPGA synchronizes the week count and second count in the local time information with the week count and intra-week second count in the time synchronization information according to the time synchronization information; Each time a 122.76MHz clock signal arrives, the 122.76MHz counter register is incremented by 1. After the 122.76MHz counter register has counted for 1ms, it is cleared to zero, and the millisecond counter register is incremented by 1. After the millisecond counter register has counted for 1s, it is cleared to zero, and the second counter register is incremented by 1. After the second counter register has counted for one cycle, it is cleared to zero, and the cycle counter register is incremented by 1.

5. The method according to claim 4, characterized in that, The antifuse FPGA synchronizes the week count and second count in the local time information with the week count and intra-week second count in the time synchronization information according to the time synchronization information, including: The DSP delays the week-inclusive seconds count in the time synchronization information by 1 second, writes the week count and week-inclusive seconds count into the second count configuration register and week count configuration register of the antifuse FPGA, respectively, and enables the time synchronization control register of the antifuse FPGA, thereby controlling the antifuse FPGA to synchronize the values ​​of the second count register and week count register with the values ​​of the second count configuration register and week count configuration register.

6. The method according to claim 1, characterized in that, The SRAM-type FPGA, based on received time information and using a millisecond pulse signal as a time reference, determines the starting point for generating pseudocode for each signal component according to the millisecond count. Pseudocode generation begins at each starting point. The DSP writes the navigation message into the SRAM-type FPGA and configures the message broadcast start position determined by the second and millisecond counts to the SRAM-type FPGA. At the message transmission time, the SRAM-type FPGA reads the navigation message from the message broadcast start position, modulates the message into pseudocode, and then performs carrier modulation to generate a satellite navigation signal, including: The SRAM-type FPGA determines the periodicity type of the pseudocode based on the satellite navigation signal format; For pseudocode with a period of 1 millisecond, the SRAM-type FPGA detects the rising edge of the millisecond pulse and starts generating pseudocode through the code generation module to complete the rapid recovery of pseudocode. For pseudocode with a period greater than 1 millisecond, the SRAM-type FPGA pre-stores the pseudocode sequence in ROM. After detecting the rising edge of the millisecond pulse, the SRAM-type FPGA reads the millisecond count transmitted by the antifuse-type FPGA, and then calculates the code offset address of the pseudocode stored in ROM based on the millisecond count, the period of the pseudocode, and the code length of the pseudocode. The pseudocode sequence in ROM is read according to the code offset address until all the pseudocode in the current pseudocode period has been read, thus completing the rapid recovery of pseudocode. The DSP enables the signal generation channel of the SRAM-type FPGA and writes a message frame into the storage RAM of the SRAM-type FPGA via the EMIF bus. The DSP calculates the RAM read start address of the message based on the second count, millisecond count, message frame length, and symbol period, and configures the RAM read start address of the message to the SRAM-type FPGA via the EMIF bus. The SRAM-type FPGA reads the navigation message from the RAM starting address of the message at the time of message transmission and modulates the read navigation message into pseudocode. The SRAM-type FPGA performs carrier modulation on the modulated pseudo-code to generate satellite navigation signals.

7. The method according to claim 6, characterized in that, The pseudocode is modulated with subcodes, which are generated by pre-storing them in ROM.

8. A device for rapid replay of spaceborne navigation signals, characterized in that, The device includes: The continuous wave device construction module is used to build a navigation signal rapid continuous wave device based on a hierarchical time maintenance mechanism, which is constructed from SRAM-type FPGA, DSP and antifuse-type FPGA. The time synchronization information acquisition module is used to receive external time synchronization instructions through the DSP and obtain local time information from the SRAM-type FPGA to obtain time synchronization information, and send the time synchronization information to the antifuse-type FPGA; A time correction and maintenance module is used for the antifuse FPGA to perform local time calibration based on the time calibration information and to maintain the local time through cycle counting; An anomaly calibration module is used to send a reset signal, load data, and time information to the SRAM-type FPGA when the antifuse-type FPGA detects an anomaly in the SRAM-type FPGA, so as to reset and reload the SRAM-type FPGA; the time information includes a millisecond pulse signal, a millisecond count, a second count, and a week count; The signal generation module is used by the SRAM-type FPGA to determine the starting point for generating pseudocode for each signal component based on the received time information and the millisecond pulse signal as the time reference. The DSP writes the navigation message into the SRAM-type FPGA and configures the message broadcast start position determined by the second count and millisecond count to the SRAM-type FPGA. At the message transmission time, the SRAM-type FPGA reads the navigation message from the message broadcast start position, modulates the message into pseudocode, and then performs carrier modulation to generate a satellite navigation signal.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.

Images