Data reading and writing method and electronic device

Abstract

The application discloses a data read-write method and an electronic device, relates to the technical field of storage systems, and divides logical volume storage space into a plurality of independently managed logical segments according to a preset address segment length, and forms a plurality of space domains based on the logical segments; when a read-write request is received, the logical block address and the logical volume identifier corresponding to the read-write request are extracted, a target space domain is determined through calculation, and the read-write request is routed to a controller corresponding to the target space domain for processing. The read-write request of the same logical address interval is processed by the same controller, the cache data version disorder caused by cross-controller routing is avoided, the cache repeated retrieval overhead is reduced, and the data read-write performance is improved.

Description

Technical Field

[0001] This application relates to the field of storage system technology, and in particular to data read / write methods and electronic devices. Background Technology

[0002] In data storage, storage systems employ a cluster architecture with multiple redundant controllers to ensure high availability. However, in related technologies, read and write operations within the same logical address range may be routed to different controllers, leading to cache misses, cross-node data version conflicts, and severe load imbalances within the cluster. Summary of the Invention

[0003] This application provides a data reading and writing method and an electronic device to at least solve the problem of low data reading and writing performance in related technologies.

[0004] This application provides a data read / write method, including:

[0005] Receive read / write requests and determine the logical block address and logical volume identifier from the read / write requests;

[0006] Based on the preset address segment length, the logical storage space corresponding to the logical volume identifier is evenly divided into multiple logical segments. Based on the number of controllers, the multiple logical segments are allocated space domains to obtain multiple space domains.

[0007] The target spatial domain is determined from multiple spatial domains based on the logical block address and logical volume identifier;

[0008] Based on the mapping relationship between spatial domains and controllers, the target controller corresponding to the target spatial domain is determined, and the read and write requests are executed by calling the cache through the target controller.

[0009] This application also provides a data read / write device, including:

[0010] The receiving module is used to receive read / write requests and determine the logical block address and logical volume identifier from the read / write requests;

[0011] The mapping module is used to evenly divide the logical storage space corresponding to the logical volume identifier into multiple logical segments according to the preset address segment length, and to allocate space domains to the multiple logical segments according to the number of controllers to obtain multiple space domains.

[0012] The determination module is used to determine the target spatial domain from multiple spatial domains based on the logical block address and logical volume identifier;

[0013] The execution module is used to determine the target controller corresponding to the target spatial domain based on the mapping relationship between the spatial domain and the controller, and to execute read and write requests by calling the cache through the target controller.

[0014] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the steps of any of the above data read / write methods when executing the computer program.

[0015] This application also provides a non-volatile computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described data read / write methods.

[0016] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described data read / write methods.

[0017] This application divides the logical volume storage space into multiple independently managed logical segments according to a preset address segment length, and allocates multiple space domains based on these logical segments. When a read / write request is received, the logical block address and logical volume identifier corresponding to the read / write request are extracted, the target space domain is determined through calculation, and the read / write request is routed to the controller corresponding to that target space domain for processing. This ensures that read / write requests within the same logical address range are processed by the same controller, avoiding cached data version inconsistencies caused by cross-controller routing, reducing cache duplication retrieval overhead, and improving data read / write performance. Attached Figure Description

[0018] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A schematic diagram of the two-copy circular mirroring mechanism provided in the embodiments of this application;

[0020] Figure 2 A schematic diagram illustrating the four-copy full mirroring mechanism provided in this application embodiment;

[0021] Figure 3 This is a schematic diagram illustrating an application scenario of a data read / write method provided in an embodiment of this application.

[0022] Figure 4 A flowchart illustrating a data read / write method provided in an embodiment of this application;

[0023] Figure 5 A flowchart illustrating another data read / write method provided in an embodiment of this application;

[0024] Figure 6 A schematic diagram of the storage system architecture provided in an embodiment of this application;

[0025] Figure 7 A schematic diagram of spatial domain allocation provided for embodiments of this application;

[0026] Figure 8 A schematic diagram illustrating data writing provided in the embodiments of this application;

[0027] Figure 9 A schematic diagram of fault handling provided in the embodiments of this application;

[0028] Figure 10 A schematic diagram illustrating invalid data processing provided in an embodiment of this application;

[0029] Figure 11 This is a schematic diagram of the structure of a data read / write device provided in an embodiment of this application;

[0030] Figure 12 This is a schematic diagram of another data read / write device provided in an embodiment of this application;

[0031] Figure 13 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0033] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0034] For example, the availability of a storage system refers to the system's ability to provide services continuously. The longer the system can provide services continuously, the higher its availability. In related technologies, the mainstream cache high availability solutions for four-controller high availability storage systems are mainly divided into two types.

[0035] Below, in conjunction with Figure 1 The two-copy circular mirroring mechanism is explained.

[0036] Figure 1 This is a schematic diagram illustrating the two-copy circular mirroring mechanism provided in an embodiment of this application. Figure 1 As shown, the first scheme employs a two-replica circular mirroring mechanism, which sequentially mirrors dirty data that has not been written to disk in the controller cache to adjacent controllers. This scheme has significant drawbacks: simultaneous failure of any two controllers (especially adjacent controllers) or a specific combination of controllers, as well as simultaneous failure of any three controllers, will lead to service interruption; furthermore, each data item retains only one mirror copy, resulting in a true memory utilization rate of only 50% for a single controller.

[0037] Below, in conjunction with Figure 2 Explain the four-replica full mirror mechanism.

[0038] Figure 2 This is a schematic diagram illustrating the four-copy full mirroring mechanism provided in an embodiment of this application. For example... Figure 2 As shown, the second approach employs a four-replica full mirroring mechanism, simultaneously mirroring dirty data to the caches of the other three controllers. The trade-off is that write requests must wait for all three mirrored copies to complete before returning success, significantly increasing write latency and placing extremely high demands on the interconnect bandwidth between controllers. Furthermore, maintaining three copies of each piece of data drastically reduces actual memory utilization to 25%, severely squeezing the cache space for valuable hot data, thereby lowering cache hit rate and overall system performance.

[0039] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0040] This section describes the specific application environment architecture upon which the data read / write methods depend. (References) Figure 3 The host is used to generate and distribute read / write requests, sending them to the storage cluster. The storage cluster consists of multiple controllers connected via cluster interconnect links. Each controller has a local cache used to cache business data. The main storage contains several storage devices used for persistent storage of business data.

[0041] In related technologies, read and write requests are typically configured to directly specify the main controller based on business settings, or all business requests for the entire logical volume are routed to a specific controller based on logical volume binding relationships. After receiving a read or write request, the controller utilizes local caching to improve input / output (IO) processing speed, and simultaneously performs log backups for write requests through log storage partitions. When the amount of dirty data in the cache reaches a threshold, the dirty data is flushed to the backend main storage.

[0042] However, assigning a large number of read and write requests to a single controller can lead to a sharp increase in I / O pressure on the bound controller when some logical volumes experience heavy traffic, while other controllers remain idle, resulting in underutilization of cluster computing resources. Furthermore, for read and write requests involving consecutive large address segments across different data segments, requests cannot be properly distributed, easily causing congestion in the single controller's queue, increased I / O latency, and a decline in overall cluster I / O processing performance.

[0043] Figure 4 This is a flowchart illustrating the data read / write method provided in the embodiments of this application, as shown below. Figure 4 As shown, embodiments of this application provide a data read / write method, which is described in detail below:

[0044] S401. Receive read / write requests and determine the logical block address and logical volume identifier from the read / write requests.

[0045] For example, read and write requests sent by the host are received through a front-end interface. The front-end interface can support protocols such as Fibre Channel (FC), Internet Small Computer System Interface (iSCSI), and Non-Volatile Memory Express (NVMe).

[0046] For example, the received read / write request is parsed, and the address information of the target data location is extracted from the command description block of the read / write request. This address information includes the logical volume identifier and the logical block address.

[0047] The logical volume identifier is used to uniquely identify the logical volume accessed by the read / write request, i.e., the logical unit seen by the host; the logical block address is used to identify the offset position of the data accessed by the read / write request within the corresponding logical volume address space.

[0048] To illustrate with a scenario example, the process of determining the logical block address and logical volume identifier from read / write requests essentially transforms the host's access request to the logical address space into location parameters recognizable within the storage system. When initiating read / write operations, the host does not need to determine how the data is partitioned or stored within the storage system; the host only issues access requests to a contiguous logical address space.

[0049] For example, taking a write request as an example, the host requests to write data to the logical volume with logical volume identifier 2. After parsing, the controller learns that the logical block address of the request is 4MB of data starting at 64MB. The controller registers this request as an I / O request to be processed and uses the logical volume identifier 2 and the logical block address 64MB as attributes of the I / O request.

[0050] For read requests, the controller also resolves the logical volume identifier and logical block address, thereby determining the data area that the read request should access, and preparing for the determination of the subsequent read path.

[0051] S402. Based on the preset address segment length, the logical storage space corresponding to the logical volume identifier is evenly divided into multiple logical segments. Based on the number of controllers, the multiple logical segments are allocated to multiple space domains to obtain multiple space domains.

[0052] For example, the preset address segment length is a length benchmark pre-set by the storage system for dividing the address space. The preset address segment length represents the length of the continuous address range covered by a logical segment. The storage controller uses the preset address segment length as the unit of division to uniformly divide the logical storage space corresponding to the logical volume identifier.

[0053] Starting from the beginning address of the logical storage space, it is sequentially divided according to a preset address segment length, resulting in multiple logical segments with non-overlapping address ranges and equal lengths. Uniform division discretizes the logical storage space into a finite number of logical segments of uniform size, with a clear order between the logical segments, ensuring that any logical block address falls within a certain logical segment.

[0054] Taking a preset address segment length of 32MB as an example, the first 32MB interval of the logical storage space constitutes the first logical segment, the second 32MB interval constitutes the second logical segment, and so on.

[0055] For example, a spatial domain is an abstract region within a storage system used to organize read and write loads. Each spatial domain corresponds to several logical segments, and the storage controller that carries read and write requests for the same spatial domain is relatively fixed.

[0056] The storage controller allocates space domains to multiple logical segments based on the number of storage controllers in the storage system. That is, the total number of space domains corresponds to the total number of storage controllers. Multiple logical segments are allocated to each space domain in a sequential and cyclical manner, so that each space domain contains a considerable number of evenly distributed logical segments.

[0057] Taking a storage system with four storage controllers as an example, the storage system is set up with four space domains, numbered from 0 to 3. Multiple logical segments are sequentially and cyclically allocated to space domain 0, space domain 1, space domain 2, and space domain 3, and then back to space domain 0. This spreads continuous access requests across multiple space domains in terms of address dimension, avoiding access hotspots from being concentrated in a single space domain.

[0058] For example, the purpose of space domain allocation is to divide the logical storage space into several non-overlapping ownership intervals, so that read and write requests within each ownership interval are centrally handled by a storage controller. Since the total number of space domains corresponds to the total number of storage controllers, each storage controller carries the same number of space domains, and ideally, each storage controller has the same address space size, thereby achieving load balancing among storage controllers at the request routing level.

[0059] Optionally, the results of space domain allocation can be established once during the storage system initialization phase and stored in each storage controller in the form of a mapping table; when the number of storage controllers changes, the results of space domain allocation are updated accordingly.

[0060] Using a scenario example, assume there are 4 space domains, a preset address segment length of 32MB, and space domains numbered sequentially from 0 to 3. The storage system includes 4 controllers. The logical storage space of the logical volume with logical volume identifier 0 is evenly divided into multiple sequentially arranged logical segments. The first logical segment covers the address range from 0MB to 32MB, the second from 32MB to 64MB, the third from 64MB to 96MB, and the fourth from 96MB to 128MB. After cyclically allocating space domains, the first logical segment belongs to space domain 0, the second to space domain 1, the third to space domain 2, the fourth to space domain 3, and the fifth back to space domain 0, thus forming a sequentially numbered structure in the logical storage space.

[0061] With the example of the scenario, the first and second operation results describe the "spatial domain affiliation of the logical block in the address dimension" and the "spatial domain bias of the logical volume in the volume dimension", respectively. The combination of the two can achieve uniform load distribution in both the address dimension and the volume dimension, which can prevent continuous access within a single logical volume from hitting the same spatial domain, and also prevent logical blocks with the same number in multiple logical volumes from hitting the same spatial domain at the same time.

[0062] S403. Determine the target spatial domain from multiple spatial domains based on the logical block address and logical volume identifier.

[0063] For example, the target space domain refers to the space domain to which the data accessed by this read / write request belongs. The target space domain is used to indicate which storage controller should subsequently handle the read / write request. The basis for determining the target space domain includes both the logical block address and the logical volume identifier. The logical block address is used to locate the logical segment where the data accessed by the read / write request is located within the logical storage space, and the logical volume identifier is used to distinguish the object to which the read / write request belongs among multiple logical volumes.

[0064] If the attribution is determined solely based on the logical block address, logical segments with the same number in different logical volumes will all fall into the same spatial domain. This results in access to the same relative address location in multiple logical volumes being concentrated on the same storage controller, making it difficult to distribute the concurrent access pressure of the host across multiple logical volumes. Introducing the logical volume identifier to participate in the attribution determination can introduce the differences in the logical volume dimension into the spatial domain attribution result, thereby achieving a uniform distribution of read and write load in both the address dimension and the volume dimension.

[0065] For example, the process of determining a target spatial domain from multiple spatial domains is a deterministic mapping process involving both logical volume identifiers and logical block addresses. The storage controller determines the logical segment to which the read / write request falls based on the logical block address, and then determines the correspondence between the logical segment and the spatial domain based on the logical volume identifier. The combination of these two methods can uniquely determine a target spatial domain among the pre-divided spatial domains.

[0066] Since the above mapping process only relies on the logical block address and logical volume identifier carried by the read / write request itself, as well as the current logical segment number of the storage system, read / write requests for the same logical block address in the same logical volume will calculate the same target space domain regardless of which storage controller receives them, thus ensuring the global consistency and reproducibility of request routing.

[0067] With the example scenario, the storage system includes four storage controllers, each corresponding to a spatial domain, with a preset address segment length of 32MB. When a storage controller receives a read / write request pointing to logical volume identifier 2 and logical block address 0MB, it determines that the request falls within the first logical segment of the logical volume with logical volume identifier 2 based on the logical block address 0MB. Then, considering the spatial domain affiliation relationship corresponding to logical volume identifier 2, it determines that the target spatial domain for the read / write request is spatial domain 2. The storage controller continues to receive read / write requests pointing to logical volume identifier 2 and logical block address 32MB. Based on the logical block address 32MB, it determines that the request falls within the second logical segment. Considering the spatial domain affiliation relationship corresponding to logical volume identifier 2, it determines that the target spatial domain for the read / write request is spatial domain 3. As the logical block address progresses in the direction of increasing address, the target spatial domain changes sequentially, and consecutive address ranges are smoothly allocated to each spatial domain.

[0068] S404. Based on the mapping relationship between the spatial domain and the controller, determine the target controller corresponding to the target spatial domain, and execute the read / write request by calling the cache through the target controller.

[0069] For example, the mapping relationship between space domains and controllers is used to indicate which storage controller is responsible for handling the read and write operations of each space domain. The mapping relationship can be planned based on the total number of space domains and the total number of storage controllers. When the total number of space domains is equal to the total number of storage controllers, one storage controller can be assigned to each space domain to establish a one-to-one mapping relationship; when the total number of space domains is greater than the total number of storage controllers, one storage controller can handle the operations of multiple space domains.

[0070] Optionally, the mapping relationship can be statically established and stored in the memory of each storage controller during the storage system initialization phase, or it can be dynamically adjusted in scenarios such as storage controller going online or offline, so as to always ensure that spatial domain services have corresponding storage controllers to carry them.

[0071] For example, after obtaining the target spatial domain, the storage controller queries the mapping relationship based on the target spatial domain to determine the storage controller that carries the services of the target spatial domain, and then identifies that storage controller as the target controller.

[0072] With the example scenario, because the target spatial domain is globally deterministic and the mapping relationship remains consistent across all storage controllers, read and write requests for the same spatial domain will be reliably routed to the same target controller. The target controller's cache can continuously accumulate and maintain the latest data for the target spatial domain, and subsequent read and write operations for the target spatial domain can be completed in the target controller's cache, thus ensuring that the correspondence between cached data and request routing is not disrupted.

[0073] For example, after the target controller is determined, the target controller schedules its own cache resources to execute read and write requests.

[0074] For write requests, the target controller temporarily stores the data to be written in the local cache and flushes the data in the cache to the backend storage at the appropriate time. For read requests, the target controller first retrieves the target data in the local cache. If the cache is hit, the data is returned directly from the cache to avoid the additional latency caused by accessing the backend storage.

[0075] Because a definite binding relationship is established between read / write requests and the spatial domain and target controller, the storage location of data in the cache is consistent with the retrieval location when it is read, avoiding cache lookups and data migrations across controllers and improving cache hit rate.

[0076] To illustrate with a scenario example, in a four-controller storage system, there are four space domains, each hosted by a separate controller. When controller A receives a write request pointing to logical volume identifier 0 and logical block address 0MB, it calculates the target space domain identifier as 0 using steps S402 and S403. It then determines that controller A corresponding to space domain 0 is the target controller and writes the requested data to its own cache. Subsequently, when the host initiates a read request for logical volume identifier 0 and logical block address 0MB, regardless of which controller the read request is sent to, that controller will calculate the same target space domain identifier 0 and route the request back to controller A. Controller A can then retrieve the latest data from its own cache and return it.

[0077] Based on this, the storage system achieves both balanced load distribution among controllers and ensures that cached data is always maintained by a single controller, avoiding the performance loss caused by cross-controller mirroring and consistency coordination in related technical solutions.

[0078] The data read / write method provided in this application embodiment receives a read / write request and determines the logical block address and logical volume identifier from the read / write request; according to the preset address segment length, the logical storage space corresponding to the logical volume identifier is evenly divided into multiple logical segments to obtain multiple logical segments; the multiple logical segments are allocated space domains according to the number of controllers to obtain multiple space domains; the target space domain is determined from the multiple space domains according to the logical block address and logical volume identifier; the target controller corresponding to the target space domain is determined according to the mapping relationship between the space domain and the controller, and the read / write request is executed by calling the cache through the target controller.

[0079] The above scheme divides the logical volume storage space into multiple independently managed logical segments according to a preset address segment length, and allocates multiple space domains based on these logical segments. When a read / write request is received, the logical block address and logical volume identifier corresponding to the read / write request are extracted, the target space domain is determined through calculation, and the read / write request is routed to the controller corresponding to that target space domain for processing. This ensures that read / write requests within the same logical address range are handled by the same controller, avoiding cached data version inconsistencies caused by cross-controller routing, reducing cache duplication retrieval overhead, and improving data read / write performance.

[0080] Based on any of the above embodiments, the following, in conjunction with Figure 5 The detailed process of data reading and writing methods is explained.

[0081] Figure 5 This is a flowchart illustrating another data read / write method provided in an embodiment of this application. Figure 5 As shown, the method includes the following steps:

[0082] S501. Receive read / write requests and determine the logical block address and logical volume identifier from the read / write requests.

[0083] Below, in conjunction with Figure 6 Describe the storage system architecture.

[0084] Figure 6 This is a schematic diagram of the storage system architecture provided in an embodiment of this application. Figure 6 As shown, the storage pool for storing data is divided into two types based on different storage media. One type is a log storage partition composed of disks using SCM (Storage Class Memory) media. SCM is a new type of non-volatile storage medium whose performance and characteristics fall between traditional DRAM and NAND flash memory (such as SSDs). It combines the high speed and low latency of memory with the durability of storage devices (data is not lost when power is off). The other type is the main storage, composed of mechanical hard drives, SSDs, or a combination of both. The main storage is the storage pool in the general sense. The log storage partition's storage space is composed of SCM media disks, divided into four storage areas: Log Area A, Log Area B, Log Area C, and Log Area D. These four log areas serve as backup spaces for writing cached data to the four controllers.

[0085] For example, data written to the cache of controller A will simultaneously be written to the storage space of log area A. After both the cache and the log area are written, a success message can be returned to the host. Because the latency of SCM media is slightly higher than that of DRAM memory, but much lower than that of SSD NAND media, the write latency fully meets the latency requirements of critical business applications.

[0086] S502. Obtain multiple segment starting boundaries corresponding to multiple spatial domains.

[0087] For example, the segment start boundary refers to the boundary address in the logical storage space used to define the boundary position between adjacent logical segments.

[0088] The storage system divides the logical storage space corresponding to the logical volume identifier into multiple consecutive logical segments based on a preset address segment length. The starting position of each logical segment is a segment start boundary. When the logical storage space is continuously divided starting from address 0 with the preset address segment length, the segment start boundary is an integer multiple of the preset address segment length. When the preset address segment length is adjusted, the segment start boundary is recalculated. Obtaining multiple segment start boundaries corresponding to multiple spatial domains is equivalent to establishing a set of partitioning scales for the logical storage space. Any subsequent logical block address can be compared with the above scale to determine whether the logical block address is exactly aligned with the boundary of a certain logical segment.

[0089] For example, the segment start boundary can be calculated in real time by the storage system based on the current address segment length, or it can be pre-maintained by the storage system and stored in the controller's memory. Taking a preset address segment length of 32MB as an example, the segment start boundary of the logical volume address space includes address locations such as 0MB, 32MB, 64MB, 96MB, and 128MB.

[0090] It should be noted that the segment start boundary is not limited to a form in which the segment starts at address 0 and is distributed at equal intervals with a fixed preset address segment length. When the storage system configures different address segment lengths for different logical volumes or different address ranges, the segment start boundary can be a set of addresses that are not equally spaced, and its distribution pattern corresponds one-to-one with the address segment length configuration.

[0091] With the example scenario, any logical volume's space is partitioned using a two-level address segmentation length. The first half of the logical volume's address space is divided into 16MB segment lengths, and the second half is divided into 32MB segment lengths. Therefore, the set of segment start boundaries for this logical volume includes address locations such as 0MB, 16MB, 32MB, 48MB, 64MB, 96MB, and 128MB. When processing read / write requests to this logical volume, the controller first obtains the aforementioned set of segment start boundaries to accurately determine the logical block range corresponding to any logical block address.

[0092] S503. Based on multiple segment start boundaries, when the logical block address does not fall on any segment start boundary, the logical block address is rounded up to the nearest segment start boundary to obtain the rounded logical block address.

[0093] For example, in an input / output scenario, the logical block address carried by the read / write request issued by the host may not fall exactly on the segment start boundary. A large number of read / write requests may have their starting addresses falling inside a certain logical block interval, i.e., not on any segment start boundary. For such requests, the controller performs a rounding process based on the segment start boundary and the address segment length, rounding the logical block address upwards to the nearest segment start boundary.

[0094] Upward straightening means that, among the segment start boundaries encountered along the address increase direction of the logical block address, the segment start boundary closest to the logical block address is selected as the straightening target. The logical block address is then adjusted to this boundary position, resulting in a straightened logical block address. This straightening process ensures that previously unaligned accesses are uniformly incorporated into the complete logical block, guaranteeing that the data area covered by a single read / write request can be fully included in a single logical block for management.

[0095] For example, the rounding process resolves the ambiguity in attribution caused by misalignment between read / write requests and logical block boundaries. Without rounding misaligned logical block addresses, the same read / write request might span two adjacent logical blocks, leading to duplicate segmentation or even allocation to two different spatial domains, thus compromising request routing stability. By rounding upwards to the nearest segment start boundary, the attribution region of a read / write request is uniquely determined. Regardless of the starting address of the request within the logical block, it can be consistently mapped to the complete range covered by that logical block, ensuring that read / write requests for the same data region are always routed to the same target controller and maintaining cached data consistency.

[0096] With the example scenario, the address segment length is set to 32MB, and the logical volume segment start boundaries include address locations such as 0MB, 32MB, 64MB, and 96MB. A write request from the host has a logical block address of 40MB. This address does not fall on any segment start boundary. The nearest segment start boundary along the address increment direction is 64MB. Therefore, the controller rounds up the logical block address from 40MB to 64MB. The rounded logical block address is 64MB, meaning the data area accessed by the write request is entirely assigned to a logical block starting at 64MB.

[0097] S504. Determine the target spatial domain from multiple spatial domains based on the normalized logical block address and logical volume identifier.

[0098] One feasible implementation method is to determine the target spatial domain by means of the following:

[0099] The ratio of the normalized logical block address to the preset address segment length is used as the logical segment number;

[0100] The first result is obtained by performing a modulo operation on the logical segment number based on the number of spatial domains, and the second result is obtained by performing a modulo operation on the logical volume identifier based on the number of spatial domains in the storage system.

[0101] The sum of the first and second operation results is modulo the number of spatial domains to obtain the target spatial domain identifier;

[0102] Among multiple spatial domains, the spatial domain corresponding to the target spatial domain identifier is determined as the target spatial domain.

[0103] For example, the logical segment number is a sequence number used to identify the position of a logical segment in the logical storage space. The logical segment numbers start from 0 and increase sequentially. The logical segment with sequence number 0 covers an address interval starting from the beginning address of the logical storage space and with a length equal to the preset address segment length. The logical segment with sequence number 1 covers the second address interval immediately following it, and so on. The storage controller determines the logical segment number by the ratio of the normalized logical block address to the preset address segment length. Since the normalized logical block address has been aligned to the segment start boundary, its value must be an integer multiple of the preset address segment length. Therefore, the above ratio is an integer and uniquely determined. The introduction of the logical segment number compresses the huge logical address space into a finite set of numbers that are easy to compute, providing a unified computational object for subsequent spatial domain calculations.

[0104] For example, the number of space domains represents the total number of space domains that the storage system divides for load balancing. The modulo operation is the operation of finding the remainder of division. The modulo operation is performed on the logical segment number using the number of space domains, that is, using the number of space domains as the modulus and the logical segment number as the dividend to find the remainder. The remainder obtained is the first operation result.

[0105] Since the logical segment number increases sequentially with the logical block address, the modulo operation allows logical segments with adjacent sequence numbers to be allocated sequentially and cyclically to different spatial domains. This naturally spreads hotspots of continuous writes or reads across multiple spatial domains, preventing access hotspots from concentrating in a single spatial domain. Similarly, by performing a modulo operation on the logical volume identifier using the number of spatial domains, the remainder is the second operation result. This second operation result reflects the phase offset between logical volumes and is used to stagger the spatial domains to which logical segments with the same sequence number belong in different logical volumes.

[0106] For example, the first calculation result represents the spatial domain affiliation of logical segments in the address dimension, and the second calculation result represents the spatial domain offset of logical volumes in the volume dimension. If spatial domain affiliation is determined solely based on the first calculation result, logical segments with the same sequence number in multiple logical volumes will all fall into the same spatial domain. When the host concurrently accesses the same relative address location of multiple logical volumes, the access pressure will be concentrated on the storage controller that carries the services of that spatial domain.

[0107] After introducing the second operation result, the spatial domains of different logical volumes are staggered as a whole, and logical segments with the same sequence number in multiple logical volumes fall into different spatial domains, thereby achieving uniform distribution of read and write loads in both the address dimension and the volume dimension.

[0108] With the example scenario, the preset address segment length is set to 32MB, and the number of spatial fields is 4. After receiving a write request for a logical block address of 40MB, the controller first rounds the logical block address from 40MB up to 64MB based on the segment start boundary. Then, it divides the 64MB into segments of 32MB, resulting in logical block number 2. Next, it takes the modulo of logical block number 2 with the number of spatial fields (4), and the first operation result is 2. The logical block number 2 corresponding to this write request is uniquely identified. Even if the host subsequently initiates access to the same data area with a different starting address, the rounding process will uniformly classify this access into logical block number 2, thus ensuring that access to the same data area always has the same spatial field identifier in the address dimension.

[0109] Optionally, the calculation process for spatial domain affiliation can be represented by the following formula:

[0110]

[0111] Where Aligned_LBA represents the normalized logical block address, SegmentSize represents the preset address segment length, and N represents the number of space fields; in the embodiment where the preset address segment length is 32MB and the number of space fields is 4, the above formula is specified as:

[0112]

[0113] It should be noted that normalization and integer division are two consecutive steps and cannot be substituted for each other: the logical segment number obtained by directly performing integer division on the unnormalized 40MB is 1, while the number obtained by performing division after normalization to 64MB is 2. The two correspond to different spatial domain affiliations.

[0114] Below, in conjunction with Figure 7 The allocation of spatial domains is explained.

[0115] Figure 7 This is a schematic diagram illustrating the spatial domain allocation provided in an embodiment of this application. Figure 7 As shown, taking LUN0 as an example, the first 32MB space belongs to Domain0, the second 32MB to Domain1, the third 32MB to Domain2, the fourth 32MB to Domain3, and the fifth 32MB back to Domain0, and so on. Other LUN spaces in the storage system are also divided into these four Domains based on the same address segment length. To avoid load imbalance caused by all volumes having the same LBA access falling to the same controller, the first 32MB of LUN1 belongs to Domain1, the first 32MB of LUN2 belongs to Domain2, and the first 32MB of LUN3 belongs to Domain3.

[0116] Based on the above implementation method, by obtaining the segment start boundary of the logical block, and when the logical block address does not fall on any segment start boundary, it is normalized upwards to the nearest segment start boundary to obtain the normalized logical block address. Then, the normalized logical block address is divided according to the address segment length to obtain the logical block number. This solves the problem of ambiguity in the attribution determination when the read / write request is not aligned with the logical block boundary, and ensures that read / write requests in the same data area have consistent and stable logical block numbers in the address dimension. This provides normalized input for the accurate calculation of the subsequent spatial domain identifier, thereby improving the performance of data read / write.

[0117] One feasible implementation method is to dynamically adjust the address segment length by: periodically collecting the access characteristics of each logical segment, the access characteristics including at least one of the following: request size distribution, access frequency, and consecutive access span; determining the access pattern of each logical segment based on the access characteristics; and adjusting the address segment length of each logical segment based on the access pattern.

[0118] For example, the service access patterns carried by different logic blocks vary significantly. Some logic blocks carry a large number of continuous streaming writes, while others carry scattered random small inputs and outputs. The fixed address segment length is difficult to adapt to the access characteristics of all logic blocks.

[0119] The controller periodically collects access characteristics of each logical block. Request size distribution describes the length distribution of read / write requests received by each logical block; access frequency describes the number of times each logical block is accessed per unit time; and continuous access span describes the address range length covered when each logical block is accessed consecutively. The controller combines these access characteristics to determine the access mode of each logical block, such as a continuous large block access mode, a random small block access mode, or a mixed access mode, and adjusts the address segment length of each logical block accordingly.

[0120] For example, for logical blocks with large continuous access spans and requests that are mostly large-scale continuous read and write operations, the address segment length of the logical block can be appropriately increased to carry streaming access in a larger continuous interval, thereby reducing the number of logical block segments and thus reducing the overhead of spatial domain computing and metadata management.

[0121] For logical blocks with high access frequency and requests consisting mostly of random small chunks, the address segment length of the logical block can be appropriately reduced to make the spatial domain division more refined, thereby achieving a more balanced load distribution among different spatial domains. After the address segment length is adjusted, the segment start boundary is updated accordingly, and subsequent read and write requests are divided and consolidated according to the updated address segment length.

[0122] Optionally, the controller can set an adjustment cycle, such as performing access feature collection and address segment length adjustment every 30 seconds, to ensure that the address segment length configuration is updated in a timely manner according to the dynamic changes in business load. During the adjustment process, the controller needs to ensure that the address segment length adjustment results for the same logical block are consistent within the cluster, avoiding inconsistent spatial domain assignments calculated by different controllers based on different address segment lengths.

[0123] In this feasible implementation, by periodically sensing the access characteristics of each logical block and dynamically adjusting the address segment length accordingly, the spatial domain partitioning can conform to the access patterns of actual business. This reduces partitioning overhead in continuous streaming access scenarios and improves load balancing accuracy in random small block access scenarios, thereby enhancing the adaptability of spatial domain partitioning and the overall system processing efficiency, and thus improving data read and write performance.

[0124] S505: Obtain the original mapping relationship between the pre-configured spatial domain and the controller.

[0125] For example, the original mapping relationship is the correspondence between the space domains pre-configured in the storage system and the storage controllers, which indicates which storage controller is responsible for the read and write operations of each space domain in principle.

[0126] S506. Obtain historical access statistics of the target spatial domain, and adjust the original mapping relationship according to the priority of the historical access statistics to obtain the adjusted mapping relationship.

[0127] For example, historical access statistics are the statistical results of the access to the target spatial domain over a period of time, including at least the access frequency, access data volume, and access time distribution of the target spatial domain.

[0128] The storage controller prioritizes the original mapping relationship based on historical access statistics. For example, for space domains with high access frequency and large access data volume, the priority of the storage controller carrying the services of that space domain is increased in the candidate queue, so that the storage controller with higher priority is selected as the candidate controller. For space domains with low access frequency, the priority of its corresponding storage controller can be appropriately reduced, thereby achieving a more balanced service carrying capacity among multiple space domains.

[0129] S507. Based on the corrected mapping relationship, determine the candidate controller corresponding to the target spatial domain.

[0130] For example, a candidate controller is a storage controller that is initially determined based on the revised mapping relationship and is qualified to carry services of the target spatial domain. The storage controller uses the target spatial domain as the query object and searches for the corresponding storage controller in the revised mapping relationship to obtain the candidate controller.

[0131] S508. Determine the operating status and load status of the candidate controller from the status information of the candidate controller.

[0132] For example, the storage controller reads the running status and load status from the status information of the candidate controller. The running status describes whether the candidate controller is in a normal online state, and the load status describes how busy the candidate controller is.

[0133] S509. When the operating status is normal online and the load status is within the preset load range, the candidate controller is determined as the target controller.

[0134] For example, when the candidate controller is running normally online and the load status is within a preset load range, it is determined that the candidate controller has the ability to accept read and write requests, and the candidate controller is identified as the target controller.

[0135] With the example of the scenario, after the storage controller receives a read / write request to the target space domain, it first obtains the pre-configured original mapping relationship, and then reads the historical access statistics of the target space domain for the past hour. It finds that the access frequency of the target space domain is 20,000 times per second, which is a high-frequency access space domain. Based on this, the priority of the storage controller carrying the business of the target space domain is increased, and the corrected mapping relationship is obtained.

[0136] After determining the candidate controller based on the corrected mapping relationship, the storage controller queries the status information of the candidate controller to confirm that the candidate controller is operating normally online and the load status is within the preset load range. Therefore, the candidate controller is determined as the target controller.

[0137] As another example, if the load status of a candidate controller exceeds the preset load range, the storage controller will reselect the target controller from other normally online storage controllers with low load.

[0138] With the scenario example, controller A receives a read / write request and determines controller C as the candidate controller through mapping. Controller A queries the status information of controller C and learns that controller C is running normally online, and the quantized value corresponding to its load status is within the preset load range. Therefore, controller A determines controller C as the target controller and routes the read / write request to controller C for execution.

[0139] In this feasible implementation, by comprehensively judging the running status and load status of the candidate controller, the candidate controller is determined as the target controller only when it is online normally and the load is within the preset load range. This effectively avoids failures and blocking caused by requests being routed to offline or overloaded controllers, thereby improving the performance of data read and write.

[0140] One feasible implementation method is to update and maintain the status information of each controller through the following steps: periodically collecting the real-time load parameters of each controller, which include at least one of the following: queue backlog, computing power utilization, and cache read / write throughput; performing a weighted summation of the real-time load parameters to obtain the real-time load status of each controller; and updating the status information of each controller based on its real-time load status.

[0141] For example, to ensure that the controller's load status reflects real-time operational conditions, the controller periodically collects real-time load parameters from each controller. Queue backlog describes the number of requests currently pending processing in the queue; a larger backlog indicates higher processing pressure on the controller. Computing utilization describes the proportion of the controller's processing units that are occupied, reflecting the busyness of computing resources. Cache read / write throughput describes the amount of read / write data completed by the controller's cache per unit time, reflecting the busyness of the cache channel. The controller assigns appropriate weights to each real-time load parameter and performs a weighted summation, using the sum as the controller's current real-time load status.

[0142] For example, different load parameters describe the controller's workload from different perspectives. Queue backlog focuses on request processing pressure, compute utilization focuses on computing resource consumption, and cache read / write throughput focuses on cache channel occupancy. A single parameter cannot fully reflect the controller's true load. By using weighted summation, multi-dimensional parameters can be converted into a unified load quantification value. For example, a real-time load status value between 0 and 100 can be used to characterize the controller's load level, with higher values ​​indicating heavier loads. The weights can be configured based on the bottleneck characteristics of the storage system's actual business. For instance, in I / O-intensive scenarios, the weight corresponding to cache read / write throughput can be increased, while in compute-intensive scenarios, the weight corresponding to compute utilization can be increased.

[0143] For example, the controller writes the calculated real-time load status of each controller into the corresponding status information, completing the update process for the status information of each controller. The updated status information can then provide a basis for subsequent controller selection, such as determining whether the load status of a candidate controller is within a preset load range.

[0144] As an example, the controller can collect real-time load parameters and update status information once per second, thereby ensuring that the status information can reflect the dynamic changes of the controller load at a finer time granularity.

[0145] In this feasible implementation, the real-time load status is obtained by periodically collecting multi-dimensional real-time load parameters and weighted summing them. The status information of each controller is then updated accordingly. This allows the controller's load judgment to be based on real-time, multi-dimensional, and quantitatively unified data, which significantly improves the accuracy of controller selection and avoids routing requests to overloaded controllers due to lagging status information, thereby improving data read and write performance.

[0146] One feasible implementation involves calling the cache to execute read / write requests, including: identifying the request type of the read / write request; when the request type is a write request, obtaining the data to be written, writing the metadata and verification information of the data to be written to the local cache of the target controller, and then writing the data payload of the data to be written to the local cache; backing up the data to be written to a preset log storage partition; when the request type is a read request, searching the local cache for the existence of corresponding cached data based on the logical block address and logical volume identifier; if the corresponding cached data is found, reading the corresponding cached data; if the corresponding cached data is not found, reading the data from the main storage.

[0147] For example, after the target controller is determined, the target controller identifies the request type of the read and write requests, which includes two types: read requests and write requests.

[0148] For write requests, the target controller obtains the data to be written, first writes the metadata and verification information of the data to be written to the local cache, and then writes the data payload of the data to be written to the local cache.

[0149] Metadata describes the ownership information of the written data, which may include logical volume identifiers, logical block addresses, etc. Verification information is used to verify data integrity during data reading or recovery. The data payload is the actual business data written by the user. Writing metadata and verification information to the cache before the data payload ensures that even if an anomaly occurs during the writing process, the data to be written can be located and recovered based on the metadata and verification information.

[0150] For example, while the data of the write request is written to the local cache, the target controller backs up the data to be written to a preset log storage partition, thereby providing a persistent copy of the data that is independent of the controller's local cache before the local cache has flushed the data to the main storage.

[0151] Log storage partitions can be deployed on persistent storage media, such as storage class memory (SCM) media, which have lower access latency than backend media such as solid state drives (SSDs) and can provide persistent protection for cached data within a controllable write overhead.

[0152] Below, in conjunction with Figure 8 Instructions for writing data are provided.

[0153] Figure 8 This is a schematic diagram illustrating data writing provided in an embodiment of this application. For example... Figure 8 As shown, the write cache space of the Dynamic Random-Access Memory (DRAM) of controller A is divided into two equal-sized cache write-ahead logs (Cache_WAL), Cache_WAL_1 and Cache_WAL_2. The corresponding log storage partition, Log Area A, is divided into two equal-sized partitions, LOG1 and LOG2. LOG1 is used to back up the data in Cache_WAL_1, and LOG2 is used to back up the data in Cache_WAL_2. Cache_WAL_1 and Cache_WAL_2 form a ping-pong write cache.

[0154] The meaning of "ping-pong" is that when the host writes data to the cache, it first writes it to a Cache_WAL, such as Cache_WAL_1. When this Cache_WAL is full, Cache_WAL_1 goes to the background for flushing, flushing the dirty data in the cache to the main storage. At this time, Cache_WAL_2 is used to receive data written by the host in the foreground. When Cache_WAL_2 is full, it goes to the background for flushing. The flushed Cache_WAL_1 is then used to receive data written by the host in the foreground. The two Cache_WALs form a pipeline of foreground writing and background flushing.

[0155] The process of writing data from the host to storage is as follows:

[0156] (1) The IO is first written to the corresponding Cache_WAL. The data written to the Cache_WAL is divided into two parts. One part is the metadata information of this IO, which includes LUN ID, LBA, and TP (timestamp, a field used for fault handling). The other part is the data part of this IO. The written data will be indexed by a hash table built in memory (the hash key is calculated using LUN ID and LBA) to facilitate fast lookup when reading the data later.

[0157] (2) IO will simultaneously write to the log area of ​​the log storage partition. The data written is the same as the data written to Cache_WAL, which also includes two parts: metadata and data.

[0158] (3) Once the IO write to Cache_WAL and LOG in the log area is complete, the host can respond that the write is complete.

[0159] (4) Subsequent IO operations follow the above process. When writing to the Cache_WAL and the log area, the data is appended from the address space to the maximum. When the Cache_WAL is full, the data is flushed in the background, and another Cache_WAL begins to receive the data written by the foreground host.

[0160] For example, for a read request, the target controller searches the local cache for corresponding cached data based on the logical block address and logical volume identifier. This search can be quickly completed using a cache index built with the logical block address and logical volume identifier as keys. When the corresponding cached data is found, it means that the data has been previously written to the local cache and has not yet been replaced; the target controller directly reads the cached data and returns it. When the corresponding cached data is not found, it means that the latest version of the data does not exist in the local cache; the target controller then reads the data from the main storage and returns it. It can also choose to backfill the read data into the local cache for future access. Through this read / write process, write requests are only successfully responded to after data has been written to disk in both the local cache and the log storage partition, while read requests prioritize hitting the local cache to reduce access latency.

[0161] With the scenario example, after the target controller identifies the current request as a write request, it sequentially writes the metadata, verification information, and data payload of the data to be written to the local cache. Simultaneously, it backs up the data to be written to the log storage partition corresponding to the target controller, and then returns a write success message to the host. Subsequently, when the host initiates a read request for the same logical block address, the target controller retrieves the corresponding cached data in its local cache and returns it directly, without accessing the main storage. If the data corresponding to the read request has not yet been written to the local cache, the target controller reads the data from the main storage and returns it, thus ensuring the integrity of the read request data.

[0162] In this feasible implementation, by executing differentiated cache read and write processes according to request type, write requests improve data reliability with the help of multi-level protection of metadata, verification information and log partitions, and read requests improve hit efficiency and reduce access latency with the priority retrieval of local cache, thereby improving the performance of data read and write.

[0163] One feasible implementation method is to aggregate multiple small write requests by: identifying and aggregating multiple concurrently received small write requests, filtering multiple small write data with consecutive addresses and belonging to the same logical block number; integrating and sorting the multiple small write data to obtain consecutive write data blocks; and performing cache write operations on the basis of consecutive write data blocks.

[0164] For example, when a host is running applications such as databases, it generates a large number of short, random write requests. If these requests are written to the cache one by one, it will introduce a lot of overhead in metadata maintenance and cache allocation, and cause fragmentation of the cache space. The controller aggregates and identifies multiple concurrently received small write requests, and filters out multiple small write data that are consecutive in address and belong to the same logical block number.

[0165] Address contiguousness means that the logical block addresses pointed to by multiple small write requests are connected end to end without any gaps. Belonging to the same logical block number means that multiple small write data are located within the address range covered by the same logical block. Multiple small write data that meet the above two conditions can be merged and processed.

[0166] For example, the controller integrates and sorts multiple small write data requests according to their logical block addresses, concatenates them into a single contiguous write data block, and then performs cache write operations on this contiguous write data block as a unit. By integrating multiple scattered small write requests into a single larger contiguous write, the number of cache writes and metadata maintenance overhead are reduced, while ensuring that the data to be written in the cache remains contiguous in address.

[0167] With the example scenario, the controller receives five write requests concurrently within a short period of time. Their logical block addresses are address A, address A plus 4KB, address A plus 8KB, address A plus 12KB, and address A plus 16KB, respectively. After aggregation and identification, it is confirmed that these five write requests have consecutive addresses and belong to the same logical block number. The controller integrates and sorts the data of these five write requests according to their address order, concatenates them into a continuous write data block covering a continuous address range of 20KB, and performs a cache write operation at once.

[0168] In this feasible implementation, by aggregating, identifying, sorting, and forming continuous write data blocks from concurrent small write requests before performing cache writes, the metadata overhead and cache allocation times during small write request processing are significantly reduced, improving cache write efficiency and cache space continuity, thereby enhancing data read and write performance.

[0169] One feasible implementation method is to perform the cache data flushing process as follows: real-time monitoring of the data usage capacity of the local cache; when the data usage capacity is greater than or equal to a preset capacity threshold, sending the cached data in the local cache to the main storage and verifying the data integrity; after the data flushing is completed and the data integrity verification is passed, deleting the corresponding backup data from the local cache.

[0170] For example, the local cache has a limited capacity. To ensure the cache can continuously handle new written data, the written data in the cache needs to be flushed to the main storage periodically or irregularly. The controller monitors the data usage of the local cache in real time and compares the data usage with a preset capacity threshold. The preset capacity threshold is a pre-set capacity limit used to trigger the flush operation.

[0171] For example, it can be set to 80% of the total local cache capacity. When the data usage is less than the preset capacity threshold, the cache space is sufficient and the refresh is not triggered. When the data usage is greater than or equal to the preset capacity threshold, the cache space becomes tight, and the controller sends the cached data in the local cache to the main storage.

[0172] For example, during the process of sending cached data to primary storage, the controller needs to verify data integrity to confirm that no data has been lost or corrupted during the transfer from the local cache to the primary storage. Data integrity verification can be implemented using methods such as checksums and comparisons. For instance, it can compare the checksum information recorded in the local cache with the checksum information recalculated by the primary storage after receiving the data. After successful verification, the data in the primary storage is considered complete and reliable persistent data. At this point, the controller deletes the corresponding backup data from the local cache, freeing up cache space to accommodate new data writes.

[0173] Below, in conjunction with Figure 9 The troubleshooting process is explained.

[0174] Figure 9 This is a schematic diagram illustrating fault handling provided in an embodiment of this application. Figure 9 As shown, when controller A fails, its cache still contains dirty data that hasn't been flushed to main storage. Controller B then takes over the services from controller A. During this takeover, controller B reads the backed-up dirty data from log area A corresponding to controller A into its cache and establishes a hash table mapping for this data in memory. At this point, the takeover is complete, and the data in Domain0 corresponding to controller A can be accessed normally. The takeover process is similar for two or three controllers failing simultaneously: the controller responsible for taking over the services reads the backed-up dirty data from its corresponding log area to complete the takeover.

[0175] Below, in conjunction with Figure 10 Explanation of invalid data handling.

[0176] Figure 10 This is a schematic diagram illustrating invalid data processing provided in an embodiment of this application. Figure 10As shown, after a controller failure and subsequent recovery, with the takeover and rollback of services, old data may appear in the controller cache. For example, if controller A fails and controller B takes over the services in Domain 0, controller B's cache will contain data from Domain 0. When controller A recovers, the services in Domain 0 will roll back to controller A, at which point the cached data for Domain 0 in controller B will become invalid old data. This data needs to be invalidated from the cache to prevent a recurrence of controller A failure and controller B retrieving incorrect old data from the cache after taking over the services in Domain 0.

[0177] The following table provides an example of fault handling:

[0178] Table 1

[0179]

[0180] Referring to Table 1, if controller A fails at time T0, the services in Domain 0 need to be taken over, so the Domain 0_TP value increments by 1 to become 1. If controller A recovers at time T1, the services in Domain 0 need to be switched back to controller A, so the Domain 0_TP value increments by 1 to become 2. If controller B fails at time T2, the services in Domain 1 need to be taken over, so the Domain 1_TP value increments by 1 to become 1. When the TP value of a Domain changes, the cluster will send the updated value to the online controller.

[0181] With the scenario example, the controller monitors in real time that the data usage of the local cache has reached the preset capacity threshold, and then triggers the flush process to send the cached data in the local cache to the main storage in batches, and verifies the integrity of the data one by one; after the data flush is completed and the data integrity verification is passed, the controller deletes the corresponding backup data from the local cache, and the data usage of the local cache decreases accordingly.

[0182] As an example, when deleting backup data, you can also invalidate the corresponding backup records in the log storage partition to free up space in the log storage partition.

[0183] In this feasible implementation, by monitoring the cache data usage capacity in real time and triggering a refresh when the preset capacity threshold is reached, and only deleting the backup data in the local cache after the refresh is completed, the continuous utilization of cache space is ensured, while ensuring the integrity of data during the migration process between the cache and the main storage, avoiding the risk of data loss and corruption, thereby improving the reliability of data reading and writing.

[0184] One feasible implementation method is to determine the data to be sent to the main storage by: obtaining the count value of a statistical counter in the local cache, the count value being used to record the access frequency and residence time of the cached data; determining the data to be sent from the cached data based on the access frequency and residence time; and sending the data to be sent to the main storage.

[0185] For example, when a cache flush is triggered, there are usually multiple cached data entries in the local cache, and the value of these different cached data entries is not the same. To improve the rationality of the flush, the controller maintains a statistical counter for the local cache. The count value of the statistical counter is used to record the access frequency and residence time of each cached data entry.

[0186] Access frequency describes the number of times each cached data is accessed within a certain period of time, while dwell time describes the duration of each cached data in the local cache since it was written. The controller reads the count value of the statistics counter and combines the access frequency and dwell time to determine whether each cached data is suitable for flushing.

[0187] For example, cached data with low access frequency and long residence time indicates that it has not been accessed for a long time and has occupied the cache for a long time. It is data that is unlikely to be accessed again, so it should be identified as data to be sent and flushed to the main storage first. Cached data with high access frequency is hot data and should be kept in the local cache as much as possible to maintain a high hit rate.

[0188] By selectively flushing based on access frequency and dwell time, cache space can be released while maximizing the retention of high-frequency hot data in the cache, thereby maintaining the cache hit rate.

[0189] To illustrate with a scenario example, cached data X in the local cache is accessed once per second and resides for 120 seconds, while cached data Y is accessed 50 times per second and resides for 3 seconds. After reading the above count values ​​through the statistical counter, the controller determines that the possibility of cached data X being accessed again is low, so it identifies cached data X as data to be sent and sends it to the main storage, while cached data Y continues to be retained in the local cache.

[0190] In this feasible implementation, a statistical counter is used to record and differentiate the flushing of cached data based on access frequency and dwell time. Low-frequency and long-dwelling cold data is flushed first, while high-frequency hot data is retained in the cache. This ensures that cache space can be continuously released while effectively maintaining the cache hit rate, thereby improving the performance of data read and write.

[0191] One feasible implementation method for managing cached data version identifiers includes: determining the target version identifier corresponding to the target space domain; binding the target version identifier to the cached data when writing cached data to the local cache; and comparing the version identifier bound to be read with the target version identifier when reading data from the local cache. If the version identifiers do not match, the data is read from the main storage.

[0192] For example, in a scenario of controller failure takeover and service rollback, the cache of a certain controller may contain old data that was previously written when carrying the spatial domain service. This old data becomes invalid after the spatial domain service has been taken over by another controller and new data has been written to it.

[0193] To distinguish between new and old cached data, the storage system maintains a version identifier for each spatial domain. The version identifier is updated as spatial domain services are taken over or switched back. When the controller writes cached data to the local cache, it determines the target version identifier currently corresponding to the spatial domain to which the data belongs, and binds the target version identifier to the cached data, that is, writes it into the metadata of the cached data, thereby marking the cached data with a version mark.

[0194] For example, when reading data from the local cache, the controller compares the version identifier bound to the cached data to be read with the target version identifier of the current space domain. If they match, it means that the cached data is new data written under the current business version of the space domain and can be read and returned directly. If they do not match, it means that the cached data is old data written in the previous business version and may have been replaced by new data written during the takeover period of other controllers. The controller does not return the old data, but instead reads the latest data from the main storage.

[0195] To illustrate with a scenario example, when the services in space domain 0 are handled by controller A, the target version identifier for space domain 0 is 1.0, and all cached data written by controller A is bound to version identifier 1.0. After controller A fails, controller B takes over the services in space domain 0, updating the target version identifier to 2.0, and all cached data written by controller B is bound to version identifier 2.0. After controller A recovers, the services in space domain 0 are switched back to controller A, the target version identifier is updated to 3.0, and all cached data written by controller A is bound to version identifier 3.0. Data in controller B's cache bound to version identifier 1 then becomes old data. If, subsequently, the services in space domain 0 are again taken over by controller B, when controller B reads the cache, it compares the version identifiers bound to each cached data. If it finds that data bound to version identifier 2.0 is inconsistent with the current target version identifier, it determines that the data is old data and reads the latest data from the main storage.

[0196] In this feasible implementation, by maintaining a version identifier for the target space domain and binding the version identifier to the cached data, the version identifier is compared during reading to identify old data. This eliminates the need for a full traversal of the cache to accurately distinguish between new and old cached data, effectively avoiding the risk of reading invalid old data in fault takeover and rollback scenarios. It also reduces the computational overhead of handling invalid old data, thereby improving the performance of data reading and writing.

[0197] One feasible implementation method for controller fault takeover is as follows: real-time monitoring of the heartbeat status and link connection status of each controller; when no heartbeat signal is received from any controller for a preset number of consecutive times, or when the link connection status is abnormal, the controller is identified as an abnormal controller; the normal controller with the lowest load among all controllers is identified as the takeover node; and the abnormal controller is taken over through the takeover node.

[0198] For example, a multi-controller storage system ensures high availability through a fault detection and takeover mechanism. Each controller periodically sends heartbeat signals to each other to confirm their liveness; simultaneously, it monitors the link connection status between controllers to confirm whether the communication links are unobstructed. Each controller monitors the heartbeat and link connection status of each controller in real time. If a controller fails to receive a heartbeat signal from a predetermined number of consecutive times, it indicates that the controller may have failed; if the link connection status of a controller is abnormal, it indicates that the controller may be alive but is unable to communicate normally. In both of these cases, the controller is identified as an abnormal controller.

[0199] For example, after the faulty controller is determined, the storage system needs to select one of the remaining normal controllers to take over the services of the faulty controller. To balance the load and ensure the quality of the takeover, the controller with the lowest load among the normal controllers is selected as the takeover node. The lowest load can be achieved by comparing the real-time load status of each normal controller, for example, selecting the normal controller with the smallest real-time load status quantization value as the takeover node. After the takeover node is determined, it takes over the space domain services carried by the faulty controller, thereby ensuring that the read and write requests carried by the faulty controller can continue to be processed.

[0200] To illustrate with a scenario example, in a four-controller storage system, controller A fails to receive a heartbeat signal from controller B three times consecutively, and controller B's link connection status is abnormal. Based on this, controller A identifies controller B as an abnormal controller. Controller A compares the real-time load status of the other normal controllers and determines that controller C, with the lowest load, is the takeover node. Controller C then takes over the spatial domain services carried by controller B.

[0201] As an example, when taking over a business, the takeover node can read the backup data that has not yet been flushed from the log storage partition corresponding to the fault controller and load it into its own cache, so that it can still provide the latest data access service after the business is taken over.

[0202] In this feasible implementation, by monitoring the heartbeat status and link connection status in real time and determining the abnormal controller based on a preset number of consecutive occurrences or link anomalies, and then selecting the normal controller with the lowest load as the takeover node to perform business takeover, controller failures can be detected in a timely and reliable manner and business migration can be completed. While maintaining load balance, the high availability and business continuity of the storage system are significantly improved, thereby improving the performance of data read and write.

[0203] One feasible implementation method is to perform data recovery after takeover by the following steps: caching the read log data to a memory buffer area through the takeover node; hierarchically dividing the data in the memory buffer area to obtain business data types, which are either core business data or ordinary business data; and implementing corresponding data recovery strategies based on the business data types.

[0204] For example, after a takeover node takes over the services of an anomaly controller, it needs to read the backup data that has not yet been flushed from the log storage partition corresponding to the anomaly controller, and cache the read log data in the takeover node's memory buffer area. The memory buffer area is a storage area allocated by the takeover node in its own memory for temporarily storing takeover data. It is used to receive data read from the log storage partition so that this data can be processed later and restored as accessible cached data. Cacheing log data in the memory buffer area first avoids repeated access to the log storage partition during the takeover process, thereby reducing takeover latency.

[0205] For example, the takeover node hierarchically divides the data in the memory buffer area, categorizing it into two types based on the business characteristics of the data: core business data and ordinary business data. Core business data refers to critical data with extremely high requirements for business continuity, such as core financial transaction data; its loss or prolonged inaccessibility would have serious consequences. Ordinary business data refers to data of relatively lower importance, which can be recovered with a certain delay within a certain period. The determination of data type can be made based on information such as the logical volume attributes to which the data belongs and the priority configuration of the logical volume identifier.

[0206] For example, the corresponding data recovery strategy is executed according to the data type of the business. For example, for core business data, the takeover node first loads it from the memory buffer area into the cache and creates an index, so that it can immediately provide read and write services to the outside world, thereby minimizing the downtime of core business. For ordinary business data, the recovery can be completed gradually according to a relatively lenient time strategy, such as loading it in batches after the core business data has been recovered.

[0207] In this feasible implementation, by caching the read log data to the memory buffer area and dividing it into core business data and ordinary business data, and then executing differentiated data recovery strategies according to the business data type, the data recovery during the takeover process can proceed in an orderly manner according to the importance of the business, prioritizing the continuity of core business, while taking into account the recovery efficiency of ordinary business data and the rational utilization of system resources, thereby improving the performance of data reading and writing.

[0208] One feasible implementation method is to maintain the consistency of the mapping relationship between spatial domain identifiers and controllers by: periodically verifying the mapping relationship between spatial domains and controllers, comparing the matching degree between the real-time calculated spatial domains and the pre-stored mapping table; automatically correcting the mapping relationship and synchronously updating the mapping cache of all cluster nodes when a mapping deviation caused by the adjustment of the preset address segment length or the online / offline status of the controller is detected; and marking the read and write requests during the correction process.

[0209] For example, the mapping relationship between spatial domain identifiers and controllers may deviate during system operation due to events such as address segment length adjustment or controller online / offline status.

[0210] For example, adjusting the address segment length will change the way logical blocks are divided, which may in turn change the correspondence between logical block numbers and spatial domains; controller online / offline status will cause changes in the carrier of spatial domain services. To promptly detect and eliminate these deviations, the controller periodically verifies the mapping relationship between spatial domain identifiers and the controller. It compares the spatial domain identifiers, which are calculated in real time based on the current address segment length and the number of spatial domains, with the records in the pre-stored mapping table to calculate the matching degree between the two.

[0211] For example, when the matching degree decreases or inconsistencies are found during comparison, i.e., when the mapping deviation caused by the adjustment of address segment length or the online / offline status of the controller is detected, the controller automatically corrects the mapping relationship to make the mapping relationship consistent with the real-time calculation result, and synchronously updates the corrected mapping relationship to the mapping cache of each node in the entire cluster, ensuring that all controllers perform request routing based on a consistent mapping relationship.

[0212] Optionally, synchronous updates can be performed using intra-cluster broadcasting or a consensus negotiation mechanism to ensure the convergence of mapping caches on each node.

[0213] Optionally, the mapping correction process has a time window. Within this time window, some read and write requests may be routed according to the old mapping, while others may be routed according to the new mapping. To avoid request routing errors and data anomalies caused by mapping switching, the controller marks read and write requests during the correction process.

[0214] For example, a transition flag can be added to read and write requests within the transition window, so that they are handled specially during the mapping switch, such as being temporarily forwarded to the original bearer controller or executed after the new mapping relationship has fully taken effect, thereby avoiding data inconsistency caused by the same data area being processed by two different controllers at the same time.

[0215] In this feasible implementation, by periodically verifying the mapping relationship and comparing the matching degree, the mapping deviation caused by address segment length adjustment and controller online / offline status can be detected and automatically corrected in a timely manner. At the same time, the mapping cache of all cluster nodes is updated synchronously, and read and write requests during the correction process are marked. This effectively ensures the consistency of the mapping relationship between controllers, avoids request routing errors and data anomalies during the mapping switch process, and thus improves the performance of data read and write.

[0216] As an example, data written to the cache can have a hash index built into the controller's memory. The hash index uses the hash value calculated from the logical volume identifier and the logical block address as the key, pointing to the storage location of the corresponding cached data in the cache. When a read request arrives, the controller calculates the hash value using the logical volume identifier and the logical block address, and uses the hash index to locate whether the corresponding cached data exists within a constant time, thus avoiding a linear traversal search of the cached data.

[0217] For example, the establishment of a hash index enables cached data to be efficiently located in both the writing and retrieval directions. When a write request writes cached data, the hash index is registered synchronously. When a read request retrieves cached data, it is located directly based on the hash index. Even in the case of controller failure takeover, the takeover node can rebuild the hash index after loading the log data into the cache, thereby ensuring that the cached data after takeover can be retrieved quickly.

[0218] In this example, by creating a hash index based on the logical volume identifier and logical block address for the cached data, both the writing and reading of the cached data can be completed in a constant time, avoiding the traversal overhead during the cache lookup process, further improving the efficiency of cache access, and supporting the rapid reconstruction of cached data in fault takeover scenarios.

[0219] Figure 11 This is a schematic diagram of a data read / write device provided in an embodiment of this application. Figure 11As shown, the data read / write device 110 may include: a receiving module 111, a mapping module 112, a determining module 113, and an execution module 114.

[0220] The receiving module 111 is used to receive read / write requests and determine the logical block address and logical volume identifier from the read / write requests.

[0221] The mapping module 112 is used to evenly divide the logical storage space corresponding to the logical volume identifier into multiple logical segments according to the preset address segment length, and to allocate space domains to the multiple logical segments according to the number of controllers to obtain multiple space domains.

[0222] The determination module 113 is used to determine the target spatial domain from multiple spatial domains based on the logical block address and the logical volume identifier.

[0223] The execution module 114 is used to determine the target controller corresponding to the target spatial domain based on the mapping relationship between the spatial domain and the controller, and to call the cache through the target controller to execute read and write requests.

[0224] Optionally, the receiving module 111 can perform... Figure 4 S401 in the embodiment.

[0225] Optionally, the mapping module 112 can execute Figure 4 S402 in the embodiment.

[0226] Optionally, module 113 can be executed. Figure 4 S403 in the embodiment.

[0227] Optionally, execution module 114 can execute Figure 4 S404 in the embodiment.

[0228] In one possible implementation, the mapping module 112 is specifically used for:

[0229] Obtain multiple segment starting boundaries corresponding to multiple spatial domains.

[0230] Based on multiple segment start boundaries, when the logical block address does not fall on any segment start boundary, the logical block address is rounded up to the nearest segment start boundary to obtain the rounded logical block address.

[0231] The target spatial domain is determined from multiple spatial domains based on the normalized logical block address and logical volume identifier.

[0232] In one possible implementation, the mapping module 112 is specifically used for:

[0233] The ratio of the normalized logical block address to the preset address segment length is used to determine the logical segment number.

[0234] The first result is obtained by performing a modulo operation on the logical segment number based on the number of spatial domains, and the second result is obtained by performing a modulo operation on the logical volume identifier based on the number of spatial domains in the storage system.

[0235] The sum of the first and second operation results is modulo the number of spatial domains to obtain the target spatial domain identifier.

[0236] Among multiple spatial domains, the spatial domain corresponding to the target spatial domain identifier is determined as the target spatial domain.

[0237] In one possible implementation, execution module 114 is specifically used for:

[0238] Obtain the original mapping relationship between the pre-configured spatial domain and the controller.

[0239] Obtain historical access statistics for the target spatial domain, and adjust the original mapping relationship based on the historical access statistics to obtain the adjusted mapping relationship.

[0240] Based on the corrected mapping relationship, the candidate controller corresponding to the target spatial domain is determined.

[0241] The operating status and load status of the candidate controller are determined from the status information of the candidate controller.

[0242] When the operating status is normal and online, and the load status is within the preset load range, the candidate controller is determined as the target controller.

[0243] In one possible implementation, execution module 114 is specifically used for:

[0244] Identify the request type for read and write requests.

[0245] When the request type is a write request, the data to be written is obtained, the metadata and verification information of the data to be written are written to the local cache of the target controller, and then the data payload of the data to be written is written to the local cache.

[0246] Back up the data to be written to the preset log storage partition.

[0247] When the request type is a read request, retrieve whether the corresponding cached data exists in the local cache based on the logical block address and logical volume identifier.

[0248] If the corresponding cached data is found, it is read. If the corresponding cached data is not found, the data is read from the main storage.

[0249] It should be noted that the data read / write device shown in the embodiments of this application can execute the technical solutions shown in the above method embodiments, and its implementation principle and beneficial effects are similar, so they will not be described again here.

[0250] Figure 12 This is a schematic diagram of another data read / write device provided in an embodiment of this application. Figure 11 Based on the illustrated embodiments, as Figure 12 As shown, the data read / write device 110 also includes: an adjustment module 115, a status update module 116, an aggregation module 117, a brush module 118, a scheduling module 119, a version management module 120, a takeover module 121, a recovery module 122, and a mapping maintenance module 123.

[0251] Adjustment module 115 is used for:

[0252] Periodically collect access characteristics of each logical segment. The access characteristics include at least one of the following: request size distribution, access frequency, and consecutive access span.

[0253] Based on access characteristics, determine the access patterns of each logical segment.

[0254] Adjust the address segment length of each logical segment according to the access mode.

[0255] State update module 116 is used for:

[0256] Periodically collect real-time load parameters of each controller. The real-time load parameters include at least one of the following: queue backlog, computing power utilization, and cache read / write throughput.

[0257] The real-time load parameters are weighted and summed to obtain the real-time load status of each controller.

[0258] The status information of each controller is updated based on the real-time load status of each controller.

[0259] Aggregation module 117 is used for:

[0260] Multiple concurrently received small write requests are aggregated and identified, and multiple small write data that are consecutive in address and belong to the same logical block number are filtered.

[0261] Multiple small write operations are combined and sorted to obtain consecutive write data blocks. Cache write operations are then performed on a per-block basis.

[0262] The downsweep module 118 is used for:

[0263] Monitor the data usage of the local cache in real time.

[0264] When the data usage capacity is greater than or equal to the preset capacity threshold, the cached data in the local cache is sent to the main storage, and the data integrity is verified.

[0265] After the data refresh is complete and the data integrity verification passes, the corresponding backup data is deleted from the local cache.

[0266] Scheduling module 119 is used for:

[0267] Get the count value of the statistics counter in the local cache. The count value is used to record the access frequency and residence time of cached data.

[0268] Based on access frequency and dwell time, determine the data to be sent from the cached data.

[0269] Send the data to be sent to the main storage.

[0270] Version management module 120 is used for:

[0271] Determine the target version identifier corresponding to the target spatial domain.

[0272] When writing cached data to the local cache, the target version identifier is bound to the cached data.

[0273] When reading data from the local cache, the version identifier bound to the data to be read is compared with the target version identifier. If the version identifiers do not match, the data is read from the main storage.

[0274] The receiver module 121 is used for:

[0275] Real-time monitoring of the heartbeat status and link connection status of each controller.

[0276] If a controller fails to receive a heartbeat signal from any controller for a preset number of consecutive times, or if the link connection status is abnormal, the controller will be identified as an abnormal controller.

[0277] The normal controller with the lowest load among all controllers is identified as the takeover node.

[0278] Take over the exception controller by taking over the node.

[0279] Recovery module 122 is used for:

[0280] The log data read is cached in a memory buffer area by taking over the node.

[0281] The data in the memory buffer area is hierarchically divided to obtain business data types, which can be either core business data or ordinary business data.

[0282] Implement corresponding data recovery strategies based on the data type of the business.

[0283] Mapping maintenance module 123 is used for:

[0284] Periodically verify the mapping relationship between the spatial domain and the controller, and compare the matching degree between the spatial domain calculated in real time and the pre-stored mapping table.

[0285] When a mapping deviation is detected due to an adjustment in the preset address segment length or the controller going online or offline, the mapping relationship is automatically corrected and the mapping cache of all nodes in the cluster is updated synchronously.

[0286] Mark read and write requests during the correction process.

[0287] Figure 13 A schematic diagram of the structure of the electronic device provided in this application. Figure 13 As shown, the electronic device 130 provided in this embodiment includes at least one processor 1301 and a memory 1302. Optionally, the electronic device 130 also includes a communication component 1303. The processor 1301, the memory 1302, and the communication component 1303 are connected via a bus.

[0288] In the specific implementation process, at least one processor 1301 executes computer execution instructions stored in memory 1302, causing at least one processor 1301 to execute the above-described data read and write method embodiment.

[0289] The specific implementation process of processor 1301 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0290] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0291] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0292] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0293] Embodiments of this application also provide a non-volatile computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described data read / write method embodiments at runtime.

[0294] In one exemplary embodiment, the aforementioned non-volatile computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0295] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described data read / write method embodiments.

[0296] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described data read / write method embodiments.

[0297] Any of the components, modules, units, parts, methods, and operations described herein can be implemented using software, firmware, hardware (e.g., fixed logic circuitry), manual processing, or any combination thereof. Alternatively or additionally, any functionality described herein can be performed at least in part by one or more hardware logic components, such as, but not limited to, a central processing unit (CPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), an application-specific standard product (ASSP), a system-on-a-chip (SoC), a complex programmable logic device (CPLD), a microprocessor (MCU), etc. The terms "system," "computing device," or "apparatus" as used herein encompass various means, devices, and machines for processing data, including, for example, one or more programmable processors, computers, SoCs, or combinations thereof. The apparatus may also include code that creates an execution environment for the computer program in question, such as code constituting processor firmware, a protocol stack, a database management system, an operating system, a cross-platform runtime environment, a virtual machine, or a combination thereof. The aforementioned computer program (also known as a program, software, software application, app, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and can be deployed in any form, including as a standalone program or as a module, component, subroutine, object, or other unit suitable for a computing environment.

[0298] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0299] The data reading and writing method and electronic device provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of this application.

Claims

1. A data read / write method, characterized in that, include: Receive read / write requests and determine the logical block address and logical volume identifier from the read / write requests; Based on the preset address segment length, the logical storage space corresponding to the logical volume identifier is evenly divided into multiple logical segments. Based on the number of controllers, the multiple logical segments are allocated spatial domains to obtain multiple spatial domains. The target spatial domain is determined from the plurality of spatial domains based on the logical block address and the logical volume identifier; Based on the mapping relationship between spatial domains and controllers, the target controller corresponding to the target spatial domain is determined, and the read / write request is executed by calling the cache through the target controller.

2. The data read / write method according to claim 1, characterized in that, Determining the target spatial domain from the plurality of spatial domains based on the logical block address and the logical volume identifier includes: Obtain the multiple segmentation start boundaries corresponding to the multiple spatial domains; Based on the multiple segment start boundaries, when the logical block address does not fall on any segment start boundary, the logical block address is rounded up to the nearest segment start boundary to obtain the rounded logical block address. The target spatial domain is determined from the plurality of spatial domains based on the normalized logical block address and the logical volume identifier.

3. The data read / write method according to claim 2, characterized in that, Based on the normalized logical block address and the logical volume identifier, the target spatial domain is determined from the plurality of spatial domains, including: The ratio of the normalized logical block address to the preset address segment length is determined as the logical segment number; A first calculation result is obtained by performing a modulo operation on the logical segment number based on the number of spatial domains, and a second calculation result is obtained by performing a modulo operation on the logical volume identifier based on the number of spatial domains of the storage system. The sum of the first and second operation results is modulo the number of spatial domains to obtain the target spatial domain identifier; Among the plurality of spatial domains, the spatial domain corresponding to the target spatial domain identifier is determined as the target spatial domain.

4. The data read / write method according to claim 3, characterized in that, The method further includes: The access characteristics of each logical segment are periodically collected, and the access characteristics include at least one of the following: request size distribution, access frequency, and consecutive access span; Based on the access characteristics, determine the access pattern of each logical segment; Adjust the address segment length of each logical segment according to the access mode.

5. The data read / write method according to claim 1, characterized in that, Determining the target controller corresponding to the target spatial domain based on the mapping relationship between the spatial domain and the controller includes: Obtain the original mapping relationship between the pre-configured spatial domain and the controller; Obtain historical access statistics of the target spatial domain, and perform priority correction on the original mapping relationship based on the historical access statistics to obtain the corrected mapping relationship; Based on the corrected mapping relationship, the candidate controller corresponding to the target spatial domain is determined; The operating status and load status of the candidate controller are determined from the status information of the candidate controller. When the operating status is normal and online, and the load status is within the preset load range, the candidate controller is determined as the target controller.

6. The data read / write method according to claim 5, characterized in that, The method further includes: The real-time load parameters of each controller are periodically collected. The real-time load parameters include at least one of the following: queue backlog, computing power utilization, and cache read / write throughput. The real-time load parameters are weighted and summed to obtain the real-time load status of each controller; The status information of each controller is updated based on the real-time load status of each controller.

7. The data read / write method according to claim 1, characterized in that, Executing the read / write request by invoking the cache through the target controller includes: Identify the request type of the read / write request; When the request type is a write request, the data to be written is obtained, the metadata and verification information of the data to be written are written to the local cache of the target controller, and then the data payload of the data to be written is written to the local cache. The data to be written is backed up to a preset log storage partition; When the request type is a read request, the system retrieves whether corresponding cached data exists from the local cache based on the logical block address and the logical volume identifier. When the corresponding cached data is retrieved, the corresponding cached data is read. If the corresponding cached data is not found, read the data from the main storage.

8. The data read / write method according to claim 7, characterized in that, The method further includes: Aggregate and identify multiple concurrently received small write requests, and filter out multiple small write data that have consecutive addresses and belong to the same logical block number; The multiple small-amount write data are integrated and sorted to obtain a continuous write data block; The cache write operation is performed in units of the consecutively written data blocks.

9. The data read / write method according to claim 8, characterized in that, The method further includes: Real-time monitoring of the data usage of the local cache; When the data occupancy capacity is greater than or equal to a preset capacity threshold, the cached data in the local cache is sent to the main storage, and the data integrity is verified. After the data refresh is completed and the data integrity verification passes, the corresponding backup data is deleted from the local cache.

10. The data read / write method according to claim 9, characterized in that, Sending the cached data in the local cache to the main storage includes: Obtain the count value of the statistical counter in the local cache, the count value being used to record the access frequency and residence time of cached data; Based on the access frequency and the dwell time, the data to be sent is determined from the cached data; The data to be sent is sent to the main storage.

11. The data read / write method according to claim 7, characterized in that, The method further includes: Determine the target version identifier corresponding to the target spatial domain; When writing cached data to the local cache, the target version identifier is bound to the cached data; When reading data from the local cache, the version identifier to be read is compared with the target version identifier. If the version identifiers do not match, the data is read from the main storage.

12. The data read / write method according to any one of claims 1-11, characterized in that, The method further includes: Real-time monitoring of the heartbeat status and link connection status of each controller; If a controller fails to receive a heartbeat signal from any controller for a preset number of consecutive times, or if the link connection status is abnormal, the controller will be identified as an abnormal controller. The normal controller with the lowest load among all controllers is identified as the takeover node; The exception controller is taken over through the takeover node.

13. The data read / write method according to claim 12, characterized in that, The method further includes: The read log data is cached in a memory buffer area through the takeover node; The data in the memory buffer area is hierarchically divided to obtain business data types, which are either core business data or ordinary business data. Implement corresponding data recovery strategies based on the data type of the business.

14. The data read / write method according to any one of claims 1-11, characterized in that, The method further includes: The mapping relationship between the spatial domain and the controller is periodically verified, and the matching degree between the spatial domain calculated in real time and the pre-stored mapping table is compared. When the preset address segment length is adjusted or the mapping deviation is caused by the controller going online or offline, the mapping relationship is automatically corrected and the mapping cache of all cluster nodes is updated synchronously. Mark read and write requests during the correction process.

15. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the data read / write method as described in any one of claims 1 to 14 when executing the computer program.

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