Parallel flashing method and device of whole vehicle controller, electronic equipment and storage medium
Patent Information
- Application Number
- CN202611197055.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-08-07
- Publication Date
- 2026-11-03
AI Technical Summary
In the existing technology, the parallel flashing process of the vehicle controller has problems such as unbalanced thread load, insufficient stability of the flashing process, and long flashing time.
By determining the parallel controller in each bus, calculating the total write time, sorting them in descending order of total write time, and allocating the parallel controllers of the bus according to the number of writeable threads, the controllers are controlled to perform parallel writes by assigning the allocated threads, thus optimizing thread allocation to achieve parallel writes.
Thread load balancing was implemented, improving the efficiency of parallel flushing.
Smart Images
Figure CN123030346A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of vehicle technology, and in particular to a parallel flashing method, apparatus, electronic device, and storage medium for a vehicle controller. Background Technology
[0002] With the continuous development of vehicle technology, electronic control units (ECUs) have been widely used in vehicles. ECUs need to download the latest version of the flashing file from the background for online flashing and upgrading.
[0003] Currently, the relevant technologies mainly rely on multiple parallel threads on the vehicle side to simultaneously flash the ECU in batches, achieving simultaneous flashing of multiple components.
[0004] However, the blind use of all thread resources and the lack of differentiated scheduling in related technologies lead to problems such as unbalanced thread load, insufficient stability of the flushing process, and prolonged flushing time, which urgently need to be addressed. Summary of the Invention
[0005] This application provides a parallel flashing method, apparatus, electronic device, and storage medium for a vehicle controller to solve the problems of unbalanced thread load, insufficient stability of the flashing process, and prolonged flashing time in related technologies, thereby improving the efficiency of parallel flashing.
[0006] To achieve the above objectives, the first aspect of this application proposes a parallel flashing method for a vehicle controller, comprising the following steps: Determine the parallel controller in each bus; Based on the parallel controller in each bus, the total write time in each bus is calculated, and the initial order of multiple buses is obtained according to the total write time in each bus. The number of currently writable threads is determined, and based on the number of currently writable threads, the parallel controllers of multiple buses are allocated to the corresponding writable threads according to the initial sorting, and the allocated writable threads are controlled to perform parallel writing.
[0007] According to one embodiment of this application, obtaining the initial order of multiple buses based on the total write / flush duration in each bus includes: Based on the total write time of each bus, the buses are sorted in descending order of total write time to obtain the initial sorting of the buses.
[0008] According to one embodiment of this application, the step of allocating the parallel controllers of multiple buses to corresponding rewritable threads based on the current number of rewritable threads and according to the initial sorting includes: Based on the number of currently writable threads, determine the parallel controllers of the buses to be allocated in the initial sorting; The parallel controllers of the bus to be allocated are sequentially allocated to the corresponding currently writable threads, and the total write time of each writable thread after allocation is obtained. Based on the total write time of each writeable thread after allocation, the first target writeable thread with the shortest total write time is determined, and the first target writeable thread is determined from the parallel controllers of the remaining buses to be allocated in the initial sorting. The parallel controllers of the target bus to be assigned are assigned to the first target flashable thread, and the total flashing time of each flashable thread after assignment is updated. The step of determining the first target flashable thread with the shortest total flashing time based on the total flashing time of each flashable thread after assignment is re-executed until the initial sorting assigns the parallel controllers of multiple buses to the corresponding flashable threads.
[0009] According to one embodiment of this application, before determining the parallel controller in each bus, the method further includes: Identify the serial controller in each bus; The serial controller in each bus is assigned to a single flash thread for flashing.
[0010] According to one embodiment of this application, the number of threads occupied by the parallel controller in each bus is less than a preset number.
[0011] The parallel flashing method for a vehicle controller proposed in this application calculates the total flashing time for each bus based on the parallel controllers in each bus, obtains an initial order of multiple buses based on the total flashing time, and allocates the parallel controllers of multiple buses to the corresponding flashable threads based on the current number of flashable threads and the initial order, controlling the allocated flashable threads to perform parallel flashing. This solves the problems of uneven thread load, insufficient stability of the flashing process, and prolonged flashing time in related technologies, thus improving the efficiency of parallel flashing.
[0012] To achieve the above objectives, a second aspect of this application provides a parallel flashing device for a vehicle controller, comprising: Determine the module, and determine the parallel controller in each bus; The calculation module calculates the total write time of each bus based on the parallel controller in each bus, and obtains the initial order of multiple buses according to the total write time of each bus. The flashing module determines the number of currently flashable threads, and based on the number of currently flashable threads, allocates the parallel controllers of multiple buses to the corresponding flashable threads according to the initial sorting, and controls the allocated flashable threads to perform parallel flashing.
[0013] According to one embodiment of this application, the computing module is specifically used for: Based on the total write time of each bus, the buses are sorted in descending order of total write time to obtain the initial sorting of the buses.
[0014] According to one embodiment of this application, the computing module is specifically used for: Based on the number of currently writable threads, determine the parallel controllers of the buses to be allocated in the initial sorting; The parallel controllers of the bus to be allocated are sequentially allocated to the corresponding currently writable threads, and the total write time of each writable thread after allocation is obtained. Based on the total write time of each writeable thread after allocation, the first target writeable thread with the shortest total write time is determined, and the first target writeable thread is determined from the parallel controllers of the remaining buses to be allocated in the initial sorting. The parallel controllers of the target bus to be assigned are assigned to the first target flashable thread, and the total flashing time of each flashable thread after assignment is updated. The step of determining the first target flashable thread with the shortest total flashing time based on the total flashing time of each flashable thread after assignment is re-executed until the initial sorting assigns the parallel controllers of multiple buses to the corresponding flashable threads.
[0015] According to one embodiment of this application, before determining the parallel controller in each bus, the determining module is further configured to: Identify the serial controller in each bus; The serial controller in each bus is assigned to a single flash thread for flashing.
[0016] According to one embodiment of this application, the number of threads occupied by the parallel controller in each bus is less than a preset number.
[0017] The parallel flashing device for a vehicle controller proposed in this application calculates the total flashing time for each bus based on the parallel controllers in each bus, obtains an initial order of multiple buses based on the total flashing time, allocates the parallel controllers of multiple buses to the corresponding flashable threads based on the current number of flashable threads, and controls the allocated flashable threads to perform parallel flashing. This solves the problems of uneven thread load, insufficient stability of the flashing process, and prolonged flashing time in related technologies, thus improving the efficiency of parallel flashing.
[0018] To achieve the above objectives, a third aspect of this application provides an electronic device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the parallel flashing method for the vehicle controller as described in the above embodiments.
[0019] To achieve the above objectives, a fourth aspect of this application provides a computer-readable storage medium having a computer program stored thereon, which is executed by a processor to implement the parallel flashing method for the vehicle controller as described in the above embodiments.
[0020] To achieve the above objectives, a fifth aspect of this application provides a computer program product, which, when executed by a processor, implements the parallel flashing method for the vehicle controller as described in the above embodiments.
[0021] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description
[0022] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 This is a flowchart of a parallel flashing method for a vehicle controller according to an embodiment of this application; Figure 2 This is a schematic diagram illustrating the initial ordering of multiple buses according to an embodiment of this application; Figure 3 This is a schematic diagram of parallel controller thread allocation based on the number of writable threads and initial order according to an embodiment of this application; Figure 4 This is a schematic diagram illustrating the thread allocation of a parallel controller for multiple buses according to an embodiment of this application. Figure 5 This is a schematic diagram of a serial controller and a parallel controller for multiple buses according to an embodiment of this application; Figure 6 This is a schematic diagram illustrating the allocation of a single brush thread for a serial controller according to an embodiment of this application; Figure 7 This is a block diagram of a parallel flashing device for a vehicle controller provided according to an embodiment of this application; Figure 8 This is a schematic diagram of the structure of an electronic device provided according to an embodiment of this application. Detailed Implementation
[0023] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.
[0024] The parallel flashing method, apparatus, electronic device, and storage medium for a vehicle controller according to embodiments of this application will now be described with reference to the accompanying drawings. First, the parallel flashing method for a vehicle controller according to embodiments of this application will be described with reference to the accompanying drawings.
[0025] Figure 1 This is a flowchart of a parallel flashing method for a vehicle controller according to an embodiment of this application.
[0026] like Figure 1 As shown, the parallel flashing method for the vehicle controller includes the following steps: In step S101, the parallel controller in each bus is determined.
[0027] In this context, "bus" refers to the standardized data communication channel in the vehicle's electronic control system that connects the onboard controller, domain controller, and OTA (Over-the-Air Technology) master controller. "Parallel controller" refers to an onboard electronic control unit that supports simultaneous firmware flashing with other controllers.
[0028] Specifically, in this embodiment of the application, the parallel controllers that can participate in synchronous writing within each bus are determined based on the writing characteristics of the vehicle controller and the parallel constraints of the bus.
[0029] In step S102, based on the parallel controller in each bus, the total write time in each bus is calculated, and the initial order of multiple buses is obtained according to the total write time in each bus.
[0030] Optionally, in some embodiments, the initial sorting of multiple buses is obtained based on the total write duration in each bus, including: sorting the multiple buses in descending order of total write duration based on the total write duration in each bus to obtain the initial sorting of multiple buses.
[0031] The total flashing time for each bus refers to the total time taken for all controllers on a vehicle communication bus to complete the firmware upgrade.
[0032] Specifically, such as Figure 2 As shown, Figure 2 This diagram illustrates the initial ordering of multiple buses according to an embodiment of this application. As shown, this embodiment uses a Tbox (Telematics Box, in-vehicle remote information terminal) as the main control unit for vehicle-side OTA upgrades, responsible for flashing eight buses (BUS A to BUS H). The buses are ordered in descending order of the total upgrade time required for each bus. Figure 2 The length of the grid occupied by each parallel controller is positively correlated with the brushing time.
[0033] In step S103, the number of currently writable threads is determined, and based on the number of currently writable threads, the parallel controllers of multiple buses are allocated to the corresponding writable threads according to the initial sorting, and the allocated writable threads are controlled to perform parallel writing.
[0034] Optionally, in some embodiments, based on the current number of writable threads, the parallel controllers of multiple buses are allocated to the corresponding writable threads according to the initial sorting, including: determining the parallel controllers of the buses to be allocated in the initial sorting based on the current number of writable threads; sequentially allocating the parallel controllers of the buses to be allocated to the corresponding current writable threads, and obtaining the total write time of each writable thread after allocation; determining the first target writable thread with the shortest total write time based on the total write time of each writable thread after allocation, and determining the first-ranked parallel controller of the target bus to be allocated from the remaining parallel controllers of the buses to be allocated in the initial sorting; allocating the parallel controller of the target bus to be allocated to the first target writable thread, updating the total write time of each writable thread after allocation, and re-executing the step of determining the first target writable thread with the shortest total write time based on the total write time of each writable thread after allocation, until the initial sorting allocates the parallel controllers of multiple buses to the corresponding writable threads.
[0035] Among them, it refers to the execution unit that is determined in real time by the domain controller based on hardware capabilities and bus constraints during the vehicle OTA flashing process, is in an idle and available state, and can carry out parallel controller firmware flashing tasks.
[0036] Specifically, embodiments of this application determine the number of currently writable threads. For example... Figure 3 As shown, Figure 3This is a schematic diagram illustrating the parallel controller thread allocation based on the number of writable threads and the initial order, according to an embodiment of this application. As shown in the diagram, the controller is allocated to the currently writable threads according to the order of bus duration, i.e., the initial order of multiple buses. That is, according to the embodiment of this application... Figure 2 The bus sequence is determined by listing the parallel controllers of the first four buses into threads respectively.
[0037] like Figure 4 As shown, Figure 4 This is a schematic diagram illustrating the thread allocation of parallel controllers for multiple buses according to an embodiment of this application. As shown in the diagram, after the parallel controllers of the first four buses are respectively listed as threads, starting from the fifth bus, the parallel controllers of the buses are assigned to the threads with the shortest total duration. For example, since thread 4 has the shortest total duration, the controller in BUS-A is inserted into thread 4, the parallel controller in BUS-E is inserted into thread 3, the controller in BUS-F is inserted into thread 2, and the parallel controller in BUS-G is inserted into thread 1.
[0038] Furthermore, if there are still unallocated buses, the thread with the shortest time is found, and the parallel controller is inserted into the thread. Then, using the thread with the shortest time as the standard, it is determined whether there are still parallel controllers waiting to be written in other threads after this shortest time. If so, the parallel controller is moved to the thread with the shortest total time, until there is no parallel controller position that meets the above requirements. At this time, the controller arrangement in the threads is the optimal order for parallel writing of the vehicle, and parallel writing is performed according to the allocated writeable threads.
[0039] Furthermore, in some embodiments, the number of threads occupied by the parallel controller in each bus is less than a preset number.
[0040] The preset quantity can be a quantity pre-set by the user, a quantity obtained through a limited number of experiments, or a quantity obtained through a limited number of computer simulations.
[0041] Specifically, the bus has a maximum limit on the number of parallel writes; the number of controllers simultaneously written within the bus must not exceed the maximum parallel write limit set for the bus. Furthermore, during the migration scheduling process for the parallel controller targeting the shortest-duration thread, if a target parallel controller to be migrated is selected, the current operating status of the bus to which that controller belongs needs to be verified first. Only if the number of parallel write threads currently occupied by that bus is less than a preset number can the parallel controller be moved to the thread with the shortest total duration. If the bus has already reached the preset number, the current controller is skipped, and subsequent controllers are selected sequentially for repeated verification and scheduling judgments. This ensures that while achieving global load balancing for vehicle-wide writes and reducing the total upgrade time, the number of online parallel controllers on any bus remains below the preset maximum parallel limit.
[0042] Therefore, under the premise of complying with the parallel writing rules, the total writing time is configured to be as short as possible. The master controller / domain controller supports multi-way parallel writing of the add-on. The number of parallel writing processes is configured based on the actual test results of the domain controller and the line, and the controller is assigned to all threads of the domain controller according to the writing time value of the controller being written. The goal is to minimize the total writing time. This solves the problems of uneven thread load, insufficient stability of the writing process, and long writing time in related technologies, and improves the efficiency of parallel writing.
[0043] Furthermore, in order to avoid serial tasks crowding out parallel resources, this application embodiment first needs to identify the serial controller in the bus.
[0044] Optionally, in some embodiments, before determining the parallel controller in each bus, the method further includes: identifying the serial controller in each bus; assigning the serial controller in each bus to a single brush thread for brushing via the single brush thread.
[0045] Among them, the serial controller refers to an electronic control unit that, in the scenario of vehicle OTA firmware flashing, is limited by hardware architecture and communication protocol, does not support synchronous parallel upgrades, and can only occupy a single flashing thread to complete the flashing operation independently and sequentially.
[0046] Specifically, such as Figure 5 As shown, Figure 5 This diagram illustrates a serial controller and a parallel controller for multiple buses according to an embodiment of this application. As shown in the diagram, the ECC (Error Check and Correction Control Unit), marked in red, is a controller that is serially written and does not support parallel writing. In this embodiment, the serial controller needs to be written first. Figure 6 As shown, Figure 6This diagram illustrates the allocation of a single flashing thread for a serial controller according to an embodiment of this application. As shown in the diagram, this embodiment assigns the serial controller to a dedicated single flashing thread for independent flashing. Regardless of the total capacity of parallel flashing threads supported by the host computer, the serial controller occupies only one thread to run the upgrade task throughout the entire process. After all serial controllers have been independently upgraded in a preset order, the batch parallel flashing process for subsequent parallel controllers begins.
[0047] Therefore, the serial flashing controller prioritizes the flashing order and executes them sequentially in the same process. After the flashing is completed, the parallel controller is started to flash, which avoids the serial task occupying parallel resources and disrupting the overall scheduling rhythm, thus ensuring the controller's flashing efficiency.
[0048] Therefore, domain controllers with the same flashing power requirements can be flashed in parallel, and buses under a domain controller can also be flashed in parallel. Controllers within a bus are divided into two types: those supporting serial flashing and those supporting parallel flashing. Serial flashing controllers have priority in flashing order and are executed sequentially within the same process. After flashing is complete, parallel flashing is initiated. The number of parallel threads supported by a domain controller needs to be tested and verified in advance, and the number of parallel flashing threads supported by each domain controller must be confirmed. There is a maximum limit to the number of parallel flashing operations on a bus; the number of controllers flashing simultaneously within a bus must not exceed the maximum parallel flashing limit set for the bus. Controllers within a domain controller are grouped according to their thread count, and the total flashing time of each group should be as close as possible while meeting the above conditions. This application embodiment flexibly configures the number of parallel flashing threads for each domain controller and bus based on the actual vehicle bus capabilities, and combines this with the individual flashing time to achieve the optimized sorting with the shortest overall vehicle flashing time.
[0049] The parallel flashing method for a vehicle controller proposed in this application calculates the total flashing time for each bus based on the parallel controllers in each bus, obtains an initial order of multiple buses based on the total flashing time, and allocates the parallel controllers of multiple buses to the corresponding flashable threads based on the current number of flashable threads and the initial order, controlling the allocated flashable threads to perform parallel flashing. This solves the problems of uneven thread load, insufficient stability of the flashing process, and prolonged flashing time in related technologies, thus improving the efficiency of parallel flashing.
[0050] Next, referring to the accompanying drawings, a parallel flashing device for a vehicle controller according to an embodiment of this application is described.
[0051] Figure 7 This is a block diagram of a parallel flashing device for a vehicle controller according to an embodiment of this application.
[0052] like Figure 7 As shown, the parallel flashing device 10 of the vehicle controller includes: a determination module 100, a calculation module 200, and a flashing module 300.
[0053] Determine module 100, and determine the parallel controller in each bus; The computing module 200 calculates the total write time of each bus based on the parallel controller in each bus, and obtains the initial order of multiple buses according to the total write time of each bus. The flashing module 300 determines the number of currently flashable threads and, based on the current number of flashable threads, allocates the parallel controllers of multiple buses to the corresponding flashable threads according to the initial sorting, and controls the allocated flashable threads to perform parallel flashing.
[0054] According to one embodiment of this application, the calculation module 200 is specifically used for: Based on the total write time in each bus, the multiple buses are sorted in descending order of total write time to obtain the initial sorting of the multiple buses.
[0055] According to one embodiment of this application, the calculation module 200 is specifically used for: Based on the current number of writable threads, determine the parallel controllers of the buses to be allocated in the initial sorting; The parallel controllers of the bus to be allocated are sequentially allocated to the corresponding currently writable threads, and the total write time of each writable thread after allocation is obtained. Based on the total write time of each writeable thread after allocation, the first target writeable thread with the shortest total write time is determined, and the first target writeable thread is determined from the parallel controllers of the remaining buses to be allocated in the initial sort. Assign the parallel controllers of the target bus to be assigned to the first target flashable thread, update the total flashing time of each flashable thread after assignment, and re-execute the step of determining the first target flashable thread with the shortest total flashing time based on the total flashing time of each flashable thread after assignment, until the initial sorting assigns the parallel controllers of multiple buses to the corresponding flashable threads.
[0056] According to one embodiment of this application, before determining the parallel controller in each bus, the determination module 100 is further configured to: Identify the serial controller in each bus; Assign a single brush thread to the serial controller in each bus so that brushing is performed via a single brush thread.
[0057] According to one embodiment of this application, the number of threads occupied by the parallel controller in each bus is less than a preset number.
[0058] It should be noted that the foregoing explanation of the parallel flashing method embodiment for the vehicle controller also applies to the parallel flashing device for the vehicle controller in this embodiment, and will not be repeated here.
[0059] The parallel flashing device for a vehicle controller proposed in this application calculates the total flashing time for each bus based on the parallel controllers in each bus, obtains an initial order of multiple buses based on the total flashing time, allocates the parallel controllers of multiple buses to the corresponding flashable threads based on the current number of flashable threads, and controls the allocated flashable threads to perform parallel flashing. This solves the problems of uneven thread load, insufficient stability of the flashing process, and prolonged flashing time in related technologies, thus improving the efficiency of parallel flashing.
[0060] Figure 8 This is a schematic diagram of an electronic device provided in an embodiment of the present invention. The electronic device may include: The memory 801, the processor 802, and the computer program stored on the memory 801 and capable of running on the processor 802.
[0061] When the processor 802 executes the program, it implements the parallel flashing method for the vehicle controller provided in the above embodiments.
[0062] Furthermore, electronic devices also include: Communication interface 803 is used for communication between memory 801 and processor 802.
[0063] The memory 801 is used to store computer programs that can run on the processor 802.
[0064] The memory 801 may include high-speed RAM (Random Access Memory) memory, and may also include non-volatile memory, such as at least one disk storage.
[0065] If the memory 801, processor 802, and communication interface 803 are implemented independently, then the communication interface 803, memory 801, and processor 802 can be interconnected via a bus to complete communication between them. The bus can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus, etc. The bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 8The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.
[0066] Optionally, in a specific implementation, if the memory 801, processor 802, and communication interface 803 are integrated on a single chip, then the memory 801, processor 802, and communication interface 803 can communicate with each other through an internal interface.
[0067] The processor 802 may be a CPU (Central Processing Unit), an ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement embodiments of the present invention.
[0068] This invention also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the parallel flashing method for the vehicle controller described above.
[0069] This application also provides a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above embodiments of the parallel flashing method for a vehicle controller.
[0070] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0071] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0072] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.
Claims
1. A parallel flashing method for a vehicle controller, characterized in that, include: Determine the parallel controller in each bus; Based on the parallel controller in each bus, the total write time in each bus is calculated, and the initial order of multiple buses is obtained according to the total write time in each bus. The number of currently writable threads is determined, and based on the number of currently writable threads, the parallel controllers of multiple buses are allocated to the corresponding writable threads according to the initial sorting, and the allocated writable threads are controlled to perform parallel writing.
2. The method according to claim 1, characterized in that, The initial sorting of multiple buses based on the total write / flush duration of each bus includes: Based on the total write time of each bus, the buses are sorted in descending order of total write time to obtain the initial sorting of the buses.
3. The method according to claim 2, characterized in that, The step of allocating the parallel controllers of multiple buses to the corresponding rewritable threads according to the initial sorting based on the current number of rewritable threads includes: Based on the number of currently writable threads, determine the parallel controllers of the buses to be allocated in the initial sorting; The parallel controllers of the bus to be allocated are sequentially allocated to the corresponding currently writable threads, and the total write time of each writable thread after allocation is obtained. Based on the total write time of each writeable thread after allocation, the first target writeable thread with the shortest total write time is determined, and the first target writeable thread is determined from the parallel controllers of the remaining buses to be allocated in the initial sorting. The parallel controllers of the target bus to be assigned are assigned to the first target flashable thread, and the total flashing time of each flashable thread after assignment is updated. The step of determining the first target flashable thread with the shortest total flashing time based on the total flashing time of each flashable thread after assignment is re-executed until the initial sorting assigns the parallel controllers of multiple buses to the corresponding flashable threads.
4. The method according to claim 1, characterized in that, Before determining the parallel controller in each bus, the following is also included: Identify the serial controller in each bus; The serial controller in each bus is assigned to a single flash thread for flashing.
5. The method according to any one of claims 1-4, characterized in that, The number of threads in each parallel controller on each bus is less than the preset number.
6. A parallel flashing device for a vehicle controller, characterized in that, include: Determine the module, and determine the parallel controller in each bus; The calculation module calculates the total write time of each bus based on the parallel controller in each bus, and obtains the initial order of multiple buses according to the total write time of each bus. The flashing module determines the number of currently flashable threads, and based on the number of currently flashable threads, allocates the parallel controllers of multiple buses to the corresponding flashable threads according to the initial sorting, and controls the allocated flashable threads to perform parallel flashing.
7. The apparatus according to claim 6, characterized in that, The computing module is specifically used for: Based on the total write time of each bus, the buses are sorted in descending order of total write time to obtain the initial sorting of the buses.
8. An electronic device, characterized in that, include: The system includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the parallel flashing method for the vehicle controller as described in any one of claims 1-5.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that, The program is executed by the processor to implement the parallel flashing method for the vehicle controller as described in any one of claims 1-5.
10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the parallel flashing method for the vehicle controller as described in any one of claims 1-5.