Chip entry reconfiguration method, system, device and readable storage medium

Abstract

The application provides a chip entry reconfiguration method, system, device and readable storage medium. The method comprises: configuring a counter and at least one reconfiguration trigger node for each target entry of a chip; counting the read enable times of the corresponding target entry based on the counter; and when the count value of the counter reaches the reconfiguration trigger node of the corresponding target entry, reconfiguring the target entry reaching the reconfiguration trigger node based on a preset reconfiguration target value. Compared with the prior art, no matter how much difference exists in the simulation speed of each processing module, each processing module can complete reconfiguration switching under the same logical processing progress, so that the processing progress is always aligned during the whole reconfiguration process, and the comparator does not need to be closed throughout the whole process, and there is no comparison blind area in the reconfiguration window.

Description

Technical Field

[0001] This invention belongs to the field of network communication technology, and specifically relates to a chip entry reconfiguration method, system, device, and readable storage medium. Background Technology

[0002] During the operation of network chips, when network topology changes, service requirements are adjusted, or fault recovery occurs, the contents of the chip's tables (such as routing tables, forwarding tables, and access control lists) need to be dynamically updated in real time. If there are problems with the dynamic reconfiguration of chip tables, service processing will be affected for a short period of time, and in severe cases, it may even cause the chip to crash. Therefore, the verification of dynamic reconfiguration of chip tables is particularly important.

[0003] In chip verification, chip functionality is typically verified by comparing the results of the device under test (DUT) with the reference model (MDL). For verification of dynamically reconfigured entries, one existing approach is to shut down the comparator during the reconfiguration process and then restart it after completion. However, during the time window from the start to the completion of the reconfiguration, the comparator is in a closed state, making it impossible to accurately compare the processing results of the DUT and MDL. This could lead to missing faults occurring within this time window, resulting in verification vulnerabilities. Furthermore, shutting down and restarting the comparator requires additional control logic, increasing the complexity and risk of the verification environment.

[0004] Therefore, in order to address the above-mentioned technical problems, it is necessary to provide a chip entry reconfiguration method, system, device, and readable storage medium.

[0005] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide a chip entry reconfiguration method, system, device, and readable storage medium, which can solve the technical problem of comparison blind spots in the verification window during dynamic reconfiguration.

[0007] To achieve the above objectives, the technical solution provided by the present invention is as follows:

[0008] In a first aspect, the present invention provides a method for reconfiguring chip entries, comprising:

[0009] Configure counters and at least one reconfiguration trigger node for each target entry in the chip;

[0010] The counter counts the number of read enable operations for the corresponding target table entry.

[0011] When the counter value reaches the reconfiguration trigger node of the corresponding target entry, the target entry that has reached the reconfiguration trigger node is reconfigured based on the preset reconfiguration target value.

[0012] In one or more embodiments of the present invention, the target entry includes a first target entry configured in a first processing module and a second target entry configured in a second processing module, wherein the second processing module is a reference processing module for the first processing module, and the method further includes:

[0013] Based on the message processing order, the processing result of the first target entry on the data packet is compared with the processing result of the second target entry on the same data packet one by one;

[0014] If the processing results are consistent, then the reconfiguration is correct;

[0015] If the processing results are inconsistent, an error indication message will be output.

[0016] In one or more embodiments of the present invention, the first target entry and the second target entry establish a correspondence based on a preset index identifier.

[0017] In one or more embodiments of the present invention, the method further includes:

[0018] A corresponding reconfiguration data queue is established for each of the target entries. The reconfiguration data queue is used to store at least one of the reconfiguration target values ​​in a preset reconfiguration order. The number of reconfiguration trigger nodes is the same as the number of reconfiguration target values ​​stored in the queue.

[0019] When performing the configuration change operation, the configuration change target value is assigned to the read data port of the target table entry.

[0020] In one or more embodiments of the present invention, the method further includes:

[0021] After each target entry completes the reconfiguration operation, the counter continues to count.

[0022] When the counter reaches the next reconfiguration trigger node, the reconfiguration operation is performed on the target entry again based on the next preset reconfiguration target value in the reconfiguration data queue.

[0023] In one or more embodiments of the present invention, the method further includes:

[0024] When at least two target entries arrive at the corresponding reconfiguration trigger node simultaneously or in adjacent moments, the preset priority of each target entry is determined.

[0025] Based on the preset priority, the reconfiguration order of each target entry is determined;

[0026] According to the reconfiguration order, the reconfiguration operation is performed on each of the target entries in sequence.

[0027] In one or more embodiments of the present invention, the method further includes:

[0028] During the reconfiguration operation of the currently selected target table entry, no reconfiguration operation will be performed on other target table entries;

[0029] After the reconfiguration operation of the currently selected target entry is completed, the reconfiguration operation will be performed on the next target entry in the order of priority.

[0030] In a second aspect, the present invention provides a chip entry reconfiguration system, comprising:

[0031] The configuration module is used to configure counters and at least one reconfiguration trigger node for each target entry in the chip;

[0032] The statistics module is used to count the number of read enable operations for the corresponding target table entry based on the counter.

[0033] The reconfiguration module is used to reconfigure the target entry that has reached the reconfiguration trigger node based on a preset reconfiguration target value when the counter value reaches the reconfiguration trigger node of the corresponding target entry.

[0034] Thirdly, the present invention provides an electronic device comprising:

[0035] At least one processor; and a memory storing instructions that, when executed by the at least one processor, cause the at least one processor to perform the chip entry reconfiguration method.

[0036] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to execute the chip entry reconfiguration method.

[0037] Compared with existing technologies, the chip entry reconfiguration method provided by this invention configures a counter independently for each target entry and uses the packet count node as the reconfiguration trigger condition. This allows each processing module to trigger reconfiguration when it reaches the same packet count position, rather than reconfiguring simultaneously at the same absolute time point. Since the reconfiguration operation occurs after each processing module has processed the same number of data packets, regardless of the difference in simulation speed among the processing modules, each module can complete the reconfiguration switch at the same logical processing progress. This ensures that the processing progress remains aligned throughout the entire reconfiguration process, the comparator does not need to be closed throughout, and there are no blind spots in the comparison within the reconfiguration window.

[0038] Meanwhile, in the technical solution of this invention, each target entry is independently configured with a counter and a trigger node. Different entries can be configured with different trigger nodes according to their own needs, without being limited by the entry type or specific application scenario. It can be applied to any chip entry verification scenario that requires dynamic reconfiguration. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram of the modified control unit architecture in one embodiment of the present invention;

[0041] Figure 2 This is a flowchart of a chip entry reconfiguration method in one embodiment of the present invention;

[0042] Figure 3 This is a structural block diagram of a chip table reconfiguration system according to another embodiment of the present invention;

[0043] Figure 4 This is a structural block diagram of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0044] To enable those skilled in the art to better understand the technical solutions of this invention, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this invention.

[0045] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components.

[0046] Existing technical solutions employ a method of shutting down the comparator to avoid false alarms. Specifically, after initiating a dynamic reconfiguration operation between the device under test (DUT) and the reference model, the verification personnel immediately shut down the comparator, pausing the comparison of the output results from both the DUT and the reference model. The comparator is then restarted to resume the comparison after the DUT has completed the reconfiguration operation and both have cleared their pending data packets. However, since the reconfiguration command is issued simultaneously in absolute time, and the simulation execution speed of the reference model is significantly faster than that of the DUT, there is a difference in the number of data packets processed by the two at the same absolute moment. If the comparator remains on, numerous false alarms will occur due to the inconsistent processing progress, thus forcing the verification personnel to shut down the comparator. This technical solution inevitably presents the following problems: firstly, there is a blind spot in the comparison process within the time window from the start to the completion of the reconfiguration, making it impossible to capture potential faults during this period; secondly, additional switching control logic is required, increasing the complexity of the verification environment.

[0047] The inventors of this invention discovered that the main drawback of the prior art stems from the choice of reconfiguration triggering timing. Simultaneous reconfiguration triggering in the absolute time dimension inevitably conflicts with the speed differences between different processing modules. Based on an in-depth analysis of this drawback, the inventors proposed a new technical approach, switching the reconfiguration triggering timing from the absolute time dimension to the logical progress dimension reached by each processing module. Specifically, an independent counter is configured for each target entry to count the number of times its read enable is valid, and the condition for each module to independently trigger reconfiguration is based on the value of its respective counter reaching a preset packet count node. In this way, each processing module performs the reconfiguration switch after processing the same number of data packets, ensuring that each module uses the same configuration when processing the same data packet after reconfiguration, thus fundamentally avoiding the impact of speed differences on the synchronization of processing progress. Even if the processing progress of the device under test and the reference model are naturally misaligned in absolute time, the logical position of the reconfiguration, i.e., the packet count node, remains consistent. Through this method, the comparator remains on throughout the entire reconfiguration process, eliminating the need for a shutdown operation and thus completely eliminating the comparison blind spot.

[0048] Please refer to Figure 1 The diagram shows a schematic of the reconfiguration control unit architecture provided by the present invention in one embodiment. The reconfiguration control unit specifically includes: a reconfiguration data queue 101, a reconfiguration trigger node sequence 102, a counter alignment module 103, a priority arbitration module 104, and a force injection module 105.

[0049] The configuration reconfiguration data queue 101 is used to store the dynamic configuration reconfiguration target values ​​for each target table entry. Specifically, in one implementation, a separate configuration reconfiguration data queue, denoted as Q_table[i], can be configured for each target table entry that needs to be dynamically reconfigured, where i = 0, 1, ..., N-1, and N is the total number of target table entries that need to be dynamically reconfigured. Each queue stores one or more configuration reconfiguration target values ​​for the corresponding table entry in a first-in-first-out (FIFO) manner. The data structure of each data entry in the queue includes two fields: configuration reconfiguration target value and priority level. The configuration reconfiguration target value specifies the updated configuration content of the target table entry, and the priority level determines the configuration reconfiguration priority order of each table entry when multiple table entries are reconfigured concurrently. The configuration reconfiguration data queue 101 provides a storage and management mechanism for the configuration reconfiguration target values ​​of each target table entry, ensuring that the corresponding configuration reconfiguration target value can be quickly obtained when the triggering condition is met.

[0050] The reconfiguration trigger node sequence 102 is used to configure one or more reconfiguration trigger nodes for each target entry. The number of configurable trigger nodes for each target entry corresponds one-to-one with the number of reconfiguration target values ​​stored in the reconfiguration data queue 101. Reconfiguration trigger nodes are represented by counter values; when the counter value of the corresponding target entry reaches a certain trigger node, the reconfiguration operation at that node is triggered. By configuring multiple sequentially arranged trigger nodes, multiple dynamic reconfigurations can be achieved during a single simulation of the same target entry.

[0051] The counter alignment module 103 is used to count the number of times each target entry is enabled for read. The counter alignment module 103 maintains two sets of counters independently for each target entry. The first set of counters counts the number of times the target entry is enabled for read in the device under test (DUT), denoted as CNT_DUT[i]; the second set of counters counts the number of times the target entry is enabled for read in the reference model, denoted as CNT_MDL[i]. The two sets of counters accumulate independently, each reflecting the processing progress of the target entry in its corresponding processing module. The counter alignment module 103 monitors in real time whether the count value of each counter reaches the trigger node configured for the entry in the reconfiguration trigger node sequence 102, and when a trigger node is detected, sends a corresponding reconfiguration request to the priority arbitration module 104.

[0052] The priority arbitration module 104 is used to arbitrate and sort the reconfiguration requests when multiple target entries arrive at their respective reconfiguration trigger nodes simultaneously or in adjacent timeframes. When the counter alignment module 103 detects that the count values ​​of multiple entries arrive at their respective reconfiguration trigger nodes at the same simulation time or in adjacent simulation timeframes, the priority arbitration module 104 determines the priority based on the priority level pre-configured in the reconfiguration data queue 101 for each request entry. This module sequentially selects the highest priority request from all pending reconfiguration requests in descending order of priority as the arbitration result.

[0053] The force injection module 105 receives the arbitration result from the priority arbitration module 104 and executes the force injection operation on each target table entry sequentially according to the arbitration order. Specifically, the force injection module 105, based on the table entry determined by the arbitration result and its corresponding reconfiguration target value, uses the force statement of the simulation tool to forcibly assign the reconfiguration target value to the read data port of the corresponding target table entry, thereby completing the reconfiguration operation of the table entry. The force injection module 105 follows a sequential execution mechanism when performing the reconfiguration operation, that is, it only performs the force injection operation on one target table entry at a time, and only performs the reconfiguration operation on the next target table entry after the reconfiguration operation of the current table entry is completed.

[0054] Please refer to Figure 2 The diagram shown illustrates a process for reconfiguring chip entries according to an embodiment of the present invention. The chip entry reconfiguration method specifically includes the following steps:

[0055] S201: Configure counters and at least one reconfiguration trigger node for each target entry in the chip;

[0056] It should be noted that, in this invention, a target entry refers to a basic data unit in the chip that stores forwarding decision information. This may include, but is not limited to, routing entries, forwarding entries, access control list entries, and statistical entries. When forwarding data packets, the chip looks up the corresponding entry based on the key fields of the data packet, reads its configuration value, and then decides how to process the data packet. During the actual operation of the network chip, when network topology changes, service requirements are adjusted, or fault recovery occurs, the contents of the aforementioned entries need to be dynamically updated in real time to meet the real-time and reliability requirements of the chip's services. In this invention, the reconfiguration operation of each target entry is independent, and the reconfiguration operations between target entries do not affect each other.

[0057] On the other hand, in this invention, a counter is used to count the number of times the read enable signal for the corresponding target entry is active. The read enable signal is a control signal when the chip accesses an entry; each time a target entry is read, the corresponding read enable signal is activated once. The counter accumulates the number of times the read enable signal is activated to reflect the number of data packets that the target entry has participated in processing.

[0058] Specifically, the counter increments by one each time a valid read enable signal is detected, and the increment of its count value corresponds one-to-one with the progress of the target entry in processing data packets. Since different target entries have different access frequencies and access times in the chip, the counters configured for each target entry operate independently, and their respective count values ​​reflect the processing progress of their corresponding target entry in processing data packets.

[0059] It should also be noted that the reconfiguration trigger node refers to a pre-set count value target used to determine when a target entry should perform a dynamic reconfiguration operation. Each target entry is configured with at least one reconfiguration trigger node, which is represented by a count value. That is, when the counter value reaches the preset value, a reconfiguration operation for the target entry is triggered.

[0060] It is understood that the number of reconfiguration trigger nodes can be flexibly configured according to actual verification needs, and this embodiment of the invention does not impose any restrictions on this. If only one reconfiguration needs to be performed, then one trigger node is sufficient; if multiple reconfigurations need to be performed in the same simulation process, then multiple trigger nodes arranged in sequence can be configured for the same target entry.

[0061] For example, a first trigger node and a second trigger node can be configured for a target entry. When the counter value reaches the first trigger node, the first reconfiguration is performed, and when the counter continues to count to the second trigger node, the second reconfiguration is performed. The count value of each trigger node determines the location of the reconfiguration operation in the simulation process.

[0062] S202: Count the number of read enable operations for the corresponding target table entry based on the counter;

[0063] As described in step S201, the read enable signal is one of the basic control signals when the chip accesses an entry. During chip operation, when configuration information needs to be read from a target entry to process a data packet, the chip can send a read enable signal to the target entry. When this signal is valid, the entry outputs its stored configuration value to the read data port for use by subsequent processing logic. The validity of the read enable signal is determined by its electronic state. For example, when the read enable signal is high, it indicates that the read operation is enabled, and the entry performs a valid read operation. Each valid pull of the read enable signal corresponds to the target entry participating in the processing of a data packet. Therefore, by counting the number of valid read enable signals for the target entry, the number of data packets that the entry has participated in processing can be accurately reflected.

[0064] It should be noted that the counter only counts valid read enable signals. That is, when the read enable signal is at a valid level and the table entry readability condition is met, the read operation is counted. If the read enable signal is invalid or the table entry cannot be read due to reset, busy state, etc., the signal is not included in the count. In this way, the counter's recorded count accurately reflects the number of valid reads actually completed by the target table entry, i.e., the number of data packets actually processed by that entry.

[0065] The counters corresponding to each target entry operate independently and do not interfere with each other. Since different target entries have different access frequencies, access timings, and access modes within the chip, each counter only counts the read enable signal of its specific associated target entry, without counting across entries. The initial value of each counter is set to zero at simulation startup and continues to accumulate throughout the simulation until it ends or is reconfigured. Each counter maintains its own count value, unaffected by read operations from other entries. This independent statistical mechanism ensures that the processing progress of each target entry can be accurately tracked, providing an accurate data basis for independently triggering reconfiguration operations when the respective count value of each entry reaches the preset reconfiguration trigger node in subsequent steps.

[0066] Preferably, the bit width of the counter can be configured according to the maximum number of read enable operations that the target entry may reach during the simulation process, so as to ensure that the counter will not overflow during the entire simulation.

[0067] For example, if a target entry is expected to be read a maximum of one million times during the entire simulation, the counter bit width should be configured to at least twenty bits to accommodate the entire counting range.

[0068] S203: When the counter value reaches the reconfiguration trigger node of the corresponding target entry, the target entry that has reached the reconfiguration trigger node is reconfigured based on the preset reconfiguration target value.

[0069] Reconfiguration refers to the process of modifying the configuration information stored in a target table entry. In network chips, target tables store configuration information that determines how data packets are processed. Examples include the mapping between destination addresses and next-hop ports in routing tables and the mapping between addresses and forwarding ports in forwarding tables. A reconfiguration operation changes the currently stored configuration value in the target table entry to a new value, enabling the chip to make forwarding decisions based on the new configuration when processing data packets. In verification scenarios, dynamic reconfiguration is used to simulate real-world operating conditions such as network topology changes, service requirement adjustments, or fault recovery, to verify the chip's correctness in handling dynamic updates to table entries.

[0070] The preset reconfiguration target value refers to the pre-determined configuration value of the target entry after the reconfiguration operation is completed.

[0071] It is understood that the target value for reconfiguration described in this invention is set according to specific verification requirements. For example, when verifying the route switching function, the next-hop port of a routing table entry can be changed from port A to port B, and the port number of port B is the preset target value for this reconfiguration. The preset target value for reconfiguration is determined and stored in the corresponding data structure before the reconfiguration operation is executed, and is retrieved and used to execute the reconfiguration when the triggering condition is met.

[0072] In one embodiment of the present invention, the reconfiguration operation can be performed using the assignment mechanism provided by the simulation tool to modify the configuration value of the target entry. In chip verification, the `force` statement is a commonly used method for forcibly assigning signal values, enabling the modification of signals, registers, or nets within the design to specified values ​​at any point during the simulation process. This forced assignment operation overrides the original driving values ​​within the design, ensuring that the forced signal exhibits the specified value during the period the force is active.

[0073] In this invention, when the counter reaches the reconfiguration trigger node, a preset reconfiguration target value is forcibly assigned to the read data port of the target entry using a force statement. The read data port is the interface through which the target entry outputs its stored configuration value. Other logic modules within the chip read the configuration information of the entry through this port for subsequent processing. Modifying the output value of the read data port via the force method is equivalent to modifying the configuration content stored in the target entry, thereby realizing the reconfiguration of the target entry. Since the force operation directly acts on the signal level and does not depend on the actual write operation path inside the chip, the reconfiguration can be completed quickly and accurately during simulation, without being limited by the chip's internal timing and interface protocols.

[0074] Preferably, the preset reconfiguration target values ​​can be pre-stored in the corresponding reconfiguration data queue. The reconfiguration data queue is maintained independently for each target entry, storing one or more reconfiguration target values ​​according to a preset reconfiguration order. When a target entry is configured with multiple reconfiguration trigger nodes, the number of reconfiguration target values ​​stored in the queue is the same as the number of reconfiguration trigger nodes, and they correspond one-to-one with each trigger node according to the order in which the reconfiguration is triggered. When a reconfiguration trigger node is triggered, the corresponding reconfiguration target value is retrieved from the queue for the reconfiguration operation.

[0075] It should be noted that in real-world chip verification scenarios, multiple entries within the same processing module often require dynamic reconfiguration simultaneously. For example, when verifying the routing switching function of a network chip, multiple entries in the routing table, forwarding table, and access control list may need to be updated at the same time. When the counter values ​​of multiple target entries reach their respective reconfiguration trigger nodes at the same simulation time or adjacent simulation times, multiple reconfiguration requests will be generated simultaneously or within a very short time interval. In this case, it is necessary to determine the reconfiguration execution order of each entry.

[0076] Based on this, in one embodiment of the present invention, a corresponding priority can be configured for each target entry. The priority is used to determine the order in which each entry receives the reconfiguration service when multiple reconfiguration requests occur concurrently. Specifically, the priority configuration can be represented numerically; for example, priority level 0 represents the highest priority, and a larger value indicates a lower priority. Priority allocation can be set according to the importance of each entry in the verification scenario, the urgency of the reconfiguration operation, or the dependencies between entries; this embodiment of the present invention does not impose any limitations on this.

[0077] When at least two target entries arrive at their respective reconfiguration trigger nodes at the same simulation time or adjacent simulation time, the preset priority of each target entry is first determined. Adjacent time refers to the time interval between the arrival times of the target entries' counts arriving at their corresponding reconfiguration trigger nodes sequentially on the simulation timeline, typically within a few simulation clock cycles or the order within the same simulation time step. In such concurrent scenarios, multiple reconfiguration requests are generated almost simultaneously, requiring the service order to be determined based on the preset priority of the target entries. Thus, when multiple target entries arrive at the reconfiguration trigger node simultaneously or adjacently, the reconfiguration operations of each entry can be completed in a definite and predictable order, avoiding the uncertainty of the execution order when multiple entries are concurrently reconfigured, and ensuring the controllability of the verification process and the repeatability of the results.

[0078] In another embodiment of the present invention, during the reconfiguration operation of the currently selected target entry, no reconfiguration operations are performed on other target entries; after the reconfiguration operation of the currently selected target entry is completed, the reconfiguration operation is then performed on the next target entry in the order of priority. This avoids resource contention and signal conflicts that may be caused by the simultaneous execution of multiple reconfiguration operations.

[0079] In the verification environment in which this invention is applied, target entries exist independently in the first processing module corresponding to the device under test (DUT) and the second processing module corresponding to the reference model. The target entries in the DUT are those used during actual chip operation, and modifications to their configuration values ​​directly affect the chip's processing behavior. The target entries in the reference model are those maintained in the reference model to simulate chip functionality, and their configuration values ​​are used to generate the desired processing results.

[0080] In this implementation, the reconfiguration of the target entry in the device under test (DUT) and the reconfiguration of the corresponding target entry in the reference model are triggered independently. That is, the reconfiguration of the target entry in the DUT is triggered by a counter that counts the number of times the DUT side reads are enabled, while the reconfiguration of the target entry in the reference model is triggered by a counter that counts the number of times the reference model side reads are enabled.

[0081] Because the counters of both devices independently count the number of valid read enable operations in their respective processing modules, and their reconfiguration trigger times are determined by the time their respective counter values ​​reach the reconfiguration trigger node, the reconfiguration of the target entry in the device under test (DUT) and the corresponding target entry in the reference model occur at different absolute time points. Specifically, the faster reference model reaches the reconfiguration trigger node first and executes the reconfiguration first, while the slower DUT arrives at the reconfiguration trigger node later and executes the reconfiguration later. Although the absolute times of the reconfiguration differ, the logical location of the reconfiguration is the same, both occurring after processing the same number of data packets.

[0082] It is understood that in the verification environment, the target entries configured in the device under test and the reference model can be compared and checked throughout the simulation without any anomalies.

[0083] Specifically, in an exemplary embodiment, the target entry includes a first target entry configured in a first processing module and a second target entry configured in a second processing module. The second processing module is a reference processing module for the first processing module. The method further includes: comparing the processing result of the first target entry on the same data packet with the processing result of the second target entry on the same data packet, one by one, based on the packet processing order; if the processing results are consistent, the configuration is correct; if the processing results are inconsistent, an error indication message is output. The first target entry and the second target entry establish a correspondence based on a preset index identifier.

[0084] Please refer to Figure 3 As shown, based on the same inventive concept as the aforementioned chip entry reconfiguration method, one embodiment of the present invention provides a chip entry reconfiguration system 300, including: a configuration module 301, a statistics module 302, and a reconfiguration module 303.

[0085] Specifically, the configuration module 301 is used to configure counters and at least one reconfiguration trigger node for each target entry in the chip;

[0086] The statistics module 302 is used to count the number of read enable times of the corresponding target table entry based on the counter;

[0087] The reconfiguration module 303 is used to reconfigure the target entry that has reached the reconfiguration trigger node based on a preset reconfiguration target value when the counter value reaches the reconfiguration trigger node of the corresponding target entry.

[0088] Please refer to Figure 4 As shown, embodiments of the present invention also provide an electronic device 400, which includes at least one processor 401, a memory 402 (e.g., non-volatile memory), a main memory 403, and a communication interface 404, wherein the at least one processor 401, the memory 402, the main memory 403, and the communication interface 404 are connected together via an internal bus 405. The at least one processor 401 is configured to invoke at least one program instruction stored or encoded in the memory 402 to cause the at least one processor 401 to perform various operations and functions of the chip entry reconfiguration method described in the various embodiments of this specification.

[0089] In the embodiments of this specification, electronic device 400 may include, but is not limited to: personal computer, server computer, workstation, desktop computer, laptop computer, notebook computer, mobile electronic device, smartphone, tablet computer, cellular phone, personal digital assistant (PDA), handheld device, messaging device, wearable electronic device, consumer electronic device, etc.

[0090] This invention also provides a computer-readable medium carrying computer-executable instructions. When executed by a processor, these instructions can be used to implement various operations and functions of the chip entry reconfiguration method described in the various embodiments of this specification.

[0091] The computer-readable medium in this invention can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this invention, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0092] In this invention, the computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. This propagated data signal may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. The computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wireless, wireline, optical fiber, RF, etc., or any suitable combination thereof.

[0093] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0094] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus, systems, and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, as well as combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0095] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments of the invention, as well as various different choices and variations. The scope of the invention is intended to be defined by the claims and their equivalents.

[0096] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0097] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A method for reconfiguring chip entries, characterized in that, include: Configure counters and at least one reconfiguration trigger node for each target entry in the chip; The counter counts the number of read enable operations for the corresponding target table entry. When the counter value reaches the reconfiguration trigger node of the corresponding target entry, the target entry that has reached the reconfiguration trigger node is reconfigured based on the preset reconfiguration target value.

2. The chip entry modification method according to claim 1, characterized in that, The target entry includes a first target entry configured in the first processing module and a second target entry configured in the second processing module, wherein the second processing module is a reference processing module for the first processing module, and the method further includes: Based on the message processing order, the processing result of the first target entry on the data packet is compared with the processing result of the second target entry on the same data packet one by one; If the processing results are consistent, then the reconfiguration is correct; If the processing results are inconsistent, an error indication message will be output.

3. The chip entry modification method according to claim 2, characterized in that, The first target entry and the second target entry establish a correspondence based on a preset index identifier.

4. The chip entry modification method according to claim 1, characterized in that, The method further includes: A corresponding reconfiguration data queue is established for each of the target entries. The reconfiguration data queue is used to store at least one of the reconfiguration target values ​​in a preset reconfiguration order. The number of reconfiguration trigger nodes is the same as the number of reconfiguration target values ​​stored in the queue. When performing a configuration change operation, the configuration change target value is assigned to the read data port of the target table entry.

5. The chip entry modification method according to claim 4, characterized in that, The method further includes: After each target entry completes the reconfiguration operation, the counter continues to count. When the counter reaches the next reconfiguration trigger node, the reconfiguration operation is performed on the target entry again based on the next preset reconfiguration target value in the reconfiguration data queue.

6. The chip entry reconfiguration method according to claim 1, characterized in that, The method further includes: When at least two target entries arrive at the corresponding reconfiguration trigger node simultaneously or in adjacent moments, the preset priority of each target entry is determined. Based on the preset priority, the reconfiguration order of each target entry is determined; According to the reconfiguration order, the reconfiguration operation is performed on each of the target entries in sequence.

7. The chip entry reconfiguration method according to claim 1, characterized in that, The method further includes: During the reconfiguration operation of the currently selected target table entry, no reconfiguration operation will be performed on other target table entries; After the reconfiguration operation of the currently selected target entry is completed, the reconfiguration operation will be performed on the next target entry in the order of priority.

8. A chip entry reconfiguration system, characterized in that, include: The configuration module is used to configure counters and at least one reconfiguration trigger node for each target entry in the chip; The statistics module is used to count the number of read enable operations for the corresponding target table entry based on the counter. The reconfiguration module is used to reconfigure the target entry that has reached the reconfiguration trigger node based on a preset reconfiguration target value when the counter value reaches the reconfiguration trigger node of the corresponding target entry.

9. An electronic device, characterized in that, include: At least one processor; as well as A memory that stores instructions, which, when executed by the at least one processor, cause the at least one processor to perform the chip entry reconfiguration method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a computer to perform the chip entry reconfiguration method according to any one of claims 1-7.

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