Display panel and driving method thereof

Abstract

The application provides a display panel and a driving method thereof. The display panel comprises a plurality of sub-pixels, scan lines, data lines and a gate driving module; further comprising: a voltage adjustment module, configured to adjust a first gate start voltage of a kth scan signal and / or a second gate start voltage of a (k+1)th scan signal, and output a corresponding voltage control signal; a power management module, electrically connected with the voltage adjustment module and the gate driving module, configured to provide corresponding first and second gate start voltages to the gate driving module according to the voltage control signal; the first gate start voltage is less than the second gate start voltage. Each row of sub-pixels is divided into a plurality of pixel groups, each pixel group comprising 2n adjacent sub-pixels; the 1st to nth sub-pixels are connected with the kth scan line, and the (n+1)th to 2nth sub-pixels are connected with the (k+1)th scan line; the ath sub-pixel and the (a+n)th sub-pixel are connected with the same corresponding data line. The display panel can improve the phenomenon of vertical bright and dark lines.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and its driving method. Background Technology

[0002] With the development and advancement of display technology, Half-Source Driver (HSD) technology is a commonly used low-cost production solution in the field of display technology. This solution doubles the number of scan lines, allowing a single data line to correspond to two columns of sub-pixels, thereby saving half of the source driver integrated chips.

[0003] In the H-type architecture, a loop group consists of 2n subpixels horizontally. Odd-numbered scan lines control the opening and closing of the first n subpixels, while even-numbered scan lines control the opening and closing of the last n subpixels. Horizontally, data line D1 inputs data signals to the 1st and (n+1)th subpixels, data line D2 inputs data signals to the 2nd and (n+2)th subpixels, and so on.

[0004] However, due to the capacitive coupling effect, vertical bright and dark lines may appear on the display panel, affecting the display effect. Summary of the Invention

[0005] This application provides a display panel and its driving method, aiming to solve the problem of vertical bright and dark lines in the H-type structure display panel in the prior art.

[0006] To address the aforementioned technical problems, the first technical solution provided in this application is: to provide a display panel. This display panel includes multiple sub-pixels, multiple scan lines, multiple data lines, and a gate driving module; Each row of subpixels is divided into multiple pixel groups, and each pixel group includes 2n adjacent subpixels, where n is a positive integer. The 1st to nth subpixels are connected to the kth scan line, and the (n+1)th to 2nth subpixels are connected to the (k+1)th scan line, where k is a positive integer. The ath subpixel and the (a+n)th subpixel are connected to the same corresponding data line, where a is a positive integer and a≤n. The display panel also includes: The voltage adjustment module is used to adjust the first gate start voltage of the k-th scan signal and / or the second gate start voltage of the (k+1)-th scan signal, and output the corresponding voltage control signal. The power management module is electrically connected to the voltage regulation module and the gate drive module, and is used to provide the gate drive module with a corresponding first gate start-up voltage and a second gate start-up voltage according to the voltage control signal; wherein the first gate start-up voltage is less than the second gate start-up voltage.

[0007] In some embodiments, the display panel further includes: The voltage acquisition unit includes a first acquisition line and a second acquisition line; the first acquisition line is electrically connected to at least one of the 1st to nth sub-pixels and is used to acquire the first pixel voltage of the 1st to nth sub-pixels; the second acquisition line is electrically connected to at least one of the (n+1)th to 2nth sub-pixels and is used to acquire the second pixel voltage of the (n+1)th to 2nth sub-pixels. The voltage adjustment module is electrically connected to the voltage acquisition unit and is used to adjust the first gate start voltage and / or the second gate start voltage according to the voltage difference between the first pixel voltage and the second pixel voltage.

[0008] In some embodiments, the voltage acquisition unit further includes a first switching transistor and a second switching transistor, the first switching transistor being connected in series in the first acquisition line and the second switching transistor being connected in series in the second acquisition line, and the gates of the first switching transistor and the second switching transistor being respectively connected to the acquisition control signal.

[0009] In some embodiments, the first acquisition line corresponds one-to-one with at least two of the 1st to nth sub-pixels and is electrically connected, and the second acquisition line corresponds one-to-one with at least two of the (n+1)th to 2nth sub-pixels and is electrically connected; the voltage adjustment module is used to calculate a first average value of the first pixel voltage of at least two of the 1st to nth sub-pixels, calculate a second average value of the second pixel voltage of at least two of the (n+1)th to 2nth sub-pixels, and adjust the first gate start-up voltage and / or the second gate start-up voltage according to the voltage difference between the first average value and the second average value; or, The first acquisition line is electrically connected to one of the 1st to nth sub-pixels, and the second acquisition line is electrically connected to one of the (n+1)th to 2nth sub-pixels; the voltage adjustment module is used to adjust the first gate start voltage and / or the second gate start voltage according to the voltage difference between the first pixel voltage acquired by the first acquisition line and the second pixel voltage acquired by the second acquisition line.

[0010] In some embodiments, the voltage adjustment module is used to perform the following steps: Step 1: Set the voltage adjustment range, which includes a left endpoint value and a right endpoint value; use the initial gate turn-off voltage as the initial value of the left endpoint value and the initial gate start-up voltage as the initial value of the right endpoint value of the voltage adjustment range. Step 2: Calculate the average of the left and right endpoint values; Step 3: Use the average value as the target gate start-up voltage and output the corresponding voltage control signal; Step 4: Determine whether the target gate start-up voltage meets the conditions for stopping adjustment; Step 5: In response to the condition for stopping regulation being met, stop regulating the first gate startup voltage and / or the second gate startup voltage; Step 6: In response to the failure to meet the conditions for stopping adjustment, redetermine the left or right endpoint value, and continue to adjust the first gate start voltage and / or the second gate start voltage based on the new voltage adjustment range.

[0011] In some embodiments, the conditions for stopping the adjustment include the number of iterations being greater than or equal to a preset number of iterations; Step three is followed by: incrementing the iteration count by one and updating it to the new iteration count; Step four includes: determining whether the new iteration number is greater than or equal to the preset iteration number.

[0012] In some embodiments, the condition for stopping adjustment includes the absolute value of the voltage difference between the first pixel voltage and the second pixel voltage being less than or equal to a threshold. Step 3 is followed by: obtaining the first pixel voltage and the second pixel voltage under the target gate start voltage; Step four includes: determining whether the absolute value of the voltage difference between the first pixel voltage and the second pixel voltage is less than or equal to a threshold.

[0013] In some embodiments, between step four and step six, the method further includes: in response to the failure to meet the stop adjustment condition, acquiring the first pixel voltage and the second pixel voltage under the target gate start voltage; Step six includes: Calculate the voltage difference between the first pixel voltage and the second pixel voltage; Determine if the pressure difference is less than zero; In response to a pressure difference greater than zero, the left endpoint value is kept unchanged, and the average value is updated to the new right endpoint value; In response to a pressure difference of less than zero, the average value is updated to the new left endpoint value, while the right endpoint value remains unchanged; Based on the new right endpoint value or the new left endpoint value, execute steps two through six.

[0014] To address the aforementioned technical problems, the second technical solution provided in this application is: a driving method for a display panel. The display panel includes multiple sub-pixels, multiple scan lines, multiple data lines, and a gate driving module; each row of sub-pixels is divided into multiple pixel groups, and each pixel group includes 2n adjacent sub-pixels, where n is a positive integer; the 1st to nth sub-pixels are connected to the kth scan line, and the (n+1)th to 2nth sub-pixels are connected to the (k+1)th scan line, where k is a positive integer; the ath sub-pixel and the (a+n)th sub-pixel are connected to the same corresponding data line, where a is a positive integer and a≤n; the driving method includes: Step 1: Set the voltage adjustment range, which includes a left endpoint value and a right endpoint value; use the initial gate turn-off voltage as the initial value of the left endpoint value and the initial gate start-up voltage as the initial value of the right endpoint value. Step 2: Calculate the average of the left and right endpoint values; Step 3: Use the average value as the target gate start-up voltage and output the corresponding voltage control signal; Step 4: Determine whether the target gate start-up voltage meets the conditions for stopping adjustment; Step 5: In response to the condition for stopping regulation being met, stop regulating the first gate startup voltage and / or the second gate startup voltage; Step 6: In response to the failure to meet the conditions for stopping adjustment, redetermine the left or right endpoint value, and continue to adjust the first gate start voltage and / or the second gate start voltage based on the new voltage adjustment range.

[0015] In some implementations, the conditions for stopping the adjustment include: The number of iterations is greater than or equal to the preset number of iterations; or, The absolute value of the voltage difference between the first pixel voltage and the second pixel voltage is less than or equal to the threshold; or, The absolute value of the brightness difference between the 1st to nth sub-pixels and the (n+1)th to 2nth sub-pixels is less than or equal to the preset difference; The interval between step four and step six also includes: In response to the failure to meet the stop adjustment condition, the first pixel voltage and the second pixel voltage at the target gate start voltage are acquired; or, In response to the failure to meet the stop adjustment condition, the first brightness of the 1st to nth sub-pixels and the second brightness of the (n+1)th to 2nth sub-pixels under the target gate start voltage are obtained; Step six includes: Calculate the voltage difference between the first pixel voltage and the second pixel voltage; or, calculate the brightness difference between the first brightness and the second brightness. Determine if the pressure difference or brightness difference is less than zero; In response to a pressure difference or brightness difference greater than zero, the left endpoint value is kept unchanged, and the average value is updated to the new right endpoint value; In response to a pressure difference or brightness difference being less than zero, the average value is updated to the new left endpoint value, while the right endpoint value remains unchanged; Based on the new right endpoint value or the new left endpoint value, execute steps two through six.

[0016] The beneficial effects of this application are as follows: Unlike the prior art, this application provides a display panel and its driving method. The display panel includes multiple sub-pixels, multiple scan lines, multiple data lines, and a gate driving module. Each row of sub-pixels is divided into multiple pixel groups, and each pixel group includes 2n adjacent sub-pixels. The 1st to nth sub-pixels are connected to the kth scan line, and the (n+1)th to 2nth sub-pixels are connected to the (k+1)th scan line. In each pixel group, the ath sub-pixel and the (a+n)th sub-pixel are connected to the same corresponding data line, where a≤n. Furthermore, the display panel also includes an electrically connected voltage adjustment module and a power management module. The voltage adjustment module adjusts the first gate start voltage VGH1 of the k-th scan signal and / or the second gate start voltage VGH2 of the (k+1)-th scan signal, and transmits the corresponding voltage control signal to the power management module. The power management module then transmits the adjusted first gate start voltage VGH1 and / or second gate start voltage VGH2 to the gate drive module according to the voltage control signal. This adjusts the on-state of the drive transistors in the 1st to nth sub-pixels and / or the (n+1)th to 2nth sub-pixels, thereby controlling the brightness of the 1st to nth sub-pixels and / or the (n+1)th to 2nth sub-pixels. This reduces the brightness difference between the 1st to nth sub-pixels and the (n+1)th to 2nth sub-pixels in each pixel group, effectively improving the problem of vertical bright and dark lines that appear on the display panel during display and enhancing the display effect. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of related technology; Figure 2 This is a brightness acquisition diagram of a display panel provided in an embodiment of related technology; Figure 3 This is a schematic diagram of the pressure difference performance of the first n sub-pixels provided in an embodiment of this application; Figure 4 This is a pressure difference-brightness curve of a display panel provided in an embodiment of this application; Figure 5 This is a schematic diagram of the structure of the display panel provided in the first embodiment of this application; Figure 6 This is a schematic diagram of the structure of the display panel provided in the second embodiment of this application; Figure 7This is a schematic diagram of the structure of the display panel provided in the third embodiment of this application; Figure 8 This is a schematic diagram of the structure of the display panel provided in the fourth embodiment of this application; Figure 9 This is a schematic diagram of the structure of the display panel provided in the fifth embodiment of this application; Figure 10 This is a flowchart illustrating a method for driving a display panel according to an embodiment of this application.

[0019] Figure label: 100 / 200 - Display panel; 201 - Display area; 202 - Non-display area; 102 / 102k / 102(k+1) / 22 / 22k / 22(k+1) - Scan lines; 103 / 103j / 103(j+1) / 103(j+6) / 23 / 23m / 23(m+1) / 23(m+2) - Data lines; 20 - Array substrate; 104 / 21 - Pixel group; 101 / 211 - Sub-pixel; 24 - Gate driving module; 30 - Voltage adjustment module; 40 - Power management module; 251 - First acquisition line; 252 - Second acquisition line; 253 - First photosensitive device; 254 - Second photosensitive device; Q1 - First switching transistor; Q2 - Second switching transistor; Q3 - Third switching transistor; Q4 - Fourth switching transistor; VGH - Gate startup voltage; VGH1 - First gate startup voltage; VGH2 - Second gate startup voltage; VGL - Gate shutdown voltage; Vs1 / Vs2 - Pixel voltage; Is1 - First current; Is2 - Second current; Vcom - Common voltage. Detailed Implementation

[0020] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0021] In the following description, specific details such as particular system architectures, interfaces, and technologies are presented for illustrative purposes rather than for limiting purposes, in order to provide a thorough understanding of this application.

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0023] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0024] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0025] Please see Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of related technology. Figure 2This is a brightness acquisition diagram of a display panel provided in an embodiment of the related technology. In the related technology, the display panel 100 includes a plurality of sub-pixels 101 arranged in an array, a plurality of scan lines 102 extending along the row direction, and a plurality of data lines 103 extending along the column direction. Each row of sub-pixels 101 is divided into a plurality of pixel groups 104, and each pixel group 104 includes twelve adjacent sub-pixels 101. The first to sixth sub-pixels 101 are electrically connected to the k-th row scan line 102k, and the seventh to twelfth sub-pixels 101 are electrically connected to the (k+1)-th row scan line 102(k+1). Along the column direction, sub-pixels 101 with the same index in each pixel group 104 form a column of sub-pixels 101. The first column of sub-pixels 101 and the seventh column of sub-pixels 101 are electrically connected to the j-th data line 103j, the second column of sub-pixels 101 and the eighth column of sub-pixels 101 are electrically connected to the (j+1)-th data line 103(j+1), and so on. The sixth column of sub-pixels 101 and the twelfth column of sub-pixels 101 are electrically connected to the (j+6)-th data line 103(j+6). Here, k and j are both positive integers.

[0026] During the display process, in each pixel group 104, after the scan signal on the k-th scan line 102k changes from the gate-on voltage VGH to the gate-off voltage VGL, the 1st to 6th sub-pixels 101 are turned off; the scan signal on the (k+1)-th scan line 102(k+1) changes from the gate-off voltage VGL to the gate-on voltage VGH, and the 7th to 12th sub-pixels 101 are turned on for charging. Due to the capacitive coupling effect, the impact of voltage changes on the k-th scan line 102k is reduced. Simultaneously, in the next frame, the pixel voltage is also affected and decreases, but due to polarity reversal, the voltage difference between the pixel voltage Vs2 and the common voltage Vcom increases. Furthermore, due to the different sensitivities of the human eye to brightness, the final phenomenon is as follows: Figure 2 As shown.

[0027] Please see Figure 3 and Figure 4 , Figure 3 This is a schematic diagram of the pressure difference performance of the first n sub-pixels according to an embodiment of this application. Figure 4This is a voltage difference-brightness curve of a display panel provided in an embodiment of this application. Specifically, in the H-type architecture described above, the first to sixth sub-pixels 101 in each pixel group 104 form bright lines along the column direction of sub-pixels 101. Due to the feed-through effect, when the scanning signal changes from the gate start voltage VGH to the gate turn-off voltage VGL, the corresponding pixel voltage also decreases due to the presence of parasitic capacitance. In the current frame, the brightness is low because the voltage difference between the pixel voltage Vs1 and the common voltage Vcom is insufficient. In the next frame, the pixel voltage will also be affected and decrease, but due to the polarity reversal, the absolute value of the voltage difference between the pixel voltage Vs2 and the common voltage Vcom increases, resulting in a higher brightness.

[0028] Specifically, such as Figure 4 As shown, since the changes in pressure difference and brightness are not linear, within a certain range, the absolute values ​​of brightness and pressure difference increase exponentially, making the brightness difference between the next frame and the target brightness greater than the brightness difference between the current frame and the target brightness. Therefore, along the column direction of sub-pixels 101, the 1st to 6th sub-pixels 101 in each pixel group 104 will produce brighter vertical lines after the brightness of the two frames is neutralized, while the 7th to 12th sub-pixels 101, due to the smaller degree of influence, will appear as dark lines relative to the 1st to 6th sub-pixels 101.

[0029] This application provides a display panel 200 (see...) Figure 5 The method and its driving mechanism are used to solve the above-mentioned technical problems. For specific technical solutions, please refer to the following detailed explanation.

[0030] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0031] Please see Figure 5 , Figure 5 This is a schematic diagram of the structure of a display panel provided in the first embodiment of this application. In this embodiment, a display panel 200 is provided, which includes a plurality of sub-pixels 211, a plurality of scan lines 22, a plurality of data lines 23, and a gate driving module 24. Each row of sub-pixels 211 is divided into a plurality of pixel groups 21, and each pixel group 21 includes 2n adjacent sub-pixels 211, where n is a positive integer. The 1st to nth sub-pixels 211 are connected to the kth row of scan lines 22, and the (n+1)th to 2nth sub-pixels 211 are connected to the (k+1)th row of scan lines 22, where k is a positive integer. The ath sub-pixel 211 and the (a+n)th sub-pixel 211 are connected to the same corresponding data line 23, where a is a positive integer and a≤n.

[0032] Furthermore, the display panel 200 also includes: The voltage adjustment module 30 is used to adjust the first gate start voltage VGH1 of the k-th scan signal and / or the second gate start voltage VGH2 of the (k+1)-th scan signal, and output the corresponding voltage control signal. The power management module 40 is electrically connected to the voltage regulation module 30 and the gate drive module, and is used to provide the gate drive module 24 with a corresponding first gate start-up voltage VGH1 and a second gate start-up voltage VGH2 according to the voltage control signal; wherein the first gate start-up voltage VGH1 is less than the second gate start-up voltage VGH2.

[0033] In each pixel group 21, the number of sub-pixels 211 is even, specifically 2n. For the same row of sub-pixels 211, in each pixel group 21, the first n sub-pixels 211 are electrically connected to the k-th row scan line 22k, and the last n sub-pixels 211 are electrically connected to the (k+1)-th row scan line 22(k+1), that is, the first n sub-pixels 211 and the last n sub-pixels 211 are electrically connected to the two adjacent rows of scan lines 22k and 22(k+1), respectively. Specifically, the pixel groups 21 can be numbered, and the label of the pixel group 21 can be denoted as (b, c), where b represents the row number of the pixel group 21 and c represents the column number of the pixel group 21. The multiple sub-pixels 211 are arranged in an array. Along the column direction, sub-pixels 211 in the same column are electrically connected to the same data line 23; furthermore, in pixel groups 21 with the same column number, sub-pixels 211 in the first column and sub-pixels 211 in the (n+1)th column are electrically connected to the mth data line 23m, sub-pixels 211 in the second column and sub-pixels 211 in the (n+2)th column are electrically connected to the (m+1)th data line 23(m+1), and so on, with sub-pixels 211 in the nth column and sub-pixels 211 in the 2nth column being electrically connected to the (m+n)th data line 23(m+n); where m is a positive integer.

[0034] During display driving, when the k-th scan signal is the gate-on voltage VGH, the first n sub-pixels 211 in each pixel group 21 of the corresponding row are turned on, and the corresponding n data lines 23 transmit data signals to the first n sub-pixels 211 of each pixel group 21. After the k-th scan signal changes from the gate-on voltage VGH to the gate-off voltage VGL, the (k+1)-th scan signal changes from the gate-off voltage VGL to the gate-on voltage VGH, and the last n sub-pixels 211 in each pixel group 21 of the corresponding row, i.e., the (n+1) to 2n sub-pixels 211, are turned on, and the corresponding n data lines 23 transmit data signals to the last n sub-pixels 211 of each pixel group 21. By using the time-division multiplexing of the data lines 23, the display panel 200 can be displayed. At the same time, this driving method reduces the number of source driver integrated chips by half, thus reducing production costs.

[0035] Furthermore, in this embodiment, the voltage adjustment module 30 adjusts the first gate start voltage VGH1 of the k-th scan signal and / or the second gate start voltage VGH2 of the (k+1)-th scan signal, and transmits the corresponding voltage control signal to the power management module 40. The power management module 40 then transmits the adjusted first gate start voltage VGH1 and / or second gate start voltage VGH2 to the gate drive module 24 according to the voltage control signal, thereby adjusting the on-state of the driving transistors in the 1st to nth sub-pixels 211 and / or the (n+1)th to 2nth sub-pixels 211, thereby controlling the brightness of the 1st to nth sub-pixels 211 and / or the (n+1)th to 2nth sub-pixels 211, reducing the brightness difference between the 1st to nth sub-pixels 211 and the (n+1)th to 2nth sub-pixels 211 in each pixel group 21, effectively improving the problem of vertical bright and dark lines appearing on the display panel 200 during display, and enhancing the display effect.

[0036] Specifically, in one embodiment, the adjustment parameters of the voltage adjustment module 30 can be debugged through experimental testing during the testing phase of the display panel 200. After debugging, the debugged parameters can be burned into the voltage adjustment module 30, so that when the display panel 200 is performing display work, the voltage adjustment module 30 provides the corresponding voltage control signal to the power management module 40 according to the preset parameters, so that the power management module 40 provides the corresponding first gate start voltage VGH1 and second gate start voltage VGH2 to the gate drive module 24 according to the voltage control signal, thereby controlling the opening degree of the first n sub-pixels 211 and the last n sub-pixels 211 in each pixel group 21, so as to reduce the brightness difference between the first n sub-pixels 211 and the last n sub-pixels 211 in each pixel group 21, effectively improving the problem of vertical bright and dark lines that appear in the display panel 200 during display, and improving the display effect.

[0037] In a specific embodiment, a binary search iterative logic can be used. Specifically, an initial voltage adjustment range is first set, and the corresponding number of iterations is set. After the iteration is completed, the brightness difference between the first n columns of sub-pixels 211 and the last n columns of sub-pixels 211 in each pixel group 21 can be detected to determine whether the display requirements are met. A threshold can be set according to the display requirements. If the absolute value of the brightness difference is less than or equal to the threshold, no further iteration is needed. The first gate start voltage VGH1 or the second gate start voltage VGH2 after the last iteration can be used as the final target gate start voltage, and the corresponding voltage control signal is sent to the power management module 40. The power management module 40 then sends the adjusted first gate start voltage VGH1 or the second gate start voltage VGH2 to the gate driving module 24 according to the voltage control signal. This makes the first gate start voltage VGH1 of the k-th scan signal or the second gate start voltage VGH2 of the (k+1)-th scan signal generated by the gate driving module 24 the adjusted target gate start voltage, thereby improving the problem of vertical bright and dark lines during display. If the absolute value of the brightness difference is greater than the threshold, the number of iterations can be increased until the absolute value of the brightness difference is less than or equal to the threshold, at which point the iteration stops.

[0038] Specifically, the display panel 200 also includes an array substrate 20, on which the aforementioned sub-pixels 211, scan lines 22, data lines 23, and gate driving module 24 are all disposed. Specifically, the voltage adjustment module 30 may adjust only the first gate activation voltage VGH1; or, it may adjust only the second gate activation voltage VGH2; or, it may adjust both the first gate activation voltage VGH1 and the second gate activation voltage VGH2 simultaneously. The specific adjustment scheme for the gate activation voltage VGH can be selected according to the actual brightness adjustment requirements, and no specific limitation is made thereto. For example, the following embodiments of this application use the adjustment of the first gate activation voltage VGH1 as an example.

[0039] Please see Figure 6 , Figure 6 This is a schematic diagram of the structure of a display panel provided in the second embodiment of this application. In this embodiment, the display panel 200 further includes a voltage acquisition unit, which includes a first acquisition line 251 and a second acquisition line 252. The first acquisition line 251 is electrically connected to at least one of the 1st to nth sub-pixels 211 and is used to acquire the first pixel voltage of the 1st to nth sub-pixels 211. The second acquisition line 252 is electrically connected to at least one of the (n+1)th to 2nth sub-pixels 211 and is used to acquire the second pixel voltage of the (n+1)th to 2nth sub-pixels 211. The voltage adjustment module 30 is electrically connected to the voltage acquisition unit and is used to adjust the first gate start-up voltage VGH1 and / or the second gate start-up voltage VGH2 according to the voltage difference between the first pixel voltage and the second pixel voltage.

[0040] The number of the first acquisition line 251 and the second acquisition line 252 can be one or more, respectively.

[0041] When the number of first acquisition lines 251 and second acquisition lines 252 is both one, the first acquisition line 251 can be electrically connected to one column of sub-pixels 211 in the first n columns of sub-pixels 211 in the most representative column of pixel group 21, for acquiring the first pixel voltage; similarly, the second acquisition line 252 can be electrically connected to one column of sub-pixels 211 in the last n columns of sub-pixels 211 in the most representative column of pixel group 21, for acquiring the second pixel voltage.

[0042] When there are multiple first acquisition lines 251 and multiple second acquisition lines 252, the first acquisition lines 251 and multiple second acquisition lines 252 can be evenly distributed in multiple columns of pixel groups 21. The first acquisition line 251 is electrically connected to at least one column of sub-pixels 211 in the first n columns of sub-pixels 211 in each column of pixel group 21, and the second acquisition line 252 is electrically connected to at least one column of sub-pixels 211 in the last n columns of sub-pixels 211 in each column of pixel group 21, so as to acquire multiple first pixel voltages and multiple second pixel voltages respectively.

[0043] Specifically, the first brightness acquisition can be replaced by acquiring the first pixel voltage and the second pixel voltage. The voltage adjustment module 30 is electrically connected to the first acquisition line 251 and the second acquisition line 252. When adjusting the gate start voltage VGH, the voltage adjustment module 30 controls the voltage acquisition unit to acquire the first pixel voltage and the second pixel voltage through the first acquisition line 251 and the second acquisition line 252. By replacing the brightness difference with the voltage difference between the first pixel voltage and the second pixel voltage, the first gate start voltage VGH1 and / or the second gate start voltage VGH2 are adjusted according to the voltage difference between the first pixel voltage and the second pixel voltage, so as to reduce the brightness difference between the first n sub-pixels 211 and the last n sub-pixels 211 in each pixel group 21, effectively improving the problem of vertical bright and dark lines that appear in the display panel 200 described above, and improving the display effect.

[0044] Meanwhile, by replacing the brightness difference with the voltage difference between the first and second pixels, no additional brightness acquisition equipment is needed. Moreover, by acquiring the voltage of the first and second pixels instead of the brightness acquisition, the adjustment of the first gate start-up voltage VGH1 and / or the second gate start-up voltage VGH2 can be performed at any time, no longer limited to the testing stage of the display panel 200. If the above-mentioned display problems occur during the use of the display panel 200, the first gate start-up voltage VGH1 and / or the second gate start-up voltage VGH2 can also be adjusted in the above manner to improve the display problem of vertical bright and dark lines at any time, and significantly improve the display quality of the display panel.

[0045] Specifically, when there are multiple first acquisition lines 251 and multiple second acquisition lines 252, the voltage acquisition unit can acquire multiple first pixel voltages and multiple second pixel voltages each time. After receiving multiple first pixel voltages and multiple second pixel voltages, the voltage adjustment module 30 can first preprocess the multiple first pixel voltages and multiple second pixel voltages. For example, it can first remove obviously abnormal data from the multiple first pixel voltage data, and then calculate the average value. The average value is used as the first pixel voltage for adjusting the first gate start voltage VGH1 and / or the second gate start voltage VGH2. The second pixel voltage is preprocessed in the same way.

[0046] Please see Figure 7 , Figure 7 This is a schematic diagram of the display panel structure provided in the third embodiment of this application. In this embodiment, the voltage acquisition unit further includes a first switching transistor Q1 and a second switching transistor Q2. The first switching transistor Q1 is connected in series in the first acquisition line 251, and the second switching transistor Q2 is connected in series in the second acquisition line 252. The gates of the first switching transistor Q1 and the second switching transistor Q2 are respectively connected to the acquisition control signal.

[0047] In this embodiment, the gates of the first switching transistor Q1 and the second switching transistor Q2 are connected to a data acquisition control signal to control the acquisition of the first pixel voltage and the second pixel voltage. In a specific embodiment, during the adjustment of the first gate activation voltage VGH1 and / or the second gate activation voltage VGH2, when it is necessary to acquire the first pixel voltage and the second pixel voltage, the first switching transistor Q1 and the second switching transistor Q2 are turned on by the data acquisition control signal, so that the first pixel voltage and the second pixel voltage are transmitted to the voltage adjustment module 30. By controlling the on / off state of the first switching transistor Q1 and the second switching transistor Q2 to control the acquisition of the first pixel voltage and the second pixel voltage, the power consumption of the display panel 200 can be further reduced.

[0048] Specifically, the first switching transistor Q1 and the second switching transistor Q2 can be thin-film transistors (TFTs), such as metal-oxide-semiconductor field-effect transistors (MOSFETs), amorphous silicon TFTs (a-Si TFTs), low-temperature polycrystalline silicon TFTs (LTPS TFTs), indium gallium zinc oxide TFTs (IGZO TFTs), etc., which can be set according to actual needs.

[0049] like Figure 6 and Figure 7 As shown, in some embodiments, the first acquisition line 251 is electrically connected to one of the 1st to nth sub-pixels 211, and the second acquisition line 252 is electrically connected to one of the (n+1)th to 2nth sub-pixels 211; the voltage adjustment module 30 is used to adjust the first gate start voltage VGH1 and / or the second gate start voltage VGH2 according to the voltage difference between the first pixel voltage acquired by the first acquisition line 251 and the second pixel voltage acquired by the second acquisition line 252.

[0050] In this embodiment, each pixel group 21 is provided with a first acquisition line 251 and a second acquisition line 252. The first acquisition line 251 is electrically connected to one of the first n sub-pixels 211, and the second acquisition line 252 is electrically connected to one of the last n sub-pixels 211. The voltage adjustment module 30 acquires the first pixel voltage and the second pixel voltage in each pixel group 21 through the first acquisition line 251 and the second acquisition line 252.

[0051] In one embodiment, the voltage adjustment module 30 can perform a subtraction operation on the first pixel voltage and the second pixel voltage collected in each pixel group 21 to obtain the voltage difference between the two, and perform a weighted average operation on the voltage difference in each pixel group 21 to obtain the final difference between the first pixel voltage and the second pixel voltage, and further adjust the first gate start voltage VGH1 and / or the second gate start voltage VGH2 according to the difference.

[0052] In another embodiment, the voltage adjustment module 30 may first perform a weighted average calculation on multiple first pixel voltages to obtain the average value of the first pixel voltage, and then perform a weighted average calculation on multiple second pixel voltages to obtain the average value of the second pixel voltage; then calculate the difference between the average value of the first pixel voltage and the average value of the second pixel voltage, and further adjust the first gate start voltage VGH1 and / or the second gate start voltage VGH2 according to the difference.

[0053] Please see Figure 8 , Figure 8This is a schematic diagram of the display panel structure provided in the fourth embodiment of this application. In this embodiment, the first acquisition line 251 corresponds one-to-one with at least two of the 1st to nth sub-pixels 211 and is electrically connected, and the second acquisition line 252 corresponds one-to-one with at least two of the (n+1)th to 2nth sub-pixels 211 and is electrically connected; the voltage adjustment module 30 is used to calculate the first average value of the first pixel voltage of at least two of the 1st to nth sub-pixels 211, calculate the second average value of the second pixel voltage of at least two of the (n+1)th to 2nth sub-pixels 211, and adjust the first gate start voltage VGH1 and / or the second gate start voltage VGH2 according to the voltage difference between the first average value and the second average value.

[0054] Specifically, in each pixel group 21, at least two first acquisition lines 251 and at least two second acquisition lines 252 are provided. The at least two first acquisition lines 251 are electrically connected one-to-one with the same number of sub-pixels 211 in the first n sub-pixels 211, and the at least two second acquisition lines 252 are electrically connected one-to-one with the same number of sub-pixels 211 in the last n sub-pixels 211. It should be noted that in the same column of pixel group 21, the same column of sub-pixels 211 are electrically connected to the same first acquisition line 251 or the same second acquisition line 252.

[0055] The voltage adjustment module 30 is used to acquire the first pixel voltage and the second pixel voltage through the first acquisition line 251 and the second acquisition line 252. After the acquisition is completed, the voltage adjustment module 30 is also used to preprocess the multiple first pixel voltages and the multiple second pixel voltages. The preprocessing includes removing abnormal data and calculating the weighted average of the multiple acquired first pixel voltages, and using the weighted average as the first average. The preprocessing also includes removing abnormal data and calculating the weighted average of the multiple acquired second pixel voltages, and using the weighted average as the second average. By setting at least two first acquisition lines 251 and at least two second acquisition lines 252 in each pixel group 21 to acquire multiple first pixel voltages and multiple second pixel voltages, and preprocessing the acquired data, the preprocessed first pixel voltage and second pixel voltage data are more accurate. This makes the reference data used to adjust the first gate start voltage VGH1 and / or the second gate start voltage VGH2 more reliable, and makes the brightness difference between the 1st to nth sub-pixels 211 and the (n+1)th to 2nth sub-pixels 211 in each pixel group 21 smaller. This further improves the problem of vertical bright and dark lines appearing in the display panel 200 during display and enhances the display effect.

[0056] Please see Figure 9 , Figure 9This is a schematic diagram of the structure of a display panel provided in the fifth embodiment of this application. In this embodiment, the array substrate 20 is divided into a display area 201 and a non-display area 202, with the non-display area 202 surrounding the display area 201. Sub-pixels are disposed in the display area 201, and a gate driving module is disposed on one side of the display area 201. Further, the display panel 200 also includes a first photosensitive device 253 and a second photosensitive device 254 disposed on the array substrate 20. The first photosensitive device 253 and the second photosensitive device 254 are located in the non-display area 202 and are disposed adjacent to the display area 201. The first photosensitive device 253 is disposed in the light-emitting area above the 1st to nth sub-pixels in the adjacent pixel group 21, and is used to collect the brightness of the 1st to nth sub-pixels and convert the brightness into a first current Is1. The second photosensitive device 254 is disposed in the light-emitting area above the (n+1) to 2nth sub-pixels in the adjacent pixel group 21, and is used to collect the brightness of the (n+1) to 2nth sub-pixels and convert the brightness into a second current Is2. Specifically, the first photosensitive device 253 and the second photosensitive device 254 can be photoresistors, photodiodes, or other photosensitive devices, as long as they can meet the requirements of the above signal conversion and current signal acquisition. By placing the photosensitive devices in the non-display area, the influence of the photosensitive devices on the image display can be reduced; furthermore, the first photosensitive device 253 and the second photosensitive device 254 are transparent devices, thereby further reducing the influence of the photosensitive devices on the image display.

[0057] Furthermore, the voltage adjustment module 30 is electrically connected to the first photosensitive device 253 and the second photosensitive device 254, and is used to calculate the current difference between the first current Is1 and the second current Is2, and adjust the first gate start voltage VGH1 and / or the second gate start voltage VGH2 according to the current difference. Specifically, in each pixel group 21, when the display brightness difference between the current n sub-pixels 211 and the next n sub-pixels 211 reaches the expected value, the brightness difference between the two types of sub-pixels will affect the current difference of the photosensitive device. Therefore, the current difference between the first current Is1 and the second current Is2 when the expected value is reached can be used as a threshold, and this threshold can be used as a judgment threshold for adjusting whether the first gate start voltage VGH1 and / or the second gate start voltage VGH2 meet the requirements. When the absolute value of the current difference between the first current Is1 and the second current Is2 monitored in real time is less than the threshold, the adjustment is completed.

[0058] It should be noted that when adjusting the first gate start voltage VGH1 and / or the second gate start voltage VGH2, the single variable test principle must be followed. The same data voltage, such as gray level 255 voltage, gray level 123 voltage, etc., must be input to each sub-pixel 211 in the sampling pixel group 21. Then, whether further adjustment is needed is determined by detecting whether the current difference flowing through the first photosensitive device 253 and the second photosensitive device 254 is less than the threshold.

[0059] and Figure 7 and Figure 8 The design for collecting pixel voltages in the embodiments is similar. A representative sub-pixel can be selected for brightness acquisition, or the brightness of multiple sub-pixels can be acquired. Then, the converted current data is preprocessed, and the current difference between the preprocessed first current Is1 and the second current Is2 is calculated. The first gate start-up voltage VGH1 and / or the second gate start-up voltage VGH2 are adjusted according to the current difference.

[0060] Furthermore, a third switching transistor is connected in series in the signal path between the first photosensitive device 253 and the voltage adjustment module 30, and a fourth switching transistor is connected in series in the signal path between the second photosensitive device 254 and the voltage adjustment module 30. The gates of the third and fourth switching transistors are respectively connected to the acquisition control signal, so as to control the acquisition of the first current Is1 and the second current Is2 through the acquisition control signal.

[0061] In a specific embodiment, during the adjustment of the first gate startup voltage VGH1 and / or the second gate startup voltage VGH2, when it is necessary to collect the first current Is1 and the second current Is2, the third switching transistor Q3 and the fourth switching transistor Q4 are turned on by a collection control signal, so that the first current Is1 and the second current Is2 are transmitted to the voltage adjustment module 30. By controlling the conduction state of the third switching transistor Q3 and the fourth switching transistor Q4 to control the collection of the first current Is1 and the second current Is2, the power consumption of the display panel 200 can be further reduced.

[0062] By setting up a photosensitive device, the photoelectric conversion function of the photosensitive device is used to replace the brightness difference, eliminating the need to redesign and modify the wiring layout of the display area 201. Moreover, by using the photosensitive device to collect light and convert brightness information into current information, the adjustment of the first gate start-up voltage VGH1 and / or the second gate start-up voltage VGH2 can be performed at any time, no longer limited to the testing stage of the display panel 200. During the use of the display panel 200, if the above-mentioned display problems occur, the first gate start-up voltage VGH1 and / or the second gate start-up voltage VGH2 can also be adjusted in the above manner to improve the display problem of vertical bright and dark lines at any time, significantly improving the display quality of the display panel.

[0063] Specifically, the methods for adjusting the first gate start-up voltage VGH1 and / or the second gate start-up voltage VGH2 based on the voltage difference between the first average value and the second average value of the pixel voltage, and the methods for adjusting the first gate start-up voltage VGH1 and / or the second gate start-up voltage VGH2 based on the current difference between the first current Is1 and the second current Is2 are described below. For details, please refer to the following description.

[0064] In a specific embodiment, the voltage adjustment module 30 is used to perform the following steps: Step 1: Set the voltage adjustment range, which includes a left endpoint value and a right endpoint value; use the initial gate turn-off voltage VGL as the initial value of the left endpoint value and the initial gate start-up voltage VGH as the initial value of the right endpoint value of the voltage adjustment range. Step 2: Calculate the average of the left and right endpoint values; Step 3: Use the average value as the target gate start-up voltage and output the corresponding voltage control signal; Step 4: Determine whether the target gate start-up voltage meets the conditions for stopping adjustment; Step 5: In response to the condition for stopping regulation being met, stop regulating the first gate startup voltage VGH1 and / or the second gate startup voltage VGH2; Step 6: In response to the failure to meet the conditions for stopping adjustment, redetermine the left or right endpoint value, and continue to adjust the first gate start voltage VGH1 and / or the second gate start voltage VGH2 based on the new voltage adjustment range.

[0065] For example, the adjustment of the first gate activation voltage VGH1 is described. In step one, a voltage adjustment range is first set. As mentioned above, the brightness of the first n sub-pixels 211 in each pixel group 21 is greater than the brightness of the last n sub-pixels 211. Therefore, the first gate activation voltage VGH1 needs to be adjusted downward. In this embodiment, the initial gate shutdown voltage VGL is used as the initial value of the left endpoint, and the initial gate activation voltage VGH is used as the initial value of the right endpoint of the voltage adjustment range. That is, the adjustment range of the first gate activation voltage VGH1 is between the left endpoint value and the right endpoint value, including the endpoint value. Here, the initial gate shutdown voltage VGL is the gate shutdown voltage VGL initially set in the display panel 200, and the initial gate activation voltage VGH is the gate activation voltage VGH initially set in the display panel 200.

[0066] It should be noted that the target gate start-up voltage mentioned here refers to the real-time optimal gate drive voltage when the display panel 200 is displaying. The initial values ​​of the first gate start-up voltage VGH1 and the second gate start-up voltage VGH2 are only used to initially define a large range for finding the optimal gate drive voltage. The optimal gate drive voltage value lies within this defined range, while the final actual target gate start-up voltage depends on the number of iterations and the comparison with front-end detection. Front-end detection includes the detection of pixel voltage or the detection of photosensitive device current as described in the above embodiments.

[0067] In step three, the average value of the left endpoint and the right endpoint is used as the target gate start voltage. The target gate start voltage is provided to the gate drive module 24 through the power management module 40, so that the gate drive module 24 uses the target gate start voltage as the new first gate start voltage VGH1 to drive the first n sub-pixels 211 in each pixel group 21.

[0068] Step four is used to determine whether the condition for stopping the adjustment of the gate startup voltage VGH is met after the new target gate startup voltage is substituted. If the condition for stopping the adjustment is met, the adjustment of the first gate startup voltage VGH1 is stopped. If the condition for stopping the adjustment is not met, the left or right endpoint value is re-determined based on the effect after substituting the target gate startup voltage, the voltage adjustment range is reset, and the first gate startup voltage VGH1 is adjusted according to the above steps based on the newly set voltage adjustment range.

[0069] In one embodiment, the condition for stopping the adjustment includes the number of iterations being greater than or equal to a preset number of iterations; Step three is followed by: incrementing the iteration count by one and updating it to the new iteration count; Step four includes: determining whether the new iteration number is greater than or equal to the preset iteration number.

[0070] The number of iterations can be counted using a counter. For example, a preset iteration count of 5 can be set, indicating that adjustment will stop after 5 iterations; it can also be set to 10 for higher precision adjustment. This method can be implemented using a microcontroller or a dedicated adjustment IC, where the counter automatically increments after each iteration, triggering a stop logic when the preset value is reached. The set value of the iteration count can be adjusted according to actual needs, such as using different preset iteration counts to optimize adjustment efficiency for different display panels 200 with varying response characteristics.

[0071] In this embodiment, by controlling the number of iterations as the stopping condition, the voltage regulation error can decrease exponentially with the increase of the number of iterations, so that the first gate start voltage VGH1 and / or the second gate start voltage VGH2 more accurately approach the optimal value, thereby reducing vertical bright and dark lines, improving the uniformity of display brightness, avoiding visual interference perceived by the eye, and improving display quality.

[0072] In one embodiment, the condition for stopping adjustment includes the absolute value of the voltage difference between the first pixel voltage and the second pixel voltage being less than or equal to a threshold. Step 3 is followed by: obtaining the first pixel voltage and the second pixel voltage under the target gate start voltage; Step four includes: determining whether the absolute value of the voltage difference between the first pixel voltage and the second pixel voltage is less than or equal to a threshold.

[0073] The absolute value of the voltage difference between the first pixel voltage and the second pixel voltage can be used to reflect the brightness difference between bright and dark lines. The adjustment stop condition is based on the absolute value of the voltage difference being less than or equal to a threshold, ensuring the brightness balance between the first n columns of sub-pixels 211 and the last n columns of sub-pixels 211 in each pixel group 21. The first pixel voltage and the second pixel voltage can be obtained by acquiring the first acquisition line 251 and the second acquisition line 252 provided in the above embodiment. The judgment in step four can be executed by a microprocessor, comparing the voltage difference value with the threshold. For example, a microcontroller can be used as the adjustment IC, with a built-in binary search algorithm; a field-programmable gate array (FPGA) can also be used to implement high-speed iterative calculation, dynamically adjusting the VGH value according to the brightness difference; in a specific embodiment, an operational amplifier can be used to construct a voltage comparison circuit, combined with a digital signal processor to realize the real-time calculation of the absolute value of the voltage difference.

[0074] In this embodiment, closed-loop feedback control for brightness balance is achieved by determining whether the absolute value of the voltage difference between the first pixel voltage and the second pixel voltage is less than or equal to a threshold, effectively reducing the problem of vertical bright and dark lines. This adjustment method does not rely on experience-based settings but is dynamically optimized based on real-time monitoring data, which can effectively improve the uniformity of display brightness. At the same time, the binary iterative logic ensures that the adjustment accuracy increases with the number of iterations, thereby reducing adjustment time and improving system reliability while ensuring display effect.

[0075] In one embodiment, between step four and step six, the method further includes: in response to the failure to meet the stop adjustment condition, acquiring the first pixel voltage and the second pixel voltage under the target gate start voltage; Step six includes: Calculate the voltage difference between the first pixel voltage and the second pixel voltage; Determine if the pressure difference is less than zero; In response to a pressure difference greater than zero, the left endpoint value is kept unchanged, and the average value is updated to the new right endpoint value; In response to a pressure difference of less than zero, the average value is updated to the new left endpoint value, while the right endpoint value remains unchanged; Based on the new right endpoint value or the new left endpoint value, execute steps two through six.

[0076] Specifically, in the binary iterative adjustment process, the voltage difference between the first pixel voltage and the second pixel voltage directly reflects the brightness difference between bright and dark lines, and is used to dynamically control the voltage range adjustment. When the voltage difference is greater than zero, it means that the brightness of the first n columns of sub-pixels 211 in the same column pixel group 21 is higher than that of the last n columns of sub-pixels 211. The first gate start voltage VGH1 needs to be reduced to reduce the brightness. Therefore, the left endpoint value is kept unchanged and the average value is updated to the new right endpoint value. When the voltage difference is less than zero, it means that the brightness of the first n columns of sub-pixels 211 in the same column pixel group 21 is lower than that of the last n columns of sub-pixels 211. The first gate start voltage VGH1 needs to be increased to increase the brightness. Therefore, the average value is updated to the new left endpoint value and the right endpoint value is kept unchanged.

[0077] In another embodiment, the condition for stopping the adjustment includes the absolute value of the current difference between the first current Is1 and the second current Is2 being less than or equal to a threshold. Step 3 is followed by: obtaining the first current Is1 and the second current Is2 under the target gate startup voltage; Step four includes: determining whether the absolute value of the current difference between the first current Is1 and the second current Is2 is less than or equal to a threshold.

[0078] Between steps four and six, the method further includes: in response to the failure to meet the stop adjustment condition, acquiring the first current Is1 and the second current Is2 under the target gate start voltage; Step six includes: Calculate the current difference between the first current Is1 and the second current Is2; Determine if the current difference is less than zero; In response to a current difference greater than zero, the left endpoint value is kept unchanged, and the average value is updated to the new right endpoint value; In response to a current difference of less than zero, the average value is updated to the new left endpoint value, while the right endpoint value remains unchanged; Based on the new right endpoint value or the new left endpoint value, execute steps two through six.

[0079] Specifically, in the bisection iterative adjustment process, the absolute value of the current difference between the first current Is1 and the second current Is2 can also be directly used to reflect the brightness difference between bright and dark lines, and can be used for dynamic control of voltage range adjustment. The method for obtaining the first current Is1 and the second current Is2 can be achieved through the technical solution provided in the above embodiment, which uses the first photosensitive device 253 and the second photosensitive device 254 to convert the optical signal into the first current Is1 and the second current Is2, respectively.

[0080] During the adjustment process, when the current difference is greater than zero, it means that the brightness of the first n columns of sub-pixels 211 in the same column pixel group 21 is higher than that of the last n columns of sub-pixels 211. The first gate start voltage VGH1 needs to be reduced to decrease the brightness. Therefore, the left endpoint value is kept unchanged and the average value is updated to the new right endpoint value. When the current difference is less than zero, it means that the brightness of the first n columns of sub-pixels 211 in the same column pixel group 21 is lower than that of the last n columns of sub-pixels 211. The first gate start voltage VGH1 needs to be increased to increase the brightness. Therefore, the average value is updated to the new left endpoint value and the right endpoint value is kept unchanged.

[0081] In this embodiment, closed-loop feedback control for brightness balance is achieved by determining whether the absolute value of the current difference between the first current Is1 and the second current Is2 is less than or equal to a threshold, effectively reducing the problem of vertical bright and dark lines. This adjustment method also does not rely on experience-based settings; it is dynamically optimized based on real-time monitoring data, effectively improving the uniformity of display brightness. Simultaneously, the binary iterative logic ensures that the adjustment accuracy increases with the number of iterations, thereby reducing adjustment time and improving system reliability while maintaining display quality.

[0082] Specifically, the initial value setting condition for the left endpoint of the voltage adjustment range is that the brightness of the sub-pixel 211 corresponding to the initial value is not higher than the brightness of the sub-pixel 211 corresponding to the initial value of the gate start voltage VGH. Reducing the gate start voltage VGH decreases the opening degree of the corresponding sub-pixel 211, thereby reducing the charging efficiency of the liquid crystal capacitor. There exists a suitable gate start voltage VGH such that the brightness of the first n columns of sub-pixels 211 after charging in each pixel group 21 decreases, and the brightness after the first and second frames are neutralized is comparable to the brightness of the last n columns of sub-pixels 211.

[0083] Please refer to Table 1 below. Table 1 is a table for adjusting the first gate startup voltage VGH1 according to an embodiment of this application. For example, by adjusting the first gate startup voltage VGH1 using the above-described binary adjustment logic, the initial value of the gate turn-off voltage VGL can be used as the left endpoint of the initial voltage adjustment range, and the right endpoint is the initial value of the gate startup voltage VGH. The initial value of the gate turn-off voltage VGL is 20V, and the initial value of the gate startup voltage VGH is 33V.

[0084] Table 1: Adjustment table of the first gate startup voltage VGH1 provided in an embodiment of this application

[0085] As shown in the table above, assuming the appropriate target gate start-up voltage for the first gate start-up voltage VGH1 is 31.4V, after selecting a 20V input, the first n columns are lit and the last n columns are dark. When the input gate start-up voltage VGH is 33V, the first n columns are lit and the last n columns are dark. If the second gate start-up voltage VGH2 input to the last n columns remains unchanged, the brightness of the last n columns will not change. Therefore, the appropriate range for the first gate start-up voltage VGH1 is between 20V and 33V.

[0086] Then, the target gate start-up voltage is calculated using a binary search method. After each voltage adjustment, the brightness of the first n columns of sub-pixels 211 and the last n columns of sub-pixels 211 in any column of pixel group 21 is compared (if more precise calculation is required, the brightness difference can be detected for adjustment). If the brightness of the first n columns of sub-pixels 211 is significantly lower than that of the last n columns of sub-pixels 211, the current target gate start-up voltage is used as the new left endpoint value, while the right endpoint value remains unchanged. The average of the new left endpoint value and the right endpoint value is then calculated and transmitted to the power management module 40 as the new target gate start-up voltage. If the brightness of the first n columns of sub-pixels 211 is significantly higher than that of the last n columns of sub-pixels 211, the brightness needs to be reduced. In this case, the current left endpoint value remains unchanged, the current target gate start-up voltage is used as the new right endpoint value, and the average of the new left endpoint value and the right endpoint value is calculated and transmitted to the power management module 40 as the new target gate start-up voltage.

[0087] Alternatively, adjustment can be made by comparing the first pixel voltage of the first n columns of sub-pixels 211 with the pixel voltage of the last n columns of sub-pixels 211 in any column of pixel group 21. If the first pixel voltage of the first n columns of sub-pixels 211 is less than the second pixel voltage of the last n columns of sub-pixels 211, it means that the brightness of the first n columns of sub-pixels 211 is lower than the brightness of the last n columns of sub-pixels 211, and the brightness needs to be increased. In this case, the current target gate start voltage is used as the new left endpoint value, the right endpoint value remains unchanged, and the average value of the new left endpoint value and the right endpoint value is calculated as the new target gate start voltage and transmitted to the power management module 40. If the first pixel voltage of the first n columns of sub-pixels 211 is greater than the second pixel voltage of the last n columns of sub-pixels 211, it means that the brightness of the first pixel of the first n columns of sub-pixels 211 is higher than the brightness of the last n columns of sub-pixels 211, and the brightness needs to be decreased. In this case, the left endpoint value remains unchanged, the current target gate start voltage is used as the new right endpoint value, and the average value of the new left endpoint value and the right endpoint value is calculated as the new target gate start voltage and transmitted to the power management module 40.

[0088] By monitoring the voltage difference between the first and second pixels in real time and dynamically adjusting the voltage range, the brightness of the first n columns of sub-pixels 211 and the last n columns of sub-pixels 211 in each pixel group 21 are quickly balanced, effectively eliminating the phenomenon of vertical bright and dark lines caused by capacitive coupling in the H-type architecture. Using the voltage difference as a direct quantitative indicator of brightness difference avoids the subjective setting error of static adjustment, realizes closed-loop feedback optimization, and can significantly improve adjustment accuracy. At the same time, by adopting a binary iterative mechanism, the adjustment efficiency can be controlled by adjusting the number of iterations. Increasing the number of iterations makes the voltage value closer to the optimal solution, and the error accuracy increases with the number of iterations, thereby achieving a balance between display uniformity and adjustment speed to meet different display quality requirements.

[0089] Alternatively, the converted current signal can be obtained by setting the aforementioned photosensitive device, and then the adjustment can be made by comparing the first current Is1 in the first photosensitive device 253 with the second current Is2 in the second photosensitive device 254. If the first current Is1 is less than the second current Is2, it means that the brightness of the first n columns of sub-pixels 211 is lower than the brightness of the last n columns of sub-pixels 211, and the brightness needs to be increased. In this case, the current target gate start-up voltage is used as the new left endpoint value, the right endpoint value remains unchanged, and the average value of the new left endpoint value and the right endpoint value is calculated as the new target gate start-up voltage and transmitted to the power management module 40. If the first current Is1 is greater than the second current Is2, it means that the brightness of the first pixel of the first n columns of sub-pixels 211 is higher than the brightness of the last n columns of sub-pixels 211, and the brightness needs to be reduced. In this case, the left endpoint value remains unchanged, the current target gate start-up voltage is used as the new right endpoint value, and the average value of the new left endpoint value and the right endpoint value is calculated as the new target gate start-up voltage and transmitted to the power management module 40.

[0090] Please see Figure 10 , Figure 10 This is a schematic flowchart of a driving method for a display panel provided in one embodiment of this application. In this embodiment, the display panel 200 includes a plurality of sub-pixels 211, a plurality of scan lines 22, a plurality of data lines 23, and a gate driving module 24; wherein, each row of sub-pixels 211 is divided into a plurality of pixel groups 21, and each pixel group 21 includes 2n adjacent sub-pixels 211, where n is a positive integer; wherein, the 1st to nth sub-pixels 211 are connected to the kth row of scan lines 22, and the (n+1)th to 2nth sub-pixels 211 are connected to the (k+1)th row of scan lines 22, where k is a positive integer; the ath sub-pixel 211 and the (a+n)th sub-pixel 211 are connected to the same corresponding data line 23, where a is a positive integer and a≤n.

[0091] The driving methods include: S1: Set a voltage adjustment range, which includes a left endpoint value and a right endpoint value; use the initial gate turn-off voltage VGL as the initial value of the left endpoint value and the initial gate start-up voltage VGH as the initial value of the right endpoint value; S2: Calculate the average of the left endpoint value and the right endpoint value; S3: Use the average value as the target gate start-up voltage and output the corresponding voltage control signal; S4: Determine whether the target gate start-up voltage meets the condition for stopping adjustment; S5: In response to the condition for stopping adjustment being met, stop adjusting the first gate startup voltage VGH1 and / or the second gate startup voltage VGH2; S6: In response to the failure to meet the conditions for stopping adjustment, the left endpoint value or the right endpoint value is redefined, and the first gate start voltage VGH1 and / or the second gate start voltage VGH2 are adjusted based on the new voltage adjustment range.

[0092] Specifically, the structure and function of the display panel 200 are the same as those of the display panel 200 provided in the above embodiment, and can achieve the same technical effect. Please refer to the relevant description above for details. In this embodiment, the first gate start-up voltage VGH1 of the first n columns of sub-pixels 211 in each pixel group 21 is adjusted through a binary iterative mechanism. The left endpoint of the initial voltage adjustment interval is set as the initial gate turn-off voltage VGL, and the right endpoint is set as the initial gate start-up voltage VGH. The average value is calculated as the target gate start-up voltage output. Specifically, the above driving method can be executed by the voltage adjustment module 30 in the display panel 200, achieving closed-loop feedback by monitoring the difference between the first pixel voltage of the first n columns of sub-pixels 211 and the second pixel voltage of the last n columns of sub-pixels 211. Specifically, automatic adjustment can be performed after the display panel 200 is powered on, through back-power timing control, or continuous adjustment during real-time display.

[0093] For example, in one embodiment, a voltage range of 20V to 33V can be used to dynamically update endpoint values ​​based on brightness comparison results or pixel voltage comparison results. For instance, if the brightness of the current n columns is lower than that of the next n columns, the left endpoint value is updated to the current average value; conversely, the right endpoint value is updated to the current average value, ensuring accurate adjustment direction. Here, the gate turn-off voltage VGL refers to the VGL value (low voltage level), and the gate start-up voltage VGH refers to the VGH value (high voltage level). The voltage control signal is generated by the voltage adjustment module 30 and transmitted to the power management module 40. The power management module 40 then transmits the adjusted first gate start-up voltage VGH1 and second gate start-up voltage VGH2 to the gate drive module 24 according to the voltage control signal.

[0094] In this embodiment, the driving method dynamically iteratively adjusts the first gate activation voltage VGH1 using a binary search method, balancing the brightness of the first n columns of sub-pixels 211 in each pixel group 21 with that of the last n columns, thus eliminating vertical bright-dark lines caused by capacitive coupling. The initial range setting ensures the inclusion of the optimal solution (the left endpoint corresponds to the darkest brightness, and the right endpoint corresponds to the initial value of the gate activation voltage VGH). The iterative process is based on brightness difference feedback (achieved through Vs voltage monitoring or Is current monitoring). As the number of iterations increases, the adjustment accuracy improves, ultimately achieving uniform brightness display. For example, within the 20V to 33V range, through multiple iterations (e.g., calculating an average of 26.5V from 20V and 33V, and adjusting the endpoints based on brightness comparisons), the voltage is precisely adjusted to 31.4V, causing the bright-dark lines to disappear, thereby solving the problem of vertical bright-dark lines in the H-type architecture display panel 200 and improving display quality.

[0095] In some implementations, the conditions for stopping the adjustment include: The number of iterations is greater than or equal to the preset number of iterations; or, The absolute value of the voltage difference between the first pixel voltage and the second pixel voltage is less than or equal to the threshold; or, The absolute value of the current difference between the first current Is1 and the second current Is2 is less than or equal to the threshold; or, The absolute value of the brightness difference between the 1st to nth sub-pixels 211 and the (n+1)th to 2nth sub-pixels 211 is less than or equal to a preset difference.

[0096] It is understandable that a preset number of iterations can be set in advance, and the gate start voltage VGH adjustment should be stopped by judging whether the number of iterations is greater than or equal to the preset number of iterations; if it is greater than or equal to the preset number of iterations, the adjustment is stopped, otherwise the adjustment continues.

[0097] Alternatively, the voltages of the first and second pixels can be acquired in real time, preprocessed, and then the absolute value of the voltage difference between the first and second pixels can be calculated. The gate start voltage VGH adjustment can be stopped by judging whether the absolute value is less than or equal to the threshold. If it is less than or equal to the threshold, the adjustment is stopped; otherwise, the adjustment continues.

[0098] Alternatively, the first current Is1 and the second current Is2 can be acquired in real time, and the first current Is1 and the second current Is2 can be preprocessed. Then, the absolute value of the current difference between the first current Is1 and the second current Is2 can be calculated. The gate start voltage VGH adjustment can be stopped by judging whether the absolute value is less than or equal to the threshold. If it is less than or equal to the threshold, the adjustment is stopped; otherwise, the adjustment continues.

[0099] Alternatively, in each pixel group 21, the first brightness of the first n columns of sub-pixels 211 and the second brightness of the last n columns of sub-pixels 211 can be collected. Then, the gate start voltage VGH adjustment is stopped by judging whether the absolute value of the brightness difference between the first brightness and the second brightness is less than or equal to a preset difference. If it is less than or equal to the threshold, the gate start voltage VGH adjustment is stopped; otherwise, the adjustment continues.

[0100] In specific implementations, suitable conditions for stopping adjustment can be selected according to actual needs and adjustment precision, so that the driving method can be applied to different stages and scenarios.

[0101] In some embodiments, steps S4 and S6 further include: S71: In response to the condition that the stop adjustment is not met, acquire the first pixel voltage and the second pixel voltage under the target gate start voltage; or, S72: In response to the condition that the stop adjustment is not met, acquire the first brightness of the 1st to nth sub-pixels 211 and the second brightness of the (n+1)th to 2nth sub-pixels 211 under the target gate start voltage; or, S73: In response to the failure to meet the stop regulation condition, acquire the first current Is1 and the second current Is2 under the target gate start voltage; Step S6 includes: S61: Calculate the voltage difference between the first pixel voltage and the second pixel voltage; or, calculate the brightness difference between the first brightness and the second brightness; or, calculate the current difference between the first current Is1 and the second current Is2. S62: Determine whether the pressure difference, brightness difference, or current difference is less than zero; S63: In response to a pressure difference, brightness difference, or current difference being greater than zero, keep the left endpoint value unchanged and update the average value to the new right endpoint value; S64: In response to a pressure difference, brightness difference, or current difference being less than zero, update the average value to the new left endpoint value while keeping the right endpoint value unchanged. S65: Based on the new right endpoint value or the new left endpoint value, execute steps two through six.

[0102] Specifically, the brightness difference can be used to determine whether the average value of the left and right endpoints is updated to the left endpoint value or the right endpoint value, based on the brightness difference between the first n columns of sub-pixels 211 and the last n columns of sub-pixels 211 in the same column of pixel group 21. If the brightness difference is less than zero, the brightness of the first n columns of sub-pixels 211 is lower than that of the last n columns of sub-pixels 211, and the target gate start-up voltage needs to be increased. In this case, the average value of the left and right endpoints is used as the new left endpoint value, while the right endpoint value remains unchanged. If the brightness difference is greater than zero, the brightness of the first n columns of sub-pixels 211 is higher than that of the last n columns of sub-pixels 211, and the target gate start-up voltage needs to be decreased. In this case, the average value of the left and right endpoints is used as the new right endpoint value, while the left endpoint value remains unchanged.

[0103] Alternatively, the voltage difference between the first n columns of sub-pixels 211 and the last n columns of sub-pixels 211 in the same pixel group 21 can be used to determine whether the average value of the left and right endpoints is updated to the left endpoint value or the right endpoint value. Here, the first pixel voltage refers to the pixel voltage of the first n columns of sub-pixels 211, and the second pixel voltage refers to the pixel voltage of the last n columns of sub-pixels 211. If the voltage difference is less than zero, the brightness of the first n columns of sub-pixels 211 is lower than that of the last n columns of sub-pixels 211, and the target gate activation voltage needs to be increased. In this case, the average value of the left and right endpoints is used as the new left endpoint value, while the right endpoint value remains unchanged. If the voltage difference is greater than zero, the brightness of the first n columns of sub-pixels 211 is higher than that of the last n columns of sub-pixels 211, and the target gate activation voltage needs to be decreased. In this case, the average value of the left and right endpoints is used as the new right endpoint value, while the left endpoint value remains unchanged.

[0104] Alternatively, the brightness difference between the first n columns of sub-pixels 211 and the last n columns of sub-pixels 211 in the same pixel group 21 can be determined by judging the current difference of the current signal converted by the photoelectric device, and then the average value of the left and right endpoints can be updated to the left endpoint value or the right endpoint value. The specific method of updating the endpoint values ​​is the same as the related update method described in the above embodiment, and can be referred to the above description for details, which will not be repeated here.

[0105] In this embodiment, the first gate-start voltage VGH1 is iteratively adjusted using a dynamic binary search method to precisely balance the brightness of the first n columns of sub-pixels 211 with that of the last n columns of sub-pixels 211, effectively eliminating the vertical bright-dark line problem caused by capacitive coupling in the H-type architecture display panel 200. This driving method, based on closed-loop feedback of brightness monitoring, avoids the defect of static gate-start voltage VGH setting being unable to adapt to voltage fluctuations, and solves the root cause problem of the capacitive coupling effect causing the brightness of the first n columns of sub-pixels 211 to be too bright. Increasing the number of iterations can improve accuracy, achieving gradual convergence from the initial voltage adjustment range to the precise value of the final target gate-start voltage, ultimately significantly improving display uniformity, resulting in a more natural visual effect, and meeting the practical requirements of the high-resolution display panel 200.

[0106] The above are merely embodiments of this application and do not limit the scope of patent protection of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A display panel, comprising multiple sub-pixels, multiple scan lines, multiple data lines, and a gate driving module; Its features are, Each row of subpixels is divided into multiple pixel groups, and each pixel group includes 2n adjacent subpixels, where n is a positive integer; wherein, the 1st to nth subpixels are connected to the kth scan line, the (n+1)th to 2nth subpixels are connected to the (k+1)th scan line, where k is a positive integer; the ath subpixel and the (a+n)th subpixel are connected to the same corresponding data line, where a is a positive integer and a≤n; The display panel also includes: The voltage adjustment module is used to adjust the first gate start voltage of the k-th scan signal and / or the second gate start voltage of the (k+1)-th scan signal, and output the corresponding voltage control signal. The power management module is electrically connected to the voltage adjustment module and the gate drive module, and is used to provide the gate drive module with the corresponding first gate start-up voltage and second gate start-up voltage according to the voltage control signal; wherein the first gate start-up voltage is less than the second gate start-up voltage.

2. The display panel according to claim 1, characterized in that, The display panel also includes: A voltage acquisition unit includes a first acquisition line and a second acquisition line; the first acquisition line is electrically connected to at least one of the 1st to nth sub-pixels and is used to acquire the first pixel voltage of the 1st to nth sub-pixels; the second acquisition line is electrically connected to at least one of the (n+1)th to 2nth sub-pixels and is used to acquire the second pixel voltage of the (n+1)th to 2nth sub-pixels. The voltage adjustment module is electrically connected to the voltage acquisition unit and is used to adjust the first gate start-up voltage and / or the second gate start-up voltage according to the voltage difference between the first pixel voltage and the second pixel voltage.

3. The display panel according to claim 2, characterized in that, The voltage acquisition unit further includes a first switching transistor and a second switching transistor. The first switching transistor is connected in series in the first acquisition line, and the second switching transistor is connected in series in the second acquisition line. The gates of the first switching transistor and the second switching transistor are respectively connected to the acquisition control signal.

4. The display panel according to claim 2, characterized in that, The first acquisition line corresponds one-to-one with at least two of the 1st to nth sub-pixels and is electrically connected; the second acquisition line corresponds one-to-one with at least two of the (n+1)th to 2nth sub-pixels and is electrically connected. The voltage adjustment module is used to calculate a first average value of the first pixel voltage of at least two of the 1st to nth sub-pixels, calculate a second average value of the second pixel voltage of at least two of the (n+1)th to 2nth sub-pixels, and adjust the first gate start-up voltage and / or the second gate start-up voltage according to the voltage difference between the first average value and the second average value; or, The first acquisition line is electrically connected to one of the 1st to nth sub-pixels, and the second acquisition line is electrically connected to one of the (n+1)th to 2nth sub-pixels; The voltage adjustment module is used to adjust the first gate start-up voltage and / or the second gate start-up voltage according to the voltage difference between the first pixel voltage acquired by the first acquisition line and the second pixel voltage acquired by the second acquisition line.

5. The display panel according to claim 2, characterized in that, The voltage adjustment module is used to perform the following steps: Step 1: Set the voltage adjustment range, which includes a left endpoint value and a right endpoint value; use the initial gate turn-off voltage as the initial value of the left endpoint value and the initial gate start-up voltage as the initial value of the right endpoint value of the voltage adjustment range; Step 2: Calculate the average of the left endpoint value and the right endpoint value; Step 3: Use the average value as the target gate start-up voltage and output the corresponding voltage control signal; Step 4: Determine whether the target gate start-up voltage meets the conditions for stopping adjustment; Step 5: In response to the condition for stopping adjustment being met, stop adjusting the first gate startup voltage and / or the second gate startup voltage; Step Six: In response to the failure to meet the conditions for stopping adjustment, the left endpoint value or the right endpoint value is redefined, and the first gate start-up voltage and / or the second gate start-up voltage are continued to be adjusted based on the new voltage adjustment range.

6. The display panel according to claim 5, characterized in that, The conditions for stopping the adjustment include the number of iterations being greater than or equal to the preset number of iterations; Following step three, the process also includes: incrementing the iteration count by one and updating it to the new iteration count; Step four includes: determining whether the new iteration number is greater than or equal to the preset iteration number.

7. The display panel according to claim 5, characterized in that, The conditions for stopping adjustment include the absolute value of the voltage difference between the first pixel voltage and the second pixel voltage being less than or equal to a threshold. Following step three, the method further includes: acquiring the first pixel voltage and the second pixel voltage under the target gate start-up voltage; Step four includes: determining whether the absolute value of the voltage difference between the first pixel voltage and the second pixel voltage is less than or equal to a threshold.

8. The display panel according to claim 6 or 7, characterized in that, Between step four and step six, the method further includes: in response to the condition of not meeting the stop adjustment, acquiring the first pixel voltage and the second pixel voltage under the target gate start voltage; Step six includes: Calculate the voltage difference between the first pixel voltage and the second pixel voltage; Determine whether the pressure difference is less than zero; In response to the pressure difference being greater than zero, the left endpoint value is kept unchanged, and the average value is updated to the new right endpoint value; In response to the pressure difference being less than zero, the average value is updated to a new left endpoint value, while the right endpoint value remains unchanged; Based on the new right endpoint value or the new left endpoint value, perform steps two through six.

9. A driving method for a display panel, the display panel comprising a plurality of sub-pixels, a plurality of scan lines, a plurality of data lines, and a gate driving module; wherein, Each row of subpixels is divided into multiple pixel groups, and each pixel group includes 2n adjacent subpixels, where n is a positive integer; wherein, the 1st to nth subpixels are connected to the kth scan line, the (n+1)th to 2nth subpixels are connected to the (k+1)th scan line, where k is a positive integer; the ath subpixel and the (a+n)th subpixel are connected to the same corresponding data line, where a is a positive integer and a≤n; The driving method is characterized by comprising: Step 1: Set the voltage adjustment range, which includes a left endpoint value and a right endpoint value; use the initial gate turn-off voltage as the initial value of the left endpoint value and the initial gate start-up voltage as the initial value of the right endpoint value; Step 2: Calculate the average of the left endpoint value and the right endpoint value; Step 3: Use the average value as the target gate start-up voltage and output the corresponding voltage control signal; Step 4: Determine whether the target gate start-up voltage meets the conditions for stopping adjustment; Step 5: In response to the condition for stopping adjustment being met, stop adjusting the first gate startup voltage and / or the second gate startup voltage; Step 6: In response to the failure to meet the conditions for stopping adjustment, the left endpoint value or the right endpoint value is redefined, and the first gate start-up voltage and / or the second gate start-up voltage are continued to be adjusted based on the new voltage adjustment range.

10. The driving method according to claim 9, characterized in that, The conditions for stopping the adjustment include: The number of iterations is greater than or equal to the preset number of iterations; or, The absolute value of the voltage difference between the first pixel voltage and the second pixel voltage is less than or equal to a threshold; or, The absolute value of the brightness difference between the 1st to nth sub-pixels and the (n+1)th to 2nth sub-pixels is less than or equal to a preset difference value; The following also applies between step four and step six: In response to the condition that the adjustment stop is not met, the first pixel voltage and the second pixel voltage at the target gate start voltage are acquired; or, In response to the failure to meet the stop adjustment condition, the first brightness of the 1st to nth sub-pixels and the second brightness of the (n+1)th to 2nth sub-pixels under the target gate start voltage are obtained; Step six includes: Calculate the voltage difference between the first pixel voltage and the second pixel voltage; or, calculate the brightness difference between the first brightness and the second brightness. Determine whether the pressure difference or the brightness difference is less than zero; In response to the pressure difference or the brightness difference being greater than zero, the left endpoint value is kept unchanged, and the average value is updated to the new right endpoint value; In response to the pressure difference or the brightness difference being less than zero, the average value is updated to a new left endpoint value while the right endpoint value remains unchanged; Based on the new right endpoint value or the new left endpoint value, perform steps two through six.

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