A voice control method and system for a companion robot for voice interaction

Abstract

The application discloses a voice control method and system of a companion robot for voice interaction, and belongs to the technical field of voice interaction and embedded control. The method comprises the following steps: S1, a first processor continuously collects audio and locally detects a wake-up word; S2, when the wake-up word is detected, the first processor controls a power switch circuit to be turned on through a GPIO, so that a second power supply domain is powered on, and a second processor is started; S3, the first processor transmits audio data to shared memory of the second processor through a dedicated audio interface in a DMA mode, without passing through a CPU bus; S4, the second processor executes a voice processing task; S5, when a conversation ends, the second processor sends an end instruction; and S6, the first processor controls a power switch to be turned off, the second power supply domain is powered off, and low-power standby is restored. According to the application, through a dual-processor dual-power supply domain architecture, the whole-board power consumption is controlled to be below about 50 mW in a standby listening state, while complete local voice interaction capability and microsecond-level audio link delay are maintained.

Description

Technical Field

[0001] This invention relates to the field of voice interaction and embedded control technology, and more specifically, to a voice control method and system for a companion robot with voice interaction. Background Technology

[0002] Companion robots are increasingly used in scenarios such as children's education, elderly care, and emotional interaction, with voice interaction being their core function. A companion robot with voice interaction capabilities needs to continuously monitor voice signals in the environment, detect wake words in real time, and complete processing tasks such as speech recognition, semantic understanding, and speech synthesis after being awakened by the user.

[0003] In existing technologies, companion robots typically use a single processor to handle all the above tasks. The drawback of this approach is that the processor must always operate at full capacity, making it impossible to differentiate between the power consumption differences between "standby listening" and "active conversation" modes. For battery-powered portable companion robots, this directly results in short standby time and insufficient battery life.

[0004] Some high-end solutions employ high-performance processors with integrated neural network acceleration engines, enabling the local execution of large-parameter language models for offline voice interaction. While these solutions offer better response quality, their overall power consumption typically ranges from several watts to tens of watts, requiring active cooling and making them unsuitable for extended operation in small, battery-powered companion robots. Furthermore, the system operates at full power regardless of whether in voice interaction or silent standby mode, resulting in no difference in power consumption.

[0005] More importantly, in a single-processor architecture, audio data captured from the microphone must first pass through the CPU bus buffer before being moved to the processing engine by the CPU. This path introduces additional transmission latency and CPU load overhead, which significantly impacts the user experience in scenarios requiring rapid interruption and continuous dialogue. Especially when there is only one processor and it needs to handle multiple tasks simultaneously, such as communication, sensor polling, and display refreshing, the real-time performance of audio processing cannot be reliably guaranteed.

[0006] Therefore, there is a need for a voice control method that can maintain the quality of voice interaction, keep standby power consumption at a low level, and have sufficiently short audio processing latency. Summary of the Invention

[0007] The present invention aims to provide a voice control method and system for companion robots with voice interaction, in order to solve the problems of low power standby and high-quality voice processing that cannot be achieved simultaneously in existing solutions, as well as the high latency of audio data transmission paths.

[0008] To achieve the above objectives, the present invention provides a voice control method for a companion robot with voice interaction, applied to a hardware system including a first processor, a second processor, a power switch circuit, and an audio acquisition module. The first processor is continuously powered by a first power supply domain, and the second processor is powered by a second power supply domain. The on / off state of the second power supply domain is controlled by the general-purpose input / output terminal of the first processor. The method is characterized by including the following steps: Step S1: The first processor continuously acquires audio signals from the audio acquisition module and runs a wake-up word detection algorithm locally; Step S2: When a wake word is detected, the first processor outputs a conduction control signal to the power switch circuit through its general-purpose input / output terminal to power on the second power supply domain and start the second processor. Step S3: The first processor transmits the audio signal to the shared memory area of ​​the second processor via a dedicated audio data interface through direct memory access. This transmission process does not pass through the CPU bus. Step S4: The second processor reads the audio signal from the shared memory region and performs a voice processing task; Step S5: When it is determined that a dialogue process has ended, the second processor sends a dialogue end command to the first processor. Step S6: After receiving the dialogue end instruction, the first processor outputs a cutoff control signal to the power switch circuit through its general-purpose input / output terminal, so that the second power supply domain is powered off and the system returns to the standby listening state where only the first processor works.

[0009] The core idea behind this method is to allocate two processors to two independent power domains. A low-power processor, always on, is dedicated to wake-up monitoring, while a high-power voice processor is powered on only when needed—thus achieving "on-demand power supply." Simultaneously, a direct audio data path, bypassing the CPU bus, is established between the two processors to further reduce latency. Working together, the system can seamlessly switch between standby power consumption in the tens of milliwatts range and conversational capabilities in the several watts range.

[0010] In one embodiment, the power switching circuit in step S2 includes a P-channel MOSFET. The gate of the P-channel MOSFET is connected to the general-purpose input / output terminal of the first processor via a current-limiting resistor, the source is connected to the power input, and the drain is connected to the power input terminal of the second power supply domain. The turn-on control signal is a low-level signal, and the turn-off control signal is a high-level signal. Using a PMOS transistor to implement power gating has the advantages of low on-resistance, low turn-off leakage current, and low device cost.

[0011] In one implementation, the dedicated audio data interface in step S3 is either an I2S interface or a TDM interface. Both of these interfaces are industry standards for inter-chip audio transmission and do not require additional protocol conversion circuitry.

[0012] In one embodiment, in step S1, after acquiring the audio signal, the first processor further performs front-end preprocessing on it. The front-end preprocessing includes at least one of echo cancellation, ambient noise suppression, and beamforming. Since the above preprocessing is completed before wake-up, the second processor can directly obtain a clean human voice signal after power-on without repeated processing.

[0013] In one implementation, in step S4, the neural network acceleration engine built into the second processor reads audio data from the shared memory region and performs at least one task among speech recognition, semantic understanding, and speech synthesis. The neural network acceleration engine performs matrix and vector operations in hardware, significantly improving the throughput of local speech processing.

[0014] In one implementation, the wake-word detection algorithm in step S1 runs locally in the on-chip storage of the first processor, without relying on cloud services. Local wake-word detection avoids network latency and privacy risks, which is especially important for home-based devices such as companion robots.

[0015] In one implementation, the first processor is a digital signal processor or a Bluetooth audio system-on-a-chip, and the second processor is a system-on-a-chip integrating a neural network acceleration engine. Both types of chips are readily available and reasonably priced in the consumer electronics sector, which facilitates large-scale product production.

[0016] To achieve the above objectives, the present invention also provides a voice control system for a companion robot with voice interaction, comprising: The first audio processing unit is continuously powered by the first power supply domain and is configured to continuously acquire audio signals and detect wake words locally. The power switch circuit has its control terminal connected to the general-purpose input / output terminal of the first audio processing unit, and its power channel is connected in series in the power supply path of the second power supply domain. The second audio processing unit is powered by the second power supply domain and has a built-in shared memory controller. A dedicated audio data link is connected between the audio data output interface of the first audio processing unit and the shared memory controller of the second audio processing unit; The first audio processing unit is further configured to: when a wake word is detected, control the power switch circuit to turn on to power on the second power supply domain, and send the collected audio signal to the shared memory area of ​​the second audio processing unit via the dedicated audio data link in a direct memory access manner; and after receiving a dialogue end signal, control the power switch circuit to turn off to power off the second power supply domain.

[0017] In one embodiment, the power switching circuit includes a P-channel MOSFET and a current-limiting resistor. The gate of the P-channel MOSFET is connected to the general-purpose input / output terminal of the first audio processing unit via the current-limiting resistor, the source is connected to the output terminal of the voltage conversion unit, and the drain is connected to the power input node of the second power supply domain.

[0018] In one embodiment, the dedicated audio data link is deployed on the top signal layer of a four-layer PCB board, with a trace length not exceeding 40 mm. Grounded copper shielding is provided on both sides of the trace, using the ground layer as a reference plane. The short trace combined with ground shielding effectively suppresses electromagnetic radiation from high-speed digital signals and controls the link transmission delay to the microsecond level.

[0019] The technical solution provided by this invention has the following beneficial effects: Through a dual-processor, dual-power-domain architecture, the normally-on, low-power wake-up monitoring task is decoupled from the voice processing task that only powers on after wake-up. This allows the system's overall power consumption to be controlled below approximately 50 milliwatts in standby monitoring mode, while providing complete local voice interaction capabilities in conversation mode. Simultaneously, the direct audio link between processors avoids the latency and load overhead caused by CPU bus relay. Testing shows that the end-to-end link latency from microphone acquisition to the second processor receiving audio data is typically only in the microsecond range, with negligible impact on the real-time performance of voice interaction. Attached Figure Description

[0020] Figure 1 Flowchart of voice control method Figure 2 Schematic diagram of data flow in the audio data direct link Figure 3 : Architecture diagram of the voice control system. Detailed Implementation

[0021] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] Example 1 Reference Figure 1-3 This embodiment provides a voice control system, whose hardware platform mainly includes: a first audio processing unit, a second audio processing unit, a power switch circuit, at least one MEMS microphone, and an audio power amplifier.

[0023] The first audio processing unit uses the JL AC6956C chip. This chip is a Bluetooth audio system-on-a-chip with a built-in 16-bit digital signal processor core, supports dual-channel I2S microphone input, and integrates echo cancellation and ambient noise suppression algorithms in its firmware. In continuous audio acquisition and wake-word detection operation, the chip consumes approximately tens of milliwatts; in standby mode, maintaining only clock and GPIO monitoring, the power consumption is typically only a few milliwatts.

[0024] The second audio processing unit uses the Allwinner R128-S3 chip. This chip integrates a vector acceleration engine of approximately 0.5 TOPS and a shared memory controller, enabling it to complete model loading and initialization quickly after a new word wake-up, and supports local speech synthesis and lightweight natural language processing. Its power consumption is approximately 1 watt at full speed.

[0025] The core component of the power switch circuit is a P-channel MOSFET Q1, such as an AO3401 or a small surface-mount PMOS transistor of equivalent specifications, paired with a gate current-limiting resistor R1 of approximately 10kΩ. The source of Q1 is connected to the second output terminal of the system voltage conversion unit, the drain is connected to the power input node of the second power supply domain VDD2, and the gate is connected to the GPIO_PA4 pin of the AC6956C chip via R1. In addition, the system also includes a battery charging management unit and a voltage conversion unit. The battery charging management unit converts the 5V input from the USB-C port into lithium battery charging current; the voltage conversion unit converts the battery voltage, nominally 3.7V (actual range approximately 3.0-4.2V), into the 3.3V operating voltage required by each domain.

[0026] The MEMS microphone is a Knowles SPH0641LM4H-1 or other I2S digital output microphones with a signal-to-noise ratio higher than 60dB. The two microphones are arranged side by side with a spacing of approximately 20 mm to form a dual microphone array, which is connected to the AC6956C chip via an I2S0 interface.

[0027] The following is for reference Figures 1-3 The voice control method flow of this embodiment will be described in detail.

[0028] Step S1 – Standby Monitoring After the system powers on, the first power supply domain VDD1 is immediately powered. The AC6956C chip starts up and loads the wake-word detection firmware. GPIO_PA4 is high by default, or in a high-impedance state, Q1 is cut off, the second power supply domain VDD2 is powered off, and the R128-S3 chip is not working. At this time, the total power consumption of the board is about 20 milliwatts.

[0029] The AC6956C chip continuously acquires digital audio signals from two MEMS microphones via the I2S0 interface, utilizing its built-in audio front-end preprocessing module for echo cancellation and noise suppression. Subsequently, the wake-word detection engine continuously matches the processed audio stream locally. The wake-word can be customized by the user via the Bluetooth configuration interface and is stored in the chip's on-chip flash memory, independent of network connectivity.

[0030] Step S2 – Wake-up and Power-on When a wake-word match is detected, the AC6956C chip immediately performs the following operations: GPIO_PA4 is driven low. At this time, the gate-source voltage of PMOS transistor Q1 reaches the turn-on threshold, approximately -0.7V to -1.5V, Q1 turns on, and the second output of the voltage conversion unit supplies power to the second power supply domain VDD2 via Q1. The R128-S3 chip powers on and loads firmware from the external SPI Flash, completing peripheral initialization and model loading. This startup process typically completes within hundreds of milliseconds.

[0031] VDD1 maintains a constant high level after the system is powered on; the wake-up word signal is a pulse event; GPIO_PA4 immediately flips from high to low level after the wake-up word pulse; VDD2 rises to the rated voltage within a few milliseconds (Q1 conduction time plus the second processor startup time) after the GPIO flip.

[0032] Step S3 – Audio Passthrough The AC6956C chip's second audio data interface, I2S1, is configured as a master device, while the R128-S3 chip's corresponding interface is configured as a slave device. The AC6956C outputs the digital audio signal, which has been captured by the microphone and pre-processed by the front end, through the bit clock line, frame clock line, and data line of the I2S1 interface.

[0033] The R128-S3 chip's internal DMA controller automatically moves data from the I2S receive buffer to the shared memory area. Since this data transfer does not pass through the CPU bus, it does not generate additional CPU load or introduce bus arbitration latency. The I2S1 interface traces are routed on the top signal layer of a 4-layer PCB, with trace lengths typically controlled within 40 mm. The ground plane is used as the reference plane, and grounded shielding copper foil is laid on both sides of the traces. Under these conditions, the rise / falling edge quality of the I2S signal is good, and the end-to-end audio data transmission delay is typically only a few microseconds, with negligible impact on the real-time performance of voice interaction.

[0034] Step S4 – Speech Processing The R128-S3 chip reads audio data from the shared memory area and calls the built-in vector acceleration engine to perform the following tasks in sequence: automatic speech recognition, converting the audio stream into text; natural language understanding, extracting user intent and entities from the text; dialogue management, matching response strategies according to intent; and speech synthesis, synthesizing the response text into an audio waveform.

[0035] The synthesized audio data is sent to the NS4830 Class D audio power amplifier via the I2S output interface of the R128-S3 to drive the external speaker to play the response voice.

[0036] Step S5 – Dialogue End Determination The R128-S3 chip continuously monitors the dialogue status during the voice processing flow. A dialogue flow is determined to end when any of the following conditions are met: no human voice is detected for several consecutive seconds; the semantic understanding module recognizes the intention to end the dialogue, such as the user saying "It's okay" or "Go and rest"; or the synthesized reply voice has been played completely and the user has not responded within the specified time limit.

[0037] Step S6 – Power off and resume standby After determining that the dialogue has ended, the R128-S3 chip sends a pre-defined dialogue termination command to the AC6956C chip via the UART serial port. Upon receiving this command, the AC6956C chip restores GPIO_PA4 from low to high, Q1 is immediately turned off, the second power supply domain VDD2 is powered off, and the R128-S3 chip stops working. The system returns to a standby listening state where only the AC6956C is running, and the overall board power consumption returns to approximately 20 milliwatts.

[0038] After this, the system re-enters step S1 and continues to listen for the next wake-up event.

[0039] Storage security In the folded state after power loss, i.e., standby listening mode, the second power supply domain is completely disconnected, and the R128-S3 chip and its peripherals consume no leakage current. The first power supply domain only maintains the basic operation of the AC6956C chip and MEMS microphone, and will not automatically enter the dialogue state without external force or abnormal event triggering, ensuring that the battery power will not be unexpectedly depleted.

[0040] Example 2 The difference between this embodiment and Embodiment 1 lies in the chip selection and audio interface configuration.

[0041] The first audio processing unit uses the Hengxuan BES2600 chip, a 28nm process, with a dual-core ARM Cortex-M33 and a tri-core Audio DSP, consuming approximately 8 milliwatts. It can simultaneously connect to three MEMS microphones and supports a three-microphone adaptive beamforming algorithm to achieve sound source localization and directional noise suppression.

[0042] The second audio processing unit uses the StarChip SSC338Q chip, a dual-core ARM Cortex-A7 processor with a 1 TOPS neural network acceleration engine, consuming approximately 1.8 watts at full speed. The audio pass-through link adopts the TDM8 protocol, configured for 4-channel, 16kHz sampling rate, and 16-bit bit depth synchronous audio transmission, meeting the data bandwidth requirements of multi-microphone arrays.

[0043] The method steps in this embodiment are the same as those in Embodiment 1, and will not be repeated.

[0044] Other implementation methods Those skilled in the art should understand that the step numbers and order given in the above embodiments are not necessarily in strict chronological order. For example, step S3, audio pass-through transmission, and the latter half of step S2, where the second processor starts, can partially overlap—after the second processor powers on and completes basic initialization, its DMA controller and I2S slave interface are often ready before the application layer, and data pass-through transmission can begin before the application layer's processing capabilities are fully available.

[0045] Similarly, step S5, the dialogue end determination, can be executed in parallel with step S4, the speech processing. While the latter processes the current statement, the former monitors the dialogue status.

[0046] The above description is merely a preferred embodiment of the present invention and does not constitute a limitation on the scope of protection of the present invention. Any modifications, equivalent substitutions, or improvements made by those skilled in the art without departing from the principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A voice control method for a companion robot with voice interaction, applied to a hardware system including a first processor, a second processor, a power switch circuit, and an audio acquisition module, wherein the first processor is continuously powered by a first power supply domain, the second processor is powered by a second power supply domain, and the on / off state of the second power supply domain is controlled by the general-purpose input / output terminal of the first processor, characterized in that, Includes the following steps: Step S1: The first processor continuously acquires audio signals from the audio acquisition module and runs a wake-up word detection algorithm locally; Step S2: When a wake word is detected, the first processor outputs a conduction control signal to the power switch circuit through its general-purpose input / output terminal to power on the second power supply domain and start the second processor. Step S3: The first processor transmits the audio signal to the shared memory area of ​​the second processor via a dedicated audio data interface through direct memory access. This transmission process does not pass through the CPU bus. Step S4: The second processor reads the audio signal from the shared memory region and performs a voice processing task; Step S5: When it is determined that a dialogue process has ended, the second processor sends a dialogue end command to the first processor. Step S6: After receiving the dialogue end instruction, the first processor outputs a cutoff control signal to the power switch circuit through its general-purpose input / output terminal, so that the second power supply domain is powered off and the system returns to the standby listening state where only the first processor works.

2. The voice control method according to claim 1, characterized in that, The power switch circuit in step S2 includes a P-channel MOSFET. The gate of the P-channel MOSFET is connected to the general-purpose input / output terminal of the first processor via a current-limiting resistor. The source is connected to the power input, and the drain is connected to the power input terminal of the second power supply domain. The turn-on control signal is a low-level signal, and the turn-off control signal is a high-level signal.

3. The voice control method according to claim 1, characterized in that, The dedicated audio data interface in step S3 is either an I2S interface or a TDM interface.

4. The voice control method according to claim 1, characterized in that, Step S1 further includes: after acquiring the audio signal, the first processor performs front-end preprocessing on it, the front-end preprocessing including at least one of echo cancellation, ambient noise suppression and beamforming.

5. The voice control method according to claim 1, characterized in that, In step S4, the neural network acceleration engine built into the second processor reads audio data from the shared memory region and performs at least one of the tasks of speech recognition, semantic understanding and speech synthesis.

6. The voice control method according to claim 1, characterized in that, The wake word detection algorithm in step S1 runs locally in the on-chip storage space of the first processor and does not rely on cloud services.

7. The voice control method according to claim 1, characterized in that, The first processor is a digital signal processor or a Bluetooth audio system-on-a-chip, and the second processor is a system-on-a-chip with an integrated neural network acceleration engine.

8. A voice control system for a companion robot used for voice interaction, characterized in that, include: The first audio processing unit is continuously powered by the first power supply domain and is configured to continuously acquire audio signals and detect wake words locally. The power switch circuit has its control terminal connected to the general-purpose input / output terminal of the first audio processing unit, and its power channel is connected in series in the power supply path of the second power supply domain. The second audio processing unit is powered by the second power supply domain and has a built-in shared memory controller. A dedicated audio data link is connected between the audio data output interface of the first audio processing unit and the shared memory controller of the second audio processing unit, and is configured to transmit audio data through direct memory access without going through the CPU bus. The first audio processing unit is further configured to: when a wake word is detected, control the power switch circuit to turn on to power on the second power supply domain, and send the collected audio signal to the shared memory area of ​​the second audio processing unit via the dedicated audio data link; And upon receiving a dialogue end signal, control the power switch circuit to turn off to de-energize the second power supply domain.

9. The voice control system according to claim 8, characterized in that, The power switch circuit includes a P-channel MOSFET and a current-limiting resistor. The gate of the P-channel MOSFET is connected to the general-purpose input / output terminal of the first audio processing unit via the current-limiting resistor, the source is connected to the output terminal of the voltage conversion unit, and the drain is connected to the power input node of the second power supply domain.

10. The voice control system according to claim 8, characterized in that, The dedicated audio data link is deployed on the top signal layer of a 4-layer PCB board, with a trace length not exceeding 40 mm. Grounded copper shielding is provided on both sides of the trace, with the grounding layer as the reference plane.

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