Multi-mode step-down conversion circuit and mode switching method thereof

Abstract

The application provides a multi-mode step-down conversion circuit and a mode switching method thereof, and belongs to the technical field of integrated circuits. The circuit comprises a power conversion module, which converts an input voltage into an output voltage according to signals received by high-side and low-side drive ends; a feedback comparison module, which compares the output voltage with a preset reference voltage and generates a pulse modulation signal and a pass-through voltage stabilization signal; a mode control module, which converts the pulse modulation signal into high-side and low-side pulse drive signals and outputs a mode switching signal according to preset circuit operation parameters; and a drive selection module, which selects the high-side pulse drive signal or the pass-through voltage stabilization signal according to the mode switching signal and outputs the signal to the high-side drive end. The mode control module controls the multi-mode step-down conversion circuit to switch between at least multiple modes including a pulse width modulation mode and a low-voltage-difference linear voltage stabilization pass-through mode. The application realizes a step-down conversion scheme that can widen the working voltage range, reduce static power consumption and realize stable mode switching.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a multi-mode buck converter circuit and its mode switching method. Background Technology

[0002] With the rapid proliferation of IoT devices, portable smart terminals, and autonomous systems, power management integrated circuits, as core power supply components, directly determine the system's energy efficiency, reliability, and battery life. Buck DC-DC converters, due to their high efficiency, are widely used in the power management units of various portable devices. However, in practical applications, portable devices typically need to cope with a wide range of input voltage variations and extremely large load current fluctuations.

[0003] Existing buck converters, when faced with battery voltage decay or high duty cycle demands, struggle to achieve smooth operation at high duty cycles due to limitations in the high-side power transistor's drive mechanism and minimum turn-off time. Furthermore, under light load or standby conditions, the control loop and analog module of traditional converters remain active, making it difficult to significantly reduce static power consumption. In addition, existing mode-switching schemes are prone to causing severe fluctuations in output voltage ripple or critical transition instability. Summary of the Invention

[0004] This invention provides a multi-mode buck converter circuit and its mode switching method, which solves the technical problems of limited operating voltage range, high standby power consumption and insufficient mode switching stability of existing buck converter circuits, and realizes a buck converter scheme that can widen the operating voltage range, reduce static power consumption and achieve stable mode switching.

[0005] In a first aspect, the present invention provides a multi-mode buck converter circuit, comprising: The power conversion module is used to convert the input voltage at the power input terminal into the output voltage at the step-down output terminal based on the signals received at its high-side drive terminal and low-side drive terminal. The feedback comparison module is used to compare the output voltage of the buck output terminal with the preset reference voltage and generate a pulse modulation signal and a direct-through regulated signal; The mode control module is connected to the low-side drive terminal of the feedback comparison module and the power conversion module respectively, and is used to convert the pulse modulation signal into a high-side pulse drive signal and a low-side pulse drive signal, and output a mode switching signal according to the preset circuit operating parameters. The drive selection module is connected to the feedback comparison module, the mode control module and the power conversion module respectively, and is used to select the high-side pulse drive signal or the direct-through regulated signal to be output to the high-side drive terminal according to the mode switching signal, and output the low-side pulse drive signal to the low-side drive terminal. The mode control module is used to control the multi-mode buck converter circuit to switch between multiple modes, including at least pulse width modulation mode and low dropout linear regulator pass-through mode. In the low dropout linear regulator pass-through mode, the transistor circuit inside the power conversion module is reused as the low dropout voltage regulation adjustment structure.

[0006] In some embodiments, the power conversion module includes: A high-side controllable switch, the control terminal of which serves as the high-side drive terminal, and the first terminal connected to the power input terminal; A low-side controllable switch, the control terminal of which serves as the low-side drive terminal, the first terminal of which is connected to the second terminal of the high-side controllable switch, and the second terminal connected to the reference ground voltage; The energy storage filter element has its first end connected to the second end of the high-side controllable switch, and its second end connected to the step-down output terminal.

[0007] In some embodiments, the feedback comparison module includes: An impedance network is connected between the step-down output terminal and the reference ground voltage and a feedback node is led out. An error amplifier, whose inverting input is connected to the feedback node and whose non-inverting input is connected to a first preset reference voltage; A pulse modulator, the input of which is connected to the output of the error amplifier, and the output of which outputs the pulse modulation signal to the mode control module; The direct comparator has its non-inverting input connected to the feedback node, its inverting input connected to a second preset reference voltage, and its output terminal outputting the direct-through regulated signal to the drive selection module.

[0008] In some embodiments, it also includes: The sleep management module has a first driving sampling terminal connected to the high-side driving terminal, a second driving sampling terminal connected to the low-side driving terminal, and a control output terminal connected to the mode control module. It is used to output a sleep state signal through the control output terminal when the power conversion module is in an inactive state for a preset time, so as to control the multi-mode buck converter circuit to enter a low-power sleep mode.

[0009] In some embodiments, the hibernation management module includes: The dead-time signal filtering circuit includes a first inverter, a second inverter, a first logic delay component, a second logic delay component, a first OR gate, a second OR gate, a third OR gate, and a fourth OR gate; Wherein, the first driving sampling terminal is connected to the first input terminal of the first OR gate via the first inverter and the first logic delay component, and is connected to the second input terminal of the first OR gate via the first inverter; the second driving sampling terminal is connected to the first input terminal of the second OR gate via the second logic delay component, and is connected to the second input terminal of the second OR gate. The outputs of the first OR gate and the second OR gate are respectively connected to the first and second inputs of the third OR gate. The output of the third OR gate is connected to the first input of the fourth OR gate. The start-up completion signal is connected to the second input of the fourth OR gate via the second inverter. The output of the fourth OR gate outputs an inactivity detection signal.

[0010] In some embodiments, the hibernation management module further includes: The first control switch has its control terminal connected to the control output terminal via a third inverter, and its first terminal connected to the power input terminal. An energy storage capacitor element, the first end of which is connected to the second end of the first control switch, and the second end is connected to a reference ground voltage; The third control switch is connected in parallel across the two ends of the energy storage capacitor element, and the control terminal is connected to the inactive detection signal; The fourth control switch is connected in parallel across the two ends of the energy storage capacitor element; A sleep comparator, whose non-inverting input is connected to the first end of the energy storage capacitor element to form a timing capacitor node, and whose inverting input is connected to a second preset reference voltage; The state latch has its clock input connected to the output of the sleep comparator and the control terminal of the fourth control switch. Its output is inverted and used as the control output. It also includes a set / reset terminal.

[0011] In some embodiments, it also includes: The wake-up management module, whose feedback sampling terminal is electrically connected to the buck output terminal, is used to control the multi-mode buck converter circuit to restart when the voltage drop at the buck output terminal is greater than or equal to a preset ratio.

[0012] In some embodiments, the wake-up management module includes: The self-biased impedance network is composed of multiple series of field-effect transistors connected in a diode-connected structure and operating in the subthreshold region. It is connected across the buck output terminal and the reference ground voltage, and leads out the subthreshold voltage divider node. The wake-up comparator has its non-inverting input terminal electrically connected to the subthreshold voltage divider node, its inverting input terminal connected to the second preset reference voltage, and its output terminal outputting a wake-up reset signal to the set / reset terminal of the hibernation management module.

[0013] In some embodiments, it also includes: The buck enable logic module has multiple AND gate input terminals connected to an external buck enable signal, the control output terminal, and the mode switching signal, respectively, and the output terminal outputs the actual buck enable signal.

[0014] In a second aspect, the present invention also provides a mode switching method for a multi-mode buck converter circuit, executed by the multi-mode buck converter circuit as described in the first aspect, the method comprising: The control voltage reflecting the load current intensity and the duty cycle of the high-side pulse drive signal are obtained; The control voltage and duty cycle are used to control the multi-mode buck converter circuit to switch between multiple modes, including at least pulse width modulation mode and low dropout linear regulator pass-through mode.

[0015] In some embodiments, controlling the multi-mode buck converter circuit to switch between multiple modes, including at least a pulse width modulation mode and a low dropout linear regulator shoot-through mode, based on the control voltage and the duty cycle includes: When the duty cycle is less than a preset duty cycle threshold and the control voltage is greater than a first preset voltage threshold, the mode control module converts the pulse modulation signal into complementary high-side pulse drive signals and low-side pulse drive signals, and outputs an invalid mode switching signal to control the multi-mode buck converter circuit to operate in the pulse width modulation mode. When the duty cycle is greater than or equal to the preset duty cycle threshold, the mode control module outputs the effective mode switching signal and blocks the low-side pulse drive signal to control the multi-mode buck converter circuit to seamlessly switch to the low-dropout linear regulator pass-through mode, and reuses the transistor circuit inside the power conversion module as the low-dropout regulator adjustment structure in the low-dropout linear regulator pass-through mode.

[0016] In some embodiments, it also includes: When the duty cycle is less than a preset duty cycle threshold and the control voltage is less than or equal to a second preset voltage threshold, the mode control module intermittently blocks the high-side pulse drive signal and the low-side pulse drive signal to control the multi-mode buck converter circuit to work in burst mode. Wherein, the first preset voltage threshold is higher than the second preset voltage threshold, so as to form a switching hysteresis window between the pulse width modulation mode and the burst mode.

[0017] In some embodiments, it also includes: When the power conversion module is inactive for a duration exceeding a preset threshold, the multi-mode buck converter circuit is controlled to enter a low-power sleep mode. In the low-power sleep mode, when the output voltage of the buck output terminal drops by more than a preset proportion of the nominal value, the multi-mode buck converter circuit is controlled to restart and resume normal operation.

[0018] This invention achieves efficient integration of buck switching mode and linear shoot-through regulation mode by setting up a drive selection module and using a mode control module for signal path selection, without introducing complex auxiliary drive circuits. In shoot-through mode, the transistor circuit inside the power conversion module is directly reused, significantly widening the circuit's supply voltage adaptability range, improving the energy utilization efficiency of the energy storage device, and ensuring the smoothness of the mode switching process. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced one by one below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the low-dropout linear regulator direct-through mode negative feedback structure in a multi-mode buck converter circuit provided by an embodiment of the present invention; Figure 2 This is a schematic diagram of the sleep management and wake-up detection structure in a multi-mode buck converter circuit provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the dead-time signal filtering structure in a multi-mode buck converter circuit provided in an embodiment of the present invention; Figure 4 This is a schematic flowchart of a mode switching method for a multi-mode buck converter circuit provided in an embodiment of the present invention; Figure 5 This is a logic diagram of a low-dropout linear regulator pass-through mode that supports full duty cycle operation and its seamless switching, provided by an embodiment of the present invention. Figure 6 This is a schematic diagram of the simulation results of seamless switching between pulse width modulation mode and burst mode provided by an embodiment of the present invention; Figure 7 This is a schematic diagram of the simulation results of a low-dropout linear voltage regulation direct-through mode provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of the simulation results of a hibernation and restart function provided in an embodiment of the present invention; Figure 9 This is a static current simulation curve provided by an embodiment of the present invention under different ambient temperatures and input voltages. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0022] With the booming development of the Internet of Things (IoT), the scale of portable and autonomous systems is rapidly expanding, from consumer wearables and smartphones to implantable medical devices and wireless sensor networks. In these ecosystems, power management integrated circuits (Power Management ICs) serve as key enabling devices, directly determining the system's energy efficiency, reliability, and user experience. To meet the demands of miniaturized devices for long battery life and high performance, modern Power Management Units (PMUs) must achieve low quiescent power consumption and high conversion efficiency over a wide input voltage and load range, while maintaining a compact structure for easy integration.

[0023] In existing technologies, buck DC-DC converters typically employ a dual-mode control strategy combining pulse width modulation (PWM) with pulse cycle modulation (PWM) or pulse frequency modulation (PWM). Under heavy load, the system operates in PWM mode to reduce output voltage ripple, while under light load, it switches to PWM or PWM mode to reduce switching losses. However, existing technologies still have significant shortcomings in practical applications. First, the static power consumption under light load conditions needs further reduction. Specifically, after entering PWM mode, although the switching frequency of the power transistors is reduced, most of the internal analog control modules, such as the bandgap reference source, error amplifier, oscillator, and comparator, remain continuously operating or on standby. This mechanism results in the overall static power consumption typically remaining at the microamp level, making it difficult to meet the standby requirements of battery-powered devices for months or even years. Secondly, there is the limitation on the maximum duty cycle of the buck converter circuit. Specifically, in a battery-powered system, as the battery supply voltage and output voltage requirements change, the duty cycle of the buck converter circuit will also change. When the duty cycle is greater than the maximum duty cycle of the buck converter circuit, the circuit will not work properly.

[0024] While existing technologies have attempted to address some of these issues, such as proposing the concept of full duty cycle operation, these often require complex auxiliary circuits or cannot be smoothly integrated with existing control loops. Few solutions can achieve seamless full duty cycle switching while maintaining low power consumption. Consequently, existing buck converter circuit technologies either focus on achieving full duty cycle through complex and energy-intensive circuits such as charge pumps, or employ incomplete sleep strategies to keep error amplifiers or complex digital logic circuits running. This makes it difficult to reduce static power consumption to the nanoampere level. In other words, existing technologies generally lack a comprehensive system-level solution that can achieve low-dropout linear regulation shoot-through mode using low-complexity circuits without the need for additional charge pumps, and can smoothly switch between sleep mode and normal operation mode with low static power consumption.

[0025] To address the aforementioned technical problems, this invention provides a low-power synchronous buck converter circuit with seamless multi-mode switching. This design achieves seamless switching between different modes through logic control. Under heavy load, pulse width modulation (PWM) mode is used. Under light load, the output of the error amplifier is detected, naturally transitioning to pulse cross-cycle modulation mode. A hysteresis window is set to control output ripple and prevent repeated mode switching. A sleep mode is introduced under extremely light load, employing a sleep management circuit based on activity timing monitoring. To ensure rapid recovery performance during load fluctuations, the wake-up logic uses a voltage drop ratio monitoring strategy. When the duty cycle exceeds a set maximum value, a low-dropout linear regulator pass-through mode is entered. This mode reuses the buck converter circuit structure, including the P-channel MOSFET power transistor, feedback network, and output network. Therefore, by using nanoampere-level bias and efficient sleep detection technology, the circuit achieves a low static power consumption of 200 nanoamperes. By adding a low dropout linear regulator pass-through mode, the inherent duty cycle limitation of peak current mode control is overcome, achieving full duty cycle operation. Seamless switching between various modes can be performed, thereby meeting the requirements of IoT devices for high power efficiency, long battery life, and stable reliability.

[0026] This invention provides a multi-mode buck converter circuit. Figure 1 This is a schematic diagram of the low-dropout linear regulator shoot-through mode negative feedback structure in a multi-mode buck converter circuit provided by an embodiment of the present invention. Figure 1 As shown, the multi-mode buck converter circuit includes a power conversion module 1, a feedback comparison module 2, a mode control module Logic, and a drive selection module Mux. The power conversion module 1 is used to select the mode based on its high-side drive terminal S. HS With low-side drive end S LS The received signal converts the input voltage at the power input terminal VDD into a step-down output voltage at the power output terminal V. OUT The output voltage; feedback comparison module 2 is used to compare the buck output terminal V.OUT The output voltage is compared with the preset reference voltage to generate a pulse modulation signal and a direct-through regulated signal ldo-comp; the mode control module Logic is connected to the low-side drive terminal S of the feedback comparison module 2 and the power conversion module 1 respectively. LS The system is used to convert the pulse modulation signal into a high-side pulse drive signal duty_h and a low-side pulse drive signal duty_l, and output a mode switching signal ldo according to preset circuit operating parameters. The drive selection module Mux is connected to the feedback comparison module 2, the mode control module Logic, and the power conversion module 1, and is used to select the high-side pulse drive signal duty_h or the direct-through regulated signal ldo-comp according to the mode switching signal ldo and output it to the high-side drive terminal S. HS The low-side pulse drive signal duty_l is output to the low-side drive terminal S. LS The Logic mode control module controls the switching of the multi-mode buck converter circuit between multiple modes, including at least pulse width modulation mode and low dropout linear regulation pass-through mode. In the low dropout linear regulation pass-through mode, the transistor circuit inside the power conversion module 1 is reused as the low dropout regulation adjustment structure.

[0027] Specifically, a multi-mode buck converter circuit refers to a DC-DC buck power supply hardware circuit capable of switching between multiple operating modes, such as pulse width modulation mode and low dropout linear regulation direct-through mode, based on circuit operating parameters. Power conversion module 1 refers to the module used to receive the high-side drive input S... HS The control signal at the low-side drive terminal converts the voltage at the power input terminal VDD into energy and outputs it to the step-down output terminal V. OUT The main power circuit component that outputs a stable voltage. Feedback comparator module 2 refers to the module used to sample the buck output V. OUT The voltage is compared with a preset reference voltage to generate a first pulse modulation signal and a direct-through regulated signal ldo-comp. The mode control module (Logic) is a hardware logic control unit that processes the first pulse modulation signal into high-side and low-side pulse drive signals duty_l, and outputs a mode switching signal ldo according to preset circuit operating parameters. The drive selection module (Mux) selects either the high-side pulse drive signal duty_h or the direct-through regulated signal ldo-comp based on the mode switching signal ldo and outputs it to the high-side drive terminal S. HS The signal selection switch unit. Low dropout linear regulation direct-through mode refers to the voltage regulation operation state in which the internal transistor of the multiplexed power conversion module 1 works as a linear adjustment tube under conditions of extremely small input-output voltage difference or high duty cycle.

[0028] During circuit operation, feedback comparison module 2 continuously samples the step-down output V. OUTThe output voltage is compared with a preset reference voltage, and a pulse modulation signal and a direct-through regulated signal ldo-comp are output. The mode control module Logic receives the pulse modulation signal and converts it into a high-side pulse drive signal duty_h and a low-side pulse drive signal duty_l. Simultaneously, the mode control module Logic monitors the preset circuit operating parameters in real time. When the parameters meet specific conditions, the mode control module Logic outputs a mode switching signal ldo to the drive selection module Mux. The drive selection module Mux, based on the mode switching signal ldo, selects either the high-side pulse drive signal duty_h or the direct-through regulated signal ldo-comp to output to the high-side drive terminal S of the power conversion module 1. HS The low-side pulse drive signal duty_l is output to the low-side drive terminal. In the low-dropout linear regulator shoot-through mode, the mode control module Logic controls the drive selection module Mux to select the shoot-through regulator signal ldo-comp through the mode switching signal ldo, driving the transistor circuit inside the power conversion module 1 as a low-dropout regulator adjustment structure for linear regulation. For example, the circuit may also include a capacitor C0 and a resistor R, which are used as the output filter capacitor and load resistor, respectively.

[0029] Therefore, this embodiment of the invention achieves efficient integration of buck switching mode and linear pass-through regulation mode by setting a drive selection module Mux and using a mode control module Logic for signal path selection, without introducing complex auxiliary drive circuits. In pass-through mode, the transistor circuit inside the power conversion module 1 is directly reused, which significantly widens the circuit's supply voltage adaptation range, improves the energy utilization efficiency of the energy storage device, and ensures the smoothness of the mode switching process.

[0030] In some embodiments, the power conversion module 1 includes a high-side controllable switch, a low-side controllable switch, and an energy storage filter element L0, with the control terminal of the high-side controllable switch serving as the high-side drive terminal S. HS The first terminal is connected to the power input terminal VDD; the control terminal of the low-side controllable switch serves as the low-side drive terminal S. LS The first terminal is connected to the second terminal of the high-side controllable switch, and the second terminal is connected to the reference ground voltage; the first terminal of the energy storage filter element L0 is connected to the second terminal of the high-side controllable switch, and the second terminal is connected to the step-down output terminal V. OUT .

[0031] Specifically, the high-side controllable switch refers to the switch whose first terminal is connected to the power input terminal VDD and whose control terminal is connected to the high-side drive terminal S. HS A controlled semiconductor switching assembly. A low-side controllable switch refers to a controlled semiconductor switching assembly whose first terminal is connected to the second terminal of a high-side controllable switch, the second terminal is connected to a reference ground voltage, and the control terminal is connected to the low-side drive terminal. An energy storage filter element L0 refers to an element whose first terminal is connected to the common node of the high-side and low-side switches, and whose second terminal is connected to the step-down output terminal V.OUT A filter component used to store and smooth out electrical energy.

[0032] The first terminal of the high-side controllable switch is connected to the power input terminal VDD, and its control terminal is connected to the high-side drive terminal S. HS The first terminal of the low-side controllable switch and the second terminal of the high-side controllable switch are both connected to the internal node. The second terminal is connected to the reference ground voltage, and its control terminal is connected to the low-side drive terminal. The energy storage filter element L0 is connected across the internal node and the step-down output terminal V. OUT During the turn-on process, when the high-side controllable switch is turned on, the power input terminal VDD charges the energy storage filter element L0. When the high-side controllable switch is turned off and the low-side controllable switch is turned on, the energy storage filter element L0 releases energy through the low-side controllable switch, thereby converting the input voltage into a stable step-down output voltage.

[0033] Therefore, the embodiments of the present invention adopt a topology structure in which high-side and low-side dual switches work together, which significantly reduces the conduction loss of the freewheeling path, improves the conversion efficiency, and, together with the energy storage filter element L0, can effectively suppress output ripple and improve the power output quality.

[0034] In some embodiments, the feedback comparison module 2 includes an impedance network, an error amplifier EA, a pulse modulator, and a pass-through comparator, with the impedance network connected to the step-down output V. OUT A feedback node is established between the reference ground voltage and the error amplifier EA; the inverting input of the error amplifier EA is connected to the feedback node, and the non-inverting input is connected to the first preset reference voltage; the input of the pulse modulator is connected to the output of the error amplifier EA, and the output outputs a pulse modulation signal to the mode control module Logic; the non-inverting input of the through comparator is connected to the feedback node, and the inverting input is connected to the second preset reference voltage V. REF The output terminal outputs a direct-through regulated signal ldo-comp to the drive selection module Mux.

[0035] Specifically, the impedance network refers to the network connected across the step-down output terminal V. OUT Between the reference ground voltage and the impedance combination circuit unit used for voltage division sampling of the output voltage, for example, includes a first resistor R1 and a second adjustable resistor R2. The error amplifier EA refers to the amplifier used to amplify the deviation between the feedback node voltage and the first preset reference voltage and output a control voltage V. C The amplifier circuit unit. A pulse modulator refers to a circuit used to modulate the control voltage V. C A modulation circuit unit that converts the signal into a pulse modulation signal. A direct comparator is used to compare the feedback node voltage with a second preset reference voltage V. REF It is a comparator circuit unit that outputs a direct-through regulated voltage signal ldo-comp.

[0036] Step-down output V OUTThe voltage is divided by an impedance network and a sampling voltage is generated at the feedback node. The inverting input of the error amplifier EA receives the feedback node voltage, and the non-inverting input is connected to a first preset reference voltage. After comparison, a control voltage V is generated at the output. C The signal is then fed into a pulse modulator, which converts it into a pulse modulated signal and sends it to the mode control module Logic. The non-inverting input of the pass-through comparator receives the feedback node voltage, while the inverting input is connected to the second preset reference voltage V. REF By comparing the feedback node voltage with the second preset reference voltage V REF The magnitude relationship determines the output of the direct-through regulated signal ldo-comp to the drive selection module Mux.

[0037] Therefore, in this embodiment of the invention, the pulse modulation path and the direct-through voltage regulation comparison path are designed in parallel architecture within the feedback comparison module 2, so that the switching voltage regulation control signal and the direct-through voltage regulation control signal are generated independently, avoiding loop interference during mode switching and improving voltage regulation accuracy and direct-through switching response speed.

[0038] Figure 2 This is a schematic diagram of the sleep management and wake-up detection structure in a multi-mode buck converter circuit provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of the dead-time signal filtering structure in a multi-mode buck converter circuit provided in an embodiment of the present invention. Combined with... Figures 1 to 3 The multi-mode buck converter circuit also includes a sleep management module (Sleep Controller), whose first drive sampling terminal is connected to the high-side drive terminal (S). HS The second driving sampling terminal is connected to the low-side driving terminal, and the control output terminal sd is connected to the mode control module Logic. It is used to output a sleep state signal through the control output terminal sd when the power conversion module 1 is in an inactive state for a preset time, so as to control the multi-mode buck converter circuit to enter the low-power sleep mode.

[0039] Specifically, the Sleep Controller module is a control unit that samples the high-side and low-side drive signals and, when it determines that the power conversion module 1 has been in a continuous inactive state for more than a preset time, controls the output terminal sd to output a sleep state signal to control the circuit to enter a low-power sleep mode.

[0040] The first and second driver sampling terminals of the Sleep Controller module monitor the high-side driver S in real time. HS The signal level changes relative to the low-side drive terminal. When the high-side drive terminal S... HSThe signal from the low-side drive terminal indicates that the power conversion module 1 is continuously in an inactive state of being either non-conducting or off. When the duration of this inactive state reaches the preset duration, the sleep management module Sleep Controller outputs a sleep state signal to the mode control module Logic through its control output terminal sd, thereby controlling the multi-mode buck converter circuit to shut down the main circuit power supply and enter a low-power sleep mode.

[0041] Therefore, by introducing a time-domain monitoring mechanism for the driving state of the power conversion module 1, this embodiment of the invention can accurately identify inactive periods when the system is in a light-load or idle state, and promptly switch to a low-power sleep mode, thereby reducing the static power consumption of the system to an extremely low level and greatly extending the battery life of portable devices in standby mode.

[0042] In some embodiments, the Sleep Controller module includes a dead-time signal filtering circuit, which includes a first inverter A1, a second inverter A2, a first logic delay component A3, a second logic delay component A4, a first OR gate A5, a second OR gate A6, a third OR gate A7, and a fourth OR gate A8. A first drive sampling terminal is connected to the first input terminal of the first OR gate A5 via the first inverter A1 and the first logic delay component A3, and is also connected to the second input terminal of the first OR gate A5 via the first inverter A1. A second drive sampling terminal is connected to the first input terminal of the second OR gate A6 via the second logic delay component A4, and is also connected to the second input terminal of the second OR gate A6. The output terminals of the first OR gate A5 and the second OR gate A6 are respectively connected to the first and second input terminals of the third OR gate A7. The output terminal of the third OR gate A7 is connected to the first input terminal of the fourth OR gate A8. A start-up completion signal Start_ok is connected to the second input terminal of the fourth OR gate A8 via the second inverter A2. The output terminal of the fourth OR gate A8 outputs an inactivity detection signal Sleep.

[0043] Specifically, the dead-zone signal filtering circuit refers to a dead-zone shielding logic unit that uses a combination of inverters, logic delay components, and logic gates to eliminate overlapping pulse interference generated by the high-side and low-side drive signals during dead-zone switching.

[0044] The signal from the first driving sampling terminal is split into two paths after being flipped by the first inverter A1. One path passes through the first logic delay component A3 and is connected to the first input of the first OR gate A5, while the other path is directly connected to the second input of the first OR gate A5. The signal from the second driving sampling terminal is also split into two paths. One path passes through the second logic delay component A4 and is connected to the first input of the second OR gate A6, while the other path is directly connected to the second input of the second OR gate A6. The output signals of the first OR gate A5 and the second OR gate A6 are fed into the third OR gate A7 for logical OR operation. The output of the third OR gate A7 is then ORed with the start_ok signal (flipped by the second inverter A2) in the fourth OR gate A8. Finally, the output of the fourth OR gate A8 outputs the inactivity detection signal Sleep. During this process, the short-duration pulse generated during dead-time switching is shielded by the logic delay components and logic gates.

[0045] Therefore, the embodiments of the present invention effectively filter the transient shutdown signal of the power switch during the normal switching dead time, avoid the false triggering of sleep judgment due to dead time overlap, ensure the accuracy of the inactive detection signal Sleep, and prevent the circuit from falsely entering sleep mode.

[0046] In some embodiments, the Sleep Controller module further includes a first control switch K1, an energy storage capacitor C1, a third control switch K3, a fourth control switch K4, a sleep comparator EC, and a state latch D. The control terminal of the first control switch K1 is connected to the control output terminal sd via a third inverter A9, and the first terminal is connected to the power input terminal VDD. The first terminal of the energy storage capacitor C1 is connected to the second terminal of the first control switch K1, and the second terminal is connected to a reference ground voltage. The third control switch K3 is connected in parallel across the two ends of the energy storage capacitor C1, and its control terminal is connected to the inactivity detection signal Sleep. The fourth control switch K4 is connected in parallel across the two ends of the energy storage capacitor C1. The non-inverting input terminal + of the sleep comparator EC is connected to the first terminal of the energy storage capacitor C1 to form a timing capacitor node V2, and the inverting input terminal - is connected to a second preset reference voltage V. REF The clock input of the state latch D is connected to the output of the sleep comparator EC and the control terminal of the fourth control switch K4. The output is inverted and used as the control output sd. It also includes the set / reset terminal RS.

[0047] Specifically, the first control switch K1 refers to the charging switch assembly connected between the power input terminal VDD and the first terminal of the energy storage capacitor element C1, and controlled by the inverted output signal sd. The energy storage capacitor element C1 refers to the capacitor assembly used to receive charging and construct the timing capacitor node V2 voltage at its first terminal. The third control switch K3 refers to the switch assembly connected in parallel across the energy storage capacitor element C1, controlled by the inactivity detection signal Sleep to clear and discharge the capacitor. The fourth control switch K4 refers to the switch assembly connected in parallel across the energy storage capacitor element C1, controlled by the output of the state latch D. The sleep comparator EC refers to the switch assembly used to compare the timing capacitor node V2 voltage with the second preset reference voltage V. REF The comparison circuit unit. The state latch D refers to the trigger unit used to latch the toggling state of the sleep comparator EC output and hold the sleep state signal at the control output sd.

[0048] When the inactivity detection signal Sleep indicates that the power transistor is inactive, the third control switch K3 is open, and the power input terminal VDD charges the energy storage capacitor C1 through the first control switch K1. The voltage at the timing capacitor node V2 gradually increases over time. The non-inverting input terminal + of the sleep comparator EC monitors the voltage at the timing capacitor node V2 in real time. When this voltage rises above the second preset reference voltage V connected to its inverting input terminal -, REF When the sleep comparator EC outputs a toggle signal, it triggers the state latch D. The state latch D outputs a valid sleep state signal at the control output terminal sd and turns on the fourth control switch K4. The sleep state signal at the control output terminal sd simultaneously acts on the first control switch K1 through the third inverter A9, and the corresponding control signal is sd1.

[0049] Therefore, this embodiment of the invention utilizes a charge / discharge and comparison latch mechanism to construct a precise time-domain timer. The sleep state signal is only triggered when the duration of the inactive state clearly exceeds the preset sleep threshold, thus eliminating the risk of false sleep during the light load pulse-jumping process and ensuring the reliability of circuit operation.

[0050] In some embodiments, the multi-mode buck converter circuit further includes a wake-up management module, a Wake-up Detector, whose feedback sampling terminal is electrically connected to the buck output terminal V. OUT Used at the step-down output V OUT When the voltage drop is greater than or equal to a preset ratio, the multi-mode buck converter circuit is restarted.

[0051] Specifically, the Wake-up Detector module refers to the module used to sample the step-down output V. OUTThe voltage is monitored, and the control circuit restarts to restore the main power supply when the output voltage drops by more than a preset percentage. The feedback sampling terminal of the Wake-up Detector module is directly connected to the step-down output terminal V. OUT Electrical connection, real-time monitoring of the step-down output V OUT The voltage level. When the load suddenly draws current or the output voltage drops due to leakage, the step-down output V... OUT When the voltage drop is greater than or equal to a preset ratio, the Wake-up Detector in the wake-up management module responds quickly, generates a wake-up control command to act on the circuit, forcibly releases the low-power sleep mode and controls the multi-mode buck converter circuit to restart and restore normal regulated output.

[0052] Therefore, the embodiments of the present invention endow the circuit with the ability to respond quickly to load changes under extremely low power standby conditions, avoid system anomalies caused by large drops in output voltage, and ensure the robustness of the system and the reliability of power supply.

[0053] In some embodiments, the wake-up management module Wake-up Detector includes a self-biased impedance network MOS divider and a wake-up comparator ED. The self-biased impedance network MOS divider is composed of multiple series-connected field-effect transistors in a diode-connected structure, operating in the subthreshold region, and is connected across the buck output terminal V. OUT Between the reference ground voltage and the subthreshold voltage divider node V1 is led out; the positive input terminal + of the wake-up comparator ED is electrically connected to the subthreshold voltage divider node V1, and the negative input terminal - is connected to the second preset reference voltage V. REF The output terminal outputs a wake-up reset signal to the set / reset terminal RS of the Sleep Controller module.

[0054] Specifically, the self-biased impedance network MOS divider refers to a high-impedance voltage divider network circuit unit composed of multiple series-connected field-effect transistors operating in the subthreshold region. The wake-up comparator ED is used to compare the voltage at the subthreshold voltage divider node V1 with the second preset reference voltage V. REF It also outputs a wake-up reset signal to the comparison circuit unit of the state latch D set reset terminal RS.

[0055] The self-biased impedance network MOS divider is connected across the buck output terminal V. OUT Between the voltage and the reference ground voltage, the high equivalent impedance of the internal multi-stage diode structure field-effect transistor operating in the subthreshold region limits the quiescent current of the voltage divider branch to an extremely small nanoampere level, and a sampling voltage is drawn from the subthreshold voltage divider node V1. The non-inverting input terminal of the wake-up comparator ED is connected to the subthreshold voltage divider node V1, and the inverting input terminal is connected to the second preset reference voltage V.REF When the step-down output terminal V OUT The voltage drop caused the voltage at the subthreshold voltage divider node V1 to fall below the second preset reference voltage V. REF When the wake-up comparator ED flips, it outputs a wake-up reset signal to the set / reset terminal RS of the state latch D in the Sleep Controller module, forcibly clearing the sleep state signal.

[0056] Therefore, this embodiment of the invention utilizes the small current characteristics of subthreshold field-effect transistors to construct a voltage divider network, which achieves high-sensitivity monitoring of the output voltage while greatly reducing the static power consumption of the wake-up monitoring branch itself. Combined with the wake-up comparator ED, it can realize real-time monitoring of output voltage drops and fast wake-up response.

[0057] In some embodiments, the multi-mode buck converter circuit further includes a buck enable logic module BUCK Enable. The multiple AND gate processing inputs of the buck enable logic module BUCK Enable are respectively connected to an external buck enable signal sell, a control output terminal sd, and a mode switching signal ldo. The output terminal outputs the actual buck enable signal sel.

[0058] Specifically, the buck enable logic module BUCK Enable refers to a combinational logic circuit unit that performs logical operations on the external buck enable signal sell, the sleep control output signal sd, and the mode switching signal ldo, outputting the actual buck enable signal sel. The buck enable logic module BUCK Enable utilizes its internal multi-input AND gates to perform coordinated logical operations on the input external buck enable signal sell, the sleep state signal of the control output sd, and the mode switching signal ldo output by the mode control module Logic. Only when the external enable is valid, the circuit is not in sleep mode, and the mode logic allows, will its output terminal output the valid actual buck enable signal sel to activate the corresponding buck conversion path.

[0059] Therefore, the embodiments of the present invention establish a clear hierarchical enable control logic, ensuring that the system enables the buck converter circuit only when the safety, voltage regulation and mode matching conditions are met, avoiding abnormal mode overlap or untimely false start-up, and improving the working rigor of the overall power management system.

[0060] Figure 4 This is a schematic flowchart illustrating a mode switching method for a multi-mode buck converter circuit provided in an embodiment of the present invention. The mode switching method for the multi-mode buck converter circuit can be executed by the multi-mode buck converter circuit provided in this embodiment of the present invention. Figure 4 As shown, the mode switching method of the multi-mode buck converter circuit includes the following steps: Step 101: Obtain the control voltage reflecting the load current intensity and the duty cycle of the high-side pulse drive signal.

[0061] Step 102: Control the multi-mode buck converter circuit to switch between multiple modes, including at least pulse width modulation mode and low dropout linear regulator shoot-through mode, according to the control voltage and duty cycle.

[0062] Specifically, control voltage V C The voltage signal output by the error amplifier EA in feedback comparison module 2 reflects the current load current intensity. The duty cycle is the ratio of the on-time of the high-side pulse drive signal duty_h in a single cycle to the total cycle, reflecting the voltage difference between the power input VDD and the buck output V. OUT The voltage difference between voltages.

[0063] During operation, the multi-mode buck converter circuit first acquires the control voltage V generated by the feedback comparison module 2. C And the duty cycle of the high-side pulse drive signal duty_h. The mode control module Logic will control the voltage V. C The load strength threshold is compared with the preset load strength threshold, and the duty cycle is compared with the preset differential voltage threshold. Based on the combined judgment of these two parameters, the Logic mode control module outputs control commands to control the multi-mode buck converter circuit to seamlessly switch between multiple modes, including at least pulse width modulation mode and low dropout linear regulator shoot-through mode.

[0064] Therefore, this embodiment of the invention realizes a mode switching control mechanism based on dual-dimensional sensing of load current and input-output voltage difference, enabling the circuit to automatically select the matching operating mode according to real-time operating conditions, taking into account both the voltage regulation accuracy under heavy load and the conversion efficiency under high duty cycle.

[0065] In some embodiments, based on the control voltage V C The duty cycle-controlled multi-mode buck converter circuit switches between multiple modes, including at least pulse width modulation mode and low dropout linear regulator shoot-through mode, including: when the duty cycle is less than a preset duty cycle threshold and the control voltage V CWhen the voltage exceeds the first preset threshold, the mode control module Logic converts the pulse modulation signal into complementary high-side pulse drive signal duty_h and low-side pulse drive signal duty_l, and outputs an invalid mode switching signal ldo to control the multi-mode buck converter circuit to operate in pulse width modulation mode. When the duty cycle is greater than or equal to the preset duty cycle threshold, the mode control module Logic outputs an valid mode switching signal ldo and blocks the low-side pulse drive signal duty_l to control the multi-mode buck converter circuit to seamlessly switch to low dropout linear regulator pass-through mode, and reuses the transistor circuit inside the power conversion module 1 as the low dropout regulator adjustment structure in the low dropout linear regulator pass-through mode.

[0066] Specifically, the preset duty cycle threshold refers to the duty cycle threshold used to determine whether the circuit has entered the shoot-through mode. The first preset voltage threshold refers to the control voltage V used to determine whether the circuit is in a medium-heavy load state. C Threshold. When the duty cycle is detected to be less than the preset duty cycle threshold and the control voltage V... C When the voltage exceeds the first preset threshold, it indicates that the system is under medium to heavy load and the input-output voltage difference is within the normal step-down range. The mode control module Logic converts the pulse modulation signal into complementary high-side pulse drive signal duty_h and low-side pulse drive signal duty_l, and simultaneously outputs an invalid mode switching signal ldo, with the control circuit operating in pulse width modulation mode. When the duty cycle is detected to be greater than or equal to the preset duty cycle threshold, it indicates that the input voltage is close to the output voltage. The mode control module Logic outputs an valid mode switching signal ldo and blocks the low-side pulse drive signal duty_l, controlling the multi-mode buck converter circuit to seamlessly switch to low-dropout linear regulation shoot-through mode. In this mode, the transistor circuit inside the power conversion module 1 is reused as the low-dropout regulation adjustment structure.

[0067] Therefore, the embodiments of the present invention supplement the switching action and tube control details between pulse width modulation mode and low dropout linear regulator shoot-through mode. By blocking the low-side drive signal and utilizing the parasitic diode freewheeling in shoot-through mode, unnecessary switching losses of the low-side switch are eliminated, ensuring stable system operation under high duty cycle.

[0068] In some embodiments, the mode switching method of the multi-mode buck converter circuit further includes: when the duty cycle is less than a preset duty cycle threshold and the control voltage V C When the voltage is less than or equal to the second preset voltage threshold, the mode control module Logic intermittently blocks the high-side pulse drive signal duty_h and the low-side pulse drive signal duty_l to control the multi-mode buck converter circuit to operate in burst mode; wherein, the first preset voltage threshold is higher than the second preset voltage threshold to form a switching hysteresis window between pulse width modulation mode and burst mode.

[0069] Specifically, the second preset voltage threshold refers to the control voltage V, which is lower than the first preset voltage threshold and is used to determine whether the circuit has entered a light-load state. C Threshold. The switching hysteresis window refers to the voltage difference range between the first preset voltage threshold and the second preset voltage threshold, used to prevent the mode from frequently switching at the critical point.

[0070] When the duty cycle is less than the preset duty cycle threshold, and the control voltage V C When the voltage drops further to less than or equal to the second preset voltage threshold, it indicates that the load current is extremely small. The Logic mode control module then activates burst mode control, intermittently blocking the high-side pulse drive signal duty_h and the low-side pulse drive signal duty_l, thus reducing the switching frequency. When the load increases, causing the control voltage V... C When the voltage rises again and exceeds the first preset voltage threshold which is higher than the second preset voltage threshold, the circuit switches back to pulse width modulation mode, suppressing critical oscillations through the switching hysteresis window formed by the first preset voltage threshold and the second preset voltage threshold.

[0071] Therefore, the embodiments of the present invention introduce burst mode and switching hysteresis window, which reduces switching losses under light load conditions, improves conversion efficiency across the entire load range, and avoids repeated and frequent mode switching at critical loads, thus ensuring stable output voltage.

[0072] In some embodiments, the mode switching method of the multi-mode buck converter circuit further includes: when the power conversion module 1 is inactive for a duration longer than a preset threshold, controlling the multi-mode buck converter circuit to enter a low-power sleep mode; in the low-power sleep mode, when the buck output terminal V OUT When the output voltage drops by more than a preset percentage of the nominal value, the multi-mode buck converter circuit is restarted to resume normal operation.

[0073] Specifically, the inactive state refers to a state where both the high-side and low-side controllable switches are in a cut-off, non-switching state. During circuit operation, the dead-time signal filtering circuit samples the drive terminal signal, filters the dead-time pulse, and outputs an inactive detection signal (Sleep). When the power conversion module 1 remains in the cut-off state for a duration exceeding a preset threshold, the multi-mode buck converter circuit is controlled to enter a low-power sleep mode. In this sleep mode, the wake-up management module (Wake-up Detector) continuously monitors the buck output terminal V. OUT Voltage, once stepped down, output terminal V OUT If the output voltage drops by a preset percentage greater than the nominal value, the multi-mode buck converter circuit will quickly restart and resume normal operation.

[0074] Therefore, the embodiments of the present invention refine the control logic from inactivity state detection, timeout sleep determination to undervoltage trigger restart, ensuring that the circuit can enter low power standby when under very light load or idle, and can be woken up and restarted in time when the load resumes current extraction, thus realizing intelligent energy efficiency management.

[0075] Figure 5 This is a logic diagram illustrating a low-dropout linear regulator direct-through mode supporting full duty cycle operation and its seamless switching, provided by an embodiment of the present invention. Figure 5 The diagram illustrates the control logic relationships from the power input terminal VDD, for example, an input voltage Vin ranging from 2.3V to 4.2V, after being connected to the soft-start unit, entering three parallel steady-state operating paths. Each path corresponds to an operating time T greater than a preset time, for example, greater than 900µs, with a corresponding control voltage V. C When the voltage is less than the first preset voltage threshold, for example, 450mV, and the duty cycle of the high-side pulse drive signal duty_h is less than the preset duty cycle threshold, for example, 80%, the circuit enters burst mode. Path two corresponds to a running time T greater than a preset time, for example, greater than 900µs, and the control voltage V... C When the voltage exceeds the first preset threshold (e.g., 500mV) and the duty cycle is less than the preset duty cycle threshold (e.g., 80%), the circuit enters pulse width modulation (PWM) mode. For path three, when the running time T exceeds the preset time (e.g., greater than 900µs), the pass-through mode enable signal is active (ldo_start=1), and the duty cycle is greater than the preset duty cycle threshold (e.g., 80%), the circuit enters low-dropout linear regulator (LDO) mode.

[0076] Furthermore, when the high-side controllable switch control signal and the low-side controllable switch control signal remain in the same off state, for example, when the high-side drive signal is 1 and the low-side drive signal is 0, the power transistors are all turned off, and the sampling signal is put into sleep mode. Figure 5 When the signal slp in the circuit is 1 and the duration T1 exceeds the preset sleep time, such as 100us, the circuit switches to low-power sleep mode. In low-power sleep mode, when the buck output V... OUT Voltage drop amplitude ΔV OUT Greater than the preset ratio, for example, the step-down output V OUT When the voltage drop exceeds 10% of the nominal value, a restart logic is triggered to wake up the circuit. Figure 5 Restart in the middle.

[0077] In summary, as Figure 5 As shown, in order to optimize energy efficiency and broaden the output voltage range across the entire load range, the control voltage V is monitored in real time.C And the duty cycle, thus realizing three parallel steady-state operating paths. When the control voltage V is monitored... C When the load is less than the first preset voltage threshold and the duty cycle is less than the preset duty cycle threshold, the system determines that the load demand is low and enters burst mode, reducing switching losses by decreasing the switching frequency. As the load gradually increases, causing the control voltage V to... C When the voltage exceeds the second preset threshold, the system automatically and seamlessly switches to pulse width modulation mode to provide better voltage regulation accuracy and dynamic response characteristics. When the duty cycle is greater than or equal to the preset duty cycle threshold and the shoot-through mode enable signal is active high, the circuit enters the low dropout linear regulator shoot-through mode.

[0078] The following are specific examples. Figures 1 to 3 The structure shown and its working principle are described in detail: like Figure 1 The negative feedback path of the low-dropout linear regulator in shoot-through mode is illustrated. The core feature of this architecture lies in the high degree of topology multiplexing between the two operating modes. In shoot-through mode, the high-side controllable switch, such as a high-side P-channel MOSFET, operates as the regulating power transistor of the low-dropout linear regulator, while the energy storage filter element L0, such as an energy storage inductor, is equivalent to a low-impedance DC link. Simultaneously, the low-side controllable switch, such as a low-side N-channel MOSFET, remains off to eliminate unnecessary switching losses. The system employs a drive selection module (Mux), such as a multiplexer, to determine the drive source of the high-side controllable switch, allowing it to operate within pulse-width modulation logic and... Figure 1 The low-dropout linear regulator feedback loop is marked with a dashed line. The low-dropout linear regulator feedback loop monitors the feedback voltage via a shoot-through comparator, such as a hysteresis comparator, to control the high-side controllable switch. It also reuses the drive circuit of the P-channel MOSFET, keeping the high-side controllable switch on throughout its full duty cycle. The low-dropout linear regulator mode employs a quasi-static regulation mechanism. When the high-side controllable switch is off, the parasitic diode of the low-side controllable switch freewheels, ensuring the continuity of the inductor current. This mode not only ensures system stability but also reduces the shoot-through voltage drop, widening the range of output voltage that can be provided.

[0079] like Figure 3The low static power consumption sleep management architecture and its wake-up shown in the buck converter circuit introduce a dead time to prevent current shoot-through between the high-side and low-side switches. At the same time, to avoid the high-side controllable switch and the low-side controllable switch being in the off state during the dead time and being mistakenly judged as a load idle signal, dead time signal filtering is implemented. For example, dead time shielding logic effectively filters the synchronous turn-off pulse at the moment of switch switching by sampling the first drive sampling terminal signal and the second drive sampling terminal signal and combining the first logic delay component A3 and the second logic delay component A4.

[0080] like Figure 2 The sleep and wake-up management shown herein, after the soft-start process, if the logic circuit detects that the power conversion module 1 remains inactive, it will generate a valid inactivity detection signal, Sleep. This signal then triggers the timing logic in the Sleep Controller module, charging the energy storage capacitor C1 through a low-power constant current source, such as a 10nA low-power current source. Only when the power transistor's off-time exceeds the preset sleep duration, such as 150µs, i.e., the voltage at the timing capacitor node V2 reaches the second preset reference voltage V... REF The state latch D, such as the data trigger, will be set and generate a sleep state signal at the control output sd, thereby ensuring that the system will not mistakenly enter the sleep state due to normal light load pulses and mode switching operations.

[0081] To reduce the static power consumption of the output monitoring circuit, a wake-up detection scheme based on an ultra-high impedance metal-oxide-semiconductor voltage divider is adopted. Traditional resistor-based voltage divider networks exhibit significant static leakage current in nanoampere applications. Therefore, this circuit utilizes a self-biased impedance network, a MOS divider, such as a voltage divider chain composed of multiple diode-connected field-effect transistors (FETs) operating in the subthreshold region. These FETs operate in the subthreshold region, and their extremely high equivalent impedance limits the current in the voltage divider branches to the nanoampere level. This self-biased impedance network, the MOS divider, steps down the output voltage V... OUT Voltage changes are fed back to the wake-up comparator ED in real time, such as a low-power comparator. Once the load resumes pumping current, it causes a step-down output V. OUTIf the voltage drop exceeds a preset percentage of the nominal value, such as 10%, the wake-up comparator ED will output a wake-up reset signal to the set / reset terminal RS of the state latch D, forcibly clearing the sleep state signal and triggering a system restart. Finally, the system uses the buck enable logic module BUCK Enable, for example, an AND gate circuit to perform a logical operation on the external buck enable signal sell, the control output sd sleep state signal, and the mode switching signal ldo. The low-dropout linear regulation mode has higher priority than the buck mode, and the actual buck enable signal sel is output as the actual enable signal for the buck mode. Similarly, the control output sd sleep state signal and the pass-through mode enable signal are ANDed to serve as the actual enable signal for the low-dropout linear regulation mode.

[0082] In sleep mode, the circuit retains only the reference voltage modules, such as the bandgap reference source and the wake-up comparator ED. Both modules use a dedicated nano-ampere bias circuit for sleep mode to achieve a quiescent current of, for example, 200nA. During restart, this nano-ampere current is used to accelerate the startup of the micro-ampere bias circuit for a rapid circuit restart, preventing the buck output V from being degraded. OUT The voltage drops further, and this hierarchical control strategy ensures that the system only activates buck or direct regulation when all safety and voltage regulation conditions are met, thereby extending the standby life of portable IoT devices while achieving intelligent energy efficiency management.

[0083] In summary, the ultra-low power multi-mode buck converter circuit for IoT applications provided in this invention aims to achieve low static power consumption and high conversion efficiency over a wide input voltage and load range. By supporting a low-dropout linear regulator pass-through mode with full duty cycle operation and its seamless switching scheme, it addresses the limitations of traditional buck converter circuits, which are constrained by minimum turn-off time and subharmonic oscillation risks, making it difficult to achieve high duty cycle operation. A multi-mode control strategy integrating the low-dropout linear regulator pass-through mode is designed, enabling high or full duty cycle operation, broadening the system's operating input voltage range, and improving the discharge depth and energy utilization of the energy storage device. Furthermore, combined with a low static power consumption sleep management architecture and its wake-up scheme, it addresses the problem of excessive static energy consumption caused by IoT devices being in standby mode for extended periods. A sleep and wake-up power management mechanism based on activity time awareness is designed, ensuring transient response and output voltage accuracy while controlling the overall system static power consumption to the nanoampere level, thus extending the battery life of portable IoT devices.

[0084] Figure 6 This is a schematic diagram of the simulation results of seamless switching between pulse width modulation mode and burst mode provided by an embodiment of the present invention. Figure 6 The horizontal axis represents time, and the vertical axis, from top to bottom, includes the step-down output V. OUT The voltage and the control voltage V at the output of the error amplifier EA.C Load current I load And the current of the energy storage filter element L0, such as the inductor current I. L Step-down output V OUT The overall voltage ripple amplitude remains within approximately 6mV, and the load current varies between 10mA and 200mA according to a preset variation period T. f For example, the change is made every 0.5ms. Figure 6 The document also demonstrates the smooth and seamless transition of the circuit from pulse width modulation mode to burst mode at 1.4ms, and from burst mode back to pulse width modulation mode at 1.61ms. Additionally, Figure 6 For the inductor current I under burst mode L The waveform has been magnified in a local area. The magnified schematic diagram clearly shows the pulse group jump and low-frequency ripple characteristics of the L0 current of the energy storage filter element under burst mode.

[0085] Figure 7 This is a schematic diagram of the simulation results of a low-dropout linear voltage regulation direct-through mode provided in an embodiment of the present invention. Figure 7 The horizontal axis represents time, and the vertical axis, from top to bottom, includes the step-down output V. OUT The voltage of the direct-through regulated signal ldo-comp, and the control voltage V C The current of the energy storage filter element L0, such as the inductor current I. L The input voltage divider Va, the output voltage divider Vb, the voltage of the mode switching signal ldo, and the voltage of the pass-through mode enable signal ldo_start. The buck output V... OUT The voltage waveform, the buck output V during mode transition. OUT Voltage drop amplitude ΔV OUT It is approximately 35mV. Figure 7 The diagram shows that around 775µs, when the input voltage division Va equals the output voltage division Vb (i.e., the duty cycle is 80%), the mode switching signal ldo undergoes a level jump, and the circuit smoothly and seamlessly transitions from pulse width modulation mode to low dropout linear regulator shoot-through mode.

[0086] Figure 8 This is a schematic diagram of the simulation results of a hibernation and restart function provided in an embodiment of the present invention. Figure 8 The horizontal axis represents time, and the parameters on the vertical axis can be referenced in the aforementioned embodiment. Additionally, I... IN This is the input quiescent current. Figure 8 The circuit demonstrates that it enters the sleep detection phase at 1ms, and the voltage at the timing capacitor node V2 reaches the second preset reference voltage V at 1.09ms. REFIt then switches to low-power sleep mode, and at the 1.21ms subthreshold voltage divider node V1, the sampled voltage drops to the second preset reference voltage V. REF The waveform relationship of the wake-up restart triggered by the time.

[0087] Figure 9 This is a static current simulation curve provided by an embodiment of the present invention under different ambient temperatures and input voltages. Figure 9 The horizontal axis represents the voltage V at the power input terminal VDD. IN The vertical axis represents the static current I in the circuit. Q Test settings for step-down output V OUT The voltage is 1.5V. Figure 9 Includes three different ambient temperatures T A The simulation curves show that the circuit maintains a static current consumption in the nanoampere to submicroampere range across the entire operating voltage and wide temperature range.

[0088] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A multi-mode buck converter circuit, characterized in that, include: The power conversion module is used to convert the input voltage at the power input terminal into the output voltage at the step-down output terminal based on the signals received at its high-side drive terminal and low-side drive terminal. The feedback comparison module is used to compare the output voltage of the buck output terminal with the preset reference voltage and generate a pulse modulation signal and a direct-through regulated signal; The mode control module is connected to the low-side drive terminal of the feedback comparison module and the power conversion module respectively, and is used to convert the pulse modulation signal into a high-side pulse drive signal and a low-side pulse drive signal, and output a mode switching signal according to the preset circuit operating parameters. The drive selection module is connected to the feedback comparison module, the mode control module and the power conversion module respectively, and is used to select the high-side pulse drive signal or the direct-through regulated signal to be output to the high-side drive terminal according to the mode switching signal, and output the low-side pulse drive signal to the low-side drive terminal. The mode control module is used to control the multi-mode buck converter circuit to switch between multiple modes, including at least pulse width modulation mode and low dropout linear regulator pass-through mode. In the low dropout linear regulator pass-through mode, the transistor circuit inside the power conversion module is reused as the low dropout voltage regulation adjustment structure.

2. The multi-mode buck converter circuit according to claim 1, characterized in that, The power conversion module includes: A high-side controllable switch, the control terminal of which serves as the high-side drive terminal, and the first terminal connected to the power input terminal; A low-side controllable switch, the control terminal of which serves as the low-side drive terminal, the first terminal of which is connected to the second terminal of the high-side controllable switch, and the second terminal connected to the reference ground voltage; The energy storage filter element has its first end connected to the second end of the high-side controllable switch, and its second end connected to the step-down output terminal.

3. The multi-mode buck converter circuit according to claim 2, characterized in that, The feedback comparison module includes: An impedance network is connected between the step-down output terminal and the reference ground voltage and a feedback node is led out. An error amplifier, whose inverting input is connected to the feedback node and whose non-inverting input is connected to a first preset reference voltage; A pulse modulator, the input of which is connected to the output of the error amplifier, and the output of which outputs the pulse modulation signal to the mode control module; The direct comparator has its non-inverting input connected to the feedback node, its inverting input connected to a second preset reference voltage, and its output terminal outputting the direct-through regulated signal to the drive selection module.

4. The multi-mode buck converter circuit according to any one of claims 1-3, characterized in that, Also includes: The sleep management module has a first driving sampling terminal connected to the high-side driving terminal, a second driving sampling terminal connected to the low-side driving terminal, and a control output terminal connected to the mode control module. It is used to output a sleep state signal through the control output terminal when the power conversion module is in an inactive state for a preset time, so as to control the multi-mode buck converter circuit to enter a low-power sleep mode.

5. The multi-mode buck converter circuit according to claim 4, characterized in that, The hibernation management module includes: The dead-time signal filtering circuit includes a first inverter, a second inverter, a first logic delay component, a second logic delay component, a first OR gate, a second OR gate, a third OR gate, and a fourth OR gate; Wherein, the first driving sampling terminal is connected to the first input terminal of the first OR gate via the first inverter and the first logic delay component, and is connected to the second input terminal of the first OR gate via the first inverter; the second driving sampling terminal is connected to the first input terminal of the second OR gate via the second logic delay component, and is connected to the second input terminal of the second OR gate. The outputs of the first OR gate and the second OR gate are respectively connected to the first and second inputs of the third OR gate. The output of the third OR gate is connected to the first input of the fourth OR gate. The start-up completion signal is connected to the second input of the fourth OR gate via the second inverter. The output of the fourth OR gate outputs an inactivity detection signal.

6. The multi-mode buck converter circuit according to claim 5, characterized in that, The hibernation management module also includes: The first control switch has its control terminal connected to the control output terminal via a third inverter, and its first terminal connected to the power input terminal. An energy storage capacitor element, the first end of which is connected to the second end of the first control switch, and the second end is connected to a reference ground voltage; The third control switch is connected in parallel across the two ends of the energy storage capacitor element, and the control terminal is connected to the inactive detection signal; The fourth control switch is connected in parallel across the two ends of the energy storage capacitor element; A sleep comparator, whose non-inverting input is connected to the first end of the energy storage capacitor element to form a timing capacitor node, and whose inverting input is connected to a second preset reference voltage; The state latch has its clock input connected to the output of the sleep comparator and the control terminal of the fourth control switch. Its output is inverted and used as the control output. It also includes a set / reset terminal.

7. The multi-mode buck converter circuit according to claim 4, characterized in that, Also includes: The wake-up management module, whose feedback sampling terminal is electrically connected to the buck output terminal, is used to control the multi-mode buck converter circuit to restart when the voltage drop at the buck output terminal is greater than or equal to a preset ratio.

8. The multi-mode buck converter circuit according to claim 7, characterized in that, The wake-up management module includes: The self-biased impedance network is composed of multiple series of field-effect transistors connected in a diode-connected structure and operating in the subthreshold region. It is connected across the buck output terminal and the reference ground voltage, and leads out the subthreshold voltage divider node. The wake-up comparator has its non-inverting input terminal electrically connected to the subthreshold voltage divider node, its inverting input terminal connected to the second preset reference voltage, and its output terminal outputting a wake-up reset signal to the set / reset terminal of the hibernation management module.

9. The multi-mode buck converter circuit according to claim 4, characterized in that, Also includes: The buck enable logic module has multiple AND gate input terminals connected to an external buck enable signal, the control output terminal, and the mode switching signal, respectively, and the output terminal outputs the actual buck enable signal.

10. A mode switching method for a multi-mode buck converter circuit, characterized in that, Performed by the multi-mode buck converter circuit as described in any one of claims 1-9, the method includes: The control voltage reflecting the load current intensity and the duty cycle of the high-side pulse drive signal are obtained; The control voltage and duty cycle are used to control the multi-mode buck converter circuit to switch between multiple modes, including at least pulse width modulation mode and low dropout linear regulator pass-through mode.

11. The mode switching method for the multi-mode buck converter circuit according to claim 10, characterized in that, Controlling the multi-mode buck converter circuit to switch between multiple modes, including at least pulse width modulation mode and low dropout linear regulator shoot-through mode, based on the control voltage and the duty cycle, includes: When the duty cycle is less than a preset duty cycle threshold and the control voltage is greater than a first preset voltage threshold, the mode control module converts the pulse modulation signal into complementary high-side pulse drive signals and low-side pulse drive signals, and outputs an invalid mode switching signal to control the multi-mode buck converter circuit to operate in the pulse width modulation mode. When the duty cycle is greater than or equal to the preset duty cycle threshold, the mode control module outputs the effective mode switching signal and blocks the low-side pulse drive signal to control the multi-mode buck converter circuit to seamlessly switch to the low-dropout linear regulator pass-through mode, and reuses the transistor circuit inside the power conversion module as the low-dropout regulator adjustment structure in the low-dropout linear regulator pass-through mode.

12. The mode switching method for the multi-mode buck converter circuit according to claim 11, characterized in that, Also includes: When the duty cycle is less than a preset duty cycle threshold and the control voltage is less than or equal to a second preset voltage threshold, the mode control module intermittently blocks the high-side pulse drive signal and the low-side pulse drive signal to control the multi-mode buck converter circuit to work in burst mode. Wherein, the first preset voltage threshold is higher than the second preset voltage threshold, so as to form a switching hysteresis window between the pulse width modulation mode and the burst mode.

13. The mode switching method for the multi-mode buck converter circuit according to any one of claims 10-12, characterized in that, Also includes: When the power conversion module is inactive for a duration exceeding a preset threshold, the multi-mode buck converter circuit is controlled to enter a low-power sleep mode. In the low-power sleep mode, when the output voltage of the buck output terminal drops by more than a preset proportion of the nominal value, the multi-mode buck converter circuit is controlled to restart and resume normal operation.

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