Multi-mode high-speed parallel digital modulation method and related products

Abstract

The application relates to the field of digital communication signal processing, and provides a multi-mode high-speed parallel digital modulation method and related products.The method comprises the following steps: dynamically mapping M parallel bit streams into complex symbols based on a unified constellation mapping table and configuration parameters in a reconfigurable storage array; generating symbol injection control information and a reference fractional interval based on phase accumulation in each parallel clock cycle, and injecting a parallel polyphase forming filter output reference grid sample; determining a target fractional delay based on the reference fractional interval and a channel index, and performing phase correction on the reference grid sample to generate a baseband signal; and performing quadrature up-conversion processing on the baseband signal and converting the baseband signal into a serial data stream for output. The application realizes continuous and accurate symbol rate adjustment and multi-system flexible switching under a fixed sampling rate.

Description

Technical Field

[0001] This invention relates to the field of digital communication signal processing, and provides a multi-mode high-speed parallel digital modulation method and related products. Background Technology

[0002] In high-speed digital modulator design, to meet the service requirements of high code rates, multiple modes, and continuously variable rates, a parallel processing architecture is typically adopted to reduce the internal logic clock frequency of the FPGA, thereby satisfying timing convergence requirements. However, existing solutions often rely on integer multiple interpolation or changes to the digital-to-analog converter sampling clock to achieve continuous symbol rate adjustment, resulting in a limited symbol rate adjustment range and coarse steps, making it difficult to achieve continuous and fine adjustment over a wide range at a fixed sampling rate. Furthermore, existing fractional resampling techniques lack deep integration with parallel modulation architectures, and when supporting multiple modulation schemes (especially non-uniform constellations), they typically require independent hardware paths or complex low-level code modifications, leading to high hardware resource overhead, slow mode switching speed, and poor scalability.

[0003] Therefore, there is an urgent need for a high-speed parallel digital modulation scheme that can achieve continuous and precise adjustment of arbitrary symbol rate under a fixed clock domain and support efficient and flexible switching of multiple modes. Summary of the Invention

[0004] To address the challenges of simultaneously achieving continuous symbol rate adjustment and timing convergence in parallel architectures, as well as the fragmentation of hardware resources for multi-mode modulation, this invention utilizes a multi-mode high-speed parallel digital modulation method, apparatus, and device to achieve continuous and precise adjustment of arbitrary symbol rate and flexible switching between multiple modes under a fixed reference sampling rate.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] A multi-mode high-speed parallel digital modulation method includes: Step S1: Based on a unified constellation mapping table and configuration parameters in a reconfigurable memory array, dynamically map M parallel bit streams to M parallel complex symbols, where M is an integer greater than 1; Step S2: In each parallel clock cycle, generate symbol injection control information and a reference fraction interval based on phase accumulation, and inject the corresponding number of the complex symbols into a parallel multiphase shaping filter designed based on a fixed reference sampling rate, outputting M parallel reference grid samples; Step S3: Based on the reference fraction interval and channel index, determine the target fractional delay of each output channel, perform phase correction on the M parallel reference grid samples, and generate M parallel baseband signals; Step S4: Perform orthogonal up-conversion processing on the M parallel baseband signals and convert them into serial data stream output.

[0007] The above scheme decouples the variable rate problem into two independent processes: fixed reference filtering and fractional delay correction. This allows the parallel multiphase shaping filter to be designed and optimized based on a fixed reference sampling rate, avoiding the timing pressure and resource consumption caused by dynamically adjusting the filter coefficients or order with changes in symbol rate. At the same time, by using the symbol injection control information generated by phase accumulation and the reference fractional interval, a precise mapping from the variable symbol rate to the fixed parallel clock domain is achieved. Combined with the channel index to calculate the target fractional delay of each channel, the coordination and accuracy of phase correction under the parallel architecture are guaranteed. Thus, continuous stepless adjustment of the symbol rate is achieved while reducing hardware complexity.

[0008] Further, in step S2, generating symbol injection control information and a reference fraction interval based on phase accumulation in each parallel clock cycle includes: determining an accumulation step size based on the ratio of the target symbol rate to the fixed reference sampling rate; increasing the current phase accumulation value by the accumulation step size in each parallel clock cycle; determining the symbol injection control information based on the integer part of the increased current value, wherein the symbol injection control information represents the number of complex symbols to be injected in the current cycle; and determining the reference fraction interval based on the fractional part of the increased current value.

[0009] This invention controls the number of symbols injected by using the integer overflow mechanism of the phase accumulator and uses the fractional part as a precise measure of time offset. It transforms continuous symbol rate changes into deterministic control logic in the discrete clock domain, ensuring that the average rate of symbol injection under a fixed parallel clock is strictly equal to the target symbol rate and eliminating accumulated errors.

[0010] Further, in step S3, determining the target fractional delay of each output channel based on the reference fractional interval and channel index, and performing phase correction on the M parallel reference grid samples, includes: for each target channel among the M output channels, superimposing the reference fractional interval with the phase offset corresponding to the channel index of the target channel and taking the modulus to obtain the target fractional delay of the target channel; and performing polynomial interpolation calculation on the continuous M parallel reference grid samples based on the target fractional delay to obtain the corrected baseband samples.

[0011] This invention establishes a mathematical relationship between the fractional delay values ​​of each parallel channel. Only a baseline fractional interval needs to be maintained to derive the accurate delay value of all channels through simple addition and modulo operations. This avoids the huge storage overhead and computational latency caused by storing or calculating the delay value independently for each sample point, and significantly improves the efficiency and synchronization of parallel processing.

[0012] Further, in step S1, the step of dynamically mapping M parallel bitstreams to M parallel complex symbols based on the unified constellation mapping table and configuration parameters in the reconfigurable storage array includes: updating the unified constellation mapping table and configuration parameters in the reconfigurable storage array in response to receiving a modulation scheme switching instruction; when the modulation scheme switching instruction indicates a switch to a non-uniform constellation modulation scheme, adjusting the distribution position of constellation points based on the geometric configuration parameters in the configuration parameters, wherein the geometric configuration parameters include at least one of ring radius ratio or phase offset; and mapping the M parallel bitstreams to the corresponding complex symbols based on the updated unified constellation mapping table and the adjusted distribution positions.

[0013] This invention supports the dynamic generation and adjustment of non-uniform constellations through a parameterized configuration mechanism, enabling the same set of hardware mapping logic to adapt to multiple modulation schemes and their geometric parameters for online optimization. It eliminates the need to reserve independent hardware paths for each modulation scheme, significantly improving the reuse rate of hardware resources and the system's ability to expand to new modulation schemes.

[0014] In step S1, the phase accumulation adopts a fixed-point number format. The step of determining the symbol injection control information based on the integer part of the increased current value and determining the reference fraction interval based on the fractional part of the increased current value includes: representing the current value as a fixed-point number containing integer and fractional digits; the accumulation step size is calculated by multiplying the ratio of the target symbol rate to the fixed reference sampling rate by 2 to the power of W, where W is the bit width of the fractional digits; when the increased current value is greater than or equal to 2 to the power of W, an overflow is triggered, and the number of overflows is used as the symbol injection control information; the result of taking the modulo of the increased current value with 2 to the power of W is used as the updated current value, and the value obtained by dividing the updated current value by 2 to the power of W is used as the reference fraction interval; for each complex symbol injected in the current period, its corresponding initial fraction interval is obtained by subtracting the product of the symbol number and the accumulation step size from the reference fraction interval and taking the modulo.

[0015] This invention provides specific fixed-point implementation details for phase accumulation control, clarifies the mathematical logic of overflow handling and fractional interval decrement calculation, ensures the accuracy of symbol injection timing and fractional delay value in digital circuit implementation, and provides underlying algorithm support for high-precision symbol rate adjustment.

[0016] In step S1, the polynomial interpolation calculation based on the target fractional delay for consecutive M-way parallel reference grid samples includes: obtaining four consecutive M-way parallel reference grid samples from the global sample cache; calculating multiple linear combination coefficients based on the four M-way parallel reference grid samples; and calculating the interpolation result using a Horner nested multiplication structure, wherein the Horner nested multiplication structure represents the interpolation result as a polynomial with respect to the target fractional delay, and the coefficients of each term of the polynomial are determined by the multiple linear combination coefficients. The calculation process is achieved by successively multiplying and adding the target fractional delay with the corresponding linear combination coefficients.

[0017] This invention optimizes the computation process of polynomial interpolation by using Horner nested multiplication structure, transforming the evaluation of high-order polynomials into a series of serial multiplication and addition operations, effectively reducing the consumption of multiplier resources, and reducing the hardware overhead of parallel interpolation units while ensuring interpolation accuracy.

[0018] In step S1 and step S4, the orthogonal up-conversion processing of the M parallel baseband signals includes: generating M parallel orthogonal carrier signals, the orthogonal carrier signals including sine and cosine signals; the process of generating the M parallel orthogonal carrier signals includes: generating a phase address based on the phase accumulation of the M parallel signals based on the frequency control word and the initial phase of the M channels; extracting the high-order bits of the phase address as a quadrant control word and extracting the low-order bits of the phase address as a read address; reading the basic sample value from a symmetric storage array that stores only quarter-cycle sampling points; performing sign inversion or two's complement operation on the basic sample value based on the quadrant control word to generate the complete sine and cosine signals; and performing complex multiplication and addition operations on the M parallel baseband signals with the sine and cosine signals respectively.

[0019] This invention utilizes the quadrant symmetry of trigonometric functions to recover the complete waveform through address mapping and sign control by storing only a quarter of the sampling points. Compared with the full-cycle storage scheme, it significantly saves storage resources and is particularly suitable for resource optimization in multi-channel parallel quadrature modulation scenarios.

[0020] Furthermore, the present invention also provides a multi-mode high-speed parallel digital modulation device, comprising: a parallel mapping module configured to dynamically map M parallel bit streams to M parallel complex symbols based on a unified constellation mapping table and configuration parameters in a reconfigurable memory array, where M is an integer greater than 1; a rate control module configured to generate symbol injection control information and a reference fraction interval based on phase accumulation in each parallel clock cycle; a parallel filtering module configured to inject a corresponding number of the complex symbols into a parallel multiphase shaping filter designed based on a fixed reference sampling rate, outputting M parallel reference grid samples; a parallel interpolation module configured to determine the target fractional delay of each output channel based on the reference fraction interval and channel index, perform phase correction on the M parallel reference grid samples, and generate M parallel baseband signals; and a modulation output module configured to perform orthogonal up-conversion processing on the M parallel baseband signals and convert them into serial data stream output.

[0021] Furthermore, the present invention also provides a modulation device, including a digital-to-analog converter and a multi-mode high-speed parallel digital modulation device as described above; the output terminal of the multi-mode high-speed parallel digital modulation device is coupled to the input terminal of the digital-to-analog converter, and the digital-to-analog converter is configured to convert the serial data stream into an analog intermediate frequency signal.

[0022] The beneficial effects of this invention are as follows: By decoupling variable rate baseband molding into two independent stages, fixed reference multiphase filtering and parallel fractional delay interpolation, this invention enables the parallel filter to be statically designed and optimized based on a fixed reference sampling rate, thus completely solving the problems of dynamic updating of filter coefficients and timing convergence difficulties caused by symbol rate changes in traditional schemes.

[0023] Furthermore, this invention achieves precise mapping and phase coordination correction from variable symbol rate to fixed parallel clock domain by combining symbol injection control and reference fraction interval with channel index to calculate the target fractional delay of each parallel channel, thus ensuring continuous stepless adjustment and high-precision stepping over a wide symbol rate range.

[0024] Furthermore, this invention is based on a parameterized unified constellation mapping mechanism for reconfigurable storage arrays, which supports dynamic adjustment of non-uniform constellation distribution by configuring geometric parameters (such as ring radius ratio and phase offset). It can achieve millisecond-level fast switching of multi-mode modulation and expansion of new modes without modifying the underlying hardware logic, which significantly improves hardware resource reuse and system flexibility.

[0025] Furthermore, this invention, in conjunction with optimization techniques such as orthogonal carrier generation based on symmetric storage arrays and Horner nested interpolation calculation, further reduces the storage and computing resource overhead under the parallel architecture, enabling the overall solution to meet high performance indicators while possessing good engineering feasibility. Attached Figure Description

[0026] The above and other objects, features, and advantages of exemplary embodiments of the present invention will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of the invention are illustrated by way of example and not limitation, and like or corresponding reference numerals denote like or corresponding parts, wherein: Figure 1 This is a flowchart of the multi-mode high-speed parallel digital modulation method according to an embodiment of the present invention; Figure 2 This is a flowchart of the unified programmable parallel symbol mapping according to an embodiment of the present invention; Figure 3 This is a schematic diagram of a constellation map according to an embodiment of the present invention; Figure 4a This is a schematic diagram of the 16QAM constellation map according to an embodiment of the present invention; Figure 4b This is a schematic diagram of the 16APSK constellation map according to an embodiment of the present invention; Figure 5 This is a block diagram of the parallel orthogonal modulation implementation according to an embodiment of the present invention; Figure 6 This is a block diagram of the implementation of the parallel numerically controlled oscillation unit according to an embodiment of the present invention; Figure 7 This is a diagram showing the 16QAM modulation spectrum and constellation effect of an embodiment of the present invention. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0029] This invention provides a multi-mode high-speed parallel digital modulation method, such as... Figure 1 As shown, the main steps include: Step S1: Based on the unified constellation mapping table and configuration parameters in the reconfigurable storage array, dynamically map the M parallel bit streams to M parallel complex symbols, where M is an integer greater than 1.

[0030] In some embodiments, in response to receiving a modulation scheme switching instruction, the unified constellation mapping table and the configuration parameters in the reconfigurable storage array are updated; when the modulation scheme switching instruction indicates a switch to a non-uniform constellation modulation scheme, the distribution position of constellation points is adjusted based on the geometric configuration parameters in the configuration parameters, the geometric configuration parameters including at least one of ring radius ratio or phase offset; based on the updated unified constellation mapping table and the adjusted distribution position, the M-way parallel bit stream is mapped to the corresponding complex symbols.

[0031] Step S2: Generate symbol injection control information and reference fraction interval based on phase accumulation in each parallel clock cycle, and inject the corresponding number of complex symbols into the parallel multiphase shaping filter designed based on a fixed reference sampling rate, and output M parallel reference grid samples.

[0032] In some embodiments, the accumulation step size can be determined based on the ratio of the target symbol rate to the fixed reference sampling rate; in each parallel clock cycle, the current phase accumulation value is increased by the accumulation step size; the symbol injection control information is determined based on the integer part of the increased current value, the symbol injection control information representing the number of complex symbols to be injected in the current cycle; and the reference fraction interval is determined based on the fractional part of the increased current value.

[0033] Specifically, the current value is represented as a fixed-point number containing integer and decimal places. The accumulation step size is calculated by multiplying the ratio of the target symbol rate to the fixed reference sampling rate by 2 to the power of W, where W is the bit width of the decimal places. When the increased current value is greater than or equal to 2 to the power of W, an overflow is triggered, and the number of overflows is used as the symbol injection control information. The result of taking the modulo of the increased current value with 2 to the power of W is used as the updated current value, and the value obtained by dividing the updated current value by 2 to the power of W is used as the reference fraction interval. For each complex symbol injected in the current period, its corresponding initial fraction interval is obtained by subtracting the product of the symbol number and the accumulation step size from the reference fraction interval and taking the modulo.

[0034] Step S3: Determine the target fractional delay of each output channel based on the reference fractional interval and channel index, perform phase correction on the M parallel reference grid samples, and generate M parallel baseband signals.

[0035] In some embodiments, for each target channel among the M output channels, the reference fraction interval is superimposed with the phase offset corresponding to the channel index of the target channel and the modulus is taken to obtain the target fraction delay of the target channel; based on the target fraction delay, polynomial interpolation calculation is performed on the continuous M parallel reference grid samples to obtain the corrected baseband samples.

[0036] Specifically, four consecutive M-way parallel reference grid samples are obtained from the global sample cache; multiple linear combination coefficients are calculated based on the four M-way parallel reference grid samples; the interpolation result is calculated using a Horner nested multiplication structure, which represents the interpolation result as a polynomial with respect to the target fraction delay, wherein the coefficients of each term of the polynomial are determined by the multiple linear combination coefficients, and the calculation process is achieved by successively multiplying and adding the target fraction delay with the corresponding linear combination coefficients.

[0037] Step S4: Perform quadrature upconversion processing on the M parallel baseband signals and convert them into serial data stream output.

[0038] In some embodiments, a phase address can be generated based on the frequency control word and the initial phase of M channels, using M parallel phase accumulation; the high-order bits of the phase address are extracted as a quadrant control word, and the low-order bits of the phase address are extracted as a read address; the basic sample value is read from a symmetric memory array that stores only quarter-cycle sample points; the basic sample value is subjected to sign inversion or two's complement operation based on the quadrant control word to generate the complete sine signal and the cosine signal; the M parallel baseband signals are then multiplied and added with the sine signal and the cosine signal respectively.

[0039] Based on the above method, the present invention also provides a multi-mode high-speed parallel digital modulation device, mainly comprising: A parallel mapping module is configured to dynamically map M parallel bitstreams to M parallel complex symbols based on a unified constellation mapping table and configuration parameters in a reconfigurable storage array, where M is an integer greater than 1. In some embodiments, the parallel mapping module may include a serial-to-parallel conversion module and a programmable parallel symbol mapping module. The serial-to-parallel conversion module converts the input bitstream into M parallel bitstreams, where M is a positive integer. The programmable parallel symbol mapping module contains a unified constellation mapping table stored in Block RAM and configurable index logic, and maps the M parallel bitstreams to M parallel I / Q complex symbols according to the modulation control word issued by the host computer.

[0040] The rate control module is configured to generate symbol injection control information and a reference fractional interval based on phase accumulation within each parallel clock cycle. Specifically, the rate control module operates on M parallel clocks with an accumulation step size Δ=R. s / F base Output the number of symbol injections K and the fractional interval μ for each parallel clock cycle.

[0041] The parallel filtering module is configured to inject a corresponding number of complex symbols into a parallel multiphase shaping filter designed based on a fixed reference sampling rate, outputting M parallel reference grid samples. Specifically, based on a fixed reference symbol rate F... base The design decomposes the prototype filter into M sub-filters. Each parallel clock cycle updates the state of the sub-filters based on the injected K symbols and outputs M parallel reference grid samples.

[0042] A parallel interpolation module is configured to determine the target fractional delay of each output channel based on the reference fractional interval and channel index, perform phase correction on the M parallel reference grid samples, and generate M parallel baseband signals. In some embodiments, the parallel interpolation module may employ an oFarrow fractional delay interpolator unit, comprising M parallel Farrow interpolators, which calculate the fractional delay of each output sample based on μ of the NCO output and the channel index, perform phase correction on the reference grid samples, and output M final baseband samples.

[0043] The modulation output module is configured to perform quadrature up-conversion processing on the M parallel baseband signals and convert them into a serial data stream for output. This modulation output module may include a parallel quadrature modulation module and a parallel-to-serial conversion module. The parallel quadrature modulation module performs complex multiplication and addition operations on the I / Q baseband samples and the quadrature carriers generated by the parallel NCO, outputting M parallel intermediate frequency signals; the parallel-to-serial conversion module converts the M parallel signals into a serial data stream and outputs it to the DAC.

[0044] Application Examples I. Hardware Implementation Platform This embodiment uses a 6U VPX air-cooled digital signal processing carrier board, with two FPGAs and an AD9176 high-speed DA daughter card on board. The hardware resource allocation is as follows: XC7V7690T (V7 main processing FPGA): Executes all parallel digital modulation algorithms, including constellation mapping, NCO rate control, parallel multiphase shaping filtering, Farrow fractional interpolation, parallel quadrature carrier modulation, and all hardware logic for parallel-to-serial conversion. The internal Block RAM, DSP48, and shift registers are the core computing and storage units of this solution. XC7Z045 (Z7 coprocessor chip): The PS end is responsible for host computer interaction, modulation parameter distribution, constellation mapping table pre-calculation and update, filter coefficient distribution, and device status feedback; the PL end assists in high-speed data forwarding. AD9176 DAC: Fixed sampling rate 1.6GHz, receives serial data stream output from FPGA and converts it into analog intermediate frequency signal; Parallel architecture configuration: The number of parallel paths is set to M=8, with a single parallel reference clock Fbase=200MHz. 8 × 200MHz = 1.6GHz, perfectly matching the DAC sampling rate, thus solving the GHz-level clock timing convergence problem in high-speed serial architectures. To accommodate various modulation schemes such as BPSK, QPSK, 8PSK, 16QAM, and 16APSK, parallel symbol mapping is required. To accommodate a continuous variable symbol rate from 10Msym / s to 500Msym / s, parallel variable-speed shaping filters and interpolation filters are necessary.

[0045] The entire modulation processing flow mainly includes core modules such as baseband data generation, channel coding, constellation mapping, shaping filtering, and quadrature modulation. Each module is implemented based on a parallel polyphase structure to meet the requirements of high-speed real-time processing. This invention mainly details the implementation of unified programmable parallel symbol mapping, parallel shaping and interpolation filtering, and parallel carrier modulation.

[0046] Based on the above hardware architecture, the modulation process of this invention mainly includes the following steps: Step S101: Reconstruct a unified constellation map to generate M-way parallel complex symbols.

[0047] 1. Setting up a mapped storage architecture: A reconfigurable Block RAM storage array is deployed inside the V7 FPGA as a unified constellation mapping table. The RAM address depth is 31, and the I and Q components are quantized as 8-bit signed fixed-point numbers, with the maximum value normalized to ±127. The Z7 chip's PS terminal pre-calculates the coordinates of all constellation points based on the parameters sent from the host computer and sends them to the Block RAM to complete the table update.

[0048] 2. Dynamic switching logic of modulation scheme: The host computer sends a modulation switching command, carrying parameters: modulation type (BPSK / QPSK / 8PSK / 16QAM / 16APSK), Gray mapping rule, and 16APSK geometric parameters (ring radius ratio, phase offset). After receiving the instruction, the Z7 chip updates the Block RAM mapping table and the global configuration register.

[0049] Uniform constellation (BPSK / QPSK / 8PSK / 16QAM): Directly loads standard Gray constellation coordinates. For example, for BPSK, only the first address needs to be read; for QPSK, the first four addresses need to be read; for 8PSK, the first eight addresses need to be read with a radius of 127; for 16QAM (e.g., ... Figure 4a As shown, the first 16 addresses are read using the maximum value of 127.

[0050] Non-uniform constellation (16APSK): Calculates the amplitude of the inner and outer constellations based on the configured ring radius ratio, superimposes phase offset to correct constellation point positions, and writes the data into a mapping table. When switching to non-uniform constellations such as 16APSK (e.g., Figure 4b As shown, the PS terminal calculates the amplitude of the inner and outer constellations based on the geometric configuration parameters (such as the ring radius ratio and phase offset) in the configuration parameters. The large radius is quantized at 127, and the small radius is calculated based on the radius ratio. After correcting the constellation point position by combining the phase offset, the value is written into the mapping table.

[0051] The serial-to-parallel conversion module splits the high-speed input bitstream into eight parallel bitstreams. The combined bit values ​​serve as BlockRAM addressing addresses, and eight sets of I and Q complex symbols are read in parallel and output to the back-end parallel filtering module. The core idea is to place the constellation mapping table entirely within the FPGA's BlockRAM, with parameters sent from the host computer and constellation mapping performed by the PS pin of the Z7 chip. This simplifies the design and facilitates subsequent mode expansion. The specific design block diagram is shown below. Figure 3 As shown.

[0052] The parameters related to constellation mapping are shown in Table 1 below. Simply send the parameters to the XC7Z045 as needed, and the XC7Z045 will perform the constellation mapping calculation using the PS terminal. Different modulation methods result in different constellation mapping relationships.

[0053] Table 1

[0054] FPGAs can only process fixed-point data. IQ quantization is performed to 8 signed bits. For example, for BPSK and QPSK, the maximum point is quantized to ±127. For 8PSK, quantization is performed with a radius of 127. For 16APSK, quantization is performed with a large radius of 127, and the small radius is calculated based on the radius ratio. For 16QAM, quantization is performed with the maximum value of 127. This yields the value of a specific constellation point. After calculation, for subsequent expansion, the RAM address can be set to 31. For BPSK, the FPGA only needs to read the value of the first address; for QPSK, only the first four addresses; for 8PSK, only the first eight addresses; and for 16APSK or 16QAM, only the first 16 addresses. If higher-order modulation is extended, the value can be retrieved from the corresponding address. The serial-to-parallel conversion of the four bit streams forms the RAM address. The following diagram shows a mapping relationship between 16QAM (map1) and 16APSK (map2). The Z7 chip uses the following... Figure 4a and Figure 4b The constellations shown will be distributed. Figure 4a Mapping to the 16QAM constellation diagram. Figure 4b Mapping of the 16APSK constellation.

[0055] Step S102: NCO rate control and parallel multiphase shaping filter.

[0056] 1. NCO variable symbol rate control.

[0057] Based on an AD sampling rate of 1.6GHz, 8-channel parallel operation, symbol rate continuously variable from 10Msys to 500Msys, and a reference clock frequency for each channel. ,cycle The NCO contains a phase accumulator. bit width (32 bits), using fixed-point decimal representation, with enough bits in the integer part to cover the maximum possible cumulative amount.

[0058] Step size calculation : The actual number of fixed points used The symbol rate.

[0059] Processing for each reference clock cycle: 1) .

[0060] 2) Calculate the number of integer overflows. decimal part .

[0061] 3) If K ≥ 1, then K valid symbols need to be output in this cycle. Process j = 1…K-1 sequentially. Read the constellation-mapped symbol data from the symbol FIFO. The fractional interval corresponding to this symbol. (Take the modulus of 1, i.e., the decimal part). [The following is a list of steps It is then fed into a subsequent multiphase filter.

[0062] 4) Update the accumulator: (i.e., retain the decimal part).

[0063] 5) If If no valid symbol is injected in this cycle, Do not use (or consider invalid).

[0064] in, This represents the rounded ratio of the actual symbol rate to the reference clock frequency. Indicates the first The precise time offset of each symbol relative to the start of this reference clock cycle (in terms of...) (in units). In this way, the input symbol stream is converted into an average rate of... With timestamp Symbolic stream.

[0065] 2. Parallel polynomial shaping filter.

[0066] For the benchmark symbol rate Design a root-raised cosine (RRC) filter with a sampling rate of Roll-off factor , This is an optional value; monitoring software will issue it as needed, and it will be displayed in the Z7 PS according to... Pre-store the filter coefficients calculated in MATLAB and directly send them to V7, with update times in the millisecond range. Here, the filter order is designed to be 40. Based on the multinomial decomposition principle... Decomposed into There are 1 sub-filter, and the coefficients of each sub-filter are:

[0067] The order of the sub-filter is .

[0068] The I-path and Q-path are processed separately, but the processing steps are the same. The parallel filtering implementation steps are as follows: 1) Each sub-filter Contains a depth of shift register It is used to store historical symbols.

[0069] 2) Within each reference clock cycle, for each injected symbol Write the symbol to all The shift registers of each sub-filter (each register is shifted independently).

[0070] 3) Each sub-filter Calculate the dot product: here It is the accumulated intermediate result within this period, initially set to 0.

[0071] 4) After all injected symbols have been processed in this cycle, accumulator value That is, the output of this cycle. 1 parallel sample point (corresponding to reference grid points with time sequence of phase 0, 1, ..., M-1).

[0072] 5) Clear the accumulator and prepare for the next cycle.

[0073] The polyphase filter has a fixed output for each reference clock cycle. Each sample point has an equivalent serial sampling rate of [number] samples. The value remains constant. These sample points constitute a sampling rate of [missing value]. The baseband waveform, which corresponds to a symbol rate of A continuous-time signal.

[0074] Step S103: Phase delay correction and interpolation based on Farrow structure.

[0075] The phase of the waveform output from the polyphase filter is aligned with the reference grid (i.e., the sample points are located at...). But the actual symbol rate The corresponding ideal waveform should be:

[0076] Its sampled value With polyphase filter output There exists a time-varying fractional delay (Output from NCO) (Decision). In order to obtain accurate results , need to Perform fractional delay filtering.

[0077] This invention employs a Farrow structure for 4-point cubic Lagrange interpolation, with the input being 4 consecutive reference grid samples. The output is delayed. ( The value after )

[0078] in:

[0079] To reduce the number of multipliers, a Horner nested form is used:

[0080] in, The linear combination of the input samples is calculated as follows:

[0081] Eight parallel Farrow interpolators are used, each calculating independently, yielding eight final samples in one reference clock cycle. The workflow of each interpolator is as follows: Fetch four consecutive samples from the global sample buffer (a circular shift register with a depth ≥ 12); Delay based on the score of the current output sample (Based on benchmark) and channel offset calculate: Calculate the interpolation coefficients; obtain the interpolation result through Horner nesting.

[0082] During each reference clock cycle, the NCO output Eight parallel samples simultaneously enter eight Farrow interpolators. Each interpolator... Depend on and channel index Sure: This eliminates the need to store each sample point separately. Only one reference value is needed to calculate the entire result, and eight final samples can be obtained in one reference clock cycle. Then, the signals after the same I-path and Q-path fractional filtering are subjected to quadrature modulation.

[0083] In other embodiments, in addition to using the 4-point cubic Lagrange difference, the present invention can also use the parabolic difference (quadratic, which reduces accuracy but saves computational resources) or the 5-point 4th-order Lagrange difference (which improves accuracy but consumes more computational resources). Those skilled in the art can determine the appropriate method based on actual needs.

[0084] Step S104: Parallel orthogonal upconversion and data output. This step uses quadrature modulation, such as Figure 5 As shown, after molding, it outputs 8 parallel I and Q baseband signals, which are orthogonally modulated with the locally generated frequency signal. The principle of orthogonal modulation is as follows: , , in, , This is the baseband signal after shaping and filtering. For modulation frequency, , The block diagram for the parallel implementation of the modulated quadrature signals within the FPGA is as follows: I0~I7 and Q0~Q7 are 8 parallel filtered baseband signals, as shown below. Figure 6 As shown, cos0~cos7 and sin0~sin7 are orthogonal sine and cosine signals generated by 8 parallel NCOs.

[0085] To conserve resources, a dual-output sine and cosine signal generator based on a symmetrical ROM is used here. Utilizing the quadrant symmetry of trigonometric functions, only 1 / 4 cycle sampling points are stored. Complete sine and cosine waveforms are generated through address mapping and sign control. The specific flowchart is as follows: The input frequency control word is sent to an 8-channel parallel phase accumulator. The initial phase is shown in the diagram below. The high 12 bits of the phase accumulator output are taken and sent to a dual-port RAM. The two high bits represent quadrant control. The final sine and cosine outputs are obtained by using the positive value or two's complement of the sine and cosine from the output ROM. The frequency control word is calculated as follows: ,in f d The modulation frequency is determined by this method. This sine and cosine generation method based on symmetrical ROM saves approximately 88% of BRAM resources compared to the previous method of generating sine and cosine separately for the entire cycle.

[0086] After parallel modulation, the signal is fed into a DA9176 parallel-to-serial converter to output a multi-mode modulated signal. The output signal is then connected to a demodulator. The modulation scheme shown in the diagram is 16QAM, with a symbol rate of 500 Msym / s, a shaping factor of 0.35, and a modulation frequency deviation of 1 MHz. Figure 7 It can be seen that shaping filtering effectively compresses bandwidth, improves spectral efficiency, and prevents out-of-band leakage. Meanwhile, the constellation diagram shows good modulation quality, with EVM < 3%.

[0087] In the above-mentioned shaped filter coefficients of the present invention, the host computer pre-calculates and sends them out. As another implementation method, the coefficients can be calculated in real time according to the roll-off coefficient inside the FPGA, which is suitable for scenarios that require dynamic changes to the roll-off coefficient.

[0088] In addition, if the symbol rate requirement is less than 50Msps and the DAC sampling rate is less than 200MHz, the serial version of the core algorithm of this invention can be used, that is, all parallel channels are set to 1 channel, which is suitable for cost-sensitive low-end devices.

[0089] Based on the above method, the present invention also provides the following product embodiments: A multi-mode high-speed parallel digital modulation device includes a parallel mapping module, a rate control module, a parallel filtering module, a parallel interpolation module, and a modulation output module. The functional logic of each module corresponds one-to-one with the calculation process of steps S1 to S4 above.

[0090] Modulation equipment: includes the aforementioned multi-mode high-speed parallel digital modulation device and digital-to-analog converter (DAC). The output of the modulation device is coupled to the input of the DAC, which is used to convert the serial data stream into an analog intermediate frequency signal output.

[0091] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, or improvements made by those skilled in the art within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A multi-mode high-speed parallel digital modulation method, characterized in that, include: Step S1: Based on the unified constellation mapping table and configuration parameters in the reconfigurable storage array, dynamically map the M parallel bit streams to M parallel complex symbols, where M is an integer greater than 1; Step S2: Generate symbol injection control information and reference fraction interval based on phase accumulation in each parallel clock cycle, and inject the corresponding number of complex symbols into the parallel multiphase shaping filter designed based on a fixed reference sampling rate, and output M parallel reference grid samples; Step S3: Determine the target fractional delay of each output channel based on the reference fractional interval and channel index, perform phase correction on the M parallel reference grid samples, and generate M parallel baseband signals; Step S4: Perform orthogonal upconversion processing on the M parallel baseband signals and convert them into serial data stream output.

2. The multi-mode high-speed parallel digital modulation method according to claim 1, characterized in that, In step S2, the generation of symbol injection control information and reference fraction interval based on phase accumulation within each parallel clock cycle includes: The accumulation step size is determined based on the ratio of the target symbol rate to the fixed reference sampling rate; In each of the parallel clock cycles, the current phase accumulation value is increased by the accumulation step size; The symbol injection control information is determined based on the integer part of the increased current value, and the symbol injection control information represents the number of complex symbols to be injected in the current period; The baseline score interval is determined based on the fractional part of the current value after the increase.

3. The multi-mode high-speed parallel digital modulation method according to claim 1, characterized in that, In step S3, determining the target fractional delay of each output channel based on the reference fractional interval and channel index, and performing phase correction on the M-way parallel reference grid samples, includes: For each target channel among the M output channels, the reference score interval is superimposed with the phase offset corresponding to the channel index of the target channel and the modulus is taken to obtain the target score delay of the target channel; Based on the target fractional delay, polynomial interpolation is performed on the continuous M-path parallel reference grid samples to obtain the corrected baseband samples.

4. The multi-mode high-speed parallel digital modulation method according to claim 1, characterized in that, In step S1, the step of dynamically mapping M parallel bitstreams to M parallel complex symbols based on the unified constellation mapping table and configuration parameters in the reconfigurable storage array includes: In response to receiving a modulation scheme switching command, the unified constellation mapping table and the configuration parameters in the reconfigurable storage array are updated; When the modulation scheme switching command indicates a switch to a non-uniform constellation modulation scheme, the distribution position of constellation points is adjusted based on the geometric configuration parameters in the configuration parameters, wherein the geometric configuration parameters include at least one of ring radius ratio or phase offset. Based on the updated unified constellation mapping table and the adjusted distribution positions, the M-way parallel bit stream is mapped to the corresponding complex number symbols.

5. The multi-mode high-speed parallel digital modulation method according to claim 2, characterized in that, The phase accumulation adopts a fixed-point number format. The determination of the symbol injection control information based on the integer part of the incremented current value and the determination of the baseline fraction interval based on the fractional part of the incremented current value include: The current value is represented as a fixed-point number containing integer and decimal places. The accumulation step size is calculated by multiplying the ratio of the target symbol rate to the fixed reference sampling rate by 2 to the power of W, where W is the bit width of the decimal places. When the current value after the increase is greater than or equal to 2 to the power of W, an overflow is triggered, and the overflow count is injected as a symbol into the control information. The result of taking the modulo of the increased current value with 2 raised to the power of W is used as the updated current value, and the value obtained by dividing the updated current value by 2 raised to the power of W is used as the baseline score interval. For each complex symbol injected in the current period, its corresponding initial fractional interval is obtained by subtracting the product of the symbol number and the cumulative step size from the baseline fractional interval and taking the modulo.

6. The multi-mode high-speed parallel digital modulation method according to claim 3, characterized in that, The step of performing polynomial interpolation calculations on the continuous M-path parallel reference grid samples based on the target fractional delay includes: Obtain four consecutive M-path parallel reference grid samples from the global sample cache; Calculate multiple linear combination coefficients based on four M-path parallel reference grid samples; The interpolation result is calculated using a Horner nested multiplication structure, which represents the interpolation result as a polynomial with respect to the target fraction delay. The coefficients of each term of the polynomial are determined by the multiple linear combination coefficients. The calculation process is achieved by successively multiplying the target fraction delay with the corresponding linear combination coefficients.

7. The multi-mode high-speed parallel digital modulation method according to claim 1, characterized in that, In step S4, the orthogonal up-conversion processing of the M parallel baseband signals includes: M parallel orthogonal carrier signals are generated, the orthogonal carrier signals including sine signals and cosine signals; The process of generating M parallel orthogonal carrier signals includes: The phase address is generated based on the frequency control word and the initial phase of M channels, and the phase is accumulated in M ​​parallel paths. Extract the high-order bits of the phase address as the quadrant control word, and extract the low-order bits of the phase address as the read address; Read the base sample value from a symmetric memory array that stores only a quarter-cycle of sample points; Based on the quadrant control word, the sign inversion or two's complement operation is performed on the basic sampled value to generate the complete sine signal and the cosine signal; The M parallel baseband signals are subjected to complex multiplication and addition operations with the sine signal and the cosine signal, respectively.

8. A multi-mode high-speed parallel digital modulation device, characterized in that, include: The parallel mapping module is configured to dynamically map M parallel bit streams to M parallel complex symbols based on a unified constellation mapping table and configuration parameters in the reconfigurable storage array, where M is an integer greater than 1. The rate control module is configured to generate symbol injection control information and a reference fraction interval based on phase accumulation in each parallel clock cycle; The parallel filtering module is configured to inject the corresponding number of complex symbols into a parallel multiphase shaping filter designed based on a fixed reference sampling rate, and output M parallel reference grid samples. The parallel interpolation module is configured to determine the target fractional delay of each output channel based on the reference fractional interval and channel index, perform phase correction on the M parallel reference grid samples, and generate M parallel baseband signals. The modulation output module is configured to perform quadrature upconversion processing on the M parallel baseband signals and convert them into a serial data stream output.

9. A modulation device, characterized in that, Includes a digital-to-analog converter and a multi-mode high-speed parallel digital modulation device as described in claim 8; The output of the multi-mode high-speed parallel digital modulation device is coupled to the input of the digital-to-analog converter, which is configured to convert the serial data stream into an analog intermediate frequency signal.

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