Combining circuit for doherty power amplifier and doherty power amplifier

Abstract

The application relates to the field of semiconductor technology, in particular to a Doherty power amplifier combining circuit and a Doherty power amplifier. The combining circuit at least comprises: a carrier amplification branch for amplifying a radio frequency signal to be amplified; a first peak value amplification branch connected in parallel with the carrier amplification branch, the first peak value amplification branch being used for starting signal amplification when the power of the radio frequency signal to be amplified is greater than a first threshold value; and a second peak value amplification branch connected in parallel with a parallel connection node of the carrier amplification branch and the first peak value amplification branch, the second peak value amplification branch being used for starting signal amplification when the power of the radio frequency signal to be amplified is greater than a second threshold value; wherein the second threshold value is greater than the first threshold value; and the second peak value amplification branch is provided with a plurality of section characteristic impedance transformation lines connected in series, and the impedance of the plurality of section characteristic impedance transformation lines meets a preset combining power characteristic.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a combining circuit of a Dougherty power amplifier and a Dougherty power amplifier. Background Technology

[0002] Traditional 3-channel Doherty power amplifiers (hereinafter referred to as Doherty) structures are widely used in base stations due to their broadband characteristics. However, with the improvement of base station performance, especially the demand for broadband multi-carrier applications, the efficiency of devices needs to be stable under different carrier configurations. Traditional 3-channel Doherty amplifiers are gradually unable to meet the needs of these broadband multi-carrier application scenarios.

[0003] Therefore, there is an urgent need for a Dougherty power amplifier that can be applied to broadband multi-carrier applications. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a combining circuit for a Dougherty power amplifier and a Dougherty power amplifier.

[0005] A first aspect of this application provides a combining circuit for a Dougherty power amplifier, comprising at least: The carrier amplification branch is used to amplify the radio frequency signal to be amplified; The first peak amplification branch is connected in parallel with the carrier amplification branch. The first peak amplification branch is used to start signal amplification when the power of the radio frequency signal to be amplified is greater than a first threshold. The second peak amplification branch is connected in parallel with the parallel connection node of the carrier amplification branch and the first peak amplification branch. The second peak amplification branch is used to start signal amplification when the power of the radio frequency signal to be amplified is greater than a second threshold. The second threshold is greater than the first threshold. The second peak amplification branch is configured with multiple characteristic impedance transformation lines connected in series. The impedance of the multiple characteristic impedance transformation lines satisfies the preset combined power characteristics.

[0006] In one optional embodiment of this application, the series-connected characteristic impedance transformation lines are two series-connected impedance transformation lines of 90-degree characteristic impedances. Correspondingly, the impedances of the multiple characteristic impedance transformation lines satisfy a preset combined power characteristic, including: The pre-stage impedance of the pre-stage impedance transformation line in the two series-connected 90-degree characteristic impedance impedance transformation lines is determined based on the saturation peak output current of the carrier amplification branch, the saturation peak output current of the first peak amplification branch, the saturation peak output current of the second peak amplification branch, the preset external reference load, and the inherent load resistance of the carrier amplification branch. The impedance of the subsequent stage of the impedance transformation line in the two series-connected 90-degree characteristic impedance transformation lines is determined based on the saturation peak output current of the carrier amplification branch, the saturation peak output current of the first peak amplification branch, the saturation peak output current of the second peak amplification branch, the preset external reference load, and the inherent load resistance of the second peak amplification branch.

[0007] In one optional embodiment of this application, The preceding impedance of the preceding impedance transformation line is determined according to the following formula:

[0008] The impedance of the subsequent impedance transformation line is determined according to the following formula:

[0009] Wherein, T01 represents the preceding impedance of the preceding impedance transformation line; Z peak2_2 R represents the impedance of the subsequent stage of the impedance transformation line; LoadMain R represents the inherent load resistance of the carrier amplification branch; LoadPeak2 R represents the inherent load resistance of the second peak amplification branch; L I1 represents the saturated peak output current of the carrier amplification branch; I2 represents the saturated peak output current of the first peak amplification branch; and I3 represents the saturated peak output current of the second peak amplification branch.

[0010] In one optional embodiment of this application, the preset external reference load is greater than the inherent load resistance ratio of the carrier amplification branch.

[0011] In an optional embodiment of this application, the preset external reference load satisfies the following condition:

[0012] Among them, R L I1 represents the preset external reference load; I2 represents the saturation peak output current of the carrier amplification branch; I3 represents the saturation peak output current of the first peak amplification branch; R represents the saturation peak output current of the second peak amplification branch; LoadMain This represents the inherent load resistance of the carrier amplification branch.

[0013] In one optional embodiment of this application, the impedance transformation line of the 90-degree characteristic impedance is a 90-degree microstrip λ / 4 segment or a multi-order lumped LC fitting circuit.

[0014] In one optional embodiment of this application, the multi-order lumped LC fitting circuit is a stepped lumped quarter-wavelength line or an elliptical lumped quarter-wavelength line.

[0015] In one optional embodiment of this application, the Dougherty power amplifier is a 3-channel Dougherty power amplifier.

[0016] A second aspect of this application provides a Dougherty power amplifier, comprising: Input impedance matching circuit, used to receive the radio frequency signal to be amplified; A power transistor, the input terminal of which is connected to the output terminal of the input impedance matching circuit; In the combining circuit of the Dougherty power amplifier as described in any of the preceding claims, the input terminals of the carrier amplification branch, the first peak amplification branch, and the second peak amplification branch in the combining circuit of the Dougherty power amplifier are respectively electrically connected to the output terminal of the power transistor.

[0017] In an optional embodiment of this application, it further includes: The input impedance matching circuit adopts a two-stage low-pass matching network structure.

[0018] A third aspect of this application provides a radio frequency power amplifier chip, comprising: Chip body; The Doherty power amplifier as described in any of the preceding items.

[0019] A fourth aspect of this application provides a radio frequency power amplifier, comprising: The Dougherty power amplifier chip as described above.

[0020] A fifth aspect of this application provides a wireless signal transmission system, comprising: The radio frequency power amplifier described above. Attached Figure Description

[0021] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a schematic diagram of a traditional 3-way Doherty architecture; Figure 2 This is a schematic diagram of a traditional 3-way Doherty architecture; Figure 3 (a) shows the impedance trajectory of a traditional 3-channel Doherty circuit on a Smith chart; like Figure 3 (b) The impedance transformation trajectory of the Doherty combining circuit provided in the embodiments of this application; like Figure 4(a1) is the impedance transformation trajectory of the current source plane bandwidth response of the carrier amplification branch 100; Figure 4 (a2) is a graph showing the radio frequency characteristics of the current source plane bandwidth response of the carrier amplification branch 100. like Figure 4 (b1) is the impedance transformation trajectory of the current source plane bandwidth response of the first peak amplification branch 200; Figure 4 (b2) is a graph showing the radio frequency characteristics of the current source plane bandwidth response of the first peak amplification branch 200. Figure 4 (c1) is the impedance transformation trajectory of the current source plane bandwidth response of the second peak amplification branch 300; Figure 4 (c2) is the radio frequency characteristic curve of the current source plane bandwidth response of the second peak amplification branch 300. Figure 5 (a) is a graph of the radio frequency characteristics of the main power amplifier load modulation in a traditional 3-channel Doherty combining network; Figure 5 (b) is a graph of the radio frequency characteristics of the main power amplifier load modulation in the Doherty combiner circuit provided in the embodiments of this application; Figure 6 The carrier spacing and power amplifier efficiency characteristic curves are shown for the traditional 3-channel Doherty combining network and the Doherty combining circuit provided in the embodiments of this application. Figure 7 This is a schematic diagram of the combining circuit structure of Doherty provided in an embodiment of this application; Figure 8 (a) is the PCB layout of a traditional 3-way Doherty; Figure 8 (b) A PCB layout diagram of the Doherty combining circuit provided in an embodiment of this application; Figure 9 Fitting 90-degree impedance transformation lines for several exemplary multi-order lumped circuits; Figure 10 An exemplary input circuit of the Doherty combiner circuit provided in the embodiments of this application; Figure 11 This is a circuit board diagram showing that C is grounded using C+R in the second-stage low-pass network. Figure 12 This is the circuit board diagram for the PA unit.

[0022] in: 10. Combining circuit; 100. Carrier amplification branch; 200. First peak amplification branch; 300. Second peak amplification branch. Detailed Implementation

[0023] In the process of developing this application, the applicant discovered that traditional 3-way Doherty technology was gradually becoming unable to meet the needs of these broadband multi-carrier application scenarios.

[0024] To address the aforementioned problems, this application provides a combining circuit for a Dougherty power amplifier and a Dougherty power amplifier in its embodiments. To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description, through embodiments and in conjunction with the accompanying drawings, provides a further detailed explanation of the combining circuit for a Dougherty power amplifier and a Dougherty power amplifier. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit the scope of this application.

[0025] The serial numbers assigned to components in this document, such as "first" and "second," are used solely to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages). It should be understood that the terms "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are used solely for the convenience of describing this application and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0026] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0027] like Figure 1 and Figure 2 This diagram illustrates a traditional 3-way Doherty architecture, widely used in base stations due to its broadband characteristics. However, with the improvement of base station performance, especially the demand for broadband multi-carrier applications, the efficiency of devices needs to remain stable under different carrier configurations. The traditional 3-way Doherty architecture is gradually becoming unable to meet these broadband multi-carrier application scenarios. The bandwidth performance is reflected in the following aspects: (1) The bandwidth is limited by the low impedance of Z01: such as Figure 3 (a) is the impedance trajectory of a traditional 3-way Doherty circuit on a Smith chart. The horizontal axis represents the real part of the reflection coefficient, and the horizontal axis represents the pure resistance line with zero reactance. The rightmost point of this pure resistance line represents the pure resistance; for example, the short-circuit point is at the leftmost end, and the open-circuit point is at the rightmost end. From the center to the right end, the resistance value increases from the normalized matching point 1 to infinity. The vertical axis represents the imaginary part of the reflection coefficient, including the outer boundary and the inner arc of the chart. The arcs in the figure represent lines of equal reactance: the reactance value of the upper half-circle is positive, indicating an inductive load; the reactance value of the lower half-circle is negative, indicating a capacitive load. It should be explained that the embodiments of this application do not consider the influence of reactance, but only the influence of impedance, that is, only the real part of the reflection coefficient on the horizontal axis of the Smith chart is considered. Figure 1 When the impedance of the main path (the path corresponding to I1) passes through Z01, at Figure 3 (a) As the impedance changes from point A to point B, the Q value (quality factor) increases due to the lower impedance of Z01, and the impedance after the transformation decreases. The bandwidth of the subsequent impedance transformation network is also affected.

[0028] (2) Due to the low impedance of Z01, high-power applications require very wide trace widths, making it difficult to implement using a PCB. Specifically: like Figure 5 (a) is a graph showing the RF characteristics of a traditional 3-channel Doherty main amplifier under load modulation. The left vertical axis represents the normalized load impedance seen by the carrier main amplifier, and the right vertical axis represents the impedance percentage. The horizontal axis represents the output power, moving from back-off power to saturation high power from left to right. Different colored curves represent multiple frequency points within the bandwidth. The impedance trajectory at the center frequency point meets the design expectations, but the curves are significantly dispersed at high and low frequencies, and the impedance drops sharply in the high-power region.

[0029] Traditional 3-channel Doherty circuits use numerous λ / 4 transmission lines to construct the combining network, making their phase shift characteristics highly sensitive to frequency. Deviation from the center frequency leads to phase mismatch, active load modulation failure, and inconsistent peak power amplifier turn-on points at different frequencies. When carrying broadband high-power signals, such as... Figure 5 (a) In the spectrum, all frequency points cannot simultaneously meet the optimal load modulation conditions, and the broadband efficiency and saturation performance will decrease after the final combination. That is, due to the limited bandwidth, the broadband performance of the traditional 3-channel Doherty becomes worse after combination in high-power and high-bandwidth applications.

[0030] (3) In multi-carrier applications, the efficiency changes significantly with the carrier spacing. Figure 6 The red curve in the middle represents the correlation between the efficiency and carrier spacing of a traditional 3-way Doherty converter. The horizontal axis represents carrier spacing, and the vertical axis represents efficiency. Figure 6As can be seen from the red curve, the efficiency decreased by 4 points when the carrier spacing varied from 0 to 365 MHz.

[0031] Based on this, this application provides a Doherty combining circuit 10, please refer to [link to relevant documentation]. Figure 7 The Doherty combiner circuit 10 includes at least: a carrier amplification branch 100, a first peak amplification branch 200, and a second peak amplification branch 300, wherein: The carrier amplification branch 100 is used to amplify the radio frequency signal to be amplified; The first peak amplification branch 200 is connected in parallel with the carrier amplification branch 100, and the first peak amplification branch 200 is activated when the power of the radio frequency signal to be amplified is greater than a first threshold. The second peak amplification branch 300 is connected in parallel with the parallel connection node of the carrier amplification branch 100 and the first peak amplification branch 200. The second peak amplification branch 300 is activated when the power of the radio frequency signal to be amplified is greater than a second threshold; wherein the second threshold is greater than the first threshold; and the second peak amplification branch 300 is configured with multiple characteristic impedance transformation lines connected in series, and the impedance of the multiple characteristic impedance transformation lines satisfies the preset combined power characteristics.

[0032] The carrier amplifier branch 100 is a Class AB bias, a main power branch, and has no start-up threshold. It works continuously as long as there is RF input, and its operating range covers the entire range of small signal, medium signal, and full power saturation.

[0033] The first threshold is the first back-off position of the output power. If the power of the RF signal to be amplified is greater than the first threshold, the first peak amplification branch 200 is turned on and participates in load modulation, while the second peak amplification branch 300 remains off. The output current of the first peak amplification branch 200 pulls down the equivalent load impedance of the main power amplifier (carrier amplification branch 100). In the equivalent circuit, the carrier amplification branch 100 and the first peak amplification branch 200 constitute an equivalent two-way Doherty modulation for one load modulation.

[0034] The second threshold is the second back-off position of the output power. The operating range of the second peak amplification branch 300 is from the second threshold to the saturation power. When the power of the RF signal to be amplified is lower than the second threshold, it backs off. When the power of the RF signal to be amplified exceeds the second threshold, the second peak amplification branch 300 is turned on to perform secondary load modulation.

[0035] The impedances of the multiple characteristic impedance transformation lines satisfy a preset combined power characteristic, an example of which is as follows: Traditional 3-way Doherty circuits meet the preset combined power characteristics as shown in formula (1): (1) From B1 and B2, α1 and α2 are derived. Then, from α1 and α2, the current source Imax of each path is derived. This is the combining characteristic of the three-path Doherty circuit. In other words, when selecting ImaxC, ImaxP1, and ImaxP2 in a traditional three-path Doherty circuit, there are two PBOs (power back-off points) at B1 and B2. In this embodiment, the characteristic impedance transformation lines (e.g., ...) are adjusted. Figure 7 The impedance of TPeak2_2 in the middle makes the two PBOs B1 and B2 consistent with the traditional 3-way.

[0036] The working principle of the Doherty combining circuit 10 provided in the embodiments of this application is explained below: Firstly, as explained above and Figure 5 (a) and Figure 6 The curves show that the bandwidth of any amplifier is limited, especially since the traditional Doherty structure performs well only at specific frequency points such as the center frequency. Once the frequency deviates, the performance drops sharply.

[0037] The Doherty combiner circuit 10 provided in this embodiment has multiple series-connected characteristic impedance transformation lines configured in the second peak amplification branch 300. The impedances of these multiple characteristic impedance transformation lines satisfy a preset combiner power characteristic. The impedances of these multiple characteristic impedance transformation lines can be changed by optimizing the external reference load RL (e.g., ...). Figure 7 The impedance of the preceding stage impedance transformation line (T01) in the multi-segment characteristic impedance transformation line is reduced to decrease the combined Q value, thereby increasing the bandwidth. During load modulation, since the main power amplifier load is fixed (e.g., ...), Figure 2 Z02 and Figure 7 In the Tmain (the impedance of the Tmain), the inherent impedance is also fixed, and it is generally optimized such as... Figure 2 and Figure 7 The external reference load RL is used to adjust the load at the current source terminal of the main power amplifier, while the load at the current source terminal of a typical main power amplifier (such as...) Figure 2 Z01 and Figure 7 In the multi-segment characteristic impedance transformation line, the preceding impedance transformation line (T01) is relatively small, and the impedance after load transformation will also decrease, which will affect the bandwidth of the subsequent impedance transformation network.

[0038] To address this issue, this application embodiment modifies the impedance of the preceding stage impedance transformation line T01 and the subsequent stage impedance (located after the external reference load RL) by optimizing the external reference load RL. Figure 7(not shown in the figure) makes the equivalent overall impedance response of the carrier amplification branch 100 at the load end of the main current source more flat in the working bandwidth. In multi-carrier applications, the efficiency fluctuation is smaller as the carrier spacing changes, and at the same time, the Q value (Quality Factor) of the combiner is reduced to achieve the purpose of increasing the bandwidth.

[0039] Secondly, in this embodiment, the second peak amplification branch 300 is configured with a series of multiple characteristic impedance transformation lines. These characteristic impedance transformation lines increase the impedance of the secondary combiner (the carrier amplification branch 100 and the first peak amplification branch 200 are combined in parallel, and then combined in parallel with the second peak amplification branch 300). This provides a larger load for the current source and compensates for the reduced impedance after load transformation, thus adapting to a wider bandwidth in the subsequent impedance transformation network and avoiding issues such as… Figure 5 (a) and Figure 6 The problem of decreased broadband efficiency and saturation performance after the central merging circuit.

[0040] Since the external reference load RL is adjusted, the impedance of the first combining point (the connection point of the parallel combination of the carrier amplification branch 100 and the first peak amplification branch 200) will change after the impedance of RL changes. In this embodiment, the second peak amplification branch 300 is configured with a series multi-segment characteristic impedance transformation line. The inherent impedance of the second peak amplification branch 300 is transformed to the changed impedance through the multi-segment characteristic impedance transformation line, thereby achieving impedance matching.

[0041] For example, the current ratio at the second combining point is: (carrier amplification branch 100 + first peak amplification branch 200) : second peak amplification branch 300 = 2:1. After adjusting the external reference load RL, the impedance of carrier amplification branch 100 + first peak amplification branch 200 increases from the original 50 ohms to the current 100 ohms. However, the inherent impedance in the second peak amplification branch 300 remains unchanged. In this embodiment, by adding multiple characteristic impedance transformation lines Tpeack2_2, the impedance in the second peak amplification branch 300 is supplemented to 50 ohms, thus maintaining the ratio of carrier amplification branch 100 + first peak amplification branch 200 : second peak amplification branch 300 = 2:1, thereby maintaining the proportional architecture of each path in Doherty.

[0042] Thirdly, the embodiments of this application propose the following: Figure 7 The Doherty combiner circuit 10 shown requires the introduction of multiple characteristic impedance transformation lines in the combiner network of the second peak amplification branch 300. Any characteristic impedance transformation line among the multiple characteristic impedance transformation lines, such as Tpeak2_2, is used as an impedance transformation line, so that the combined power characteristics remain consistent with those of the traditional 3-channel Doherty.

[0043] Fourthly, the Doherty combining circuit 10 provided in this application embodiment expands the bandwidth and flattens the in-band impedance by introducing multiple characteristic impedance transformation lines into the combining network of the second peak amplification branch 300, thereby improving the PA efficiency under different carrier intervals.

[0044] Fifthly, such as Figure 3 (b) The impedance transformation trajectory of the Doherty combining circuit 10 provided in the embodiments of this application, from... Figure 3 As can be clearly seen in (b), the impedance increase of the front-stage impedance transformation line T01 of the Doherty combining circuit 10 provided in this application embodiment will not affect the Q value of the combining network. Moreover, due to the increase of the external reference load RL, after the external reference load RL is combined, only one impedance transformation line is needed to transform to the load impedance required by the customer (usually 50 ohms), and the PCB area is reduced.

[0045] like Figure 4 (a1) is the impedance transformation trajectory of the current source plane bandwidth response of the carrier amplification branch 100; as shown... Figure 4 (a2) is a graph showing the radio frequency characteristics of the current source plane bandwidth response of the carrier amplification branch 100. like Figure 4 (b1) shows the impedance transformation trajectory of the current source plane bandwidth response of the first peak amplification branch 200; as shown... Figure 4 (b2) is a graph showing the radio frequency characteristics of the current source plane bandwidth response of the first peak amplification branch 200. like Figure 4 (c1) is the impedance transformation trajectory of the current source plane bandwidth response of the second peak amplification branch 300; as shown... Figure 4 (c2) is the radio frequency characteristic curve of the current source plane bandwidth response of the second peak amplification branch 300.

[0046] in, Figure 4 (a2) Figure 4 (b2) and Figure 4 In (b2), the blue curve represents the Doherty combining circuit 10 provided in this application, and the red curve represents the conventional 3-way Doherty combining network. Figure 4 (a1)- Figure 4 (c2) shows that, due to the decrease in the Q value of the entire impedance network, the impedance response at the current source becomes relatively flat at full power and at the back-off point, and the bandwidth performance is greatly improved.

[0047] In summary, based on the above five aspects, this application provides a Doherty combining circuit 10 with superior performance, flatter impedance transformation, and smaller PCB area reduction.

[0048] Figure 5 (a) is a graph of the radio frequency characteristics of the main power amplifier load modulation in a traditional 3-channel Doherty combining network; Figure 5 (b) A graph of the radio frequency characteristics of the Doherty combiner circuit 10 main power amplifier load modulation provided in the embodiments of this application; Figure 6 The carrier spacing and power amplifier efficiency characteristic curves are shown for the conventional 3-channel Doherty combining network and the Doherty combining circuit 10 provided in the embodiments of this application. Figure 8 (a) is the PCB layout of a traditional 3-way Doherty; Figure 8 (b) is the PCB layout of the Doherty combining circuit 10 provided in an embodiment of this application. The following will be combined with... Figures 5-8 The performance of the Doherty combining circuit 10 provided in this application embodiment and the traditional 3-channel Doherty circuit were compared using data, specifically including the following aspects: Firstly, the bandwidth and flatness of the current source impedance are improved: Please see Figure 5 (a) and Figure 5 (b), Figure 5 (b) The current source plane impedance bandwidth and in-band impedance flatness in the Doherty combiner circuit 10 provided in the embodiments of this application are both better than those of the other two applications. Figure 5 (a) The traditional 3-way Doherty has been improved.

[0049] Secondly, the merging curves are more convergent and monotonous: Please see Figure 5 (a) and Figure 5 (b), by Figure 5 (a) and Figure 5 (b) It can be seen that the carrier spacing and power amplifier efficiency characteristic curves of the Doherty combiner circuit 10 provided in the embodiments of this application are more monotonous and clustered.

[0050] Thirdly, the efficiency changes are smaller when the carrier spacing changes: Please see Figure 6 The thick blue curve represents the carrier spacing and power amplifier efficiency characteristic curves of the Doherty combiner circuit 10 provided in this embodiment, while the thin red curve represents the carrier spacing and power amplifier efficiency characteristic curves of a conventional 3-way Doherty combiner network. Figure 6It can be seen that the efficiency of a traditional 3-channel Doherty circuit drops by more than 4 percentage points when the carrier spacing varies from 0 to 365 MHz; while the Doherty combining circuit 10 provided in this embodiment shows an efficiency fluctuation of approximately 1 percentage point when the carrier spacing varies from 0 to 365 MHz. In comparison, the overall fluctuation of a traditional 3-channel Doherty circuit is approximately 5 percentage points. Furthermore, under a 365 MHz wideband signal, the efficiency of the Doherty combining circuit 10 provided in this embodiment is improved by 3 percentage points.

[0051] Fourthly, the fabric board size is smaller: Please see Figure 8 ,Depend on Figure 8 (a) and Figure 8 (b) Comparison shows that, due to the increased impedance of the characteristic impedance transformation line Z01 in the Doherty combining circuit 10 provided in this application embodiment, the PCB does not need a wide trace, and the PCB size is reduced from the traditional ~62mm to the current ~32mm.

[0052] In one optional embodiment of this application, the series-connected characteristic impedance transformation lines are two series-connected impedance transformation lines of 90-degree characteristic impedances. The embodiments of this application propose, as follows: Figure 7 The Doherty combiner circuit 10 shown introduces two series-connected 90-degree characteristic impedance transformation lines into the combiner network of the second peak amplification branch 300, and uses the characteristic impedance transformation line Tpeak2_2 as the impedance transformation line, so that the combined power characteristics remain consistent with the traditional 3-channel Doherty.

[0053] Correspondingly, the impedances of the multiple characteristic impedance transformation lines satisfy a preset combined power characteristic, including: The pre-stage impedance of the pre-stage impedance transformation line in the two series-connected 90-degree characteristic impedance impedance transformation lines is determined based on the saturation peak output current of the carrier amplification branch 100, the saturation peak output current of the first peak amplification branch 200, the saturation peak output current of the second peak amplification branch 300, the preset external reference load, and the inherent load resistance of the carrier amplification branch 100. The impedance of the subsequent stage of the impedance transformation line in the two series-connected 90-degree characteristic impedance transformation lines is determined based on the saturation peak output current of the carrier amplification branch 100, the saturation peak output current of the first peak amplification branch 200, the saturation peak output current of the second peak amplification branch 300, the preset external reference load, and the inherent load resistance of the second peak amplification branch 300.

[0054] Based on the traditional 3-way Doherty structure, the impedance design of Z01 is as follows (2). (2) In an optional embodiment of this application, the preceding impedance of the preceding impedance transformation line is determined according to the following formula (3): (3) The impedance of the subsequent stage impedance transformation line is determined according to the following formula (4): (4) Wherein, T01 represents the preceding impedance of the preceding impedance transformation line; Z peak2_2 R represents the impedance of the subsequent stage of the impedance transformation line; LoadMain R represents the inherent load resistance of the carrier amplification branch 100; LoadPeak2 R represents the inherent load resistance of the second peak amplification branch 300; L I1 represents the saturated peak output current of the carrier amplification branch 100; I2 represents the saturated peak output current of the first peak amplification branch 200; and I3 represents the saturated peak output current of the second peak amplification branch 300.

[0055] The preceding impedance of the preceding impedance transformation line is calculated using formula (3) above, and the following impedance is calculated using formula (4) above, which can improve... In one optional embodiment of this application, the preset external reference load is greater than the inherent load resistance ratio of the carrier amplification branch 100.

[0056] In an optional embodiment of this application, the preset external reference load satisfies the following condition: (5) Among them, R L I1 represents the saturated peak output current of the carrier amplification branch 100; I2 represents the saturated peak output current of the first peak amplification branch 200; I3 represents the saturated peak output current of the second peak amplification branch 300; R LoadMain This represents the inherent load resistance of the carrier amplification branch 100.

[0057] The impedance of the pre-amplifier impedance transformation line T01 in the layout must satisfy formula (3) and the condition must satisfy formula (4). The impedance of the pre-amplifier impedance transformation line T01 is higher than that of the traditional 3-channel Doherty (restricted by formula (4)), so that the combined power characteristics remain consistent with the traditional 3-channel Doherty, and provide a larger load for the current source end and make up for the reduced impedance after the load transformation, thereby adapting to the wider bandwidth in the subsequent impedance transformation network and avoiding the occurrence of problems such as Figure 5 (a) and Figure 6 The problem of decreased broadband efficiency and saturation performance after the central merging circuit.

[0058] In one optional embodiment of this application, the impedance transformation line of the 90-degree characteristic impedance is a 90-degree microstrip λ / 4 segment or a multi-order lumped LC fitting circuit.

[0059] In one optional embodiment of this application, the multi-order lumped LC fitting circuit is a stepped lumped quarter-wavelength line or an elliptical lumped quarter-wavelength line.

[0060] In this embodiment of the application, for Figure 7 Each 90-degree impedance transformation line in the diagram is typically implemented using microstrip lines or multi-order lumped elements for fitting. Figure 9 Several exemplary multi-order lumped circuit fitting common forms of 90-degree impedance transformation lines are shown. The first pair of ground inductors and capacitors is optional. Each 90-degree impedance transformation line is implemented using microstrip lines. When using lumped devices, a combination of multi-order lumped circuits is typically used to increase bandwidth. Furthermore, the unit circuit design can be optimized in the design examples to expand bandwidth, increase video bandwidth (VBW), and improve stability.

[0061] In one optional embodiment of this application, the Doherty is a 3-channel Doherty.

[0062] In summary, the embodiments of this application provide a 3-channel Doherty combining circuit 10 with superior performance, flatter impedance transformation, and smaller PCB area reduction.

[0063] An optional embodiment of this application provides a Doherty, including: Input impedance matching circuit, used to receive the radio frequency signal to be amplified; A power transistor, the input terminal of which is connected to the output terminal of the input impedance matching circuit; As described in any of the preceding Doherty combiner circuits 10, the input terminals of the carrier amplification branch 100, the first peak amplification branch 200, and the second peak amplification branch 300 in the Doherty combiner circuit 10 are respectively electrically connected to the output terminal of the power transistor.

[0064] Figure 10 An exemplary input circuit of the Doherty combiner circuit 10 provided in this application embodiment, for example... Figure 10 In the DLP equivalent circuit in this embodiment, the input circuit uses a two-stage low-pass (L+C) network to achieve input impedance matching, thereby performing pre-matching to facilitate subsequent power amplification. Figure 11This is a circuit board diagram showing how C is grounded using C+R in the second-stage low-pass network. Figure 12 This is a circuit board diagram of the PA unit, where the second capacitor C ( Figure 11 and Figure 12 The portion within the blue box (in the middle) is typically grounded via a resistor to improve device stability. The device input is usually implemented using a two-stage LC low-pass network, with the capacitor C on the second stage typically grounded via R to further enhance stability.

[0065] In an optional embodiment of this application, the above structure further includes: The input impedance matching circuit adopts a two-stage low-pass matching network structure.

[0066] One embodiment of this application provides a radio frequency power amplifier chip, including: Chip body; Doherty as described in any of the previous items.

[0067] One embodiment of this application provides a radio frequency power amplifier, comprising: The Doherty power amplifier chip as described above.

[0068] One embodiment of this application provides a wireless signal transmission system, characterized in that it includes: The radio frequency power amplifier described above.

[0069] It should be understood that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order constraint on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the diagram may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0070] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0071] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A combining circuit for a Dougherty power amplifier, characterized in that, At least including: The carrier amplification branch is used to amplify the radio frequency signal to be amplified; The first peak amplification branch is connected in parallel with the carrier amplification branch. The first peak amplification branch is used to start signal amplification when the power of the radio frequency signal to be amplified is greater than a first threshold. The second peak amplification branch is connected in parallel with the parallel connection node of the carrier amplification branch and the first peak amplification branch. The second peak amplification branch is used to start signal amplification when the power of the radio frequency signal to be amplified is greater than a second threshold. The second threshold is greater than the first threshold. The second peak amplification branch is configured with multiple characteristic impedance transformation lines connected in series. The impedance of the multiple characteristic impedance transformation lines satisfies the preset combined power characteristics.

2. The combining circuit of the Dougherty power amplifier according to claim 1, characterized in that, The series-connected characteristic impedance transformation line is an impedance transformation line consisting of two series-connected 90-degree characteristic impedances. Correspondingly, the impedances of the multiple characteristic impedance transformation lines satisfy a preset combined power characteristic, including: The pre-stage impedance of the pre-stage impedance transformation line in the two series-connected 90-degree characteristic impedance impedance transformation lines is determined based on the saturation peak output current of the carrier amplification branch, the saturation peak output current of the first peak amplification branch, the saturation peak output current of the second peak amplification branch, the preset external reference load, and the inherent load resistance of the carrier amplification branch. The impedance of the subsequent stage of the impedance transformation line in the two series-connected 90-degree characteristic impedance transformation lines is determined based on the saturation peak output current of the carrier amplification branch, the saturation peak output current of the first peak amplification branch, the saturation peak output current of the second peak amplification branch, the preset external reference load, and the inherent load resistance of the second peak amplification branch.

3. The combining circuit of the Dougherty power amplifier according to claim 2, characterized in that, The preceding impedance of the preceding impedance transformation line is determined according to the following formula: ； The impedance of the subsequent impedance transformation line is determined according to the following formula: ； Wherein, the characteristic impedance transformation line preceding the impedance transformation line T01 represents the preceding impedance of the preceding impedance transformation line; Z peak2_2 R represents the impedance of the subsequent stage impedance transformation line; LoadMain R represents the inherent load resistance of the carrier amplification branch; LoadPeak2 R represents the inherent load resistance of the second peak amplification branch; L I1 represents the saturated peak output current of the carrier amplification branch; I2 represents the saturated peak output current of the first peak amplification branch; and I3 represents the saturated peak output current of the second peak amplification branch.

4. The combining circuit of the Dougherty power amplifier according to claim 2, characterized in that, The preset external reference load is greater than the inherent load resistance of the carrier amplification branch by a certain percentage.

5. The combining circuit of the Dougherty power amplifier according to claim 4, characterized in that, The preset external reference load satisfies the following conditions: ； Among them, R L I1 represents the preset external reference load; I2 represents the saturation peak output current of the carrier amplification branch; I3 represents the saturation peak output current of the first peak amplification branch; R represents the saturation peak output current of the second peak amplification branch; LoadMain This represents the inherent load resistance of the carrier amplification branch.

6. The combining circuit of the Dougherty power amplifier according to claim 2, characterized in that, The impedance transformation line of the 90-degree characteristic impedance is a 90-degree microstrip λ / 4 segment or a multi-order lumped LC fitting circuit.

7. The combining circuit of the Dougherty power amplifier according to claim 6, characterized in that, The multi-order lumped LC fitting circuit is a stepped lumped quarter-wavelength line or an elliptical lumped quarter-wavelength line.

8. The combining circuit of the Dougherty power amplifier according to any one of claims 1-7, characterized in that, The Dougherty power amplifier is a 3-channel Dougherty power amplifier.

9. A Dougherty power amplifier, characterized in that, include: Input impedance matching circuit, used to receive the radio frequency signal to be amplified; A power transistor, the input terminal of which is connected to the output terminal of the input impedance matching circuit; The combining circuit of the Dougherty power amplifier as described in any one of claims 1-8, wherein the input terminals of the carrier amplification branch, the first peak amplification branch, and the second peak amplification branch in the combining circuit of the Dougherty power amplifier are respectively electrically connected to the output terminal of the power transistor.

10. The Dougherty power amplifier according to claim 9, characterized in that, The input impedance matching circuit adopts a two-stage low-pass matching network structure.

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