An ultra-low power supply voltage 2.4ghz wake-up receiver

Abstract

The application discloses a 2.4GHz wake-up receiver with ultra-low power supply voltage, relates to radio frequency wireless communication technology, and comprises an on-chip pseudo-differential gate bias envelope detector, a Q value boosting circuit, a bulk drive baseband amplifier, a comparator and a digital correlator; a Q value boosting circuit of a single-ended interface is introduced in the front stage of the on-chip pseudo-differential gate bias envelope detector, an OOK modulated radio frequency signal is input to the on-chip pseudo-differential gate bias envelope detector for envelope detection after passing through a matching network, and a baseband signal is obtained; the baseband signal is amplified by the bulk drive baseband amplifier and then input to the comparator for digital judgment; the digital judgment signal is input to the digital correlator and matched with a preset wake-up code, and a wake-up signal is output when the matching is successful. The application realizes higher conversion gain and lower power consumption, can effectively improve the passive voltage gain of the matching network and the system sensitivity, and is suitable for low-power Internet of Things nodes, wireless body area networks and energy collection power supply scenes.

Description

Technical Field

[0001] This invention relates to radio frequency wireless communication technology, and more specifically, to a 2.4 GHz wake-up receiver with ultra-low power supply voltage. Background Technology

[0002] With the rapid development of Internet of Things (IoT) technology, low-power wireless communication nodes are widely used in environmental monitoring, smart homes, wearable devices, wireless body area networks, and industrial sensor networks. In these application scenarios, many devices are in a standby listening state for extended periods. Traditional wireless receivers typically require continuous operation of the RF front-end and baseband processing module, resulting in high system standby power consumption and severely limiting the battery life of the device nodes.

[0003] To reduce system standby power consumption, wake-up receiver (WuRx) technology has gradually become an important research direction in the field of low-power wireless communication. Wake-up receivers typically listen for wireless signals continuously with extremely low power consumption, activating the main communication system only upon detecting a specific wake-up code, thus significantly reducing overall system power consumption. Among them, wake-up receivers operating in the 2.4 GHz band have broad application prospects due to their compatibility with mainstream wireless communication protocols such as Bluetooth, ZigBee, and some Wi-Fi protocols.

[0004] Currently, low-power wake-up receivers mainly fall into two categories: RF amplifier-first architecture and envelope detector-first architecture. The RF amplifier-first architecture typically introduces active RF modules such as low-noise amplifiers at the front end to improve system sensitivity; however, this architecture has relatively high power consumption, making it unsuitable for ultra-low-power applications. In contrast, the envelope detector-first architecture eliminates the high-power RF amplifier module, directly detecting and demodulating the input RF signal using an envelope detector. Therefore, it has advantages such as simple structure and low power consumption, making it more suitable for ultra-low-power IoT nodes.

[0005] Furthermore, with the development of passive IoT and energy harvesting technologies, more and more research is beginning to attempt to combine wake-up receivers with technologies such as radio frequency energy harvesting and electromagnetic energy harvesting to achieve fully passive systems that do not require battery power. However, energy harvesting circuits typically can only provide relatively low supply voltages, thus placing higher demands on the wake-up receiver's ability to operate normally under ultra-low power supply voltage conditions.

[0006] Therefore, improving the sensitivity, gain, and system robustness of a 2.4 GHz wake-up receiver under ultra-low power consumption and ultra-low power supply voltage conditions has become an important research direction in related fields.

[0007] While existing envelope detector-priority architecture wake-up receivers have the advantage of low power consumption, their overall sensitivity is usually low due to the lack of high-gain RF front-ends such as low-noise amplifiers, making it difficult to meet the wireless wake-up requirements under long-distance or weak signal conditions.

[0008] To improve sensitivity, existing technologies typically rely on off-chip matching networks to provide passive voltage gain. However, the voltage gain of the matching network is closely related to the input impedance of the envelope detector. When the input impedance of the envelope detector is low, the passive voltage gain decreases, and the losses of the matching network itself further degrade the receiver sensitivity. Therefore, traditional structures struggle to simultaneously achieve high sensitivity and low power consumption under ultra-low power conditions. To address this issue, patent CN118921074A discloses a multi-mode wake-up receiver and communication device that uses Q-enhancement mode to enhance the receiver's signal-to-noise ratio and reduce power consumption. However, this patent's Q-value enhancement technology employs a differential cross-coupled circuit, and although its envelope detector has a single-ended input, it cannot be cascaded. A dummy circuit is added to this patent—a set of virtual, ineffective single-ended envelope detectors used to cascade the differential cross-coupled Q-value enhancement circuit. This design undoubtedly increases the circuit complexity and power consumption. Moreover, its conversion gain is limited, it lacks flexible performance adjustment capabilities, and it is easily affected by changes in process, voltage and temperature, resulting in insufficient system robustness and difficulty in adapting to performance requirements under different working environments. Summary of the Invention

[0009] The technical problem to be solved by the present invention is to provide a 2.4GHz wake-up receiver with ultra-low power supply voltage, which overcomes the shortcomings of the prior art, achieves higher conversion gain, lower power consumption, and can also effectively improve the passive voltage gain of the matching network and the system sensitivity.

[0010] The present invention discloses a 2.4GHz wake-up receiver with ultra-low power supply voltage, comprising an on-chip pseudo-differential gate bias envelope detector, a Q-value boosting circuit, a body-driven baseband amplifier, a comparator, and a digital correlator. A single-ended Q-value boosting circuit is introduced before the on-chip pseudo-differential gate bias envelope detector. The externally input OOK modulated RF signal is input to the on-chip pseudo-differential gate bias envelope detector after passing through a matching network for envelope detection, so as to convert the OOK modulated RF signal into a baseband signal. The baseband signal is amplified by the body-driven baseband amplifier and then input to the comparator for digital decision, resulting in a digital decision signal. The digital decision signal is input to the digital correlator and correlated with a preset wake-up code. When the match is successful, a wake-up signal is output.

[0011] Preferably, the on-chip pseudo-differential gate bias envelope detector includes a first detection branch, a second detection branch, and a gate bias network; The first detection branch consists of N field-effect transistors M na Composition, field-effect transistor M 1a The drain is grounded, and the field-effect transistor M na The source and field-effect transistor M （n+1）a The drains of the transistors are connected, and the field-effect transistor M... na The source and field-effect transistor M （n+1）a The drain terminal is connected through capacitor C mA The radio frequency signal RFIN output by the matching network is connected to the field-effect transistor M. Na The source of the signal serves as the differential envelope voltage V in the baseband signal. OUTP The output terminal; in the N field-effect transistors M na In the diagram, N represents an odd number of field-effect transistors M. na Each of the field-effect transistors has a gate bias network connected to its gate, and N is an even number. na The gates of all devices are connected to the gate bias voltage signal VGB of the envelope detector. The second detection branch consists of N field-effect transistors M nb Composition, field-effect transistor M 1b The source is grounded, and the field-effect transistor M nb The drain and field-effect transistor M （n+1）b The source is connected, and the field-effect transistor M nb The drain and field-effect transistor M （n+1）b The source terminal is connected through capacitor C mB The radio frequency signal RFIN output by the matching network is connected to the field-effect transistor M. Nb The drain is grounded as the differential envelope voltage V in the baseband signal. OUTN The output terminal; in the N field-effect transistors M nb In the diagram, N represents an odd number of field-effect transistors M. nb The gate of each of the field-effect transistors is connected to the signal VGB, and N is an even number of M. nb Each of the gates is connected to a gate bias network; The gate bias network includes a pseudo-resistor R. mc and capacitor C mc The pseudo resistor R mc and capacitor C mc One end is connected, and the pseudo resistor R mc and capacitor C mc One end of the connection is connected to the field-effect transistor M. mc The gate connection; the pseudo resistor R mc The other end is connected to signal VGB, and the capacitor C mcThe other end is connected to the radio frequency signal RFIN output from the matching network; Where N is a natural number greater than 1; n∈1,...,N; c is a or b; m∈1,...,M, M=N / 2.

[0012] Preferably, the pseudo resistor R nc By field-effect transistor M Ac and field-effect transistor M Bc Composition, the field-effect transistor M Ac and field-effect transistor M Bc The source terminals are respectively used as pseudo resistors R nc At both ends, the field-effect transistor M Ac and field-effect transistor M Bc The four electrodes, namely the gate and drain, are connected together.

[0013] Preferably, in N of the field-effect transistors M na In the diagram, N represents an even number of field-effect transistors M. na The source of each is connected to a capacitor C. mk Grounding; in the N field-effect transistors M nb In the diagram, N represents an even number of field-effect transistors M. nb The drain of each electrode is connected to a capacitor C. mj Grounding.

[0014] Preferably, the Q-value boosting circuit includes field-effect transistors M1, M2, M3, M4, and N field-effect transistors M1, M2, M3, M4, and N field-effect transistors M1, M2, M3, M4, and M5. an The drain of the field-effect transistor M1 is connected to a voltage source, and the gate of the field-effect transistor M1 receives the first SPI switch signal. The source of the field-effect transistor M1 is simultaneously connected to the drains of both field-effect transistors M2 and M3. The gate input of the field-effect transistor M2 is an input bit connected to the line between the on-chip pseudo-differential gate bias envelope detector and the matching network. The source of the field-effect transistor M2 is simultaneously connected to the gate of the field-effect transistor M3 and the drain of the field-effect transistor M4. a1 The drain connection of the field-effect transistor M3, the source of the field-effect transistor M a1 The source of N transistors M4 is connected to the drain of the field-effect transistor M4, the gate of the field-effect transistor M4 is connected to a voltage source, and the source of the field-effect transistor M4 is grounded. an All M gates are input with SPI switching signals, and all field-effect transistors M an The drains of all field-effect transistors M are connected. an The source poles are connected.

[0015] Preferably, the body-driven baseband amplifier includes a body-driven transistor M. 1d Body-driven transistor M 2d Body-driven transistor M 3dBody-driven transistor M 4d Body-driven transistor M 1e Body-driven transistor M 2e Body-driven transistor M 3e Body-driven transistor M 4e Body drive transistor M5, body drive transistor M6, and capacitor C3; the body drive transistor M... 1d Body-driven transistor M 2d Body-driven transistor M 1e Body-driven transistor M 2e The source of the body driving transistor M5 is simultaneously connected to a voltage source. 1d Body-driven transistor M 1e The body terminal is simultaneously connected to the differential envelope voltage V in the baseband signal. OUTP The body drive transistor M 2d Body-driven transistor M 2e The body terminal is simultaneously connected to the differential envelope voltage V in the baseband signal. OUTN The body drive transistor M 2e Body-driven transistor M 1d The gate of the body driving transistor M is connected to the gate of the body driving transistor M. 1e Body-driven transistor M 2d The gate of the body driving transistor M is connected to the gate of the body driving transistor M. 2e The drain of the body-driven transistor M is simultaneously connected to the body-driven transistor M. 4d Gate and drain, body drive transistor M 4e The gate connection of the body driving transistor M 1e Drain and body drive transistor M 4e The drain of the body-driven transistor M5, the gate of the body-driven transistor M6, and one end of capacitor C3 are connected together. The other end of capacitor C3 serves as the output terminal of the body-driven baseband amplifier and is simultaneously connected to the drain of both the body-driven transistor M5 and the drain of the body-driven transistor M6. The gate of the body-driven transistor M5 receives the gate bias voltage signal VBP. The body-driven transistor M6... 1d Drain and body drive transistor M 3d The drain connection of the body drive transistor M 2d Drain and body drive transistor M 3e The drain connection of the body drive transistor M 3d and body drive transistor M 3e The gate is simultaneously connected to the gate bias voltage signal VBN; the body driving transistor M 4d Body-driven transistor M 3d Body-driven transistor M 3e Body-driven transistor M 4e The source of the body drive transistor M6 is grounded.

[0016] Preferably, the body driving transistor M 1d Body-driven transistor M 2d Body-driven transistor M 1e Body-driven transistor M 2e Both the body drive transistor M5 and the P-type field-effect transistor M SP and P-type field-effect transistor M DP Composition, the P-type field-effect transistor M SP and P-type field-effect transistor M DP The gate of the P-type field-effect transistor M is connected to the gate of the body driving transistor. SP The source of the P-type field-effect transistor M is used as the source of the body-driven transistor. SP The drain of the P-type field-effect transistor M DP The source terminal of the P-type field-effect transistor M is connected to the body terminal of the body-driven transistor. DP The drain of the transistor is used as the drain of the body-driven transistor.

[0017] Preferably, the body driving transistor M 3d Body-driven transistor M 4d Body-driven transistor M 3e Body-driven transistor M 4e Both the body drive transistor M6 and the N-type field-effect transistor M SN and N-type field-effect transistor M DN Composition, the N-type field-effect transistor M SN and N-type field-effect transistor M DN The gate of the N-type field-effect transistor M is connected to the gate of the body driving transistor. SN The source of the N-type field-effect transistor M is used as the source of the body-driven transistor. SN The drain of the N-type field-effect transistor M DN The source terminal of the N-type field-effect transistor M is connected to the body terminal of the body-driven transistor. DN The drain of the transistor is used as the drain of the body-driven transistor.

[0018] Preferably, the comparator is a dual-tailed dynamic clock comparator.

[0019] Preferably, the digital correlator includes: A shift register array, which consists of multiple cascaded flip-flops, is used to shift and store received digital decision signals under the control of a clock signal. The XOR comparison network includes multiple XOR logic units for performing bit-by-bit XOR operations on the received code output by the shift register array and the corresponding wake-up code. The Hamming distance statistical unit is used to accumulate and statistically analyze all XOR results to obtain the Hamming distance between the received codeword and the wake-up code; The threshold decision unit includes two sets of adjustable capacitor arrays and a comparator structure; wherein, one set of adjustable capacitor arrays is used to generate an analog voltage corresponding to the Hamming distance, and the other set of adjustable capacitor arrays is used to generate an adjustable reference threshold voltage; the comparator structure compares the analog voltage and the adjustable reference threshold voltage and outputs a wake-up signal.

[0020] Beneficial effects The advantages of this invention are: 1. This invention employs a gate-biased envelope detector with single-ended input pseudo-differential input. Compared to the simple single-ended input single-ended output envelope detectors used in the prior art, the envelope detector of this invention can achieve higher conversion gain and can better control the input impedance through gate voltage adjustment, thus providing better impedance adjustment flexibility when combined with the front-end negative resistance circuit.

[0021] 2. The Q-value boosting circuit employed in this invention increases the input impedance of the envelope detector through a negative impedance structure and compensates for matching network losses. Compared to the differential cross-coupling circuit used in existing Q-value boosting techniques, this invention can be directly cascaded with a subsequent single-ended input envelope detector, solving the problem that existing envelope detectors, although single-ended input, cannot be cascaded. Furthermore, the novel single-ended input, single-ended output Q-value boosting circuit proposed in this invention eliminates the need for an additional dummy circuit for cascading differential cross-coupling Q-value boosting circuits, as required in existing technologies. Therefore, the envelope detector and Q-value boosting circuit structure of this invention not only further saves power consumption but also effectively improves the passive voltage gain of the matching network and system sensitivity.

[0022] 3. In order to achieve ultra-low power supply voltage, this invention employs a bulk-driven baseband amplifier at the baseband amplifier stage, thereby effectively reducing the system power supply voltage and enabling the receiver to operate under lower power supply voltage conditions. This makes it suitable for integration with energy harvesting systems to achieve a fully passive wake-up receiver. At the same time, transconductance enhancement technology is used to improve the problem of insufficient gain in traditional bulk-driven amplifiers. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the circuit structure of the 2.4GHz wake-up receiver with ultra-low power supply voltage according to the present invention. Figure 2 This is a schematic diagram of the on-chip pseudo-differential gate bias envelope detector circuit of the present invention; Figure 3 This is a schematic diagram of the pseudo-resistance equivalent structure of the present invention; Figure 4 This is a circuit diagram of the Q-value enhancement circuit of the present invention; Figure 5This is a schematic diagram of the body-driven baseband amplifier circuit of the present invention; Figure 6 This is a schematic diagram of the equivalent structure of the P-type body drive transistor of the present invention; Figure 7 This is a schematic diagram of the equivalent structure of the N-type body drive transistor of the present invention; Figure 8 This is a schematic diagram of the comparator circuit of the present invention; Figure 9 This is a schematic diagram of the digital correlator circuit structure of the present invention. Detailed Implementation

[0024] The present invention will be further described below with reference to embodiments, but this does not constitute any limitation on the present invention. Any limited modifications made by any person within the scope of the claims of the present invention are still within the scope of the claims of the present invention. See Figure 1 The present invention discloses a 2.4GHz wake-up receiver with ultra-low power supply voltage, characterized in that it includes an on-chip pseudo-differential gate bias envelope detector, a Q-value boosting circuit, a body-driven baseband amplifier, a comparator, and a digital correlator.

[0025] In this embodiment, the signal flow process of the 2.4GHz wake-up receiver with ultra-low power supply voltage is as follows: A single-ended Q-value boosting circuit is introduced in the pre-stage of the on-chip pseudo-differential gate bias envelope detector to compensate for the equivalent loss of the pre-stage matching network. The externally input OOK modulated RF signal is input to the on-chip pseudo-differential gate bias envelope detector for envelope detection after passing through the matching network, so as to convert the OOK modulated RF signal into a baseband signal; the baseband signal is amplified by the body-driven baseband amplifier and then input to the comparator for digital decision; the digital signal after decision is input to the digital correlator for correlation matching with the preset wake-up code, and a wake-up signal is output when the match is successful.

[0026] Compared to envelope detectors in traditional receivers, the envelope detector of this invention employs a pseudo-differential passive structure and features an adjustable gate bias voltage. The differential output structure enhances the conversion gain, while the adjustable gate bias voltage regulates the conduction state and sensitivity of the envelope detector, thereby improving system robustness. Furthermore, the Q-value boosting circuit of this invention uses a negative impedance structure to generate an equivalent negative resistance at the input of the envelope detector. This equivalent negative resistance is further used to compensate for matching network losses and improve the passive voltage gain of the matching network. Finally, for the amplifier, this invention employs a bulk-driven baseband amplifier, primarily utilizing a transconductance boosting circuit to enhance the equivalent transconductance and amplification gain under the bulk-driven structure. This design enables the wake-up receiver to operate at ultra-low supply voltages below 0.4 V.

[0027] The circuit structure of each part will be described in detail below with reference to the attached diagram.

[0028] like Figure 2 As shown, the on-chip pseudo-differential gate bias envelope detector (also referred to as envelope detector in this document) in this embodiment includes a first detection branch, a second detection branch, and a gate bias network.

[0029] The first detection branch consists of N field-effect transistors M na Composition, field-effect transistor M 1a The drain is grounded, and the field-effect transistor M na The source and field-effect transistor M （n+1）a The drains of the transistors are connected, and the field-effect transistor M... na The source and field-effect transistor M （n+1）a The drain terminal is connected through capacitor C mA The radio frequency signal RFIN output by the matching network is connected to the field-effect transistor M. Na The source of the signal serves as the differential envelope voltage V in the baseband signal. OUTP The output terminal; in the N field-effect transistors M na In the diagram, N represents an odd number of field-effect transistors M. na Each of the field-effect transistors has a gate bias network connected to its gate, and N is an even number. na The gates of all transistors are connected to the gate bias voltage signal VGB of the envelope detector. The gate bias voltage signal VGB of the envelope detector is supplied by an external power supply. This bias voltage signal can effectively adjust the gate voltage of the transistors in the envelope detector, thereby adjusting its input impedance and giving it a certain degree of robustness. In the N field-effect transistors M... na In the diagram, N represents an even number of field-effect transistors M. na The source of each is connected to a capacitor C. mk Grounding. The second detector branch consists of N field-effect transistors M. nb Composition, field-effect transistor M 1b The source is grounded, and the field-effect transistor M nb The drain and field-effect transistor M （n+1）b The source is connected, and the field-effect transistor M nb The drain and field-effect transistor M （n+1）b The source terminal is connected through capacitor C mB The radio frequency signal RFIN output by the matching network is connected to the field-effect transistor M. Nb The drain is grounded as the differential envelope voltage V in the baseband signal. OUTN The output terminal; in the N field-effect transistors M nb In the diagram, N represents an odd number of field-effect transistors M. nb The gate of each of the field-effect transistors is connected to the signal VGB, and N is an even number of M. nbA gate bias network is connected to the gate of each of the N field-effect transistors M. nb In the diagram, N represents an even number of field-effect transistors M. nb The drain of each electrode is connected to a capacitor C. mj Grounding.

[0030] Both the first and second detection branches are formed by cascading multiple NMOS transistors. The two NMOS detection chains have opposite connection directions, thereby rectifying and detecting different polarity components of the input RF signal respectively. Furthermore, the first detection branch generates a first differential envelope voltage V. OUTP The second detector branch generates the second differential envelope voltage V. OUTN These two envelope signals together constitute the pseudo-differential output signal, i.e., the baseband signal, which is then sent to the subsequent amplifier for processing. Due to the pseudo-differential structure, the common-mode noise components in the two output signals can be effectively suppressed during the subsequent differential amplification process, thereby improving the anti-interference capability and detection accuracy of the wake-up receiver.

[0031] The gate bias network of the on-chip pseudo-differential gate bias envelope detector in this embodiment includes a pseudo-resistor R. mc and capacitor C mc The pseudo resistor R mc and capacitor C mc One end is connected, and the pseudo resistor R mc and capacitor C mc One end of the connection is connected to the field-effect transistor M. mc The gate connection; the pseudo resistor R mc The other end is connected to signal VGB, and the capacitor C mc The other end is connected to the radio frequency signal RFIN output from the matching network. Where N is a natural number greater than or equal to 1; n∈1,...,N; c is a or b; m∈1,...,M, M=N / 2.

[0032] In short, the gate bias network in this embodiment consists of a resistor network and a capacitor network. On one hand, it establishes the DC bias potential of the detector transistor's gate; on the other hand, it provides an AC coupling path for the input RF signal, allowing the RF signal to act on each stage of the detector transistor simultaneously. By adjusting the bias voltage, the equivalent threshold condition of the detector transistor can be changed, thereby improving the detector's response to weak input signals.

[0033] Furthermore, such as Figure 3 As shown, the pseudo resistor R in this embodiment nc By field-effect transistor M Ac and field-effect transistor M Bc Composition. Field-effect transistor M Ac and field-effect transistor M Bc The source terminals are respectively used as pseudo resistors Rnc At both ends, the field-effect transistor M Ac and field-effect transistor M Bc The four electrodes, namely the gate and drain, are connected together.

[0034] Compared with traditional single-ended envelope detectors, this invention uses a dual NMOS detector chain with opposite directions to achieve pseudo-differential output, which can achieve better common-mode noise suppression without additional active power consumption and significantly improve conversion gain. At the same time, it uses an on-chip gate bias adjustment network to optimize the detector operating point and improve the detection sensitivity under weak signal conditions, making it suitable for ultra-low power wake-up receiver systems.

[0035] like Figure 4 As shown, the Q-boosting circuit includes field-effect transistors M1, M2, M3, M4, and N field-effect transistors M1, M2, M3, M4, and N other field-effect transistors M1, M2, M3, M4, and M5. an The drain of MOSFET M1 is connected to a voltage source, and the gate of MOSFET M1 receives the first SPI switch signal. The source of MOSFET M1 is simultaneously connected to the drains of MOSFETs M2 and M3. The gate of MOSFET M2 is an input bit connected to the line between the on-chip pseudo-differential gate bias envelope detector and the matching network. The source of MOSFET M2 is simultaneously connected to the gate of MOSFET M3 and the drain of MOSFET M4. a1 The drain connection of the field-effect transistor M3, the source of the field-effect transistor M a1 The source of N field-effect transistors M4 is connected to the drain of M4, the gate of M4 is connected to a voltage source, and the source of M4 is grounded. an The gates of all M transistors are respectively input with SPI switch signals. an The drains of all field-effect transistors M are connected. an The source and the source are connected. That is, M a1 To M aN It consists of an array of N field-effect transistors, each controlled by an SPI switch signal. By adjusting the SPI switch signal, the number of transistors in the array can be adjusted, thereby regulating the negative impedance.

[0036] The Q-value boosting circuit of this single-ended interface uses M2, M3, M4, and M... aN By implementing negative feedback with transistors, the input impedance becomes negative, making the Q-boosting circuit more streamlined compared to the original differential negative impedance circuit. Furthermore, this single-ended interface Q-boosting circuit introduces this negative impedance circuit at the envelope detector input, making it equivalently exhibit negative resistance characteristics, thereby compensating for the equivalent losses of the preceding matching network.

[0037] Specifically, this negative impedance Q-boosting circuit works synergistically with the matching network to improve the equivalent quality factor (Q-value) of the matching network without changing its center frequency, thereby offsetting the conduction losses and energy attenuation in the passive matching network to some extent. The equivalent result is a reduction in the insertion loss of the matching network and an increase in the passive voltage gain.

[0038] Furthermore, because the equivalent negative resistance at the input terminal partially cancels out the input impedance, the overall equivalent input impedance of the envelope detector is increased. This reduces the loading effect of the matching network on the signal source and increases the voltage swing of the signal before it enters the detector. Therefore, this structure can effectively increase the signal voltage amplitude at the input of the envelope detector without additional active amplification, thereby improving the overall receiving sensitivity.

[0039] Furthermore, by adding a switching transistor, namely a field-effect transistor M1, to the power supply of the circuit, the power supply can be turned on / off via SPI, thereby controlling whether the circuit works.

[0040] Furthermore, the circuit incorporates a transistor array, namely N field-effect transistors M aN The complex impedance value generated by the circuit can be effectively adjusted through SPI control, thus allowing for more flexible circuit adjustment.

[0041] The core design principle for achieving ultra-low power supply voltage lies in the fact that, since the envelope detector in the wake-up receiver system uses a passive structure, and the clock comparator and digital correlator are digital modules, they are relatively less affected by the power supply voltage. Therefore, the main module ultimately limiting the reduction of the system's power supply voltage is the baseband amplifier. Traditional baseband amplifiers operate using gate input, but their source-drain voltage limits the lowest achievable power supply voltage. To reduce the overall system power supply voltage, this invention proposes a bulk-driven baseband amplifier.

[0042] like Figure 5 As shown, the body-driven baseband amplifier specifically includes a body-driven transistor M. 1d Body-driven transistor M 2d Body-driven transistor M 3d Body-driven transistor M 4d Body-driven transistor M 1e Body-driven transistor M 2e Body-driven transistor M 3e Body-driven transistor M 4e Body drive transistor M5, body drive transistor M6, and capacitor C3. Body drive transistor M... 1d Body-driven transistor M 2d Body-driven transistor M 1e Body-driven transistor M 2eThe source of the body drive transistor M5 is simultaneously connected to a voltage source, and the body drive transistor M... 1d Body-driven transistor M 1e The body terminal is simultaneously connected to the differential envelope voltage V in the baseband signal. OUTP Body drive transistor M 2d Body-driven transistor M 2e The body terminal is simultaneously connected to the differential envelope voltage V in the baseband signal. OUTN Body drive transistor M 2e Body-driven transistor M 1d The gate is connected to the body drive transistor M. 1e Body-driven transistor M 2d The gate is connected to the body drive transistor M. 2e The drain of the body-driven transistor M is simultaneously connected to the body-driven transistor M. 4d Gate and drain, body drive transistor M 4e Gate connection, body drive transistor M 1e Drain and body drive transistor M 4e The drain of the body-driven transistor M5, the gate of the body-driven transistor M6, and one end of capacitor C3 are connected together. The other end of capacitor C3 serves as the output terminal of the body-driven baseband amplifier and is simultaneously connected to the drains of both body-driven transistor M5 and M6. The gate of body-driven transistor M5 receives the gate bias voltage signal VBP, which is provided by an external power supply. The magnitude of this bias voltage determines the current of the second-stage amplifier. 1d Drain and body drive transistor M 3d The drain connection, body drive transistor M 2d Drain and body drive transistor M 3e The drain connection, body drive transistor M 3d and body drive transistor M 3e The gate of the transistor is simultaneously connected to a gate bias voltage signal VBN, which is provided by an external power supply. The magnitude of this bias voltage determines the current of the first-stage amplifier. The body drive transistor M... 4d Body-driven transistor M 3d Body-driven transistor M 3e Body-driven transistor M 4e The source of the body drive transistor M6 is grounded.

[0043] In the body-driven baseband amplifier, the baseband signal is applied to the input transistor M. 1d M 1e， M 2d， M 2eThe body terminal modulates the drain current by changing the threshold voltage through the body effect. That is, when the baseband signal changes, the input differential level generates a corresponding current difference, which is then converted into a differential output voltage signal under the action of an active load. The body drive structure of this invention can effectively reduce the minimum operating voltage and mitigate the gain reduction problem caused by insufficient overdrive voltage in traditional gate drive structures under low voltage conditions, making it particularly suitable for ultra-low power wake-up receiver systems.

[0044] Furthermore, conventional body-driven amplifiers often have limited gain due to their low body transconductance. This invention proposes a transconductance enhancement technique to improve the gain of body-driven amplifiers. Compared to traditional body-driven amplifiers, this invention amplifies the differential input signal through two sets of transistor paths, thereby increasing the input transconductance and improving the overall gain. These paths are: M... 1d M 1e The body input terminal corresponds to the differential VIN input (i.e., the differential envelope voltage V in the baseband signal). OUTN ); M 2d， M 2e The body input terminal corresponds to the differential VIP input (i.e., the differential envelope voltage V in the baseband signal). OUTP This allows for a twofold increase in transconductance.

[0045] Furthermore, the body-driven transistor proposed in this invention is divided into two stages, and all MOS transistors in both stages employ self-cascading technology, such as... Figure 6 and Figure 7 As shown in the figure. This technology splits the original transistor into two series transistors, increasing the output impedance while keeping the total transistor size unchanged, thereby increasing the gain.

[0046] See Figure 6 Body drive transistor M 1d Body-driven transistor M 2d Body-driven transistor M 1e Body-driven transistor M 2e Both the body drive transistor M5 and the P-type field-effect transistor M SP and P-type field-effect transistor M DP Composition. P-type field-effect transistor M SP and P-type field-effect transistor M DP The gate of the P-type field-effect transistor M is connected to the gate of the body drive transistor. SP The source of the P-type field-effect transistor is used as the source of the body-driven transistor. SP The drain of the P-type field-effect transistor M DP The source terminal of the P-type field-effect transistor is connected to the body terminal of the body-driven transistor. DP The drain of the transistor is used as the drain of the body-driven transistor.

[0047] See Figure 7 Body drive transistor M 3d Body-driven transistor M 4d Body-driven transistor M 3e Body-driven transistor M 4e Both the body drive transistor M6 and the N-type field-effect transistor M SN and N-type field-effect transistor M DN Composition. N-type field-effect transistor M SN and N-type field-effect transistor M DN The gate of the N-type field-effect transistor M is connected to the gate of the body drive transistor. SN The source of the N-type field-effect transistor M is used as the source of the body-driven transistor. SN The drain of the N-type field-effect transistor M DN The source terminal of the N-type field-effect transistor is connected to the body terminal of the body-driven transistor. DN The drain of the transistor is used as the drain of the body-driven transistor.

[0048] The following is a description of the comparator used in this invention.

[0049] In this embodiment, the comparator is a dual-tailed dynamic clock comparator, and its specific circuit structure is as follows: Figure 8 As shown, the dual-tailed dynamic clock comparator mainly includes an input differential stage and a dynamic regenerative latch stage. The input differential stage receives the differential input signal and, under the control of the clock signal, converts the input voltage difference into a voltage difference at an intermediate node. The dynamic regenerative latch stage is coupled to the input differential stage and is used to perform positive feedback regenerative amplification of the voltage difference, thereby outputting a full-swing digital decision signal.

[0050] Specifically, this embodiment employs a dual-tailed comparator structure, where the input stage tail current transistor and the latch stage tail current transistor are controlled by clock signals respectively, thereby separating the input sampling stage from the latch regeneration stage. This structure effectively reduces coupling interference between the input stage and the latch stage, improving the comparator's operational stability and speed performance under low power supply voltages.

[0051] Furthermore, an intermediate floating node is set between the input stage and the latch stage to reduce kickback noise caused by clock switching and latch regeneration during dynamic comparison, thereby reducing the comparator's interference to the preceding stage and improving the overall sensitivity of the wake-up receiver.

[0052] Furthermore, this dual-tailed comparator also includes an isolation transistor for suppressing input backflip noise. The isolation transistor is positioned between the input transistor and the dynamic latch node, suppressing charge backfeeding from the internal high-speed switching node to the input during the latch regeneration phase, thereby reducing input voltage disturbances.

[0053] During the operation of the dual-tailed dynamic clock comparator, in the reset phase, the clock signal is in the first state, the internal nodes are pre-charged to a predetermined potential, and the latch stage is in the reset state; in the comparison phase, the clock signal switches to the second state, the input differential pair forms a small voltage difference at the intermediate node according to the magnitude of the input signal, and then the latch stage quickly completes regeneration amplification through cross-coupled positive feedback and outputs the corresponding digital decision signal.

[0054] The dynamic dual-tailed comparator described in this invention requires no static bias current and consumes dynamic power only during clock transitions, making it suitable for ultra-low-power wake-up receiver systems. Compared to traditional StrongARM comparators, this invention, through its dual-tailed structure and noise suppression mechanism, achieves higher comparison speed, lower kickback noise, and better input isolation performance under low supply voltage conditions.

[0055] like Figure 9 As shown, the digital correlator includes a shift register array, an XOR comparison network, a Hamming distance statistics unit, and a threshold decision unit. In this embodiment, the digital correlator uses a 16-bit correlation length. The received codeword is compared bit by bit with the 16-bit on-chip identification code, and the Hamming distance is calculated from the 16-bit XOR result. When the statistical result is less than a preset threshold, a valid correlation detection signal is output to start the subsequent receiver.

[0056] The shift register array consists of cascaded multi-stage flip-flops, used to shift and store the received digital decision signal under the control of a clock signal. Input data is sequentially written to each stage register under the drive of clocks CLK0 / CLK1, thus forming a receive codeword of length N bits.

[0057] It should be noted that the digital correlator pre-stores the on-chip identification code (Chip ID, i.e., wake-up code) for the corresponding receiving node. This on-chip identification code and the received codeword output from the shift register are respectively input to the XOR comparison network. The XOR comparison network includes multiple XOR logic units, used to perform a bitwise XOR operation between each bit of the received code output from the shift register array and the corresponding wake-up code. When the two bits of data are inconsistent, the corresponding output logic "1" is output; when the two bits of data are consistent, the corresponding output logic "0" is output.

[0058] The Hamming distance statistics unit is used to accumulate and count all XOR results to obtain the Hamming distance between the received codeword and the wake-up code. The Hamming distance represents the number of different bits between the two sets of codewords.

[0059] The threshold decision unit includes two sets of adjustable capacitor arrays and a comparator structure. One set of adjustable capacitor arrays is used to generate an analog voltage corresponding to the Hamming distance, and the other set of adjustable capacitor arrays is used to generate an adjustable reference threshold voltage. The comparator structure compares the analog voltage and the adjustable reference threshold voltage and outputs the relevant decision result.

[0060] When the Hamming distance is less than a preset threshold, the received wake-up code is determined to match the on-chip identification code, and the digital correlator outputs a valid wake-up signal; when the Hamming distance is greater than the threshold, it is determined to be an invalid codeword or interference signal, and the system wake-up is not triggered.

[0061] This invention employs a Hamming distance-based correlation detection method, which, compared to the traditional perfectly matched structure, allows for a certain number of bit errors in the received codewords, thus improving the system's detection reliability in low signal-to-noise ratio environments. Furthermore, by setting an adjustable threshold, a flexible trade-off can be made between false wake-up rate and false detection rate according to actual application requirements. In addition, the digital correlator uses a fully digital shift register structure and a dynamic comparison structure, generating dynamic power consumption only during clock switching, thereby effectively reducing the overall system power consumption and making it suitable for ultra-low power wake-up receiver systems.

[0062] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several modifications and improvements without departing from the structure of the present invention, and these will not affect the effectiveness of the implementation of the present invention or the practicality of the patent.

Claims

1. A 2.4GHz wake-up receiver with ultra-low power supply voltage, characterized in that, It includes an on-chip pseudo-differential gate bias envelope detector, a Q-value boosting circuit, a body-driven baseband amplifier, a comparator, and a digital correlator; A single-ended Q-value boosting circuit is introduced before the on-chip pseudo-differential gate bias envelope detector. The externally input OOK modulated RF signal is input to the on-chip pseudo-differential gate bias envelope detector after passing through a matching network for envelope detection, so as to convert the OOK modulated RF signal into a baseband signal. The baseband signal is amplified by the body-driven baseband amplifier and then input to the comparator for digital decision, resulting in a digital decision signal. The digital decision signal is input to the digital correlator and correlated with a preset wake-up code. When the match is successful, a wake-up signal is output.

2. The 2.4GHz wake-up receiver with ultra-low power supply voltage according to claim 1, characterized in that, The on-chip pseudo-differential gate bias envelope detector includes a first detection branch, a second detection branch, and a gate bias network. The first detection branch consists of N field-effect transistors M na Composition, field-effect transistor M 1a The drain is grounded, and the field-effect transistor M na The source and field-effect transistor M （n+1）a The drains of the transistors are connected, and the field-effect transistor M... na The source and field-effect transistor M （n+1）a The drain terminal is connected through capacitor C mA The radio frequency signal RFIN output by the access matching network, and the field effect transistor M Na The source of the signal serves as the differential envelope voltage V in the baseband signal. OUTP The output terminal; in the N field-effect transistors M na In the diagram, N represents an odd number of field-effect transistors M. na Each of the field-effect transistors has a gate bias network connected to its gate, and N is an even number. na The gates of all devices are connected to the gate bias voltage signal VGB of the envelope detector. The second detection branch consists of N field-effect transistors M nb Composition, field-effect transistor M 1b The source is grounded, and the field-effect transistor M nb The drain and field-effect transistor M （n+1）b The source is connected, and the field-effect transistor M nb The drain and field-effect transistor M （n+1）b The source terminal is connected through capacitor C mB The radio frequency signal RFIN output by the access matching network, and the field effect transistor M Nb The drain is grounded as the differential envelope voltage V in the baseband signal. OUTN The output terminal; in the N field-effect transistors M nb In the diagram, N represents an odd number of field-effect transistors M. nb The gate of each of the field-effect transistors is connected to the signal VGB, and N is an even number of M. nb Each of the gates is connected to a gate bias network; The gate bias network includes a pseudo-resistor R. mc and capacitor C mc The pseudo resistor R mc and capacitor C mc One end is connected, and the pseudo resistor R mc and capacitor C mc One end of the connection is connected to the field-effect transistor M. mc The gate connection; the pseudo resistor R mc The other end is connected to signal VGB, and the capacitor C mc The other end is connected to the radio frequency signal RFIN output from the matching network; Where N is a natural number greater than 1; n∈1,...,N; c is a or b; m∈1,...,M, M=N / 2.

3. A 2.4GHz wake-up receiver with ultra-low power supply voltage according to claim 2, characterized in that, The pseudo resistor R nc By field-effect transistor M Ac and field-effect transistor M Bc Composition, the field-effect transistor M Ac and field-effect transistor M Bc The source terminals are respectively used as pseudo resistors R nc At both ends, the field-effect transistor M Ac and field-effect transistor M Bc The four electrodes, namely the gate and drain, are connected together.

4. A 2.4GHz wake-up receiver with ultra-low power supply voltage according to claim 2, characterized in that, In N field-effect transistors M na In the diagram, N represents an even number of field-effect transistors M. na The source of each is connected to a capacitor C. mk Grounding; in the N field-effect transistors M nb In the diagram, N represents an even number of field-effect transistors M. nb The drain of each electrode is connected to a capacitor C. mj Grounding.

5. A 2.4GHz wake-up receiver with ultra-low power supply voltage according to claim 1, characterized in that, The Q-value boosting circuit includes field-effect transistors M1, M2, M3, M4, and N field-effect transistors M1, M2, M3, M4, and N field-effect transistors M1, M2, M3, M4, and M5. an The drain of the field-effect transistor M1 is connected to a voltage source. The gate of the field-effect transistor M1 receives the first SPI switch signal. The source of the field-effect transistor M1 is simultaneously connected to the drains of both field-effect transistors M2 and M3. The gate of the field-effect transistor M2 is an input bit connected to the line between the on-chip pseudo-differential gate bias envelope detector and the matching network. The source of the field-effect transistor M2 is simultaneously connected to the gate of the field-effect transistor M3 and the drain of the field-effect transistor M4. a1 The drain connection of the field-effect transistor M3, the source of the field-effect transistor M a1 The source of N transistors M4 is connected to the drain of the field-effect transistor M4, the gate of the field-effect transistor M4 is connected to a voltage source, and the source of the field-effect transistor M4 is grounded. an The gates of all M transistors are respectively input with SPI switch signals. an The drains of all field-effect transistors M are connected. an The source poles are connected.

6. A 2.4GHz wake-up receiver with ultra-low power supply voltage according to claim 1, characterized in that, The body-driven baseband amplifier includes a body-driven transistor M. 1d Body-driven transistor M 2d Body-driven transistor M 3d Body-driven transistor M 4d Body-driven transistor M 1e Body-driven transistor M 2e Body-driven transistor M 3e Body-driven transistor M 4e Body drive transistor M5, body drive transistor M6, and capacitor C3; the body drive transistor M... 1d Body-driven transistor M 2d Body-driven transistor M 1e Body-driven transistor M 2e The source of the body driving transistor M5 is simultaneously connected to a voltage source. 1d Body-driven transistor M 1e The body terminal is simultaneously connected to the differential envelope voltage V in the baseband signal. OUTP The body drive transistor M 2d Body-driven transistor M 2e The body terminal is simultaneously connected to the differential envelope voltage V in the baseband signal. OUTN The body drive transistor M 2e Body-driven transistor M 1d The gate of the body driving transistor M is connected to the gate of the body driving transistor M. 1e Body-driven transistor M 2d The gate of the body driving transistor M is connected to the gate of the body driving transistor M. 2e The drain of the transistor M is simultaneously connected to the body drive transistor. 4d Gate and drain, body drive transistor M 4e The gate connection of the body driving transistor M 1e The drain of the transistor M is simultaneously connected to the body drive transistor. 4e The drain of the body-driven transistor M5, the gate of the body-driven transistor M6, and one end of capacitor C3 are connected together. The other end of capacitor C3 serves as the output terminal of the body-driven baseband amplifier and is simultaneously connected to the drain of both the body-driven transistor M5 and the drain of the body-driven transistor M6. The gate of the body-driven transistor M5 receives the gate bias voltage signal VBP. The body-driven transistor M6... 1d Drain and body drive transistor M 3d The drain connection of the body drive transistor M 2d Drain and body drive transistor M 3e The drain connection of the body drive transistor M 3d and body drive transistor M 3e The gate is simultaneously connected to the gate bias voltage signal VBN; the body driving transistor M 4d Body-driven transistor M 3d Body-driven transistor M 3e Body-driven transistor M 4e The source of the body-driven transistor M6 is grounded.

7. A 2.4GHz wake-up receiver with ultra-low power supply voltage according to claim 6, characterized in that, The body drive transistor M 1d Body-driven transistor M 2d Body-driven transistor M 1e Body-driven transistor M 2e Both the body drive transistor M5 and the P-type field-effect transistor M SP and P-type field-effect transistor M DP Composition, the P-type field-effect transistor M SP and P-type field-effect transistor M DP The gate of the P-type field-effect transistor M is connected to the gate of the body driving transistor. SP The source of the P-type field-effect transistor M is used as the source of the body-driven transistor. SP The drain of the P-type field-effect transistor M DP The source terminal of the P-type field-effect transistor M is connected to the body terminal of the body-driven transistor. DP The drain of the transistor is used as the drain of the body-driven transistor.

8. A 2.4GHz wake-up receiver with ultra-low power supply voltage according to claim 6, characterized in that, The body drive transistor M 3d Body-driven transistor M 4d Body-driven transistor M 3e Body-driven transistor M 4e Both the body drive transistor M6 and the N-type field-effect transistor M SN and N-type field-effect transistor M DN Composition, the N-type field-effect transistor M SN and N-type field-effect transistor M DN The gate of the N-type field-effect transistor M is connected to the gate of the body driving transistor. SN The source of the N-type field-effect transistor M is used as the source of the body-driven transistor. SN The drain of the N-type field-effect transistor M DN The source terminal of the N-type field-effect transistor M is connected to the body terminal of the body-driven transistor. DN The drain of the transistor is used as the drain of the body-driven transistor.

9. A 2.4GHz wake-up receiver with ultra-low power supply voltage according to claim 1, characterized in that, The comparator is a dual-tailed dynamic clock comparator.

10. A 2.4GHz wake-up receiver with ultra-low power supply voltage according to claim 1, characterized in that, The digital correlator includes: A shift register array, which consists of multiple cascaded flip-flops, is used to shift and store received digital decision signals under the control of a clock signal. The XOR comparison network includes multiple XOR logic units for performing bit-by-bit XOR operations on the received code output by the shift register array and the corresponding wake-up code. The Hamming distance statistical unit is used to accumulate and statistically analyze all XOR results to obtain the Hamming distance between the received codeword and the wake-up code; The threshold decision unit includes two sets of adjustable capacitor arrays and a comparator structure; wherein, one set of adjustable capacitor arrays is used to generate an analog voltage corresponding to the Hamming distance, and the other set of adjustable capacitor arrays is used to generate an adjustable reference threshold voltage; the comparator structure compares the analog voltage and the adjustable reference threshold voltage and outputs a wake-up signal.

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