A method for collecting synchronization and a collecting and transmitting device

Abstract

The application discloses a kind of acquisition synchronization method and acquisition transmission equipment, it is related to data communication field, including controlling first level relay unit to generate synchronization pulse sequence and downlink transmission;For each relay unit after first level relay unit, extract the frequency and edge phase reference of the synchronization pulse sequence transmitted by last level relay unit;Based on the frequency and edge phase reference of the synchronization pulse sequence transmitted by last level relay unit, control each relay unit to generate synchronization pulse sequence and downlink transmission;Based on the local clock signal of acquisition module received by synchronization pulse sequence to acquisition module, carry out calibration;Based on the deviation between the local clock signal of acquisition module and the synchronization pulse sequence received by acquisition module, control last level relay unit to modify the original time stamp of acquisition module, obtain the modified time stamp of acquisition module, so that the sampling time of all acquisition modules corresponding to last level relay unit is synchronized on time axis.

Description

Technical Field

[0001] This application relates to the field of data communication technology, and in particular to a data acquisition synchronization method and a data acquisition and transmission device. Background Technology

[0002] In long-distance, multi-node distributed data acquisition applications, it is often necessary to deploy a large number of acquisition nodes along the transmission path to form a complete serial cascaded acquisition network. Each acquisition node in the acquisition network needs a unified clock reference in order to accurately align the multi-source acquired data and perform subsequent analysis and processing.

[0003] Currently, clock synchronization methods in serial cascaded acquisition networks typically employ three approaches: exchanging synchronization messages between devices using time protocols, directly distributing hardware synchronization pulses by laying additional dedicated synchronization cables, or embedding synchronization information in the service data encoding so that the synchronization signal is transmitted along with the service data.

[0004] However, when using time protocols to exchange synchronization messages between devices, the synchronization signal is affected by protocol stack scheduling delays and channel transmission delay jitter. After being forwarded by multiple relay devices, the jitter of storage-forward delays accumulates at each level, significantly degrading the synchronization accuracy of deep-level acquisition nodes. While dedicated synchronization cable solutions can avoid protocol layer jitter, they are costly, and the synchronization signal is prone to waveform distortion during long-distance transmission. Furthermore, due to the lack of a step-by-step regeneration mechanism, signal quality decreases with increasing cascading depth. Encoded synchronization embeds synchronization information into the service data encoding, with the synchronization signal sharing the same physical channel as the service data. In long-distance half-duplex bus scenarios, this is susceptible to bus arbitration and data frame collisions, making it difficult to guarantee synchronization accuracy.

[0005] Therefore, how to improve the clock synchronization accuracy of serial cascaded acquisition networks at low cost is a technical problem that urgently needs to be solved. Summary of the Invention

[0006] The main purpose of this application is to provide a data acquisition synchronization method and data acquisition transmission device, aiming to improve the clock synchronization accuracy of serial cascaded data acquisition networks at low cost.

[0007] This application provides a data acquisition synchronization method applied to a data acquisition and transmission device, the data acquisition and transmission device including multiple cascaded relay units and multiple data acquisition modules; a half-duplex bus is connected between each pair of adjacent relay units, and at least one data acquisition module is connected to the half-duplex bus between each pair of adjacent relay units; The method includes: The system controls the first-level relay unit to generate a synchronization pulse sequence, and transmits the synchronization pulse sequence generated by the first-level relay unit downlink via a half-duplex bus connected to the first-level relay unit. For each relay unit after the first-level relay unit, the frequency and edge phase reference of the synchronization pulse sequence transmitted by the previous-level relay unit are extracted by sampling the level transition on the half-duplex bus connected to the relay unit. Based on the frequency and edge phase reference of the synchronization pulse sequence transmitted by the previous level relay unit of each relay unit, each relay unit is controlled to generate its own synchronization pulse sequence, and the synchronization pulse sequence generated by the relay unit is transmitted downlink through the next level half-duplex bus connecting each relay unit. For any of the acquisition modules, the local clock signal of the acquisition module is calibrated based on the synchronization pulse sequence received by the acquisition module, and the deviation between the local clock signal of the acquisition module and the synchronization pulse sequence received by the acquisition module, and the original timestamp of the acquisition module are uploaded to the upstream relay unit corresponding to the acquisition module. Based on the deviation between the local clock signal of the acquisition module and the synchronization pulse sequence received by the acquisition module, the upstream relay unit corresponding to the acquisition module is controlled to correct the original timestamp of the acquisition module, so as to obtain the corrected timestamp of the acquisition module, so that the sampling time of all acquisition modules corresponding to the upstream relay unit of the acquisition module is synchronized on the time axis.

[0008] In one embodiment, before the step of calibrating the local clock signal of any acquisition module based on the synchronization pulse sequence received by the acquisition module, and uploading the deviation between the local clock signal of the acquisition module and the synchronization pulse sequence received by the acquisition module, and the original timestamp of the acquisition module to the upstream relay unit corresponding to the acquisition module, the method further includes: The control module obtains the occurrence time and direction of each level transition in the synchronization pulse sequence transmitted by the corresponding upstream relay unit by sampling the level transition on the half-duplex bus connected to the acquisition module. For any of the acquisition modules, the duration between each two adjacent levels is determined based on the occurrence time and direction of each level transition in the synchronization pulse sequence transmitted by the upstream relay unit corresponding to the acquisition module. When the level transition sequence and duration of each level transition are consistent with the level transition sequence and duration of the preset valid signal, the synchronization pulse sequence transmitted by the upstream relay unit corresponding to the acquisition module is taken as the synchronization pulse sequence received by the acquisition module.

[0009] In one embodiment, the step of calibrating the local clock signal of the acquisition module based on the synchronization pulse sequence received by the acquisition module includes: Based on the arrival times of two adjacent pulses in the synchronization pulse sequence received by the acquisition module, the arrival time interval between the two adjacent pulses is determined. Based on the arrival time interval, the actual physical frequency of the local crystal oscillator of the acquisition module is determined; Based on the preset frequency control word and phase accumulator bit width of the acquisition module, as well as the actual physical frequency of the local crystal oscillator of the acquisition module, a first pulse signal is generated as the calibrated local clock signal of the acquisition module.

[0010] In one embodiment, after the step of generating a first pulse signal based on the preset frequency control word, phase accumulator bit width, and actual physical frequency of the local crystal oscillator of the acquisition module, as the calibrated local clock signal of the acquisition module, the method further includes: The instantaneous phase deviation value is obtained based on the pulse edge of the first pulse signal and the edge of the synchronization pulse sequence received by the acquisition module. Based on the instantaneous phase deviation value, the phase parameter of the first pulse signal is corrected by closed-loop feedback until the instantaneous phase deviation value converges to within a preset instantaneous phase deviation value threshold.

[0011] In one embodiment, the deviation value corresponding to the acquisition module includes a frequency deviation value and a phase deviation value; the step of determining the deviation value corresponding to the acquisition module includes: The difference between the actual physical frequency and the nominal frequency of the acquisition module is used as the frequency deviation value between the local clock signal of the acquisition module and the synchronization pulse sequence received by the acquisition module. The instantaneous phase deviation value after convergence is used as the phase deviation value between the local clock signal of the acquisition module and the synchronization pulse sequence received by the acquisition module.

[0012] In one embodiment, the method further includes: Based on the frequency deviation value corresponding to the acquisition module, and the continuous duration from the moment when the local clock signal of the acquisition module completes calibration to the moment when the acquisition module samples, the cumulative drift of the acquisition module is determined. The original timestamp, cumulative drift, phase deviation value corresponding to the acquisition module, and the sum of the preset transmission delay parameter of the acquisition module are used as the corrected timestamp of the acquisition module.

[0013] In one embodiment, after the step of controlling the upstream relay unit corresponding to the acquisition module to correct the original timestamp of the acquisition module based on the deviation between the local clock signal of the acquisition module and the synchronization pulse sequence received by the acquisition module, to obtain the corrected timestamp of the acquisition module, so as to synchronize the local clock signals of all acquisition modules corresponding to the upstream relay unit of the acquisition module on the time axis, the method further includes: For any relay unit, the deviation values ​​of all acquisition modules associated with the relay unit are transmitted uplink to the first-level relay unit through the first-level half-duplex bus connected to the relay unit. For any acquisition module, the acquisition information of the acquisition module is transmitted to the first-level relay unit step by step through the half-duplex bus connected to the acquisition module. The first-level relay unit is controlled to calculate the acquisition information of each acquisition module at a preset standard sampling time based on the deviation between the local clock signal of each acquisition module and the synchronization pulse sequence received by each acquisition module, the acquisition information of each acquisition module, and the acquisition information of each acquisition module, according to the interpolation algorithm.

[0014] In one embodiment, before the step of transmitting the deviation values ​​of all acquisition modules associated with the relay unit to the first-level relay unit via the preceding half-duplex bus connected to the relay unit for any relay unit, the method further includes: For any relay unit, the connectivity status of the preceding half-duplex bus connected to the relay unit is determined by sampling the level transition on the preceding half-duplex bus connected to the relay unit. When the connectivity status is that the preceding half-duplex bus connected to the relay unit is interrupted, the deviation values ​​corresponding to all acquisition modules associated with the relay unit are stored in the local register. Furthermore, when the preceding half-duplex bus connected to the relay unit is reconnected, the deviation value stored in the local register is transmitted to the preceding relay unit through the preceding half-duplex bus connected to the relay unit in the order of storage.

[0015] In one embodiment, before the step of controlling the first-level relay unit to calculate the acquisition information of each acquisition module at a preset standard sampling time based on the deviation between the local clock signal of each acquisition module and the synchronization pulse sequence received by each acquisition module, and the acquisition information of each acquisition module, according to an interpolation algorithm, the method further includes: For any of the acquisition modules, determine whether the deviation between the local clock signal of the acquisition module and the synchronization pulse sequence received by the acquisition module is less than or equal to a preset deviation threshold. If the deviation between the local clock signal of the acquisition module and the synchronization pulse sequence received by the acquisition module is less than or equal to a preset deviation threshold, the first-level relay unit is controlled to calculate the acquisition information of the acquisition module at a preset standard sampling time.

[0016] In addition, to achieve the above objectives, this application also proposes a data acquisition and transmission device, which includes: a plurality of cascaded relay units, a half-duplex bus connecting each pair of adjacent relay units, and at least one acquisition module connected to the half-duplex bus connecting each pair of adjacent relay units. Multiple data acquisition modules.

[0017] This application provides a data acquisition synchronization method applied to a data acquisition and transmission device. The data acquisition and transmission device includes multiple cascaded relay units and multiple acquisition modules. A half-duplex bus connects each pair of adjacent relay units, and at least one acquisition module is connected to each half-duplex bus between each pair of adjacent relay units. The data acquisition synchronization method includes: controlling a first-level relay unit to generate a synchronization pulse sequence, and transmitting the synchronization pulse sequence generated by the first-level relay unit downstream through the half-duplex bus connected to the first-level relay unit; for each relay unit after the first-level relay unit, sampling the level transitions on the half-duplex bus connected to the previous level of the relay unit to extract the frequency and edge phase reference of the synchronization pulse sequence transmitted by the previous level relay unit; and based on the frequency and edge phase reference of the synchronization pulse sequence transmitted by the previous level relay unit of each relay unit... The system uses a reference to control each relay unit to generate a synchronization pulse sequence, which is then transmitted downlink via the next-level half-duplex bus connecting each relay unit. For any acquisition module, the local clock signal is calibrated based on the synchronization pulse sequence received by the acquisition module, and the deviation between the local clock signal and the synchronization pulse sequence received by the acquisition module, along with the original timestamp of the acquisition module, is uploaded to the corresponding upstream relay unit. Based on the deviation between the local clock signal and the synchronization pulse sequence received by the acquisition module, the upstream relay unit corresponding to the acquisition module corrects the original timestamp of the acquisition module, resulting in a corrected timestamp, so that the sampling times of all acquisition modules corresponding to the upstream relay unit are synchronized on the time axis.

[0018] By generating a synchronization pulse sequence through the first-level relay unit and transmitting it uplink on the half-duplex bus, a unique, progressively transmittable hardware time reference source is established for the entire network. This hardware time reference source does not rely on the encoding and scheduling of the upper-layer protocol stack, fundamentally avoiding the timing uncertainties introduced by half-duplex bus arbitration and software scheduling in traditional protocol layer synchronization. Based on this, each relay unit at each level extracts the frequency and edge phase reference of the upper-level synchronization pulse sequence by sampling the level transitions of the preceding half-duplex bus. It then generates a new synchronization pulse sequence based on the extracted frequency and edge phase reference and transmits it downwards. This achieves waveform regeneration and jitter isolation during the progressive transmission of the synchronization pulse sequence, ensuring that the signal quality transmitted downwards by each relay unit does not degrade with increasing cascading depth, and guaranteeing that any acquisition module can obtain a high-quality synchronization signal. For the acquisition module, calibrating the local clock signal based on the received synchronization pulse sequence and uploading the deviation between the local clock signal and the synchronization pulse sequence along with the original timestamp of the sampling time to the acquisition module, calibrating the local clock signal based on the received synchronization pulse sequence and uploading the local clock signal to the corresponding upstream relay unit, quantifies the local clock signal state of the acquisition module into calculable deviation data and feeds it back to the corresponding upstream relay unit. This provides the relay unit with quantified input to eliminate sampling time misalignment caused by physical location differences and residual deviations of the local clock signal among the acquisition modules. Furthermore, the relay unit corrects the original timestamp of the sampling time corresponding to each acquisition module based on the deviation value reported by each acquisition module, aligning the acquired data of all acquisition modules corresponding to the same relay unit on the time axis. This ensures that the data acquired by each acquisition module can be fused, compared, and analyzed based on a consistent time reference in subsequent processes.

[0019] This acquisition synchronization method is applicable to acquisition and transmission equipment that uses a half-duplex bus to connect relay units and acquisition modules. The synchronization signal shares the half-duplex bus with the normal acquisition data in a time-division multiplexed manner, without the need for additional cabling. This achieves improved clock synchronization accuracy in serial cascaded acquisition networks at low cost. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0021] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1A flowchart illustrating the data acquisition synchronization method provided in the first embodiment of this application; Figure 2 A flowchart illustrating the data acquisition synchronization method provided in the second embodiment of this application; Figure 3 A flowchart illustrating the data acquisition synchronization method provided in the third embodiment of this application; Figure 4 This is a schematic diagram of the acquisition and transmission device involved in the embodiments of this application.

[0023] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0024] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0025] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0026] The subject executing the data acquisition synchronization method of this application can be a data acquisition and transmission device with data processing, network communication and program execution functions. For example, it can be a control system or control circuit that can realize the above functions. This embodiment does not specifically limit it.

[0027] The following description uses the data acquisition and transmission device as the main execution subject to illustrate the various embodiments.

[0028] This application proposes a data acquisition synchronization method according to a first embodiment, applied to a data acquisition and transmission device. The data acquisition and transmission device includes multiple cascaded relay units and multiple data acquisition modules. A half-duplex bus is connected between each pair of adjacent relay units, and at least one data acquisition module is connected to each half-duplex bus between each pair of adjacent relay units. Please refer to... Figure 1 The data acquisition synchronization method may include steps S10 to S50: Step S10: Control the first-level relay unit to generate a synchronization pulse sequence, and transmit the synchronization pulse sequence generated by the first-level relay unit downlink through the half-duplex bus connected to the first-level relay unit.

[0029] The first-level relay unit serves as the synchronization reference source for the data acquisition and transmission equipment. It can be equipped with a high-precision local clock source or an external standard clock source, responsible for generating and distributing a synchronization pulse sequence with a fixed timing pattern, providing a unique and original synchronization time reference for the entire data acquisition and transmission equipment. A half-duplex bus is a communication bus that allows bidirectional data transmission, but only allows transmission in one direction at a time.

[0030] Understandably, the first-level relay unit generates a synchronization pulse sequence with a fixed timing pattern through its built-in high-precision local clock source or an external standard clock source. This synchronization pulse sequence, which represents the original synchronization time reference of the entire acquisition and transmission device, is transmitted to all acquisition modules corresponding to the first-level relay unit and the next-level relay unit through the half-duplex bus connected to the first-level relay unit, and finally to all relay units and all acquisition modules in the acquisition and transmission device.

[0031] Furthermore, the synchronization pulse sequence has the highest preemption priority on the half-duplex bus. When the hardware synchronization timer is triggered, the physical layer driver circuit instantaneously switches the half-duplex bus transceiver from data receive / transmit mode to synchronization pulse sequence transmission mode. This switching operation cannot be interrupted by other service requests, ensuring that the synchronization pulse sequence preempts the half-duplex bus with a deterministic delay at a predetermined time. After the synchronization pulse sequence transmission ends, the half-duplex bus state is restored to respond to data frames.

[0032] In one possible implementation, steps S101 to S103 are included before step S10: Step S101: Control each acquisition module to obtain the occurrence time and direction of each level transition in the synchronization pulse sequence transmitted by the corresponding upstream relay unit of each acquisition module by sampling the level transition on the half-duplex bus of the acquisition module.

[0033] The acquisition module is the end-point synchronous execution node and data acquisition terminal of the acquisition and transmission equipment. It can receive the synchronization pulse sequence transmitted by the corresponding upstream relay unit and complete the acquisition of environmental data and timestamp latching under clock tick drive. The level transition direction is used to characterize the type of level change, referring to the polarity of the half-duplex bus level change at the moment of transition, including the rising edge of the transition from low to high level and the falling edge of the transition from high to low level.

[0034] Step S102: For any acquisition module, based on the occurrence time and direction of each level transition in the synchronization pulse sequence transmitted by the upstream relay unit corresponding to the acquisition module, determine the duration between each two adjacent levels.

[0035] Step S103: When the level transition sequence and duration are consistent with the level transition sequence and duration of the preset valid signal, the synchronization pulse sequence transmitted by the upstream relay unit corresponding to the acquisition module is taken as the synchronization pulse sequence received by the acquisition module.

[0036] Level transition sequence refers to the order in which the directions of multiple level transitions occur on the time axis during a period of time on a half-duplex bus, and is used to characterize the timing structure of level changes.

[0037] The acquisition module monitors the level transitions on the half-duplex bus. When the actual detected level transition sequence and the duration of each level segment are consistent with the level transition sequence and the duration of each level segment of the valid signal agreed upon by both the transmitting and receiving parties, it confirms that a valid synchronization pulse sequence has been received and instantly restores the synchronization reference.

[0038] In this embodiment, the acquisition module does not need to rely on a continuous and complete pulse sequence. It only needs to capture any valid pulse edge and verify its time-domain constraints to confirm that a valid synchronization pulse sequence has been received. Even if some pulses in the synchronization pulse sequence are lost or distorted due to transient interference, as long as the remaining pulses still meet the agreed transition order and duration constraints, the acquisition module can still reliably identify and recover the synchronization reference, achieving anti-interference redundancy detection. At the same time, the synchronization reference recovered by the acquisition module is reconstructed automatically according to the agreed time-domain constraints, decoupling it from the distortions such as amplitude attenuation and edge softening superimposed during half-duplex bus transmission, thus eliminating the physical dependence of long-distance transmission on the quality of the synchronization pulse sequence.

[0039] Step S20: For each relay unit after the first-level relay unit, the frequency and edge phase reference of the synchronization pulse sequence transmitted by the previous-level relay unit are extracted by sampling the level transition on the half-duplex bus connected to the relay unit.

[0040] The edge phase reference of a synchronization pulse sequence refers to the time position information of each effective pulse edge in the synchronization pulse sequence relative to a predetermined reference time, which is used to characterize the precise time when the pulse edge appears.

[0041] Step S30: Based on the frequency and edge phase reference of the synchronization pulse sequence transmitted by the previous level relay unit of each relay unit, control each relay unit to generate the synchronization pulse sequence of the relay unit, and transmit the synchronization pulse sequence generated by the relay unit downlink through the next level half-duplex bus connecting each relay unit.

[0042] Except for the first-level relay unit, each relay unit, upon receiving the synchronization pulse sequence from the previous-level relay unit, generates a synchronization pulse sequence with the same frequency and phase as the received sequence. This sequence is then transmitted to all corresponding acquisition modules and the next-level relay unit via the next-level half-duplex bus connected to the relay unit. In essence, by locally regenerating the received synchronization pulse sequence, each relay unit ensures frequency and phase consistency during the progressive transmission process, effectively isolating waveform distortion and timing jitter from the upstream transmission link from propagating downwards.

[0043] Step S40: For any acquisition module, calibrate the local clock signal of the acquisition module based on the synchronization pulse sequence received by the acquisition module, and upload the deviation value between the local clock signal of the acquisition module and the synchronization pulse sequence received by the acquisition module, as well as the original timestamp of the acquisition module, to the corresponding upstream relay unit of the acquisition module.

[0044] The local clock signal is a periodic pulse sequence generated internally by the acquisition module from a local crystal oscillator through a numerically controlled oscillator. It contains the acquisition module's own time reference information and is used to drive analog-to-digital conversion sampling, timestamp counting, synchronization pulse regeneration, and the operation of local timing logic. The local clock signal's time-domain characteristics are jointly constituted by a frequency reference and an edge-phase reference. The frequency reference characterizes the repetition rate of the pulse sequence, while the edge-phase reference characterizes the precise moment when the effective pulse edge appears. Together, they determine the relative time relationship between the local clock signal and the external synchronization pulse sequence. The acquisition module's raw timestamp is a local count value latched by a hardware timer when the acquisition module completes analog-to-digital conversion sampling under the drive of the local clock signal. It is used to characterize the occurrence time of this sampling event on the acquisition module's local timeline.

[0045] Step S50: Based on the deviation between the local clock signal of the acquisition module and the synchronization pulse sequence received by the acquisition module, control the upstream relay unit corresponding to the acquisition module to correct the original timestamp of the acquisition module, so as to obtain the corrected timestamp of the acquisition module, so that the sampling time of all acquisition modules corresponding to the upstream relay unit of the acquisition module is synchronized on the time axis.

[0046] The correction timestamp of the acquisition module is calculated by the upstream relay unit corresponding to the acquisition module. Numerically, the correction timestamp of the acquisition module is equal to the sum of the original timestamp, cumulative drift, phase deviation, and preset transmission delay parameters. The cumulative drift characterizes the accumulated time offset due to frequency deviation within the continuous duration from the moment the local clock signal of the acquisition module completes calibration to the moment the acquisition module samples. Numerically, the cumulative drift is equal to the quotient of the frequency deviation between the local clock signal of the acquisition module and the synchronization pulse sequence received by the acquisition module, and the nominal frequency of the acquisition module, multiplied by the continuous duration from the moment the local clock signal of the acquisition module completes calibration to the moment the acquisition module samples. The nominal frequency of the acquisition module is the theoretical center frequency value calibrated at the factory under ideal operating conditions for the local crystal oscillator in the acquisition module, characterizing the expected oscillation frequency of the local crystal oscillator under design conditions. The preset transmission delay parameter is a fixed time delay required for the synchronization pulse sequence or data frame to be transmitted from the transmitting end's physical layer to the receiving end's physical layer on the half-duplex bus between the acquisition module and its corresponding upstream relay unit. This parameter can be a deterministic static parameter pre-stored in the relay unit after actual measurement or calculation based on line length and device specifications. The phase deviation value of the acquisition module refers to the offset in the phase dimension between the acquisition module's local clock signal and the received synchronization pulse sequence. The frequency deviation value of the acquisition module refers to the offset in the frequency dimension between the acquisition module's local clock signal and the received synchronization pulse sequence.

[0047] Understandably, by correcting the original timestamps of the acquisition modules, the sampling events of all acquisition modules corresponding to the same relay unit can be precisely aligned on the timeline.

[0048] This embodiment is applicable to acquisition and transmission equipment that uses a half-duplex bus to connect relay units and acquisition modules. The synchronization signal shares the half-duplex bus with the normal acquisition data in a time-division multiplexed manner, without the need for additional cabling. This achieves improved clock synchronization accuracy of serial cascaded acquisition networks at low cost.

[0049] Based on the first embodiment described above, a second embodiment of the data acquisition synchronization method of this application is proposed. For the second embodiment, please refer to... Figure 2 The step of calibrating the local clock signal of the acquisition module based on the synchronization pulse sequence received by the acquisition module includes steps S41 to S43: Step S41: Based on the arrival times of two adjacent pulses in the synchronization pulse sequence received by the acquisition module, determine the arrival time interval between two adjacent pulses.

[0050] The arrival time of two adjacent pulses refers to the instantaneous point in time when the pulse edges (rising or falling edges) of two adjacent valid pulses in the synchronization pulse sequence received by the acquisition module are sampled by the acquisition module. The arrival time interval of two adjacent pulses is the difference between the arrival times of the two adjacent pulses, which is numerically equal to one complete cycle of the synchronization pulse sequence.

[0051] Step S42: Determine the actual physical frequency of the local crystal oscillator of the acquisition module based on the arrival time interval.

[0052] The actual physical frequency of the local crystal oscillator refers to the true oscillation frequency of the local crystal oscillator of the acquisition module during actual operation. The acquisition module first uses the local crystal oscillator as a timing reference to measure the arrival time interval between two adjacent valid pulse edges in the synchronization pulse sequence, and obtains a count value expressed in terms of the number of local clock beats. The quotient of the count value and the standard period of the synchronization pulse sequence generated by the first-level relay unit is the value of the actual physical frequency of the local crystal oscillator of the acquisition module.

[0053] Step S43: Based on the preset frequency control word and phase accumulator bit width of the acquisition module, and the actual physical frequency of the local crystal oscillator of the acquisition module, a first pulse signal is generated as the local clock signal of the calibrated acquisition module.

[0054] The preset frequency control word of the acquisition module is a digital control parameter used to control the output frequency of the numerically controlled oscillator (CNC) in the acquisition module. The preset phase accumulator bit width of the acquisition module is the number of binary bits in the phase accumulator of the CNC oscillator, used to limit the counting modulus of the phase accumulator. The first pulse signal is a pulse sequence generated by the CNC oscillator of the acquisition module. The calculation method of the first pulse signal is shown in Formula 1: Formula 1 in, This refers to the frequency of the first pulse signal. This is the frequency control word preset by the acquisition module, and N is the preset phase accumulator bit width of the acquisition module. It is the actual physical frequency of the local crystal oscillator of the acquisition module.

[0055] In one possible implementation, after step S43, steps S431 to S432 may also be included: Step S431: Based on the pulse edge of the first pulse signal and the edge of the synchronization pulse sequence received by the acquisition module, the instantaneous phase deviation value is obtained.

[0056] The instantaneous phase deviation value is the time difference between the pulse edge of the first pulse signal generated under the local clock beat of the acquisition module and the corresponding edge of the synchronization pulse sequence received by the acquisition module. It represents the instantaneous phase offset between the local clock signal of the acquisition module and the synchronization pulse sequence received by the acquisition module.

[0057] Step S432: Based on the instantaneous phase deviation value, the phase parameter of the first pulse signal is corrected by closed-loop feedback until the instantaneous phase deviation value converges to within the preset instantaneous phase deviation value threshold.

[0058] The preset instantaneous phase deviation threshold is a fixed judgment benchmark preset in the acquisition module firmware based on the synchronization accuracy index. It represents the maximum absolute value range of the instantaneous phase deviation value allowed by the acquisition module and is used to determine whether the phase parameter of the first pulse signal has converged to the qualified range.

[0059] Understandably, closed-loop feedback correction refers to continuously processing the instantaneous phase deviation value through a loop filter, outputting a phase correction control quantity, and superimposing the phase correction control quantity on the phase parameters of the acquisition module, thereby changing the generation time of the next output edge of the first pulse signal until the phase parameters of the first pulse signal converge to the qualified range.

[0060] In this embodiment, the edge of the local clock signal of the acquisition module gradually approaches the edge of the synchronization pulse sequence received by the acquisition module, so that the local clock signal is strictly aligned with the synchronization pulse sequence received by the acquisition module in terms of edge phase.

[0061] In one feasible implementation, the deviation value corresponding to the acquisition module includes a frequency deviation value and a phase deviation value, and the steps for determining the deviation value corresponding to the acquisition module include steps S44 to S45: Step S44: The difference between the actual physical frequency and the nominal frequency of the acquisition module is used as the frequency deviation value between the local clock signal of the acquisition module and the synchronization pulse sequence received by the acquisition module.

[0062] Step S45: The instantaneous phase deviation value after convergence is used as the phase deviation value between the local clock signal of the acquisition module and the synchronization pulse sequence received by the acquisition module.

[0063] It is understandable that the instantaneous phase deviation value between the local clock signal, after closed-loop feedback correction, which converges to within the preset instantaneous phase deviation value threshold, and the synchronization pulse sequence received by the acquisition module is used as the phase deviation value between the local clock signal of the acquisition module and the synchronization pulse sequence received by the acquisition module.

[0064] This implementation converts the synchronization error in frequency and phase dimensions of the local clock signal of the acquisition module relative to the synchronization pulse sequence received by the acquisition module into a computable digital quantity that can be uploaded, providing the quantization input required for the original timestamp correction of the upstream relay unit corresponding to the acquisition module.

[0065] In one feasible implementation, the acquisition synchronization method further includes steps S46 to S47: Step S46: Based on the frequency deviation value corresponding to the acquisition module and the continuous duration from the moment the local clock signal of the acquisition module completes calibration to the moment the acquisition module samples, determine the cumulative drift of the acquisition module.

[0066] Step S47: The sum of the original timestamp of the acquisition module, the cumulative drift amount, the phase deviation value corresponding to the acquisition module, and the preset transmission delay parameter is used as the correction timestamp of the acquisition module.

[0067] This implementation converts the deviations of the local clock signal of the acquisition module in the frequency and phase dimensions into calculable correction quantities, thereby enabling the sampling times of all acquisition modules corresponding to the same relay unit to be located on a unified time reference.

[0068] This embodiment calculates the actual physical frequency of the local crystal oscillator by measuring the arrival interval between two adjacent pulses in the synchronization pulse sequence received by the acquisition module, so that the frequency of the first pulse signal generated by the acquisition module is consistent with the frequency of the synchronization pulse sequence received by the acquisition module, thus achieving the consistency of the local clock signal frequency of each acquisition module.

[0069] Based on the first and / or second embodiments described above, a third embodiment of the data acquisition and transmission method of this application is proposed. Please refer to [the relevant documentation]. Figure 3 After step S50, steps S51 to S53 are also included: Step S51: For any relay unit, the deviation values ​​of all acquisition modules associated with the relay unit are transmitted uplink to the first-level relay unit through the first-level half-duplex bus connected to the relay unit.

[0070] In one possible implementation, steps S501 to S503 are included before step S51: Step S501: For any relay unit, determine the connectivity status of the previous half-duplex bus connected to the relay unit by sampling the level transition on the previous half-duplex bus connected to the relay unit.

[0071] The relay unit determines whether the physical link of the preceding half-duplex bus is in normal working condition by sampling the level transitions on the bus connected to the relay unit.

[0072] Step S502: When the connectivity status is that the first half-duplex bus connected to the relay unit is interrupted, store the deviation values ​​corresponding to all acquisition modules associated with the relay unit into the local register.

[0073] The local register is a built-in local storage space of the relay unit. It can temporarily store the deviation values ​​of each acquisition module corresponding to the relay unit, as well as related acquisition information and other key data during half-duplex bus interruption, to prevent data loss.

[0074] In step S503, when the first half-duplex bus connected to the relay unit is reconnected, the deviation value stored in the local register is transmitted to the next-level relay unit of the relay unit through the first half-duplex bus connected to the relay unit in the storage order.

[0075] Understandably, after the physical link of the first half-duplex bus connected to the relay unit returns to normal operation, the data temporarily stored during the interruption will be retransmitted in order to ensure the integrity and timing consistency of the deviation data in the uplink transmission.

[0076] This implementation method employs a collaborative mechanism that includes real-time sensing of the connectivity of the preceding half-duplex bus connected to the relay unit, local temporary storage of data when the preceding half-duplex bus connected to the relay unit is interrupted, and sequential retransmission of data after the preceding half-duplex bus connected to the relay unit is restored. This mechanism enables local caching of deviation data and automatic retransmission after restoration when an interruption occurs in the preceding half-duplex bus connected between relay units. This ensures that the deviation values ​​of each acquisition module under the jurisdiction of the relay unit can be completely uploaded to the upper-level relay unit, avoiding data loss due to half-duplex bus interruption.

[0077] Step S52: For any acquisition module, the acquisition information of the acquisition module is transmitted to the first-level relay unit level by level through the half-duplex bus connected to the acquisition module.

[0078] The information acquired by the acquisition module refers to the environmental sample values ​​collected by the acquisition module under the drive of the local clock signal.

[0079] Step S53: Control the first-level relay unit to calculate the acquisition information of each acquisition module at the preset standard sampling time based on the deviation between the local clock signal of each acquisition module and the synchronization pulse sequence received by each acquisition module, the acquisition information of each acquisition module, and the acquisition information of each acquisition module, according to the interpolation algorithm.

[0080] Interpolation algorithms refer to methods that, based on the information collected by the acquisition modules at the actual sampling time, mathematically fit the data to estimate the information collected by the acquisition modules at a preset standard sampling time. This is achieved by using the data collected by each acquisition module at the actual sampling time as known data points and the preset standard sampling time as the target interpolation point to calculate the data collected by each acquisition module at the preset standard sampling time. This embodiment does not limit the specific implementation of the interpolation algorithm.

[0081] In one possible implementation, steps S531 to S532 are included before step S53: Step S531: For any acquisition module, determine whether the deviation between the local clock signal of the acquisition module and the synchronization pulse sequence received by the acquisition module is less than or equal to a preset deviation threshold.

[0082] The preset deviation threshold refers to the maximum absolute value of the deviation between the local clock signal of the acquisition module and the synchronization pulse sequence received by the acquisition module, which is used to determine whether the synchronization status of the acquisition module is qualified. It can be understood that when the deviation between the local clock signal of the acquisition module and the synchronization pulse sequence received by the acquisition module exceeds the preset deviation threshold, it indicates that the acquisition module is in an abnormal state and has no reference value.

[0083] Step S532: If the deviation between the local clock signal of the acquisition module and the synchronization pulse sequence received by the acquisition module is less than or equal to a preset deviation threshold, control the first-level relay unit to calculate the acquisition information of the acquisition module at the preset standard sampling time.

[0084] The preset standard sampling time is the unified sampling time set by all acquisition modules through the first-level relay unit.

[0085] This implementation uses a preset deviation threshold to dynamically filter and control the synchronization status of the acquisition modules, and only acquisition modules with qualified synchronization status are included in the interpolation compensation, ensuring from the source that all input data participating in global data alignment are valid data.

[0086] This embodiment obtains the acquisition information of all acquisition modules at the preset standard sampling time by globally aggregating deviation data, uploading the collected information level by level, and uniformly calculating the interpolation algorithm, thus realizing the acquisition synchronization of all acquisition modules.

[0087] This application also provides a data acquisition and transmission device; please refer to [reference needed]. Figure 4 The data acquisition and transmission equipment may include: Multiple cascaded relay units are connected by a half-duplex bus between each pair of adjacent relay units, and at least one acquisition module is connected to each half-duplex bus between each pair of adjacent relay units. Multiple data acquisition modules.

[0088] The data acquisition and transmission device provided in this application, employing the acquisition synchronization method described in the above embodiments, can solve the technical problem of improving the clock synchronization accuracy of a serially cascaded acquisition network under low cost. Compared with the prior art, the beneficial effects of the data acquisition and transmission device provided in this application are the same as those of the acquisition synchronization method provided in the above embodiments, and other technical features in the acquisition and transmission device are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0089] This application also provides a computer-readable storage medium storing a computer program that can run on a processor. The computer program is used to execute the acquisition synchronization method in the above embodiments.

[0090] The computer-readable storage medium provided in this application embodiment may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0091] The aforementioned computer-readable storage medium may be included in the acquisition and transmission device; or it may exist independently and not be assembled into the acquisition and transmission device.

[0092] The aforementioned computer-readable storage medium carries one or more programs. When the aforementioned one or more programs are executed by the acquisition and transmission device, the acquisition and transmission device causes the acquisition and transmission device to: control the first-level relay unit to generate a synchronization pulse sequence and transmit the synchronization pulse sequence generated by the first-level relay unit downstream through a half-duplex bus connected to the first-level relay unit; for each relay unit after the first-level relay unit, extract the frequency and edge phase reference of the synchronization pulse sequence transmitted by the previous-level relay unit by sampling the level transitions on the half-duplex bus connected to the relay unit; based on the frequency and edge phase reference of the synchronization pulse sequence transmitted by the previous-level relay unit of each relay unit, control each relay unit to generate its own synchronization pulse sequence and transmit it downstream through a half-duplex bus connected to the first-level relay unit. The downstream half-duplex bus of each relay unit transmits the synchronization pulse sequence generated by the relay unit. For any acquisition module, the local clock signal of the acquisition module is calibrated based on the synchronization pulse sequence received by the acquisition module, and the deviation between the local clock signal of the acquisition module and the synchronization pulse sequence received by the acquisition module, as well as the original timestamp of the acquisition module, are uploaded to the upstream relay unit corresponding to the acquisition module. Based on the deviation between the local clock signal of the acquisition module and the synchronization pulse sequence received by the acquisition module, the upstream relay unit corresponding to the acquisition module is controlled to correct the original timestamp of the acquisition module, so as to obtain the corrected timestamp of the acquisition module, so that the sampling time of all acquisition modules corresponding to the upstream relay unit of the acquisition module is synchronized on the time axis.

[0093] Computer program code for performing the operations of this disclosure can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0094] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0095] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0096] The computer-readable storage medium provided in this application embodiment stores computer-readable program instructions for executing the above-described acquisition synchronization method, which can improve the clock synchronization accuracy of a serially cascaded acquisition network at low cost. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application embodiment are the same as the beneficial effects of the acquisition synchronization method provided in the above embodiments, and will not be repeated here.

[0097] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the acquisition synchronization method described above.

[0098] The computer program product provided in this application embodiment can improve the clock synchronization accuracy of a serially cascaded acquisition network at low cost. Compared with the prior art, the beneficial effects of the computer program product provided in this application embodiment are the same as those of the acquisition synchronization method provided in the above embodiments, and will not be repeated here.

[0099] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A data acquisition synchronization method, characterized in that, The method is applied to a data acquisition and transmission device, which includes multiple cascaded relay units and multiple acquisition modules; a half-duplex bus is connected between each pair of adjacent relay units, and at least one acquisition module is connected to the half-duplex bus between each pair of adjacent relay units. The method includes: The system controls the first-level relay unit to generate a synchronization pulse sequence, and transmits the synchronization pulse sequence generated by the first-level relay unit downlink via a half-duplex bus connected to the first-level relay unit. For each relay unit after the first-level relay unit, the frequency and edge phase reference of the synchronization pulse sequence transmitted by the previous-level relay unit are extracted by sampling the level transition on the half-duplex bus connected to the relay unit. Based on the frequency and edge phase reference of the synchronization pulse sequence transmitted by the previous level relay unit of each relay unit, each relay unit is controlled to generate its own synchronization pulse sequence, and the synchronization pulse sequence generated by the relay unit is transmitted downlink through the next level half-duplex bus connecting each relay unit. For any of the acquisition modules, the local clock signal of the acquisition module is calibrated based on the synchronization pulse sequence received by the acquisition module, and the deviation between the local clock signal of the acquisition module and the synchronization pulse sequence received by the acquisition module, and the original timestamp of the acquisition module are uploaded to the upstream relay unit corresponding to the acquisition module. Based on the deviation between the local clock signal of the acquisition module and the synchronization pulse sequence received by the acquisition module, the upstream relay unit corresponding to the acquisition module is controlled to correct the original timestamp of the acquisition module, so as to obtain the corrected timestamp of the acquisition module, so that the sampling time of all acquisition modules corresponding to the upstream relay unit of the acquisition module is synchronized on the time axis.

2. The method as described in claim 1, characterized in that, Before the step of calibrating the local clock signal of any of the acquisition modules based on the synchronization pulse sequence received by the acquisition module, and uploading the deviation between the local clock signal of the acquisition module and the synchronization pulse sequence received by the acquisition module, and the original timestamp of the acquisition module to the corresponding upstream relay unit, the method further includes: The control module obtains the occurrence time and direction of each level transition in the synchronization pulse sequence transmitted by the corresponding upstream relay unit by sampling the level transition on the half-duplex bus connected to the acquisition module. For any of the acquisition modules, the duration between each two adjacent levels is determined based on the occurrence time and direction of each level transition in the synchronization pulse sequence transmitted by the upstream relay unit corresponding to the acquisition module. When the level transition sequence and duration of each level transition are consistent with the level transition sequence and duration of the preset valid signal, the synchronization pulse sequence transmitted by the upstream relay unit corresponding to the acquisition module is taken as the synchronization pulse sequence received by the acquisition module.

3. The method as described in claim 1, characterized in that, The step of calibrating the local clock signal of the acquisition module based on the synchronization pulse sequence received by the acquisition module includes: Based on the arrival times of two adjacent pulses in the synchronization pulse sequence received by the acquisition module, the arrival time interval between the two adjacent pulses is determined. Based on the arrival time interval, the actual physical frequency of the local crystal oscillator of the acquisition module is determined; Based on the preset frequency control word and phase accumulator bit width of the acquisition module, as well as the actual physical frequency of the local crystal oscillator of the acquisition module, a first pulse signal is generated as the calibrated local clock signal of the acquisition module.

4. The method as described in claim 3, characterized in that, After the step of generating a first pulse signal based on the preset frequency control word, phase accumulator bit width, and actual physical frequency of the local crystal oscillator of the acquisition module, as the calibrated local clock signal of the acquisition module, the method further includes: The instantaneous phase deviation value is obtained based on the pulse edge of the first pulse signal and the edge of the synchronization pulse sequence received by the acquisition module. Based on the instantaneous phase deviation value, the phase parameter of the first pulse signal is corrected by closed-loop feedback until the instantaneous phase deviation value converges to within a preset instantaneous phase deviation value threshold.

5. The method as described in claim 4, characterized in that, The deviation value corresponding to the acquisition module includes a frequency deviation value and a phase deviation value; the steps for determining the deviation value corresponding to the acquisition module include: The difference between the actual physical frequency and the nominal frequency of the acquisition module is used as the frequency deviation value between the local clock signal of the acquisition module and the synchronization pulse sequence received by the acquisition module. The instantaneous phase deviation value after convergence is used as the phase deviation value between the local clock signal of the acquisition module and the synchronization pulse sequence received by the acquisition module.

6. The method as described in claim 5, characterized in that, The method further includes: Based on the frequency deviation value corresponding to the acquisition module, and the continuous duration from the moment the local clock signal of the acquisition module completes calibration to the moment the acquisition module samples, the cumulative drift of the acquisition module is determined. The original timestamp, cumulative drift, phase deviation value corresponding to the acquisition module, and the sum of the preset transmission delay parameter of the acquisition module are used as the corrected timestamp of the acquisition module.

7. The method as described in claim 1, characterized in that, Following the step of controlling the upstream relay unit corresponding to the acquisition module to correct the original timestamp of the acquisition module based on the deviation between the local clock signal of the acquisition module and the synchronization pulse sequence received by the acquisition module, and obtaining the corrected timestamp of the acquisition module so that the sampling times of all acquisition modules corresponding to the upstream relay unit of the acquisition module are synchronized on the time axis, the method further includes: For any relay unit, the deviation values ​​of all acquisition modules associated with the relay unit are transmitted uplink to the first-level relay unit through the first-level half-duplex bus connected to the relay unit. For any acquisition module, the acquisition information of the acquisition module is transmitted to the first-level relay unit step by step through the half-duplex bus connected to the acquisition module. The first-level relay unit is controlled to calculate the acquisition information of each acquisition module at a preset standard sampling time based on the deviation between the local clock signal of each acquisition module and the synchronization pulse sequence received by each acquisition module, the acquisition information of each acquisition module, and the acquisition information of each acquisition module, according to the interpolation algorithm.

8. The method as described in claim 7, characterized in that, Before the step of transmitting the deviation values ​​of all acquisition modules associated with any relay unit to the first-level relay unit via the preceding half-duplex bus connected to the relay unit, the method further includes: For any relay unit, the connectivity status of the preceding half-duplex bus connected to the relay unit is determined by sampling the level transition on the preceding half-duplex bus connected to the relay unit. When the connectivity status is that the preceding half-duplex bus connected to the relay unit is interrupted, the deviation values ​​corresponding to all acquisition modules associated with the relay unit are stored in the local register. Furthermore, when the preceding half-duplex bus connected to the relay unit is reconnected, the deviation value stored in the local register is transmitted to the preceding relay unit through the preceding half-duplex bus connected to the relay unit in the order of storage.

9. The method as described in claim 7, characterized in that, Before the step of controlling the first-level relay unit to calculate the acquisition information of each acquisition module at a preset standard sampling time based on the deviation between the local clock signal of each acquisition module and the synchronization pulse sequence received by each acquisition module, and the acquisition information of each acquisition module, according to an interpolation algorithm, the method further includes: For any of the acquisition modules, determine whether the deviation between the local clock signal of the acquisition module and the synchronization pulse sequence received by the acquisition module is less than or equal to a preset deviation threshold. If the deviation between the local clock signal of the acquisition module and the synchronization pulse sequence received by the acquisition module is less than or equal to a preset deviation threshold, the first-level relay unit is controlled to calculate the acquisition information of the acquisition module at a preset standard sampling time.

10. A data acquisition and transmission device for implementing the data acquisition synchronization method as described in any one of claims 1 to 9, characterized in that, The data acquisition and transmission device includes: Multiple cascaded relay units, each pair of adjacent relay units is connected to a half-duplex bus, and at least one acquisition module is connected to the half-duplex bus between each pair of adjacent relay units. Multiple data acquisition modules.

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