Semiconductor device, method of manufacturing the same, and memory system

Abstract

Embodiments of the present disclosure provide a semiconductor device, a manufacturing method thereof, and a memory system. The semiconductor device includes a memory array including a first sub-array and a second sub-array arranged along a first direction, the first sub-array including a plurality of first active groups arranged along a second direction, and the second sub-array including a plurality of second active groups arranged along the second direction, the first direction and the second direction intersecting each other, a first bit line group disposed on a side of the first active groups away from the second active groups, and a second bit line group disposed on a side of the second active groups away from the first active groups, a first isolation structure disposed between adjacent first bit line groups along the second direction, and a second isolation structure disposed between adjacent second bit line groups along the second direction.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, including but not limited to a semiconductor device, its manufacturing method, and a memory system. Background Technology

[0002] Dynamic Random Access Memory (DRAM) comprises multiple memory cells, each typically including a transistor and a capacitor. The gate of the transistor is coupled to the word line (WL), the source (or drain) is coupled to the bit line (BL), and the drain (or source) is coupled to the capacitor. With the advent of the artificial intelligence era, various industries have an urgent need for high-density, high-capacity DRAM. As DRAM technology iterates, to continuously improve DRAM storage density, DRAM is evolving towards three-dimensional DRAM (3D DRAM), which includes horizontal word line stacking (WL Stacking) architecture and horizontal bit line stacking (BL Stacking) architecture.

[0003] Currently, 3D DRAM still needs further improvement. Summary of the Invention

[0004] In view of the above, embodiments of the present disclosure provide a semiconductor device, a method for manufacturing the same, and a memory system.

[0005] In a first aspect, embodiments of this disclosure provide a semiconductor device, the semiconductor device comprising: a memory array including a first subarray and a second subarray arranged along a first direction, the first subarray including a plurality of first active groups arranged along a second direction, the second subarray including a plurality of second active groups arranged along the second direction; the first direction and the second direction intersect; a first bit line group disposed on the side of the first active group away from the second active group, and a second bit line group disposed on the side of the second active group away from the first active group; a first isolation structure disposed between adjacent first bit line groups along the second direction, and a second isolation structure disposed between adjacent second bit line groups along the second direction.

[0006] In some embodiments, the first active group includes a plurality of first active structures spaced apart along a third direction, the first bit line group includes a plurality of first bit lines spaced apart along the third direction, and the first bit lines are coupled to the first active structures; any two of the first direction, the second direction, and the third direction intersect; the second active group includes a plurality of second active structures spaced apart along the third direction, the second bit line group includes a plurality of second bit lines spaced apart along the third direction, and the second bit lines are coupled to the second active structures.

[0007] In some embodiments, in the same first bit line group, the lengths of a plurality of first bit lines arranged sequentially along the third direction increase sequentially along the first direction, and the first bit line group forms a first sub-step structure; in the same second bit line group, the lengths of a plurality of second bit lines arranged sequentially along the third direction increase sequentially along the first direction, and the second bit line group forms a second sub-step structure.

[0008] In some embodiments, the number of the first bit line groups is the same as the number of the first active groups, and the number of the first bit lines is the same as the number of the first active structures; the number of the second bit line groups is the same as the number of the second active groups, and the number of the second bit lines is the same as the number of the second active structures.

[0009] In some embodiments, the semiconductor device further includes: a first conductive structure disposed between adjacent first bit line groups along the second direction, the first conductive structure being in contact with a first isolation structure, the first conductive structure including a plurality of first conductive layers spaced apart along the third direction; in the plurality of first bit line groups arranged along the second direction, a plurality of first bit lines at the same height position along the third direction being mutually coupled through the first conductive layers; a second conductive structure disposed between adjacent second bit line groups along the second direction, the second conductive structure being in contact with a second isolation structure, the second conductive structure including a plurality of second conductive layers spaced apart along the third direction; in the plurality of second bit line groups arranged along the second direction, a plurality of second bit lines at the same height position along the third direction being mutually coupled through the second conductive layers.

[0010] In some embodiments, the semiconductor device further includes: a first contact structure extending along the third direction, the first contact structure being coupled to the first bit line; and a second contact structure extending along the third direction, the second contact structure being coupled to the second bit line.

[0011] In some embodiments, in the same storage array, the number of the first contact structures is greater than or equal to the number of the first active structures in the first active group, and the number of the second contact structures is greater than or equal to the number of the second active structures in the second active group.

[0012] In some embodiments, among a plurality of first bit line groups arranged along the second direction, adjacent first bit line groups are isolated by the first isolation structure, and a plurality of first bit lines at the same height position along the third direction are coupled to the same first conductive line; in a plurality of second bit line groups arranged along the second direction, adjacent second bit line groups are isolated by the second isolation structure, and a plurality of second bit lines at the same height position along the third direction are coupled to the same second conductive line.

[0013] In some embodiments, the semiconductor device further includes: a plurality of first contact structures extending along the third direction, the first contact structures being coupled to the first bit lines; in a plurality of first bit line groups arranged along the second direction, a plurality of first contact structures coupled to a plurality of first bit lines at the same height position along the third direction being coupled to the same first conductive line; a plurality of second contact structures extending along the third direction, the second contact structures being coupled to the second bit lines; and in a plurality of second bit line groups arranged along the second direction, a plurality of second contact structures coupled to a plurality of second bit lines at the same height position along the third direction being coupled to the same second conductive line.

[0014] In some embodiments, in the same memory array, the number of the first contact structures is greater than or equal to the number of the first bit lines, and the number of the first active structures in the first active group is the same as the number of the first conductive lines; the number of the second contact structures is greater than or equal to the number of the second bit lines, and the number of the second active structures in the second active group is the same as the number of the second conductive lines.

[0015] In some embodiments, the first active structure includes a first surface and a second surface opposite to each other along the third direction, and a third surface connecting the first surface and the second surface, the first surface and the second surface having annular shapes; the second active structure includes a fourth surface and a fifth surface opposite to each other along the third direction, and a sixth surface connecting the fourth surface and the fifth surface, the fourth surface and the fifth surface having annular shapes.

[0016] In some embodiments, the semiconductor device further includes: a plurality of first gate structures disposed between the first surface and the second surface, wherein a plurality of first gate structures corresponding to a plurality of first active structures arranged along the third direction are coupled to the same first word line; and a plurality of second gate structures disposed between the fourth surface and the fifth surface, wherein a plurality of second gate structures corresponding to a plurality of second active structures arranged along the third direction are coupled to the same second word line.

[0017] In some embodiments, the first active structure includes a first end and a second end opposite to each other along the first direction, the first end being coupled to the first bit line, and the second active structure includes a third end and a fourth end opposite to each other along the first direction, the third end being coupled to the second bit line; wherein the distance between the first end in the first active structure and the third end in the second active structure arranged along the first direction is greater than the distance between the second end in the first active structure and the fourth end in the second active structure.

[0018] In some embodiments, the semiconductor device further includes: a plurality of first capacitors coupled to the second end; a plurality of second capacitors coupled to the fourth end; wherein the first capacitors and the second capacitors are disposed between the first active structure and the second active structure.

[0019] In some embodiments, the semiconductor device includes a three-dimensional dynamic random access memory.

[0020] In a second aspect, embodiments of this disclosure provide a method for manufacturing a semiconductor device, the method comprising: forming a memory array, the memory array including a first subarray and a second subarray arranged along a first direction; the first subarray including a plurality of first active groups arranged along a second direction; the second subarray including a plurality of second active groups arranged along the second direction; the first direction and the second direction intersecting; forming a first bit line group disposed on the side of the first active group away from the second active group, and forming a second bit line group disposed on the side of the second active group away from the first active group; forming a first isolation structure disposed between adjacent first bit line groups along the second direction, and forming a second isolation structure disposed between adjacent second bit line groups along the second direction.

[0021] In some embodiments, prior to forming the memory array, the method further includes: forming a plurality of first dielectric layers and a plurality of second dielectric layers alternately stacked along a third direction on one side of a substrate; any two of the first direction, the second direction, and the third direction intersect; etching away portions of the first dielectric layers and portions of the second dielectric layers to form an initial first step structure, a stacked structure, and an initial second step structure arranged along a first direction; wherein the step surface in the initial first step structure exposes the second dielectric layer, the stacked structure includes the first dielectric layers and the second dielectric layers alternately stacked along the third direction, and the step surface in the initial second step structure exposes the second dielectric layer.

[0022] In some embodiments, the method further includes: etching the stacked structure to form a plurality of first etched holes, a plurality of second etched holes, and a plurality of third etched holes arranged along the second direction, wherein the first etched holes, the second etched holes, and the third etched holes are arranged along the first direction; and forming a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer in the first etched holes, the second etched holes, and the third etched holes, respectively.

[0023] In some embodiments, forming a memory array includes: removing a first sacrificial layer and a third sacrificial layer; removing a portion of a second dielectric layer through a first etched hole in a direction perpendicular to the third direction to form a first groove, and removing a portion of the second dielectric layer through a third etched hole in a direction perpendicular to the third direction to form a second groove; forming an initial first active structure in the space formed by the first etched hole and the first groove, and forming an initial second active structure in the space formed by the third etched hole and the second groove; removing a portion of the initial first active structure to form a plurality of first active structures spaced apart along the third direction, and removing a portion of the initial second active structure to form a plurality of second active structures spaced apart along the third direction; the plurality of first active structures spaced apart along the third direction forming a first active group, and the plurality of second active structures spaced apart along the third direction forming a second active group.

[0024] In some embodiments, the method further includes: forming a first gate structure in the space formed by the first etched hole and the first groove, and forming a second gate structure in the space formed by the third etched hole and the second groove; wherein, a plurality of first gate structures corresponding to a plurality of first active structures arranged along the third direction are coupled to the same first word line, and a plurality of second gate structures corresponding to a plurality of second active structures arranged along the third direction are coupled to the same second word line.

[0025] In some embodiments, the first active structure includes a first end and a second end opposite to each other along the first direction, and the second active structure includes a third end and a fourth end opposite to each other along the first direction; the method further includes: removing the second sacrificial layer; removing a portion of the second dielectric layer through the second etched hole in a direction perpendicular to the third direction to form a third groove exposing the second end of the first active structure and the fourth end of the second active structure; forming an initial first electrode in the space formed by the second etched hole and the third groove; removing a portion of the initial first electrode to form a plurality of first electrodes spaced apart along the third direction; forming a third dielectric layer and a second electrode in the space formed by the second etched hole and the third groove to form a first capacitor coupled to the second end of the first active structure and a second capacitor coupled to the fourth end of the second active structure, respectively.

[0026] In some embodiments, forming a first bit line group disposed on the side of the first active group away from the second active group, and forming a second bit line group disposed on the side of the second active group away from the first active group, includes: etching the initial first step structure to form a first isolation groove dividing the initial first step structure into a plurality of initial first sub-step structures; and etching the initial second step structure to form a second isolation groove dividing the initial second step structure into a plurality of initial second sub-step structures; removing the second dielectric layer in the initial first sub-step structure through the first isolation groove to form a first gap exposing the first end of the first active structure; and removing the second dielectric layer in the initial second sub-step structure through the second isolation groove. The second dielectric layer is used to form a second gap exposing the third end of the second active structure; a conductive material is filled in the first gap to form a first bit line, and a conductive material is filled in the second gap to form a second bit line; the first bit line is coupled to the first end, the second dielectric layer in the initial first sub-step structure is replaced by the first bit line to form a first sub-step structure, and a plurality of first bit lines arranged along the third direction form a first bit line group; the second bit line is coupled to the third end, the second dielectric layer in the initial second sub-step structure is replaced by the second bit line to form a second sub-step structure, and a plurality of second bit lines arranged along the third direction form a second bit line group.

[0027] In some embodiments, the number of the first bit line groups is the same as the number of the first active groups, and the number of the first bit lines is the same as the number of the first active structures; the number of the second bit line groups is the same as the number of the second active groups, and the number of the second bit lines is the same as the number of the second active structures.

[0028] In some embodiments, forming a first isolation structure disposed between adjacent first bit line groups along the second direction and forming a second isolation structure disposed between adjacent second bit line groups along the second direction includes: filling a first isolation groove with a dielectric material to form a first isolation structure, and filling a second isolation groove with a dielectric material to form a second isolation structure.

[0029] In some embodiments, the method further includes: forming a first contact structure extending along the third direction to the first bit line, and forming a second contact structure extending along the third direction to the second bit line.

[0030] In some embodiments, the method further includes: forming a first conductive line and a second conductive line; in a plurality of first bit line groups arranged along the second direction, a plurality of first contact structures coupled to a plurality of first bit lines at the same height position along the third direction are coupled to the same first conductive line; in a plurality of second bit line groups arranged along the second direction, a plurality of second contact structures coupled to a plurality of second bit lines at the same height position along the third direction are coupled to the same second conductive line.

[0031] Thirdly, embodiments of this disclosure provide a memory system comprising: a semiconductor device as described in the above technical solutions; and a controller coupled to the semiconductor device and configured to control the semiconductor device.

[0032] This disclosure provides a semiconductor device, its manufacturing method, and a memory system. In this embodiment, multiple second dielectric layers stacked along a third direction are replaced with conductive materials using first and second isolation trenches to form first bit line groups and second bit line groups, respectively. The first and second isolation trenches are then filled to form first and second isolation structures, respectively. This enables the mutual coupling of multiple first bit lines at the same height along a third direction and multiple second bit lines at the same height along a third direction, thereby reducing the difficulty of bit line fabrication, increasing the process window for forming the first and second bit lines, and improving the storage density of the semiconductor device. Attached Figure Description

[0033] Figure 1 Three-dimensional structural diagrams of memory devices provided for some examples;

[0034] Figure 2 A three-dimensional structural diagram of a semiconductor device during the manufacturing process provided in this disclosure embodiment;

[0035] Figure 3A schematic cross-sectional view of a semiconductor device provided in an embodiment of this disclosure;

[0036] Figure 4 This is an enlarged structural schematic diagram of the first active structure provided in the embodiments of this disclosure;

[0037] Figure 5 This is an enlarged structural schematic diagram of the second active structure provided in the embodiments of this disclosure;

[0038] Figure 6 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this disclosure;

[0039] Figures 7 to 23 This is a schematic diagram of the structure of a semiconductor device during the manufacturing process provided in the embodiments of this disclosure;

[0040] Figure 24 A schematic block diagram of a memory system provided in an embodiment of this disclosure;

[0041] Figure 25 Schematic block diagrams of electronic devices provided in some embodiments of this disclosure;

[0042] Figure 26 Schematic block diagram of a memory device provided in embodiments of this disclosure;

[0043] Figure 27 Schematic block diagrams of electronic devices provided for other embodiments of this disclosure;

[0044] Figure 28 A schematic block diagram of an electronic device provided for some embodiments of this disclosure. Detailed Implementation

[0045] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0046] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0047] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0048] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0049] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0050] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0051] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0052] 3D DRAM includes horizontal word line stacking architecture and horizontal bit line stacking architecture. In the horizontal word line stacking architecture, word lines extend horizontally and bit lines extend vertically; in the horizontal bit line stacking architecture, bit lines extend horizontally and word lines extend vertically. The following explanation uses 3D DRAM based on the horizontal bit line stacking architecture as an example.

[0053] Before introducing the embodiments of this disclosure, the various directions that may be involved in the following text are defined. The stacking direction of the bit lines is defined as the Z direction, and the intersecting X and Y directions are defined in the plane intersecting the Z direction. The extension direction of the bit lines can be the X direction; wherein, any two of the X, Y, and Z directions intersect. In some embodiments, any two of the X, Y, and Z directions are perpendicular to each other. This will be used as an example for the following description.

[0054] refer to Figure 1 , Figure 1 Three-dimensional structural diagrams of memory devices are provided for some examples. For example... Figure 1 As shown, the memory device 100 includes: a plurality of active structures 101 extending along the Y direction, the plurality of active structures 101 being spaced apart along the X and Z directions, each active structure 101 including a source and a drain disposed opposite each other along the Y direction, and a channel disposed between the source and the drain; a plurality of word lines 102 extending along the Z direction and spaced apart along the X direction, the gate structures corresponding to the channel sidewalls of the plurality of active structures 101 arranged along the Z direction being coupled to the same word line 102 (e.g., Figure 1 (As shown in the dashed box); multiple bit lines 103 extending along the X direction and spaced apart along the Z direction; the sources (or drains) of multiple active structures 101 arranged along the X direction are coupled to the same bit line 103; capacitors 104 are coupled to the drains (or sources) of the active structures 101. It should be noted that... Figure 1 The diagram illustrates that the character line 102 has a dual-gate structure, meaning the dual-gate structure is located on two opposite sidewalls of the active structure 101 along the X direction. Figure 1 The diagram illustrates a dual-gate structure consisting of two sidewalls that are positioned opposite each other along the X direction and cover the same active structure 101. This structure is called a word line 102.

[0055] Here, the number of active structures 101 arranged along the X direction is the number of word lines 102, and the number of active structures 101 arranged along the Z direction is the number of bit lines 103. Figure 1The illustrated memory device 100 includes 32 active structures 101, 4 word lines 102 and 8 bit lines 103 for illustrative purposes only.

[0056] In view of the above, embodiments of the present disclosure provide a semiconductor device, a method for manufacturing the same, and a memory system.

[0057] refer to Figure 2 and Figure 3 , Figure 2 This is a three-dimensional structural diagram of a semiconductor device during the manufacturing process, provided in an embodiment of this disclosure. Figure 3 This is a schematic cross-sectional view of a semiconductor device provided in an embodiment of this disclosure. (In conjunction with...) Figure 2 and Figure 3 As shown, in a first aspect, embodiments of this disclosure provide a semiconductor device 200, which includes a memory array 201, comprising a first subarray 202 and a second subarray 203 arranged along the X direction. Figure 2 The two dashed boxes in the diagram illustrate the first subarray 202 and the second subarray 203, respectively. The first subarray 202 includes a plurality of first active groups 204 arranged along the Y direction, and the second subarray 203 includes a plurality of second active groups 205 arranged along the Y direction. Figure 2 The two dashed circles in the diagram represent the first active group 204 and the second active group 205, respectively. A first bit line group 208 is located on the side of the first active group 204 that is relatively far from the second active group 205, and a second bit line group 209 is located on the side of the second active group 205 that is relatively far from the first active group 204. That is, the first subarray 202 and the second subarray 203 are located between the first bit line group 208 and the second bit line group 209. Figure 3 The two trapezoidal dashed boxes in the middle illustrate the first line group 208 and the second line group 209, respectively; a first isolation structure 261 is provided between adjacent first line groups 208 along the Y direction, and a second isolation structure 262 is provided between adjacent second line groups 209 along the Y direction. Figure 3 The two dashed boxes in the middle represent the first isolation structure 261 and the second isolation structure 262, respectively.

[0058] It should be noted that, Figure 2 The semiconductor device shown is not the final product structure. Figure 2This is merely an illustrative example of the positions of the first isolation trench 206 and the second isolation trench 207. Multiple second dielectric layers stacked along the Z-direction are replaced with conductive materials via the first isolation trench 206 and the second isolation trench 207 to form a first line group 208 and a second line group 209, respectively. Filling the first isolation trench 206 and the second isolation trench 207 forms a first isolation structure 261 and a second isolation structure 262, respectively. Since the morphology of the first isolation trench 206 and the second isolation trench 207 arranged along the X-direction in the XY plane is similar to an "H" shape, the aforementioned first isolation trench 206 and the second isolation trench 207 can also be referred to as an H-CUT structure.

[0059] In this embodiment of the disclosure, multiple first bit lines at the same height position along the Z direction and multiple second bit lines at the same height position along the Z direction can be coupled to each other, thereby reducing the difficulty of bit line fabrication process and manufacturing cost, increasing the process window for forming the first and second bit lines, and improving the storage density of semiconductor devices.

[0060] In some embodiments, the first active group 204 includes a plurality of first active structures 214 spaced apart along the Z direction, and the first active structures 214 extend along the X direction. That is, the first subarray 202 includes a plurality of first active structures 214 spaced apart along both the Y and Z directions. The second active group 205 includes a plurality of second active structures 215 spaced apart along the Z direction, and the second active structures 215 extend along the X direction. That is, the second subarray 203 includes a plurality of second active structures 215 spaced apart along both the Y and Z directions. The first bit line group 208 includes a plurality of first bit lines 212 spaced apart along the Z direction, and the first bit lines 212 are coupled to the first active structures 214. The second bit line group 209 includes a plurality of second bit lines 213 spaced apart along the Z direction, and the second bit lines 213 are coupled to the second active structures 215.

[0061] In some embodiments, the semiconductor device 200 further includes a first dielectric layer 243 disposed between first bit lines 212 adjacent to each other in the Z direction in the first bit line group 208 and between second bit lines 213 adjacent to each other in the Z direction in the second bit line group 209. The first dielectric layer 243 is used to isolate the first bit lines 212 adjacent to each other in the Z direction and is also used to isolate the second bit lines 213 adjacent to each other in the Z direction.

[0062] Here, the first dielectric layer 243 is also disposed between the first active structures 214 arranged adjacent to each other in the Z direction in the first active group 204 and between the second active structures 215 arranged adjacent to each other in the Z direction in the second active group 205. The first dielectric layer 243 can also be used to isolate the first active structures 214 arranged adjacent to each other in the Z direction and the second active structures 215 arranged adjacent to each other in the Z direction.

[0063] In some embodiments, within the same first line group 208, among the multiple first lines 212 arranged along the Z direction, the height position of the first line 212 along the Z direction decreases sequentially, while the length of the first line 212 along the X direction increases sequentially, forming a first sub-step structure 210. Each first line 212 in the first line group 208 corresponds to one step in the first sub-step structure 210, and the step surface of each step exposes the first line 212. The height position of the first line 212 along the Z direction can be understood as the distance between the first line 212 and the base 241. The smaller the distance between the first line 212 and the base 241, the smaller the height position of the first line 212 along the Z direction. Multiple first lines 212 with the same height position along the Z direction can also be referred to as multiple first lines 212 located on the same layer.

[0064] In some embodiments, within the same second bit line group 209, among a plurality of second bit lines 213 arranged along the Z direction, the height position of the second bit lines 213 along the Z direction decreases sequentially, while the length of the second bit lines 213 along the X direction increases sequentially, forming a second sub-step structure 211. Each second bit line 213 in the second bit line group 209 corresponds to one step in the second sub-step structure 211, and the step surface of each step exposes the second bit line 213. The height position of the second bit line 213 along the Z direction can be understood as the distance between the second bit line 213 and the base 241. The smaller the distance between the second bit line 213 and the base 241, the smaller the height position of the second bit line 213 along the Z direction. Multiple second bit lines 213 with the same height position along the Z direction can also be referred to as multiple second bit lines 213 located in the same layer.

[0065] In some embodiments, each first active group 204 has a first line group 208 on one side along the X direction, meaning the number of first line groups 208 is the same as the number of first active groups 204. For first active groups 204 and first line groups 208 arranged adjacent to each other along the X direction, each first active structure 214 in the first active group 204 is coupled to a first line 212, meaning the number of first active structures 214 in each first active group 204 is the same as the number of first lines 212 in each first line group 208. In other words, in the semiconductor device 200, the number of first lines 212 is the product of the number of first line groups 208 and the number of first lines 212 in each first line group 208, and the number of first active structures 214 is the product of the number of first active groups 204 and the number of first active structures 214 in each first active group 204. Therefore, the number of first lines 212 is the same as the number of first active structures 214.

[0066] In some embodiments, each second active group 205 is provided with a second bit line group 209 on one side along the X direction, that is, the number of second bit line groups 209 is the same as the number of second active groups 205. For the second active groups 205 and the second bit line groups 209 arranged adjacent to each other along the X direction, each second active structure 215 in the second active group 205 is coupled to a second bit line 213, that is, the number of second active structures 215 in each second active group 205 is the same as the number of second bit lines 213 in each second bit line group 209. In other words, in the semiconductor device 200, the number of second bit lines 213 is the product of the number of second bit line groups 209 and the number of second bit lines 213 in each second bit line group 209, and the number of second active structures 215 is the product of the number of second active groups 205 and the number of second active structures 215 in each second active group 205. Therefore, the number of second bit lines 213 and the number of second active structures 215 are the same.

[0067] In some embodiments, the semiconductor device 200 further includes: a first conductive structure disposed between adjacent first line groups 208 along the Y direction; the first conductive structure and the first isolation structure 261 are arranged along the X direction and in contact with each other; the first conductive structure includes a plurality of first conductive layers spaced apart along the Z direction; and the first conductive layers disposed adjacently along the Z direction can also be isolated by a first dielectric layer. That is, the number of first conductive layers in each first conductive structure is the same as the number of first lines 212 in each first line group 208. In the plurality of first line groups 208 arranged along the Y direction, the plurality of first lines 212 at the same height position along the Z direction are coupled to each other through the first conductive layer; that is, the plurality of first lines 212 coupled to the plurality of first active structures 214 arranged along the Y direction in the first subarray 202 are coupled to each other, i.e., the plurality of first lines 212 located in the same layer are coupled to each other through the first conductive layer.

[0068] In some embodiments, the semiconductor device 200 further includes: a second conductive structure disposed between adjacent second bit line groups 209 along the Y direction; the second conductive structure and the second isolation structure 262 are arranged along the X direction and in contact with each other; the second conductive structure includes a plurality of second conductive layers spaced apart along the Z direction; and the second conductive layers disposed adjacently along the Z direction can also be isolated by a first dielectric layer. That is, the number of second conductive layers in each second conductive structure is the same as the number of second bit lines 213 in each second bit line group 209. In the plurality of second bit line groups 209 arranged along the Y direction, the plurality of second bit lines 213 at the same height position along the Z direction are coupled to each other through the second conductive layer; that is, the plurality of second bit lines coupled to the plurality of second active structures 215 arranged along the Y direction in the second subarray 203 are coupled to each other, i.e., the plurality of second bit lines 213 located on the same layer are coupled to each other through the second conductive layer.

[0069] In some embodiments, the semiconductor device 200 further includes a first contact structure 226 extending along the Z direction, the first contact structure 226 being coupled to the first first line 212. Here, since multiple first first lines 212 at the same height along the Z direction are coupled to each other through a first conductive layer, multiple first first lines 212 at the same height along the Z direction (that is, multiple first first lines 212 located in the same layer) can have electrical signals led out through at least one first contact structure 226. For example, the first contact structure 226 can be provided on any one of the multiple first first lines 212 arranged along the Y direction. Alternatively, a first contact structure 226 can be provided on each of the multiple first first lines 212 arranged along the Y direction.

[0070] In some embodiments, the semiconductor device 200 further includes a second contact structure 227 extending along the Z direction, the second contact structure 227 being coupled to the second bit line 213. Here, since the plurality of second bit lines 213 at the same height position along the Z direction are coupled to each other through the second conductive layer, the plurality of second bit lines 213 at the same height position along the Z direction (that is, the plurality of second bit lines 213 located in the same layer) can be used to lead out electrical signals through at least one second contact structure 227. For example, the second contact structure 227 can be provided on any one of the plurality of second bit lines 213 arranged along the Y direction. Or, for example, a second contact structure 227 can be provided on each of the plurality of second bit lines 213 arranged along the Y direction.

[0071] In some embodiments, within the same memory array 201, the number of first contact structures 226 is greater than or equal to the number of first active structures 214 in the first active group 204. If multiple first bit lines 212 located on the same layer are led out through a first contact structure 226, the number of first contact structures 226 is the same as the number of first active structures 214 arranged along the Z direction; if each first bit line 212 in the multiple first bit lines 212 located on the same layer is led out through a first contact structure 226, the number of first contact structures 226 is the same as the number of first active structures 214 in the first subarray 202. The number of second contact structures 227 is greater than or equal to the number of second active structures 215 in the second active group 205. If multiple second bit lines 213 located on the same layer are led out through a second contact structure 227, the number of second contact structures 227 is the same as the number of second active structures 215 arranged along the Z direction; if each of the multiple second bit lines 213 located on the same layer is led out through a second contact structure 227, the number of second contact structures 227 is the same as the number of second active structures 215 in the second subarray 203.

[0072] In this embodiment, on one hand, multiple first bit lines 212 located on the same layer are coupled to each other through a first conductive layer, which reduces the number of first contact structures 226; multiple second bit lines 213 located on the same layer are coupled to each other through a second conductive layer, which reduces the number of second contact structures 227. On the other hand, when multiple first bit lines 212 located on the same layer cannot be successfully coupled to each other through the first conductive layer, the first contact structures 226 can be used to lead out the electrical signal of the first bit lines 212, and then the multiple first contact structures 226 coupled to the multiple first bit lines 212 located on the same layer can be coupled to the same first conductive line, which can reduce the risk of multiple first bit lines 212 located on the same layer failing to be successfully coupled to each other and increase the process window for forming the first bit lines 212. Similarly, coupling the multiple second contact structures 227 coupled to the multiple second bit lines 213 located on the same layer to the same second conductive line can reduce the risk of multiple second bit lines 213 located on the same layer failing to be successfully coupled to each other and increase the process window for forming the second bit lines 213.

[0073] In some embodiments, among the plurality of first bit line groups 208 arranged along the Y direction, adjacent first bit line groups 208 are separated by a first isolation structure 261. At this time, no first conductive structure is provided between adjacent first bit line groups 208. Multiple first bit lines 212 at the same height position along the Z direction are coupled to the same first conductive line, that is, multiple first bit lines 212 located on the same layer are coupled to the same first conductive line. In the plurality of second bit line groups 209 arranged along the Y direction, adjacent second bit line groups 209 are separated by a second isolation structure 262. At this time, no second conductive structure is provided between adjacent second bit line groups 209. Multiple second bit lines 213 at the same height position along the Z direction are coupled to the same second conductive line, that is, multiple second bit lines 213 located on the same layer are coupled to the same second conductive line.

[0074] In some embodiments, the semiconductor device 200 further includes: a plurality of first contact structures 226 extending along the Z direction, the first contact structures 226 being coupled to a first bit line 212; in a plurality of first bit line groups 208 arranged along the Y direction, a plurality of first contact structures 226 coupled to a plurality of first bit lines 212 at the same height position along the Z direction being coupled to the same first conductive line; a plurality of second contact structures 227 extending along the Z direction, the second contact structures 227 being coupled to a second bit line 213; in a plurality of second bit line groups 213 arranged along the Y direction, a plurality of second contact structures 227 coupled to a plurality of second bit lines 213 at the same height position along the Z direction being coupled to the same second conductive line.

[0075] In some embodiments, within the same memory array 201, the number of first contact structures 226 is greater than or equal to the number of first bit lines 212, and the number of first active structures 214 in the first active group 204 is the same as the number of first conductive lines. If each of the multiple first bit lines 212 located on the same layer is led out through a first contact structure 226, then the number of first contact structures 226 is the same as the number of first bit lines 212. If each of the multiple first bit lines 212 located on the same layer is led out through multiple first contact structures 226, then the number of first contact structures 226 is greater than the number of first bit lines 212; thus, the first contact structures 226 coupled to the same first bit line 212 can be used as spare first contact structures 226 to improve the reliability of the semiconductor device 200. The number of second contact structures 227 is greater than or equal to the number of second bit lines 213, and the number of second active structures 215 in the second active group 205 is the same as the number of second conductive lines. If each of the multiple second bit lines 213 located on the same layer leads out an electrical signal through a second contact structure 227, then the number of second contact structures 227 is the same as the number of second bit lines 213. If each of the multiple second bit lines 213 located on the same layer leads out an electrical signal through multiple second contact structures 227, then the number of second contact structures 227 is greater than the number of second bit lines 213; thus, the second contact structure 227 coupled to the same second bit line 213 can be used as a spare second contact structure 227 to improve the reliability of the semiconductor device 200.

[0076] In some embodiments, the semiconductor device 200 further includes: a first filling layer covering each step in the first sub-step structure 210, a first contact structure 226 extending along the Z direction through the first filling layer and contacting the first bit line 212; and a second filling layer covering each step in the second sub-step structure 211, a second contact structure 227 extending along the Z direction through the second filling layer and contacting the second bit line 213.

[0077] In some embodiments, the cross-sectional shape of the first contact structure 226 and the second contact structure 227 along the Z direction includes, but is not limited to, a circle, an ellipse, a polygon, or a sector, etc., and this disclosure does not have any special limitation in this regard.

[0078] In some embodiments, the first active structure 214 and the second active structure 215 may include semiconductor materials (e.g., silicon) and oxide semiconductor materials, such as at least one of indium oxide (In2O3), zinc oxide (ZnO), zinc indium oxide (IZO), zinc gallium oxide (IGZO), zinc tin oxide (IZTO), and zinc oxynitride (ZnON).

[0079] In some embodiments, the first bit line 212 and the second bit line 213 may include conductive materials, such as metallic or semiconductor materials. The first bit line 212 and the second bit line 213 may be a single-layer structure or a multi-layer structure, and this disclosure does not have any particular limitation in this regard.

[0080] In some embodiments, the first contact structure 226 and the second contact structure 227 may include conductive materials, such as metallic materials or semiconductor materials, such as tungsten. The first contact structure 226 and the second contact structure 227 may be single-layer structures or multi-layer structures, and this disclosure does not have any particular limitation in this regard.

[0081] In some embodiments, the first dielectric layer, the first isolation structure 261, the second isolation structure 262, the first filling layer, and the second filling layer may include the same dielectric material or different dielectric materials, such as silicon oxide. Figure 2 The diagram illustrates that the first dielectric layer, the first isolation structure 261, the second isolation structure 262, the first filler layer, and the second filler layer all comprise the same dielectric material. Figure 3 Use the same fill pattern.

[0082] refer to Figure 4 and Figure 5 , Figure 4 This is an enlarged structural schematic diagram of the first active structure provided in an embodiment of this disclosure. Figure 5 This is an enlarged structural schematic diagram of the second active structure provided in an embodiment of this disclosure. (See attached diagram.) Figure 4 As shown, in some embodiments, the first active structure 214 includes a first surface 216 and a second surface 217 opposite each other along the Z direction, and a third surface 218 connecting the first surface 216 and the second surface 217. The first surface 216 and the second surface 217 have annular shapes. Figure 5 As shown, the second active structure 215 includes a fourth surface 219 and a fifth surface 220 opposite to each other along the Z direction, and a sixth surface 221 connecting the fourth surface 219 and the fifth surface 220. The fourth surface 219 and the fifth surface 220 are annular in shape.

[0083] like Figure 4 As shown, in some embodiments, the semiconductor device 200 further includes: a plurality of first gate structures 228, the first gate structures 228 being disposed between the first surface 216 and the second surface 217, and the plurality of first gate structures 228 corresponding to the plurality of first active structures 214 arranged along the Z direction being coupled to the same first word line 234. Figure 5As shown, in some embodiments, the semiconductor device 200 further includes: a plurality of second gate structures 231, the second gate structures 231 being disposed between the fourth surface 219 and the fifth surface 220, and the plurality of second gate structures 231 corresponding to the plurality of second active structures 215 arranged along the Z direction being coupled to the same second word line 235.

[0084] like Figure 4 As shown, in some embodiments, the first gate structure 228 includes a first gate dielectric layer 229 and a first gate electrode layer 230, with the first gate dielectric layer 229 disposed between the first active structure 214 and the first gate electrode layer 230. Figure 5 As shown, in some embodiments, the second gate structure 231 includes a second gate dielectric layer 232 and a second gate electrode layer 233, with the second gate dielectric layer 232 disposed between the second active structure 215 and the second gate electrode layer 233.

[0085] In some embodiments, the semiconductor device 200 further includes: a first adhesion layer disposed between the first gate dielectric layer 229 and the first gate electrode layer 230, and a second adhesion layer disposed between the second gate dielectric layer 232 and the second gate electrode layer 233.

[0086] In some embodiments, the first gate dielectric layer 229 and the second gate dielectric layer 232 comprise dielectric materials, such as silicon oxide; the first adhesion layer and the second adhesion layer comprise, for example, titanium nitride; and the first gate electrode layer 230 and the second gate electrode layer 233 comprise conductive materials, such as tungsten metal.

[0087] refer to Figure 4 As shown, in some embodiments, the first active structure 214 includes a first end portion 222 and a second end portion 223 opposite each other along the X direction, the first end portion 222 being coupled to the first bit line 212. (See reference...) Figure 5 As shown, the second active structure 215 includes a third end 224 and a fourth end 225 opposite to each other along the X direction, with the third end 224 coupled to the second bit line 213; wherein, the distance between the first end 222 in the first active structure 214 and the third end 224 in the second active structure 215 arranged along the X direction is greater than the distance between the second end 223 in the first active structure 214 and the fourth end 225 in the second active structure 215. Figure 4 The two dashed circles in the middle represent the first end 222 and the second end 223, respectively. Figure 5The two dashed circles in the middle respectively indicate the third end 224 and the fourth end 225. That is to say, the first active structure 214 and the second active structure 215 are mirror symmetrical about the YZ plane between the first active structure 214 and the second active structure 215, and the first bit line 212 and the second bit line 213 are mirror symmetrical about the YZ plane between the first active structure 214 and the second active structure 215.

[0088] Figure 2 and Figure 3 The schematic semiconductor device 200 includes: two first active groups 204 arranged along the Y direction, each first active group 204 including four first active structures 214 arranged along the Z direction; and two second active groups 205 arranged along the Y direction, each second active group 205 including four second active structures 215 arranged along the Z direction. Two first bit line groups 208 (or first sub-step structures 210) are arranged along the Y direction, each first bit line group 208 including four first bit lines 212 arranged along the Z direction; two second bit line groups 209 (or second sub-step structures 211) are arranged along the Y direction, each second bit line group 209 including four second bit lines 213 arranged along the Z direction; wherein, the two first bit lines 212 located on the same layer can be coupled to the same first conductive line, corresponding to four first conductive lines; the two second bit lines 213 located on the same layer can be coupled to the same second conductive line, corresponding to four second conductive lines. Two first word lines 234 are arranged along the Y direction, each first word line 234 corresponding to four first active structures 214 arranged along the Z direction; two second word lines 235 are arranged along the Y direction, each second word line 235 corresponding to four second active structures 215 arranged along the Z direction. Figure 2 and Figure 3 The number of the first active structure 214, the second active structure 215, the first bit line 212, the second bit line 213, the first word line 234, and the second word line 235 shown in the illustration are for illustrative purposes only and do not constitute a limitation on the scope of protection of this disclosure.

[0089] Return to reference Figure 3 As shown, in some embodiments, the semiconductor device 200 further includes: a plurality of first capacitors 236 coupled to the second end 223; a plurality of second capacitors 237 (e.g., ... Figure 3 (As shown in the dashed circle), the second capacitor 237 is coupled to the fourth end 225; wherein, the first capacitor 236 and the second capacitor 237 are disposed between the first active structure 214 and the second active structure 215. Here, the first capacitor 236 includes a first electrode 238, a second electrode 239, and a third dielectric layer 240 disposed between the first electrode 238 and the second electrode 239, and the first electrode 238 is in contact with the second end 223 of the first active structure 214.

[0090] In some embodiments, the second electrode 239 is shared among the multiple first capacitors 236 coupled to the multiple first active structures 214 in the first active group 204, or the second electrode 239 is shared among the multiple second capacitors 237 coupled to the multiple second active structures 215 in the second active group 205.

[0091] In some embodiments, the first electrode 238 is shared by the first capacitor 236 coupled to the first active structure 214 and the second capacitor 237 coupled to the second active structure 215, both located on the same layer. In other embodiments, the first electrode in the first capacitor 236 coupled to the first active structure 214 and the first electrode in the second capacitor 237 coupled to the second active structure 215 are isolated.

[0092] In some embodiments, the first capacitor 236 coupled to the first active structure 214 and the second capacitor 237 coupled to the second active structure 215 located on the same layer share the second electrode 239, that is, all the first capacitors 236 coupled to the first active structure 214 in the first active group 204 arranged along the X direction and all the second capacitors 237 coupled to the second active structure 215 in the second active group 205 share the second electrode 239.

[0093] In some embodiments, the semiconductor device 200 includes: 3D DRAM.

[0094] refer to Figure 6 , Figure 6 This is a schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this disclosure. Figure 6 As shown, in a second aspect, embodiments of this disclosure provide a method for manufacturing a semiconductor device, the method comprising:

[0095] Step S310: Form a storage array, the storage array including a first subarray and a second subarray arranged along the X direction; the first subarray includes a plurality of first active groups arranged along the Y direction; the second subarray includes a plurality of second active groups arranged along the Y direction; the X direction and the Y direction intersect.

[0096] Step S320: Form a first bit line group located on the side of the first active group away from the second active group, and form a second bit line group located on the side of the second active group away from the first active group;

[0097] Step S330: Form a first isolation structure between adjacent first bit groups along the Y direction, and form a second isolation structure between adjacent second bit groups along the Y direction.

[0098] refer to Figures 7 to 23 , Figures 7 to 23 This is a schematic diagram illustrating the structure of a semiconductor device during the manufacturing process, as provided in the embodiments of this disclosure. The following will be combined with… Figure 6 as well as Figures 7 to 23 The present disclosure describes in detail the manufacturing method of the semiconductor device provided in the embodiments.

[0099] like Figure 7 As shown, in some embodiments, before step S310, the method further includes: forming an initial stacking structure 242 on one side of the substrate 241 along the Z direction, the initial stacking structure 242 including a plurality of first dielectric layers 243 and a plurality of second dielectric layers 244 alternately stacked along the Z direction.

[0100] Here, substrate 241 may be a semiconductor substrate; specifically, it may include at least one elemental semiconductor material (e.g., silicon (Si) substrate, germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (e.g., gallium nitride (GaN) substrate, gallium arsenide (GaAs) substrate, indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. It may also include other substrates containing semiconductor materials, such as silicon-on-insulator (SOI) substrates, germanium-on-insulator (GeOI) substrates, polycrystalline semiconductor layers on insulating layers, silicon-germanium substrates, etc.

[0101] Here, the first dielectric layer 243 may include, for example, silicon oxide, and the second dielectric layer 244 may include, for example, silicon nitride.

[0102] In some embodiments, the process for forming the first dielectric layer 243 and the second dielectric layer 244 may include, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0103] like Figure 8As shown, in some embodiments, before step S310, the method further includes: etching away a portion of the first dielectric layer 243 and a portion of the second dielectric layer 244 to form an initial first step structure 246, a stacked structure 245, and an initial second step structure 247 arranged along the X direction; wherein, the initial first step structure 246 includes multiple steps, and the step surface of each step exposes the second dielectric layer 244; the stacked structure 245 includes the first dielectric layer 243 and the second dielectric layer 244 alternately stacked along the Z direction; and the initial second step structure 247 includes multiple steps, and the step surface of each step exposes the second dielectric layer 244. It should be noted that the stacked structure 245, the initial first step structure 246, and the initial second step structure 247 are only used for functional division and do not represent an actual interface between the stacked structure 245 and the initial first step structure 246, or between the stacked structure 245 and the initial second step structure 247. The region corresponding to the stacked structure 245 is subsequently used to form a first active structure, a second active structure, a first word line, a second word line, a first capacitor, and a second capacitor. The region corresponding to the initial first step structure 246 is subsequently used to form a first bit line group, and the region corresponding to the initial second step structure 247 is subsequently used to form a second bit line group. In some embodiments, the initial first step structure 246 and the initial second step structure 247 are mirror-symmetrical about the stacked structure 245.

[0104] Here, exemplarily, forming the initial first step structure 246 may include: removing a portion of the first dielectric layer 243 and a portion of the second dielectric layer 244 through a first etching, wherein the lengths of the plurality of first dielectric layers 243 and the plurality of second dielectric layers 244 are the same along the X direction, to form a first-level step that is closest to the substrate 241; removing a portion of the first dielectric layer 243 and a portion of the second dielectric layer 244 through a second etching to form a second-level step, wherein the distance between the second-level step and the substrate 241 is greater than the distance between the first-level step and the substrate 241, and the length of the second-level step along the X direction is less than the length of the first-level step along the X direction. The depth of the first etching is greater than the depth of the second etching; the first dielectric layer 243 and the second dielectric layer 244 may continue to be etched, with the etching depth decreasing sequentially, to form each step respectively. The above is only an exemplary description of one optional implementation of forming the initial first step structure 246; other methods may also be used to form the initial first step structure 246. Of course, a similar process can also be used to form the initial second step structure 247, which will not be described further here.

[0105] In some embodiments, the method further includes: forming a first filling layer covering the initial first step structure 246, and forming a second filling layer covering the initial second step structure 247; wherein the surface of the first filling layer is substantially flush with the surface of the topmost step in the initial first step structure 246, and the surface of the second filling layer is substantially flush with the surface of the topmost step in the initial second step structure 247.

[0106] like Figure 9 As shown, in some embodiments, the method further includes: etching the stacked structure 245 along the Z direction to form a plurality of first etched holes 248, a plurality of second etched holes 249, and a plurality of third etched holes 250 arranged along the Y direction, wherein the first etched holes 248, second etched holes 249, and third etched holes 250 are arranged along the X direction; and forming a first sacrificial layer 251, a second sacrificial layer 252, and a third sacrificial layer 253 in the first etched holes 248, second etched holes 249, and third etched holes 250, respectively. Here, the first etched holes 248 and third etched holes 250 may also be referred to as word line holes (WL Holes), and the second etched holes 249 may also be referred to as capacitor holes (Capacitor Holes).

[0107] In some embodiments, the process of etching to form the first etched hole 248, the second etched hole 249 and the third etched hole 250 may include dry etching.

[0108] In some embodiments, the processes for forming the first sacrificial layer 251, the second sacrificial layer 252, and the third sacrificial layer 253 may include, but are not limited to, CVD, PVD, ALD, or any combination thereof. Exemplarily, sacrificial materials are deposited in the first etched hole 248, the second etched hole 249, and the third etched hole 250 to form the first sacrificial material layer, the second sacrificial material layer, and the third sacrificial material layer, respectively; the first sacrificial material layer, the second sacrificial material layer, and the third sacrificial material layer are planarized to expose the surface of the stacked structure 245, the surface of the initial first step structure 246, and the surface of the initial second step structure 247, respectively, to form the first sacrificial layer 251, the second sacrificial layer 252, and the third sacrificial layer 253. The planarization process may include, but is not limited to, chemical mechanical polishing (CMP).

[0109] like Figure 10 As shown, in some embodiments, step S310 includes: removing the first sacrificial layer 251 and the third sacrificial layer 253 to open the first etched hole 248 and the third etched hole 250, respectively.

[0110] like Figure 11As shown, in some embodiments, step S310 further includes: removing a portion of the second dielectric layer 244 through the first etching hole 248 in a direction perpendicular to the Z direction (i.e., in the horizontal direction) to form a first groove 254, wherein a plurality of first grooves 254 arranged in the Z direction are connected through the first etching hole 248; and removing a portion of the second dielectric layer 244 through the third etching hole 250 in a direction perpendicular to the Z direction (i.e., in the horizontal direction) to form a second groove 255, wherein a plurality of second grooves 255 arranged in the Z direction are connected through the third etching hole 250. Figure 11 The two dashed boxes in the middle represent the first groove 254 and the second groove 255, respectively.

[0111] Here, in the space formed by multiple first grooves 254 and first etched holes 248, the horizontal dimension of this space at the height of the first dielectric layer 243 is smaller than its horizontal dimension at the height of the second dielectric layer 244. In the space formed by multiple second grooves 255 and third etched holes 250, the horizontal dimension of this space at the height of the first dielectric layer 243 is smaller than its horizontal dimension at the height of the second dielectric layer 244. Here, the first groove 254 includes a top surface and a bottom surface disposed opposite each other along the Z-direction, and a sidewall connecting the top surface and the bottom surface; the second groove 255 includes a top surface and a bottom surface disposed opposite each other along the Z-direction, and a sidewall connecting the top surface and the bottom surface.

[0112] like Figure 12 As shown, in some embodiments, step S310 further includes: forming an initial first active structure in the space formed by the first etched hole 248 and the first groove 254, that is, the initial first active structure covers the sidewall of the space formed by the multiple first grooves 254 and the first etched hole 248; and forming an initial second active structure in the space formed by the third etched hole 250 and the second groove 255, that is, the initial second active structure covers the sidewall of the space formed by the multiple second grooves 255 and the third etched hole 250. The initial first active structure covering the sidewall of the first etched hole 248 is removed to form a plurality of first active structures 214 spaced apart along the Z direction, that is, the initial first active structure at the height position of the first etched hole 248 at the height position of the first dielectric layer 243 is removed; and the initial second active structure covering the sidewall of the third etched hole 250 is removed to form a plurality of second active structures 215 spaced apart along the Z direction, that is, the initial second active structure at the height position of the third etched hole 250 at the height position of the first dielectric layer 243 is removed; the plurality of first active structures 214 arranged along the Z direction form a first active group 204, and the plurality of second active structures 215 arranged along the Z direction form a second active group 205. Figure 12 The two dashed boxes in the middle represent the first active structure 214 and the second active structure 215, respectively. Figure 12 The two dashed circles in the middle indicate the first active group 204 and the second active group 205.

[0113] In some embodiments, the process for forming the initial first active structure and the initial second active structure may include, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0114] For example, forming the first active structure 214 may include: forming an initial first active structure covering the spatial sidewalls formed by a plurality of first grooves 254 and first etched holes 248; forming a mask layer on the surface of the stacked structure 245, the mask layer exposing the first etched holes 248; and removing a portion of the initial first active structure located on the sidewalls of the first etched holes 248 using an anisotropic etching process, while retaining a portion of the initial first active structure located in the first grooves 254, to form the first active structure 214. A similar process can also be used to form the second active structure 215, which will not be described in detail here.

[0115] Combination Figure 4 As shown, the first active structure 214 includes a first surface 216 covering the top surface of the first groove 254, a second surface 217 covering the bottom surface of the first groove 254, and a third surface 218 covering the sidewalls of the first groove 254. (Combined) Figure 5 As shown, the second active structure 215 includes a fourth surface 219 covering the top surface of the second groove 255, a fifth surface 220 covering the bottom surface of the second groove 255, and a sixth surface 221 covering the sidewall of the second groove 255.

[0116] like Figure 13 As shown, in some embodiments, the method further includes: sequentially forming a first gate dielectric layer 229 and a first gate electrode layer 230 in the space formed by the first etched hole 248 and the first groove 254 to form a first gate structure 228; and sequentially forming a second gate dielectric layer 232 and a second gate electrode layer 233 in the space formed by the third etched hole 250 and the second groove 255 to form a second gate structure 231; wherein, the plurality of first gate structures 228 corresponding to the plurality of first active structures 214 arranged along the Z direction are coupled to the same first word line 234, and the plurality of second gate structures 231 corresponding to the plurality of second active structures 215 arranged along the Z direction are coupled to the same second word line 235. Figure 13 The two dashed circles in the middle represent the first character line 234 and the second character line 235, respectively.

[0117] Here, the process for forming the first gate dielectric layer 229, the first gate electrode layer 230, the second gate dielectric layer 232, and the second gate electrode layer 233 may include, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0118] In this embodiment, a first active structure 214 surrounds a first gate structure 228, and a second active structure 215 surrounds a second gate structure 231 to form a channel all-around (CAA) transistor. In the first etched hole 248, a first gate dielectric layer 229 and a first gate electrode layer 230 are sequentially included radially inward; in the third etched hole 250, a second gate dielectric layer 232 and a second gate electrode layer 233 are sequentially included radially inward.

[0119] like Figure 14 As shown, in some embodiments, the method further includes removing the second sacrificial layer 252 to open the second etched hole 249.

[0120] Still Figure 14 As shown, in some embodiments, the method further includes: removing a portion of the second dielectric layer 244 through the second etched hole 249 in a direction perpendicular to the Z direction (i.e., in the horizontal direction) to form a third groove 256 exposing the second end 223 of the first active structure 214 and the fourth end 225 of the second active structure 215, respectively. Figure 15 As shown in the dashed box in the middle, multiple third grooves 256 arranged along the Z direction are connected through the second etched hole 249.

[0121] Here, in the space formed by the multiple third grooves 256 and the second etched holes 249, the dimension of this space in the horizontal direction at the height of the first dielectric layer 243 is smaller than its dimension in the horizontal direction at the height of the second dielectric layer 244. Here, the third groove 256 includes a top surface and a bottom surface disposed opposite to each other in the Z direction, and a sidewall connecting the top surface and the bottom surface.

[0122] like Figure 15 As shown, in some embodiments, the method further includes: forming an initial first electrode in the space formed by the second etch hole 249 and the third groove 256, i.e., the initial first electrode covers the sidewall of the space formed by the multiple third grooves 256 and the second etch hole 249; removing a portion of the initial first electrode covering the sidewall of the second etch hole 249 to form a plurality of first electrodes 238 spaced apart along the Z direction, i.e., removing a portion of the initial first electrode at the height position of the second etch hole 249 at the first dielectric layer 243. Figure 16 The dashed box in the middle indicates the first electrode 238.

[0123] In some embodiments, the process for forming the initial first electrode may include, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0124] For example, forming the first electrode 238 may include: forming an initial first electrode covering a spatial sidewall formed by a plurality of third grooves 256 and a second etched hole 249; forming a mask layer on the surface of the stacked structure 245, the mask layer exposing the second etched hole 249; removing a portion of the initial first electrode located on the sidewall of the second etched hole 249 using an anisotropic etching process, retaining a portion of the initial first electrode located in the third grooves 256, to form the first electrode 238. The first electrode 238 that contacts the second end 223 of the first active structure 214 may be coupled to a first electrode 238 that contacts the fourth end 225 of the second active structure 215.

[0125] like Figure 16 As shown, in some embodiments, the method further includes: sequentially forming a third dielectric layer 240 and a second electrode 239 in the space formed by the second etched hole 249 and the third groove 256, so as to form a first capacitor 236 coupled to the second end 223 of the first active structure 214 and a second capacitor 237 coupled to the fourth end 225 of the second active structure 215, respectively. Figure 17 The two dashed circles in the diagram illustrate the first capacitor 236 and the second capacitor 237. Multiple first capacitors 236, coupled to multiple first active structures 214 formed in the first etched hole 248, and multiple second capacitors 237, coupled to multiple second active structures 215 formed in the third etched hole 250, share a second electrode 239. Here, the first electrode 238 can also be referred to as the inner electrode or inner metal, and the second electrode 239 can also be referred to as the outer electrode.

[0126] In some embodiments, the process for forming the third dielectric layer 240 and the second electrode 239 may include, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0127] In some embodiments, the method further includes: forming a third filling layer in the second etched hole 249; wherein the second etched hole 249 includes a third dielectric layer 240, a second electrode 239 and a third filling layer in a radially inward direction.

[0128] like Figure 17As shown, in some embodiments, step S320 includes: etching an initial first step structure 246 and a first filling layer to form a first isolation groove 206 that divides the initial first step structure 246 into a plurality of initial first sub-step structures 257; and etching an initial second step structure 247 and a second filling layer to form a second isolation groove 207 that divides the initial second step structure 247 into a plurality of initial second sub-step structures 258. The plurality of first isolation grooves 206 are spaced apart along the Y direction, and the first isolation grooves 206 are disposed between adjacent initial first sub-step structures 257 along the Y direction; the plurality of second isolation grooves 207 are spaced apart along the Y direction, and the second isolation grooves 207 are disposed between adjacent initial second sub-step structures 258 along the Y direction.

[0129] Figure 18 Four memory arrays are illustrated, separated from each other by a third isolation structure 263. The third isolation structure includes a first sub-isolation structure extending along the X direction and a second sub-isolation structure extending along the Y direction. The memory arrays are formed within the area enclosed by the first and second sub-isolation structures. Taking one memory array as an example, six first etched vias 248 are arranged along the Y direction, six second etched vias 249 are arranged along the Y direction, and a third etched via 250 is arranged along the Y direction. The second etched vias 249 are located between the first etched vias 248 and the third etched vias 250. It should be noted that... Figure 18 The number of memory cells or capacitors included in each memory array is shown in the illustration. This number can be determined based on the actual driving capability and does not constitute a limitation on the scope of protection of this disclosure. Figure 18 The two dashed circles in the middle represent the initial first sub-step structure 257 and the initial second sub-step structure 258, respectively.

[0130] like Figure 19 As shown, in some embodiments, step S320 further includes: removing the second dielectric layer 244 in the initial first sub-step structure 257 along the Y direction through the first isolation groove 206 to form a first gap 259 exposing the first end 222 of the first active structure 214, and removing the second dielectric layer 244 in the initial second sub-step structure 258 along the Y direction through the second isolation groove 207 to form a second gap 260 exposing the third end 224 of the second active structure 215.

[0131] Return to reference Figure 18 , Figure 18A dashed box surrounds the first isolation groove 206, and a dashed box also surrounds the second isolation groove 207. The areas indicated by the dashed boxes represent the areas where the second dielectric layer 244 needs to be removed. More specifically, the initial first sub-step structure 257 within the dashed box surrounding the first isolation groove 206 includes a first dielectric layer 243 and a second dielectric layer 244 alternately stacked along the Z direction. Removing this portion of the second dielectric layer 244 forms a first gap 259. The initial second sub-step structure 258 within the dashed box surrounding the second isolation groove 207 includes a first dielectric layer 243 and a second dielectric layer 244 alternately stacked along the Z direction. Removing this portion of the second dielectric layer 244 forms a second gap 260.

[0132] In some embodiments, a portion of the second dielectric layer 244 can be removed along the X direction by the first isolation groove 206 to form a third gap, which can connect adjacent first gaps along the Y direction. Additionally, a portion of the second dielectric layer 244 can be removed along the X direction by the second isolation groove 207 to form a fourth gap, which can connect adjacent second gaps along the Y direction.

[0133] Figure 20 Multiple second etched holes 249 are shown, in which a first electrode 238, a third dielectric layer 240, a second electrode 239, and a third filler layer are sequentially formed. A first dielectric layer 243 is provided between adjacent first electrodes 238 along the Z direction, and a second dielectric layer 244 is provided between adjacent first electrodes 238 along the Y direction.

[0134] like Figure 21As shown, in some embodiments, step S320 further includes: filling the first gap 259 with conductive material to form an initial first bit line 264, i.e., the initial first bit line 264 covers the space sidewall jointly formed by the first gap 259 and the first isolation groove 206; and filling the second gap 260 with conductive material to form an initial second bit line 265, i.e., the initial second bit line 265 covers the space sidewall jointly formed by the second gap 260 and the second isolation groove 207. A portion of the initial first bit line 264 covering the sidewall of the first isolation groove 206 is removed to form a plurality of first bit lines 212 spaced apart along the Z direction; and a portion of the initial second bit line 265 covering the sidewall of the second isolation groove 207 is removed to form a plurality of second bit lines 213 spaced apart along the Z direction. The first bit line 212 is coupled to the first end 222 of the first active structure 214. The second dielectric layer 244 in the initial first sub-step structure 257 is replaced by the first bit line 212 to form the first sub-step structure 210. The multiple first bit lines 212 arranged along the Z direction form the first bit line group 208. The second bit line 213 is coupled to the third end 224 of the second active structure 215. The second dielectric layer 244 in the initial second sub-step structure 258 is replaced by the second bit line 213 to form the second sub-step structure 211. The multiple second bit lines 213 arranged along the Z direction form the second bit line group 209.

[0135] For example, forming the first bit line 212 and the second bit line 213 may include: forming an initial first bit line 264 covering the spatial sidewall formed by the first gap 259 and the first isolation trench 206, and forming an initial second bit line 265 covering the spatial sidewall formed by the second gap 260 and the second isolation trench 207; forming a mask layer on the surface of the initial first sub-step structure 257 and the initial second sub-step structure 258, the mask layer exposing the first isolation trench 206 and the second isolation trench 207; removing a portion of the initial first bit line 264 located on the sidewall of the first isolation trench 206 using an anisotropic etching process, retaining a portion of the initial first bit line 264 located in the first gap 259 to form the first bit line 212; removing a portion of the initial second bit line 265 located on the sidewall of the second isolation trench 207 using anisotropic etching process, retaining a portion of the initial second bit line 265 located in the second gap 260 to form the second bit line 213.

[0136] In some embodiments, the third gap can be used to fill conductive material to form a first conductive layer, and the plurality of first conductive layers arranged along the Z direction form a first conductive structure, and the plurality of first conductive structures are arranged along the Y direction. The fourth gap can be used to fill conductive material to form a second conductive layer, and the plurality of second conductive layers arranged along the Z direction form a second conductive structure, and the plurality of second conductive structures are arranged along the Y direction. The plurality of first bit lines 212 located in the same layer can be coupled to each other through the first conductive layer, and the plurality of second bit lines 213 located in the same layer can be coupled to each other through the second conductive layer.

[0137] In some embodiments, the number of first bit line groups 208 (or, first sub-step structure 210) is the same as the number of first active groups 204, the number of first bit lines 212 is the same as the number of first active structures 214; the number of second bit line groups 209 (or, second sub-step structure 211) is the same as the number of second active groups 205, and the number of second bit lines 213 is the same as the number of second active structures 215.

[0138] like Figure 22 As shown, in some embodiments, step S330 includes: filling a first isolation groove 206 with a medium material to form a first isolation structure 261, and filling a second isolation groove 207 with a medium material to form a second isolation structure 262. Figure 22 The two dashed boxes in the middle represent the first isolation structure 261 and the second isolation structure 262, respectively.

[0139] In some embodiments, the process for forming the first isolation structure 261 and the second isolation structure 262 may include, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0140] like Figure 23 As shown, in some embodiments, the method further includes: etching a first filler layer along the Z direction to form a first contact hole extending along the Z direction and exposing a first bit line 212; and etching a second filler layer along the Z direction to form a second contact hole extending along the Z direction and exposing a second bit line 213; filling the first contact hole and the second contact hole with conductive material to form a first contact structure 226 extending along the Z direction to the first bit line 212 and a second contact structure 227 extending along the Z direction to the second bit line 213, respectively.

[0141] In some embodiments, the method further includes: forming a first conductive line and a second conductive line, wherein in a plurality of first first line groups 208 arranged along the Y direction, a plurality of first contact structures 226 coupled to a plurality of first first lines 212 located in the same layer are coupled to the same first conductive line; and in a plurality of second second line groups 209 arranged along the Y direction, a plurality of second contact structures 227 coupled to a plurality of second second lines 213 located in the same layer are coupled to the same second conductive line.

[0142] In this embodiment of the disclosure, the semiconductor device manufacturing method can be used to form the semiconductor device in any of the foregoing embodiments, and the technical effects that the semiconductor device in the foregoing embodiments can achieve can also be achieved by the semiconductor device manufacturing method, which will not be repeated here.

[0143] refer to Figure 24 , Figure 24 This is a schematic block diagram of a memory system provided for an embodiment of this disclosure. Figure 24 As shown, in a third aspect, embodiments of this disclosure also provide a memory system 400, comprising: at least one semiconductor device 200, the number of semiconductor devices 200 may be one or more; and a controller 402 coupled to the semiconductor device 200 and configured to control the semiconductor device 200.

[0144] In some embodiments, the memory system 400 may include high-bandwidth memory (HBM).

[0145] refer to Figure 25 , Figure 25 This disclosure includes schematic block diagrams of electronic devices provided in some embodiments. For example... Figure 25 As shown, electronic device 500 may include host 502 and memory system 400. In this embodiment of the disclosure, electronic device 500 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a memory device therein.

[0146] The host 502 may be a processor of an electronic device (e.g., a Central Processing Unit (CPU) or a System-on-Chip (SoC) (e.g., an Application Processor (AP)). The memory system 400 has one or more memory devices 512 and a controller 402. The host 502 may be configured to send data to or receive data from the memory device 512. The controller 402 is coupled to both the memory device 512 and the host 502 and is configured to control the memory device 512. The controller 402 may manage the data stored in the memory device 512 and communicate with the host 502. In some embodiments, the semiconductor device 200 may be part of the memory device 512, or the semiconductor device 200 may be the memory device 512 itself.

[0147] The controller 402 can be configured to control the operation of the memory device 512, such as read, write, and refresh operations. In some embodiments, the controller 402 is also configured to process error correction codes (ECCs) regarding data read from or written to the memory device 512. The controller 402 can also perform any other suitable function, such as formatting the memory device 512.

[0148] In some specific embodiments, the controller 402 and one or more memory devices 512 can be integrated into various types of storage devices. For example, the controller 402 can be integrated into the northbridge of a computer motherboard or directly into the computer CPU, and multiple memory devices 512 can be integrated into a memory module. In other words, the memory system 400 can be implemented and packaged into different types of terminal electronic products.

[0149] The controller 402 can send data to or receive data from the host 502, and can send commands (CMD) and addresses (ADDR) to the memory device 512. The controller 402 may include a command generator 504, an address generator 506, a device interface 508, and a host interface 510. The host interface 510 can receive commands (CMD) and addresses (ADDR) from the host 502. The command generator 504 can generate access commands, refresh commands, etc., by decoding the commands (CMD) received from the host 502, and can provide access commands and refresh commands to the memory device 512 through the device interface 508. An access command may be a signal instructing the memory device 512 to write or read data by accessing a row of the memory array 514 corresponding to the address (ADDR). A refresh command may instruct the memory array 514 of the memory device 512 to perform a data refresh operation.

[0150] The address generator 506 in controller 402 can generate the row and column addresses to be accessed in memory array 514 by decoding the address ADDR received from host interface 510. Furthermore, memory device 512 can generate addresses of memory banks to be accessed when memory array 514 includes multiple banks.

[0151] Furthermore, the controller 402 can control memory device operations such as writing and reading by providing various signals to the memory device 512 via the device interface 508. For example, the controller 402 can provide a write command to the memory device 512. The write command is used to instruct the memory device 512 to perform a write operation to store data in the memory device 512. The memory device 512 can be random access memory (RAM), such as DRAM, synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), etc.

[0152] refer to Figure 26 , Figure 26 A schematic block diagram of a memory device provided in embodiments of this disclosure. (See also...) Figure 26 As shown, the memory device 512 includes a memory array 514 and peripheral circuitry 516. The memory array 514 includes multiple memory banks. Exemplarily, each memory bank includes multiple memory blocks, each memory block includes multiple rows of memory cells and multiple columns of memory cells, each row of memory cells is coupled to a corresponding word line, and each column of memory cells is coupled to a corresponding bit line. This disclosure does not impose any special limitations on the number or arrangement of memory banks.

[0153] The peripheral circuit 516 may include: control circuits corresponding to each memory block, such as sensing amplifier circuit 520 (SA) and word line driver circuit (WLD), control circuits corresponding to each memory bank, such as row decoder 522 and column decoder 524, and control circuits corresponding to all memory banks, such as data input / output buffer 526, command buffer, command decoder, address buffer, mode register, etc.

[0154] The peripheral circuit 516 can write data to or read data from the memory array 514 based on the command CMD and address ADDR received from the controller 402, or it can provide the row decoder 522 and column decoder 524 with the control signal CTRL for refreshing the memory cells included in the memory array 514. In other words, the peripheral circuit 516 can perform all operations to process the data in the memory array 514.

[0155] Still referencing Figure 26 As shown, the memory device 512 includes at least one DRAM chip, each DRAM chip including a memory array 514, the memory array 514 including multiple memory cells 518 arranged in an array, each memory cell 518 including a transistor (T) and a capacitor (C). The main working principle of the memory cell is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0. The memory cells are arranged in an array, which can be regarded as a typical mesh structure. The memory array uses rows and columns to specify addresses. By specifying the intersection of the rows and columns (by specifying the row address and column address of the DRAM), the controller 402 can independently access each memory cell in the DRAM chip and perform read, write, or refresh operations on the data stored therein.

[0156] In some embodiments, the semiconductor device 200 may be a DRAM, which may be located outside the memory system and coupled to the host processor. In other embodiments, the DRAM may also be part of a controller within the memory system and connected to a corresponding control unit. The following will combine... Figure 27 and Figure 28 An example is provided.

[0157] refer to Figure 27 , Figure 27 This is a schematic block diagram of an electronic device provided for other embodiments of this disclosure. Electronic device 600 may include a host and a memory system coupled to the host. In this embodiment, DRAM may be disposed outside the memory system and coupled to the host processor 602.

[0158] like Figure 27 As shown, the host may include a host processor 602 and DRAM coupled to the host processor 602. The host processor 602 can serve as the central processing unit of the electronic device 600, responsible for executing various computing tasks and control instructions, and exchanging data and communicating with other modules in the electronic device 600. The DRAM coupled to the host processor 602 can provide high-speed temporary data storage space, supporting fast read and write operations of the host processor 602, and improving the overall performance of the electronic device 600.

[0159] like Figure 27As shown, the memory system may include a controller 402 and a flash memory 612 coupled to the controller 402. The controller 402 may include a host interface 604, a processor 606, a cache 608, and a first control unit 610. The host interface 604 provides a data transfer interface, supporting connection with the host processor 602 or other external devices to achieve data transfer. The host interface 604 includes a Peripheral Component Interconnect Express (PCIe) interface, a Serial Advanced Technology Attachment (SATA) interface, or other interfaces. The processor 606 is a central processing unit built into the controller 402, responsible for handling data management and control tasks within the memory system, improving data processing efficiency. The cache 608 can cache temporary data and control information within the memory system, supporting fast data access. The cache 608 includes SRAM, and the controller 402 can cache the mapping table stored in the flash memory 612 into the SRAM when the memory system is powered on. The first control unit 610 is responsible for managing various operations of the flash memory 612, including data mapping, erasing, reading, and writing, to ensure data reliability and performance.

[0160] refer to Figure 28 , Figure 28 This is a schematic block diagram of an electronic device provided for some embodiments of the present disclosure. In this embodiment, the DRAM may also be part of the controller 402 within the memory system and connected to a corresponding control unit. (Refer to...) Figure 14 As shown, the DRAM belonging to the controller 402 within the memory system is coupled to the second control unit 614. Here, the DRAM can be externally mounted and constitute part of the controller 402, and the externally mounted DRAM can be used as a cache of the controller 402. Of course, in other embodiments, the DRAM can also be integrated within the controller 402.

[0161] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0162] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: The storage array includes a first subarray and a second subarray arranged along a first direction, the first subarray including a plurality of first active groups arranged along a second direction, and the second subarray including a plurality of second active groups arranged along the second direction; the first direction and the second direction intersect. A first bit line group is provided on the side of the first active group away from the second active group, and a second bit line group is provided on the side of the second active group away from the first active group; A first isolation structure is provided between adjacent first bit line groups along the second direction, and a second isolation structure is provided between adjacent second bit line groups along the second direction.

2. The semiconductor device according to claim 1, characterized in that, The first active group includes a plurality of first active structures spaced apart along a third direction, and the first bit line group includes a plurality of first bit lines spaced apart along the third direction, the first bit lines being coupled to the first active structures; any two of the first direction, the second direction, and the third direction intersect each other; The second active group includes a plurality of second active structures spaced apart along the third direction, and the second bit line group includes a plurality of second bit lines spaced apart along the third direction, the second bit lines being coupled to the second active structures.

3. The semiconductor device according to claim 2, characterized in that, In the same first bit line group, the lengths of multiple first bit lines arranged sequentially along the third direction increase sequentially along the first direction, and the first bit line group forms a first sub-step structure; In the same second bit line group, the lengths of multiple second bit lines arranged sequentially along the third direction increase sequentially along the first direction, and the second bit line group forms a second sub-step structure.

4. The semiconductor device according to claim 2, characterized in that, The number of the first bit line group is the same as the number of the first active group, and the number of the first bit line is the same as the number of the first active structure; the number of the second bit line group is the same as the number of the second active group, and the number of the second bit line is the same as the number of the second active structure.

5. The semiconductor device according to claim 2, characterized in that, The semiconductor device further includes: A first conductive structure is provided between adjacent first bit line groups along the second direction, the first conductive structure is in contact with the first isolation structure, and the first conductive structure includes a plurality of first conductive layers spaced apart along the third direction; in the plurality of first bit line groups arranged along the second direction, a plurality of first bit lines at the same height position along the third direction are coupled to each other through the first conductive layers. A second conductive structure is provided between adjacent second bit line groups along the second direction, the second conductive structure is in contact with the second isolation structure, the second conductive structure includes a plurality of second conductive layers spaced apart along the third direction; in the plurality of second bit line groups arranged along the second direction, a plurality of second bit lines at the same height position along the third direction are coupled to each other through the second conductive layers.

6. The semiconductor device according to claim 5, characterized in that, The semiconductor device further includes: A first contact structure extending along the third direction, the first contact structure being coupled to the first bit line; A second contact structure extending along the third direction, the second contact structure being coupled to the second bit line.

7. The semiconductor device according to claim 6, characterized in that, In the same storage array, the number of the first contact structures is greater than or equal to the number of the first active structures in the first active group, and the number of the second contact structures is greater than or equal to the number of the second active structures in the second active group.

8. The semiconductor device according to claim 2, characterized in that, In a plurality of first bit line groups arranged along the second direction, adjacent first bit line groups are separated by the first isolation structure, and a plurality of first bit lines at the same height position along the third direction are coupled to the same first conductive line. In a plurality of second bit line groups arranged along the second direction, adjacent second bit line groups are separated by the second isolation structure, and a plurality of second bit lines at the same height position along the third direction are coupled to the same second conductive line.

9. The semiconductor device according to claim 8, characterized in that, The semiconductor device further includes: A plurality of first contact structures extending along the third direction are coupled to the first bit line; in a plurality of first bit line groups arranged along the second direction, a plurality of first contact structures coupled to a plurality of first bit lines at the same height position along the third direction are coupled to the same first conductive line. A plurality of second contact structures extending along the third direction, the second contact structures being coupled to the second bit lines; in a plurality of groups of second bit lines arranged along the second direction, a plurality of second contact structures coupled to a plurality of second bit lines at the same height position along the third direction are coupled to the same second conductive line.

10. The semiconductor device according to claim 9, characterized in that, In the same memory array, the number of the first contact structures is greater than or equal to the number of the first bit lines, and the number of the first active structures in the first active group is the same as the number of the first conductive lines; the number of the second contact structures is greater than or equal to the number of the second bit lines, and the number of the second active structures in the second active group is the same as the number of the second conductive lines.

11. The semiconductor device according to claim 2, characterized in that, The first active structure includes a first surface and a second surface opposite each other along the third direction, and a third surface connecting the first surface and the second surface, wherein the first surface and the second surface have annular shapes; The second active structure includes a fourth surface and a fifth surface opposite each other along the third direction, and a sixth surface connecting the fourth surface and the fifth surface, the fourth surface and the fifth surface having annular shapes.

12. The semiconductor device according to claim 11, characterized in that, The semiconductor device further includes: Multiple first gate structures are disposed between the first surface and the second surface, and multiple first gate structures corresponding to multiple first active structures arranged along the third direction are coupled to the same first word line. Multiple second gate structures are disposed between the fourth surface and the fifth surface, and multiple second gate structures corresponding to multiple second active structures arranged along the third direction are coupled to the same second word line.

13. The semiconductor device according to claim 2, characterized in that, The first active structure includes a first end and a second end opposite to each other along the first direction, the first end being coupled to the first bit line; the second active structure includes a third end and a fourth end opposite to each other along the first direction, the third end being coupled to the second bit line. Wherein, the distance between the first end of the first active structure and the third end of the second active structure arranged along the first direction is greater than the distance between the second end of the first active structure and the fourth end of the second active structure.

14. The semiconductor device according to claim 13, characterized in that, The semiconductor device further includes: Multiple first capacitors, each first capacitor being coupled to the second end; Multiple second capacitors are coupled to the fourth end; wherein the first capacitor and the second capacitor are disposed between the first active structure and the second active structure.

15. The semiconductor device according to claim 1, characterized in that, The semiconductor device includes a three-dimensional dynamic random access memory.

16. A method for manufacturing a semiconductor device, characterized in that, The method includes: A storage array is formed, the storage array including a first subarray and a second subarray arranged along a first direction; the first subarray includes a plurality of first active groups arranged along a second direction; the second subarray includes a plurality of second active groups arranged along the second direction; the first direction and the second direction intersect. A first bit line group is formed on the side of the first active group away from the second active group, and a second bit line group is formed on the side of the second active group away from the first active group; A first isolation structure is formed between adjacent first bit line groups along the second direction, and a second isolation structure is formed between adjacent second bit line groups along the second direction.

17. The manufacturing method according to claim 16, characterized in that, Before forming the storage array, the method further includes: A plurality of first dielectric layers and a plurality of second dielectric layers are formed on one side of the substrate, which are alternately stacked along a third direction; any two of the first direction, the second direction and the third direction intersect each other. Etching removes a portion of the first dielectric layer and a portion of the second dielectric layer to form an initial first step structure, a stacked structure, and an initial second step structure arranged along a first direction; wherein, the step surface of the initial first step structure exposes the second dielectric layer, the stacked structure includes the first dielectric layer and the second dielectric layer alternately stacked along the third direction, and the step surface of the initial second step structure exposes the second dielectric layer.

18. The manufacturing method according to claim 17, characterized in that, The method further includes: The stacked structure is etched to form a plurality of first etched holes, a plurality of second etched holes, and a plurality of third etched holes arranged along the second direction, wherein the first etched holes, the second etched holes, and the third etched holes are arranged along the first direction. A first sacrificial layer, a second sacrificial layer, and a third sacrificial layer are formed in the first etched hole, the second etched hole, and the third etched hole, respectively.

19. The manufacturing method according to claim 18, characterized in that, The formation of the storage array includes: Remove the first sacrificial layer and the third sacrificial layer; A portion of the second dielectric layer is removed through the first etching hole in a direction perpendicular to the third direction to form a first groove, and a portion of the second dielectric layer is removed through the third etching hole in a direction perpendicular to the third direction to form a second groove; An initial first active structure is formed in the space formed by the first etched hole and the first groove, and an initial second active structure is formed in the space formed by the third etched hole and the second groove. A portion of the initial first active structure is removed to form a plurality of first active structures spaced apart along the third direction, and a portion of the initial second active structure is removed to form a plurality of second active structures spaced apart along the third direction; the plurality of first active structures spaced apart along the third direction form a first active group, and the plurality of second active structures spaced apart along the third direction form a second active group.

20. The manufacturing method according to claim 19, characterized in that, The method further includes: A first gate structure is formed in the space formed by the first etched hole and the first groove, and a second gate structure is formed in the space formed by the third etched hole and the second groove; wherein, a plurality of first gate structures corresponding to a plurality of first active structures arranged along the third direction are coupled to the same first word line, and a plurality of second gate structures corresponding to a plurality of second active structures arranged along the third direction are coupled to the same second word line.

21. The manufacturing method according to claim 20, characterized in that, The first active structure includes a first end and a second end opposite to each other along the first direction, and the second active structure includes a third end and a fourth end opposite to each other along the first direction; the method further includes: Remove the second sacrificial layer; A portion of the second dielectric layer is removed through the second etched hole in a direction perpendicular to the third direction to form a third groove that exposes the second end of the first active structure and the fourth end of the second active structure. An initial first electrode is formed in the space formed by the second etched hole and the third groove; Remove a portion of the initial first electrode to form a plurality of first electrodes spaced apart along the third direction; A third dielectric layer and a second electrode are formed in the space formed by the second etched hole and the third groove, respectively forming a first capacitor coupled to the second end of the first active structure and a second capacitor coupled to the fourth end of the second active structure.

22. The manufacturing method according to claim 21, characterized in that, The formation of a first bit line group disposed on the side of the first active group away from the second active group, and the formation of a second bit line group disposed on the side of the second active group away from the first active group, include: The initial first step structure is etched to form a first isolation groove that divides the initial first step structure into a plurality of initial first sub-step structures, and the initial second step structure is etched to form a second isolation groove that divides the initial second step structure into a plurality of initial second sub-step structures. The second dielectric layer in the initial first sub-step structure is removed by the first isolation groove to form a first gap exposing the first end of the first active structure, and the second dielectric layer in the initial second sub-step structure is removed by the second isolation groove to form a second gap exposing the third end of the second active structure. A conductive material is filled in the first gap to form a first bit line, and a conductive material is filled in the second gap to form a second bit line; the first bit line is coupled to the first end, and the second dielectric layer in the initial first sub-step structure is replaced by the first bit line to form a first sub-step structure, and a plurality of the first bit lines arranged along the third direction form a first bit line group; the second bit line is coupled to the third end, and the second dielectric layer in the initial second sub-step structure is replaced by the second bit line to form a second sub-step structure, and a plurality of the second bit lines arranged along the third direction form a second bit line group.

23. The manufacturing method according to claim 22, characterized in that, The number of the first bit line group is the same as the number of the first active group, and the number of the first bit line is the same as the number of the first active structure; the number of the second bit line group is the same as the number of the second active group, and the number of the second bit line is the same as the number of the second active structure.

24. The manufacturing method according to claim 22, characterized in that, The first isolation structure formed between adjacent first bit line groups along the second direction, and the second isolation structure formed between adjacent second bit line groups along the second direction, include: A medium material is filled into the first isolation groove to form a first isolation structure, and a medium material is filled into the second isolation groove to form a second isolation structure.

25. The manufacturing method according to claim 24, characterized in that, The method further includes: A first contact structure is formed extending along the third direction to the first bit line, and a second contact structure is formed extending along the third direction to the second bit line.

26. The manufacturing method according to claim 25, characterized in that, The method further includes: A first conductive line and a second conductive line are formed. In a plurality of first bit line groups arranged along the second direction, a plurality of first contact structures that are coupled to a plurality of first bit lines at the same height position along the third direction are coupled to the same first conductive line. In a plurality of second bit line groups arranged along the second direction, a plurality of second contact structures that are coupled to a plurality of second bit lines at the same height position along the third direction are coupled to the same second conductive line.

27. A memory system, characterized in that, The memory system includes: The semiconductor device as claimed in any one of claims 1 to 15; and A controller coupled to the semiconductor device and configured to control the semiconductor device.

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