Semiconductor structure and method of manufacturing a semiconductor structure
Patent Information
- Application Number
- CN202510559384.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-29
- Publication Date
- 2026-11-03
AI Technical Summary
In the prior art, the coupling capacitance between adjacent bit lines limits the performance of vertical transistor memory, affecting signal integrity and anti-interference capability.
A shielding network is formed by placing shielding pillars between adjacent bit lines. By arranging source pillars and bit lines on both sides of the substrate and spacing shielding pillars between the bit lines, the shielding pillars reduce coupling capacitance, increase the process window, and improve signal integrity and anti-interference capability.
It effectively reduces the coupling capacitance between adjacent bit lines, improves signal integrity and anti-interference capability, while increasing the process window, reducing the difficulty of fabrication process, and increasing storage density.
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Figure CN123035666A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the semiconductor structure. Background Technology
[0002] As memory integration density continues to increase, higher demands are being placed on the arrangement and size of transistors in memory array structures. Researchers have developed vertical transistor structures to reduce footprint and increase storage density. However, the coupling capacitance between adjacent bit lines has become a key factor limiting the performance of vertical transistor memories. Reducing the coupling capacitance between adjacent bit lines, improving signal integrity, and enhancing interference immunity have become hot research topics. Summary of the Invention
[0003] This application addresses the shortcomings of existing methods by proposing a semiconductor structure and a method for fabricating the semiconductor structure, which reduces the coupling capacitance between adjacent bit lines, improves signal integrity, and enhances anti-interference capabilities.
[0004] According to a first aspect of the present disclosure, a semiconductor structure is provided, comprising: a substrate having a first surface and a second surface disposed opposite to each other;
[0005] Active pillars are arranged in an array along a first direction and a second direction on the first surface;
[0006] Bit lines are located on the second surface, extend along a first direction, and connect to the active pillars arranged in the first direction;
[0007] A shielding post is located on the second surface and between adjacent bit lines. A plurality of shielding posts are arranged at intervals in a first direction, with gaps between adjacent shielding posts in the first direction.
[0008] In some embodiments, the gap is located between adjacent active columns.
[0009] In some embodiments, the semiconductor structure further includes: shielding post connecting lines, wherein the shielding posts are disposed on the second surface and connect a plurality of the shielding posts.
[0010] In some embodiments, the shielding connection line extends along a first direction and connects to the shielding posts arranged along the first direction.
[0011] In some embodiments, the shielding connection line extends along a second direction and connects to the shielding posts arranged along the second direction.
[0012] In some embodiments, the semiconductor structure further includes: a word line located on the first surface, extending along a second direction, and connected to the active pillars arranged in the second direction, the second direction being perpendicular to the first direction;
[0013] An isolation layer is located between the bit line and the shielding post.
[0014] In some embodiments, the shielding post also extends between adjacent word lines on the first surface.
[0015] In some embodiments, the shielding post is located between adjacent active posts.
[0016] According to a second aspect of the present disclosure, a method for fabricating a semiconductor structure is provided, comprising providing a substrate having a first surface and a second surface disposed opposite to each other;
[0017] Active pillars are formed on the first surface, and the active pillars are arranged in an array along a first direction and a second direction, wherein the second direction is perpendicular to the first direction;
[0018] A bit line is formed on the second surface, the bit line extending along a first direction and connecting to the active pillars arranged in the first direction;
[0019] A shielding post is formed on the second surface, the shielding post being located between adjacent bit lines, and a plurality of shielding posts are arranged at intervals in a first direction, with gaps between adjacent shielding posts in the first direction.
[0020] In some embodiments, an active pillar is formed on the first surface, including:
[0021] A first groove extending in a first direction and arranged in a second direction is etched on the first surface, and a first insulating layer is filled in the first groove;
[0022] A second groove extending in a second direction and arranged in a first direction is formed on the first surface, and a second insulating layer is filled in the second groove;
[0023] The depth of the first groove is greater than the depth of the second groove.
[0024] In some embodiments, forming bit lines on the second surface includes:
[0025] The substrate is flipped over, the second surface is thinned by grinding to expose the first isolation layer, a metal material layer is deposited on the second surface, the metal material layer reacts with the substrate to form the bit line, and the unreacted metal material layer is removed.
[0026] In some embodiments, forming shielding pillars on the second surface includes:
[0027] A portion of the first isolation layer is etched away, a third groove is formed between adjacent bit lines, a shielding material layer is formed in the third groove, and the shielding material layer on the second surface is removed by grinding to form a shielding line.
[0028] Etching removes part of the shielding wire to form shielding pillars.
[0029] In some embodiments, the method further includes: forming a character line in the second groove, the character line extending along a second direction and connecting to the active posts arranged in the second direction.
[0030] In the embodiments of this disclosure, the active pillars and bit lines are located on opposite sides of the substrate, which effectively saves area and increases storage density. Shielding pillars are formed between adjacent bit lines, with multiple shielding pillars spaced apart and gaps between adjacent pillars. This reduces the coupling capacitance between adjacent bit lines, improving signal integrity and anti-interference capability. The spaced arrangement of the shielding pillars can increase the process window, reduce fabrication difficulty, or allow for further miniaturization of transistors, thereby increasing storage density. Attached Figure Description
[0031] Figure 1 This is a three-dimensional schematic diagram of a semiconductor structure according to an exemplary embodiment;
[0032] Figure 2 This is a top view schematic diagram of a semiconductor structure according to an exemplary embodiment;
[0033] Figure 3 This is a three-dimensional schematic diagram of another semiconductor structure according to an exemplary embodiment;
[0034] Figure 4 This is a three-dimensional schematic diagram of another semiconductor structure according to an exemplary embodiment;
[0035] Figure 5 This is a three-dimensional schematic diagram of another semiconductor structure according to an exemplary embodiment;
[0036] Figure 6 This is a top view schematic diagram of another semiconductor structure according to an exemplary embodiment;
[0037] Figure 7 This is a schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;
[0038] Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A and Figure 20A This is a schematic diagram of a cross-section of the memory along the aa' direction during the fabrication of the semiconductor structure;
[0039] Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B and Figure 20B This is a schematic diagram of a cross-section of the memory along the bb' direction during the fabrication of the semiconductor structure;
[0040] Figure 8C , Figure 9C , Figure 10C , Figure 11C , Figure 12C , Figure 13C , Figure 14C , Figure 15C , Figure 16C , Figure 17C , Figure 18C , Figure 19C and Figure 20C This is a schematic diagram of a cross-section of the memory along the cc' direction during the fabrication of the semiconductor structure;
[0041] Figure 8D , Figure 9D , Figure 10D , Figure 11D , Figure 12D , Figure 13D , Figure 14D , Figure 15D , Figure 16D , Figure 17D , Figure 18D , Figure 19D and Figure 20D This is a schematic diagram of a cross-section of the memory along the dd' direction during the fabrication of the semiconductor structure.
[0042] Explanation of reference numerals in the attached figures:
[0043] 10: Substrate; 11: Active post; 12: Bit line; 13: Shielding line; 14: Word line; 15: Isolation layer; 16: Void; 171: Shielding post connection line; 18: First isolation layer; 19: Second isolation layer; 191: First isolation sublayer; 192: Second isolation sublayer; 20: Gate oxide layer; 21: Capacitor; 211: Lower electrode; 212: High-K dielectric layer; 213: Upper electrode; 22: Carrier disk; 23: First metal material layer; 24: Shielding line; 25: First dielectric layer; T1: First groove; T2: Second groove; T3: Third groove; T4: Fourth groove. Detailed Implementation
[0044] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.
[0045] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.
[0046] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.
[0047] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
[0048] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.
[0049] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.
[0050] Figure 1 This is a three-dimensional schematic diagram illustrating a semiconductor structure according to an exemplary embodiment. Figure 1 It can be deduced that the semiconductor structure includes a substrate (not shown) having a first surface and a second surface disposed opposite to each other; active pillars 11, which are arranged in an array on the first surface along a first direction (e.g., the Y direction) and a second direction (e.g., the X direction); bit lines 12, which are located on the second surface and extend along the first direction (e.g., the Y direction) to connect the active pillars 11 arranged in the first direction (e.g., the Y direction); and shielding pillars 13, which are located between adjacent bit lines 12. Multiple shielding pillars 13 are arranged at intervals in the first direction, and gaps 16 are provided between adjacent shielding pillars 13 in the first direction. The active pillars 11 and bit lines 12 are located on opposite sides of the substrate, which can effectively save area and increase storage density. The shielding pillars 13 formed between adjacent bit lines 12, with multiple shielding pillars 13 arranged at intervals and gaps 16 between adjacent shielding pillars 13, can reduce the coupling capacitance between adjacent bit lines 12, improving signal integrity and anti-interference capability.
[0051] Continue to refer to Figure 1 In some embodiments, the active pillars 11 are disposed perpendicular to the substrate, and the active bodies 11 are arranged in an array on the first surface along a first direction (e.g., the Y direction) and a second direction (e.g., the X direction). The active pillars 11 can be part of the substrate and are formed by etching the substrate. The material of the active pillars 11 includes semiconductor materials, such as elemental semiconductor materials (e.g., silicon (Si) or germanium (Ge), III-V compound semiconductor materials (e.g., gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP), etc.), II-VI compound semiconductor materials (e.g., zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), etc.), organic semiconductor materials, or other semiconductor materials known in the art. In this application, a single-crystal silicon substrate is used as an example for illustration.
[0052] Continue to refer to Figure 1In some embodiments, bit lines 12 are located on a second surface of a substrate, extend along a first direction (e.g., the Y direction), and are connected to one end of active pillars 11 arranged in the first direction (e.g., the Y direction). Bit lines 12 are made of conductive materials and may include one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), cobalt (Co), nickel (Ni)); alloys (e.g., Co-based alloys, Ti-based alloys, Co and Ni-based alloys, Fe and Co-based alloys); conductive metal materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides); and conductive doped semiconductor materials (e.g., conductive doped polysilicon, conductive doped silicon germanium). In some embodiments, there is a transition contact layer (not shown) between the bit line 12 and the active post 11. The transition contact layer is made of a conductive material, such as a metal silicide, to reduce the contact resistance between the bit line 12 and the active post 11.
[0053] Continue to refer to Figure 1 In some embodiments, shielding pillars 13 are located on the second surface of the substrate, extending along a first direction (e.g., the Y direction) between adjacent bit lines 12, and alternating with bit lines 12 along a second direction (e.g., the X direction). The shielding pillars 13 are made of a conductive material, which may include one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), cobalt (Co), nickel (Ni)); alloys (e.g., Co-based alloys, Ti-based alloys, Co and Ni-based alloys, Fe and Co-based alloys); conductive metal materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides); and conductive doped semiconductor materials (e.g., conductive doped polysilicon, conductive doped silicon germanium). A plurality of shielding pillars 13 are spaced apart along the first direction, and there is a gap 16 between two adjacent shielding pillars 13 in the first direction. When the shielding post 13 is energized, it can form an electronic barrier, which can reduce the coupling capacitance between adjacent bit lines 12 and improve signal integrity and anti-interference ability.
[0054] Figure 2 This is a top view schematic diagram of a semiconductor structure according to an exemplary embodiment, combined with... Figure 1 and Figure 2In some embodiments, in the second direction, the gap 16 is located between adjacent active pillars 11, and in the first direction, the gap 16 is located between adjacent shielding pillars 13. The active pillars 11 and the shielding pillars 13 form the four sidewalls of the gap 16. The gap 16 is located in the middle of the active pillars 11, which can increase the spacing between the active pillars 11, increase the process window, reduce the difficulty of the manufacturing process, or further reduce the distance between the active pillars 11, thereby increasing the storage density.
[0055] Figure 3 This is a three-dimensional schematic diagram illustrating another semiconductor structure according to an exemplary embodiment. (Reference) Figure 1 and Figure 3 In some embodiments, the shielding post 13 protrudes from the first surface, that is, the top surface of the shielding post 13 is higher than the second surface, which facilitates connection to an external power supply. The semiconductor structure also includes a shielding post connecting line 17, which is located on the second surface and extends along a first direction. Located on the top surface of the shielding post 13, it connects the shielding posts 13 arranged along the first direction. The width of the shielding post connecting line 17 along the second direction can be wider than the width of the shielding post 13 along the second direction, which can reduce the manufacturing difficulty of the shielding post connecting line 17. The shielding post connecting line 17 is made of a conductive material, which may include one or more of the following: metal (…). For example, tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), cobalt (Co), nickel (Ni); alloys (e.g., Co-based alloys, Ti-based alloys, Co and Ni-based alloys, Fe and Co-based alloys); materials containing conductive metals (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides); and conductive doped semiconductor materials (e.g., conductive doped polycrystalline silicon, conductive doped silicon germanium). The shielding post connecting wire 17 can be prepared by one or more methods such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, and electroplating.
[0056] Figure 4 This is a three-dimensional schematic diagram illustrating another semiconductor structure according to an exemplary embodiment. (Reference) Figure 1 and Figure 4In some embodiments, the shielding post connecting line 17 extends along the second direction and is located on top of the shielding post 13 on the second surface, connecting the shielding posts 13 arranged along the second direction. The width of the shielding post connecting line 17 along the first direction can be smaller than the width of the shielding post 13 along the first direction. The shielding post connecting line 17 is perpendicular to the bit line 12 extending along the first direction. Multiple shielding post connecting lines 17 and multiple bit lines 12 form a network structure, forming a shielding network, which can better reduce the coupling capacitance between adjacent bit lines 12, improve signal integrity and anti-interference capability.
[0057] Continue to refer to Figure 1 , Figure 2 , Figure 3 and Figure 4 In some embodiments, an insulating layer 15 is further provided between the bit line 12 and the shield line 13. The insulating layer 15 can isolate the bit line 12 and the shield line 13, preventing them from contacting and forming a short circuit. The insulating layer 15 covers the surface of the bit line 12 and can also protect the bit line 12, preventing damage to the bit line 12 by subsequent processes. The material of the insulating layer 15 can be a low dielectric constant material, such as silicon oxide, silicon nitride, silicon carbide, silicon carbide nitride, or silicon oxynitride. The insulating layer 15 can be prepared by one or more processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma deposition (HDP), plasma-enhanced deposition, and spin-on dielectric (SOD).
[0058] Continue to refer to Figure 1 , Figure 2 , Figure 3 and Figure 4In some embodiments, the semiconductor structure further includes word lines 14 disposed on a first surface of the substrate. Word lines 14 extend along a second direction (e.g., the X direction) and connect to active pillars 11 along the second direction (e.g., the X direction). Word lines 14 may be disposed around active pillars 11 or on one, two, or three sides of active pillars 11 for controlling the switching on and off of transistors. The word line 14 is made of a conductive material, which may include one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), cobalt (Co), nickel (Ni)); alloys (e.g., Co-based alloys, Ti-based alloys, Co and Ni-based alloys, Fe and Co-based alloys); materials containing conductive metals (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides); and conductive doped semiconductor materials (e.g., conductive doped polysilicon, conductive doped silicon germanium). The word line 14 may be formed by one or more of the following methods: chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, electroplating, etc.
[0059] Figure 5 This is a three-dimensional schematic diagram illustrating another semiconductor structure according to an exemplary embodiment. (Reference) Figure 2 and Figure 5 In some embodiments, the shielding post 13 may also have a second surface extending to the first surface, located between adjacent word lines 14, and in the space where word lines 14 and bit lines 12 intersect. The shielding post 13 can not only better reduce the coupling capacitance between adjacent bit lines 12 and improve signal integrity and anti-interference capability, but also better reduce the coupling capacitance between adjacent word lines 14 and improve signal integrity and anti-interference capability.
[0060] Figure 6 This is a top view schematic diagram of another semiconductor structure according to an exemplary embodiment, with reference to... Figure 2 and Figure 6 In some embodiments, the shielding posts 13 are located between adjacent active posts 11, and the shielding posts 13 are spaced apart along a first direction, located between adjacent bit lines 12. The bit lines 12 and the shielding posts 13 form the sidewalls of the four sides of the gap 16. The spaced arrangement of the active posts 11 and the shielding posts 13 in the first direction can better reduce the coupling capacitance between adjacent bit lines 12, improve signal integrity and anti-interference capability, and can also better reduce the coupling capacitance between adjacent active posts 11, improving signal integrity and anti-interference capability.
[0061] Figure 7 This is a schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure; Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A and Figure 20A This is a schematic diagram of a cross-section of the memory along the aa' direction during the fabrication of the semiconductor structure; Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B and Figure 20B This is a schematic diagram of a cross-section of the memory along the bb' direction during the fabrication of the semiconductor structure; Figure 8C , Figure 9C , Figure 10C , Figure 11C , Figure 12C , Figure 13C , Figure 14C , Figure 15C , Figure 16C , Figure 17C , Figure 18C , Figure 19C and Figure 20C This is a schematic diagram of a cross-section of the memory along the cc' direction during the fabrication of the semiconductor structure; Figure 8D , Figure 9D , Figure 10D , Figure 11D , Figure 12D , Figure 13D , Figure 14D , Figure 15D , Figure 16D , Figure 17D , Figure 18D , Figure 19D and Figure 20D This is a schematic diagram of a cross-section of the memory along the dd' direction during the fabrication of the semiconductor structure.
[0062] The method for fabricating the memory provided in the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. (Refer to...) Figure 7 As shown, the preparation method includes at least the following steps:
[0063] S710: Provides a substrate having a first surface and a second surface disposed opposite to each other; active pillars are formed on the first surface, the active pillars being arranged in an array along a first direction and a second direction respectively, the second direction being perpendicular to the first direction;
[0064] S720: A bit line is formed on the second surface, the bit line extends along a first direction, and connects to active pillars arranged in the first direction;
[0065] S730: Shielding pillars are formed on the second surface, the shielding pillars are located between adjacent bit lines, multiple shielding pillars are arranged at intervals in the first direction, and gaps are provided between adjacent shielding pillars in the first direction.
[0066] It should be understood that Figure 7 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 7 The steps shown can be adjusted in order according to actual needs.
[0067] In the semiconductor structure manufacturing method disclosed herein, firstly, forming a vertical transistor structure on a first surface of a substrate can reduce the area occupied by the transistor structure and increase the storage density. Secondly, forming bit lines on a second surface of the substrate can reduce the processing difficulty and decrease the coupling capacitance between the bit lines and capacitor contacts. Thirdly, forming shielding pillars between adjacent bit lines can reduce the coupling capacitance between adjacent bit lines and improve signal integrity and anti-interference capability. Fourthly, arranging the shielding pillars at intervals can increase the process window, reduce the fabrication process difficulty, or allow for further miniaturization of the transistor size, thereby increasing the storage density.
[0068] Continue to refer to Figure 2 In some embodiments, multiple active pillars 11 are arranged in an array, multiple word lines 14 extend along a second direction (e.g., the X direction) and are arranged along a first direction (e.g., the Y direction), each word line 14 connects to an active body structure 11 arranged along the second direction (e.g., the X direction), multiple bit lines 12 extend along the first direction (e.g., the Y direction) and are arranged along the second direction (e.g., the X direction), each bit line 12 connects to an active pillar 11 arranged along the first direction (e.g., the Y direction), wherein the first direction (e.g., the Y direction) and the second direction (e.g., the X direction) are perpendicular, aa' is a cross-sectional schematic diagram along the bit line 12, bb' is a cross-sectional schematic diagram along the bit lines, cc' is a cross-sectional schematic diagram along the word line 14, and dd' is a cross-sectional schematic diagram along the word lines.
[0069] Combination Figure 2 , Figure 7 , Figure 8A , Figure 8B , Figure 8C and Figure 8DIn some embodiments, S710: A substrate 10 is provided, the substrate 10 having a first surface and a second surface disposed opposite to each other. The material of the substrate 10 includes semiconductor materials, such as elemental semiconductor materials (e.g., silicon (Si) or germanium (Ge), III-V compound semiconductor materials (e.g., gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP), etc.), II-VI compound semiconductor materials (e.g., zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), etc.), organic semiconductor materials, or other semiconductor materials known in the art. In this application, a single-crystal silicon substrate is used as an example for illustration.
[0070] refer to Figure 7 , Figure 9A , Figure 9B , Figure 9C and Figure 9D In some embodiments, S710: Active pillars 11 are formed on the first surface. The active pillars 11 are arranged in an array along a first direction and a second direction, respectively. The second direction is perpendicular to the first direction. The method of forming the active pillars 11 includes patterning and etching a plurality of first grooves T1 extending along the first direction and arranged along the second direction on the substrate 10. Specifically, one or more mask layers can be deposited on the surface of the substrate 10, photoresist can be deposited on the surface of the mask layer, an etching pattern can be formed on the photoresist after exposure, and the mask layer and the substrate 10 can be etched along the etching pattern to form the first grooves T1. The method of depositing the mask layer can include, but is not limited to, at least one of the following processes: chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma deposition (HDP), plasma-enhanced deposition, and spin-on dielectric (SOD). The etching method can be dry etching, wet etching, or a combination thereof.
[0071] refer to Figure 10A , Figure 10B , Figure 10C and Figure 10DIn some embodiments, a first insulating material is deposited in the first groove T1, and then ground flat to form a first insulating layer 18. The material of the first insulating layer 18 can be a low dielectric constant material, such as silicon oxide, silicon nitride, silicon carbide, silicon carbide nitride, or silicon oxynitride, thereby reducing the coupling between adjacent bit line structures 17. The first insulating layer 18 can be deposited using a deposition process, which may include, but is not limited to, at least one of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma deposition (HDP), plasma-enhanced deposition, and spin-on dielectric (SOD). The embodiments of this application are illustrated using silicon oxide as an example.
[0072] Continue to refer to Figure 10A , Figure 10B , Figure 10C and Figure 10D In some embodiments, a plurality of second grooves T2 extending along a second direction and arranged along a first direction are patterned and etched on the substrate 10. The first groove T1 and the second groove T2 are perpendicular to each other, and the depth of the first groove T1 is greater than the depth of the second groove T2, forming an active pillar 11 perpendicular to the substrate 10. Specifically, one or more mask layers can be deposited on the surface of the substrate 10, photoresist can be deposited on the surface of the mask layer, and after exposure, an etching pattern is formed on the photoresist. The mask layer, part of the first isolation layer 18 and the substrate 10 are etched along the etching pattern to form the second grooves T2. The method of depositing the mask layer can include, but is not limited to, at least one of the following processes: chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma deposition (HDP), plasma-enhanced deposition, and spin-on dielectric (SOD). The etching method can be dry etching, wet etching, or a combination thereof.
[0073] Continue to refer to Figure 10A , Figure 10B , Figure 10C and Figure 10DIn some embodiments, a second isolation material is deposited in the second groove T2, and then ground flat to form a second isolation layer 19. The second isolation layer 19 includes a first isolation sublayer 191 and a second isolation sublayer 192. The first isolation sublayer 191 is deposited on the sidewall of the second groove T2, and the second isolation sublayer 192 is deposited within the first isolation sublayer 191. The first and second isolation sublayers 191 and 192 completely fill the second groove T2. The materials of the first and second isolation sublayers 191 and 192 can be low-dielectric-constant materials, such as silicon oxide, silicon nitride, silicon carbide, silicon carbide nitride, or silicon oxynitride, thereby reducing coupling between adjacent active pillars 11. The materials of the first and second isolation sublayers 191 and 192 can be the same or different. The first and second isolation sublayers 191 and 192 can be deposited using processes including, but not limited to, chemical vapor deposition (CVD) and physical vapor deposition (PVD). At least one of the following processes is used: physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma deposition (HDP), plasma-enhanced deposition, and spin-on dielectric (SOD). The first isolation sublayer 191 and the second isolation sublayer 192 can be fabricated using the same or different processes. In this embodiment, the first isolation sublayer 191 is made of silicon oxide, and the second isolation sublayer 192 is made of silicon nitride.
[0074] refer to Figure 11A , Figure 11B , Figure 11C and Figure 11DIn some embodiments, a portion of the second isolation layer 18 and a portion of the first isolation sublayer 191 are selectively etched away to expose a portion of the active pillars 11, forming word lines 14 surrounding the active pillars 11. The word lines 14 extend along a second direction and connect to the active pillars 11 arranged in the second direction. The word lines 14 are made of a conductive material, which may include one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), cobalt (Co), nickel (Ni)); alloys (e.g., Co-based alloys, Ti-based alloys, Co and Ni-based alloys, Fe and Co-based alloys); conductive metal materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides); and conductive doped semiconductor materials (e.g., conductive doped polysilicon, conductive doped silicon-germanium). The word line 14 can be formed using one or more methods such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), sputtering, and electroplating. In some embodiments, before forming the word line 14, a gate oxide layer 20 is formed. The gate oxide layer 20 is located between the active pillar 11 and the word line 14. The gate oxide layer 20 can be formed using one or more methods such as In-Situ Steam Generation (ISSG), Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), and High Density Plasma (HDP). The material of the gate oxide layer 20 is selected from silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, strontium titanium oxide, or combinations thereof.
[0075] refer to Figure 12A , Figure 12B , Figure 12C and Figure 12DIn some embodiments, after forming the word line 14, a storage structure is further formed at one end of the active pillar. The storage structure may include one or more of a capacitor, a ferroelectric storage structure, a phase-change storage structure, a resistive switching storage structure, and a magnetic switching storage structure, for storing information transmitted from the bit line 12. Taking capacitor 21 as an example, capacitor 21 includes a lower electrode 211, a high-k dielectric layer 212, and an upper electrode 213. The lower electrode 211 is connected to the active pillar 11. The material of the lower electrode 211 may be selected from at least one of metals, metal nitrides, or metal oxides, such as tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), platinum (Pt), iridium (Ir), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), iridium oxide (IrO2), and titanium oxide (TiO). The high-k dielectric layer 212 covers the surface of the lower electrode 211. The material of the high-k dielectric layer 212 may be selected from at least one of high-k dielectric films with a dielectric constant greater than that of silicon oxide, such as hafnium oxide (HfO2). The upper electrode 213 covers the surface of the high-K dielectric layer 212. The material of the upper electrode 213 can be selected from at least one of metals, metal nitrides or metal oxides, such as tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), platinum (Pt), iridium (Ir), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), iridium oxide (IrO2), and titanium oxide (TiO). The materials of the upper electrode 213 and the lower electrode 211 can be the same or different.
[0076] refer to Figure 7 , Figure 13A , Figure 13B , Figure 13C and Figure 13D In some embodiments, S720: Bit lines 12 are formed on the second surface, extending along the first direction and connected to active pillars 11 arranged in the first direction. Specifically, a carrier disk 22 is formed on the first surface of the substrate. The carrier disk is located on the capacitor and can protect the capacitor from damage. The substrate 10 is flipped over, and the second surface of the substrate 10 is thinned by grinding to expose the first isolation layer 18. The carrier disk 22 can be a wafer or other carrier that can support semiconductor structures. One or more of laser cutting, chemical polishing, and etching processes can be used to thin the second surface of the substrate 10 to expose the first isolation layer 18. The substrate is divided into multiple strips extending along the first direction by the first groove T1. Multiple active pillars 11 are arranged along the first direction and disposed on the strips extending in the first direction.
[0077] refer to Figure 14A , Figure 14B , Figure 14C and Figure 14D In some embodiments, a first metal material layer 23 is deposited on the second surface of the substrate. The metal material layer 23 covers the surface of the first isolation layer 18 and the strip. The material of the metal material layer may include one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), cobalt (Co), nickel (Ni)); alloys (e.g., Co-based alloys, Ti-based alloys, Co and Ni-based alloys, Fe and Co-based alloys); conductive metal materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides); and conductive doped semiconductor materials (e.g., conductive doped polysilicon, conductive doped silicon-germanium). The method for forming the metal material layer 23 may employ one or more of the following methods: chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, electroplating, etc.
[0078] refer to Figure 15A , Figure 15B , Figure 15C and Figure 15D In some embodiments, the semiconductor structure is subjected to high-temperature treatment to react the metal material layer 23 with the substrate 10 and then the unreacted metal material layer 23 is removed, and a bit line 12 is formed on the second surface of the substrate. The bit line 12 extends along a first direction and connects to the active pillars 11 arranged along the first direction.
[0079] refer to Figure 7 , Figure 16A , Figure 16B , Figure 16C and Figure 16D In some embodiments, S730: Shielding pillars 13 are formed on the second surface. The shielding pillars 13 are located between adjacent bit lines 12. Multiple shielding pillars 13 are arranged at intervals in the first direction, and gaps 16 are provided between adjacent shielding pillars 13 in the first direction. Specifically, a portion of the second isolation layer 18 is etched away to form a third groove T3. The first isolation layer 18 and the bit line 12 are made of different materials. Self-aligned selective etching can be performed using an etching selectivity ratio, etching only the first isolation layer 18 and retaining the bit line 12. Dry etching or wet etching can be used. The bottom of the third groove T3 can be slightly lower than the position where the bit line 12 connects to the active pillar 13.
[0080] refer to Figure 17A , Figure 17B , Figure 17C and Figure 17D In some embodiments, an isolation layer 15 is deposited in the third groove T3. The isolation layer 15 is deposited conformally within the third groove T3 and covers the surface of the bit line 12, thus protecting the bit line 12 and preventing damage to it from subsequent processes. The material of the isolation layer 15 can be a low dielectric constant material, such as silicon oxide, silicon nitride, silicon carbide, silicon carbide nitride, or silicon oxynitride. The isolation layer 15 can be prepared using one or more processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma deposition (HDP), plasma-enhanced deposition, and spin-on dielectric (SOD).
[0081] refer to Figure 18A , Figure 18B , Figure 18C and Figure 18D In some embodiments, a shielding wire material is deposited on the surface of the insulating layer 15, and then ground and flattened to form a shielding wire 24. The shielding wire 24 extends along a first direction (e.g., the Y direction) and is located between adjacent bit lines 12, and alternates with the bit lines 12 along a second direction (e.g., the X direction). The shielding wire 24 is made of a conductive material, which may include one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), cobalt (Co), nickel (Ni)); alloys (e.g., Co-based alloys, Ti-based alloys, Co and Ni-based alloys, Fe and Co-based alloys); conductive metal materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides); and conductive doped semiconductor materials (e.g., conductive doped polysilicon, conductive doped silicon germanium). The shielding wire 24 may be fabricated using a chemical vapor deposition process. It is prepared by one or more processes such as physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma deposition (HDP), plasma-enhanced deposition, and spin-on dielectric (SOD).
[0082] refer to Figure 19A , Figure 19B , Figure 19C and Figure 19D In some embodiments, patterned etching removes part of the shielding line 24 to form shielding pillars 13. Specifically, one or more mask layers are deposited on the second surface of the substrate, photoresist is deposited on the mask layer surface, and after exposure, an etching pattern is formed on the photoresist. The mask layer and shielding line 24 are etched along the etching pattern to form a fourth groove T4. The fourth groove T4 divides the shielding line 24 into spaced shielding pillars 13. The method for depositing the mask layer can include, but is not limited to, at least one of the following processes: Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), High Density Plasma (HDP), Plasma Enhanced Deposition (PDE), and Spin-on Dielectric (SOD). The etching method can be dry etching, wet etching, or a combination thereof.
[0083] Reference 20A, Figure 20B , Figure 20C and Figure 20D In some embodiments, a first dielectric layer 25 is deposited on the second surface of the substrate. The first dielectric layer 25 fills a fourth groove T4, forming a void 16 within the fourth groove T4. The material of the first dielectric layer 25 can be a low dielectric constant material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or silicon oxynitride. The first dielectric layer 25 can be prepared using one or more processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma deposition (HDP), plasma-enhanced deposition, and spin-on dielectric (SOD).
[0084] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. A semiconductor structure, characterized in that, include: A substrate having a first surface and a second surface disposed opposite to each other; Active columns are arranged in an array on the first surface along a first direction and a second direction, wherein the second direction is perpendicular to the first direction; Bit lines are located on the second surface, extend along a first direction, and connect to the active pillars arranged in the first direction; A shielding post is located on the second surface and between adjacent bit lines. A plurality of shielding posts are arranged at intervals in a first direction, and there are gaps between adjacent shielding posts in the first direction.
2. The semiconductor structure according to claim 1, characterized in that, The gap is located between adjacent active columns.
3. The semiconductor structure according to claim 1, characterized in that, The top surface of the shielding post on the second surface is higher than the top surface of the bit line on the second surface.
4. The semiconductor structure according to claim 3, further comprising: A shielding post connecting line, wherein the shielding posts are disposed on the second surface and connect multiple shielding posts.
5. The semiconductor structure according to claim 4, characterized in that, The shielding connection line extends along a first direction and connects to the shielding posts arranged along the first direction.
6. The semiconductor structure according to claim 4, characterized in that, The shielding connection line extends along the second direction and connects the shielding posts arranged along the second direction.
7. The semiconductor structure according to any one of claims 1-6, further comprising: A character line, wherein the character line is disposed on the first surface, extends along the second direction, and connects the active columns arranged along the second direction; An isolation layer is located between the bit line and the shielding post.
8. The semiconductor structure according to claim 7, characterized in that, The shielding post also extends between adjacent word lines on the first surface.
9. The semiconductor structure according to claim 1, characterized in that, The shielding post is located between adjacent active posts.
10. A method for fabricating a semiconductor structure, characterized in that, A substrate is provided, the substrate having a first surface and a second surface disposed opposite to each other; Active pillars are formed on the first surface, and the active pillars are arranged in an array along a first direction and a second direction, wherein the second direction is perpendicular to the first direction; A bit line is formed on the second surface, the bit line extending along a first direction and connecting to the active pillars arranged in the first direction; A shielding post is formed on the second surface, the shielding post being located between adjacent bit lines, and a plurality of shielding posts are arranged at intervals in a first direction, with gaps between adjacent shielding posts in the first direction.
11. The preparation method according to claim 10, characterized in that, An active pillar is formed on the first surface, including: A first groove extending in a first direction and arranged in a second direction is etched on the first surface, and a first insulating layer is filled in the first groove; A second groove extending in a second direction and arranged in a first direction is formed on the first surface, and a second insulating layer is filled in the second groove; The depth of the first groove is greater than the depth of the second groove.
12. The preparation method according to claim 11, characterized in that, Forming bit lines on the second surface includes: The substrate is flipped over, the second surface is thinned by grinding to expose the first isolation layer, a metal material layer is deposited on the second surface, the metal material layer reacts with the substrate to form the bit line, and the unreacted metal material layer is removed.
13. The preparation method according to claim 12, characterized in that, Forming shielding pillars on the second surface includes: A portion of the first isolation layer is etched away, a third groove is formed between adjacent bit lines, a shielding material layer is formed in the third groove, and the shielding material layer on the second surface is removed by grinding to form a shielding line. Etching removes part of the shielding wire to form shielding pillars.
14. The preparation method according to any one of claims 11-13, further comprising: A letter line is formed in the bottom of the second groove, the letter line extends along a second direction and connects to the active columns arranged in the second direction.