Semiconductor device including a back gate electrode structure and method of manufacturing the same

Abstract

Semiconductor devices including a back gate electrode structure and methods of manufacturing the same are provided. The semiconductor device includes a bit line extending in a first direction, a word line extending in a second direction intersecting the first direction, the word line being located over the bit line in a third direction intersecting the first and second directions, a back gate electrode structure located over the bit line in the third direction, the back gate electrode structure being spaced apart from the word line in the first direction and extending in the second direction, and an active pattern located on the bit line, the active pattern being located between the word line and the back gate electrode structure in the first direction and extending in the third direction, wherein a height of the back gate electrode structure in the third direction is less than a height of the word line in the third direction.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] To ensure high performance and low price, it is necessary to increase the integration density of semiconductor devices. Since the integration density of semiconductor devices is a major factor in product pricing, it is particularly important to increase integration density.

[0003] The integration density of two-dimensional (2D) or planar semiconductor devices is typically determined by the area occupied by a single memory cell, and is therefore heavily influenced by the level of fine patterning technology. However, due to the high cost of equipment required for fine patterning, the integration density of 2D semiconductor devices, while improving, remains limited. Therefore, the use of semiconductor devices incorporating vertical-channel transistors (VCTs), where the channel extends vertically, is recommended.

[0004] The information disclosed in the background section is technical information that the inventors knew or obtained before or during the implementation of the embodiments of this application, or that they obtained during the implementation of the embodiments. Therefore, it may contain information that does not constitute prior art known to the public. Summary of the Invention

[0005] One or more example embodiments provide a semiconductor device that can enhance electrical reliability.

[0006] One or more example embodiments provide a semiconductor device that can reduce the risk of leakage current.

[0007] Other aspects will be set forth in part in the description below, and in part will be clear from the description or may be learned by practice of the embodiments presented.

[0008] According to one aspect of an example embodiment, a semiconductor device may include: a bit line extending in a first direction; a word line extending in a second direction intersecting the first direction, the word line being located above the bit line in a third direction intersecting the first and second directions; a back gate electrode structure located above the bit line in the third direction, spaced apart from the word line in the first direction, and extending in the second direction; and an active pattern located on the bit line, situated between the word line and the back gate electrode structure in the first direction, and extending in the third direction, wherein the height of the back gate electrode structure in the third direction is less than the height of the word line in the third direction, and wherein the back gate electrode structure includes: at least one back gate work function adjustment pattern; and a back gate body pattern contacting the at least one back gate work function adjustment pattern in the third direction.

[0009] According to one aspect of an example embodiment, a semiconductor device may include: a plurality of bit lines extending in a first direction and spaced apart from each other in a second direction intersecting the first direction; a back gate electrode structure extending in the second direction and located above the plurality of bit lines in a third direction intersecting the first and second directions; a first active pattern located on the plurality of bit lines, on a first side of the back gate electrode structure in the first direction, and extending upward in the third direction; a second active pattern located on the plurality of bit lines, on a second side of the back gate electrode structure in the first direction, and extending upward in the third direction; and a first word line located above the plurality of bit lines in the third direction, the first word line being located above the back gate electrode structure in the third direction. The first side of the electrode structure, and spaced apart from the back gate electrode structure in the first direction, the first active pattern is located between the first word line and the back gate electrode structure in the first direction; and the second word line, the second word line being located above the plurality of bit lines in the third direction, the second word line being located on the second side of the back gate electrode structure, and spaced apart from the back gate electrode structure in the first direction, the second active pattern being located between the second word line and the back gate electrode structure in the first direction, wherein the back gate electrode structure includes a first back gate work function adjustment pattern, a back gate main pattern and a second back gate work function adjustment pattern sequentially stacked in the third direction, and the work function of each of the first back gate work function adjustment pattern and the second back gate work function adjustment pattern is greater than the work function of the back gate main pattern.

[0010] According to one aspect of an example embodiment, a semiconductor device may include: a bit line extending in a first direction; a word line extending in a second direction intersecting the first direction, the word line being located above the bit line in a third direction intersecting the first and second directions; a back gate electrode structure located above the bit line in the third direction, spaced apart from the word line in the first direction, and extending in the second direction; an active pattern located on the bit line, situated between the word line and the back gate electrode structure in the first direction, and extending in the third direction; and a data storage pattern located above the active pattern in the third direction and connected to the active pattern, wherein a first surface and a second surface of the back gate electrode structure in the third direction are located between the first surface and the second surface of the word line in the third direction, the back gate electrode structure comprising a first back gate work function adjustment pattern, a back gate body pattern, and a second back gate work function adjustment pattern sequentially stacked in the third direction, and the work function of each of the first back gate work function adjustment pattern and the second back gate work function adjustment pattern being greater than the work function of the back gate body pattern. Attached Figure Description

[0011] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a diagram illustrating a schematic layout of a semiconductor device according to some example embodiments; Figure 2 It shows along Figure 1 A diagram of the cross-sections taken from AA and BB; Figure 3 It shows along Figure 1 A diagram of the cross-sections taken from CC and DD; Figure 4 yes Figure 2 An enlarged view of part P in the image; Figure 5 It is used to illustrate a semiconductor device according to an example embodiment. Figure 2 An enlarged view of part P in the image; Figure 6 It is used to illustrate a semiconductor device according to an example embodiment. Figure 2 An enlarged view of part P in the image; Figure 7 It is used to illustrate a semiconductor device according to an example embodiment. Figure 2 An enlarged view of part P in the image; Figure 8 It is used to illustrate a semiconductor device according to an example embodiment. Figure 2An enlarged view of part P in the image; Figure 9 It is used to illustrate a semiconductor device according to an example embodiment. Figure 2 An enlarged view of part P in the image; Figure 10 It is used to illustrate a semiconductor device according to an example embodiment. Figure 2 An enlarged view of part P in the image; Figure 11 It is used to illustrate a semiconductor device according to an example embodiment. Figure 2 An enlarged view of part P in the image; Figure 12 It is used to illustrate a semiconductor device according to an example embodiment. Figure 2 An enlarged view of part P in the image; Figure 13 It is used to illustrate a semiconductor device according to an example embodiment. Figure 2 An enlarged view of part P in the image; Figure 14 It is used to illustrate a semiconductor device according to an example embodiment. Figure 2 An enlarged view of part P in the image; Figure 15 It is used to illustrate a semiconductor device according to an example embodiment. Figure 2 An enlarged view of part P in the image; Figure 16 It is used to illustrate a semiconductor device according to an example embodiment. Figure 2 An enlarged view of part P in the image; Figure 17 It is used to illustrate a semiconductor device according to an example embodiment. Figure 2 An enlarged view of part P in the image; and Figures 18 to 71 This is a diagram illustrating the operation of a method for manufacturing a semiconductor device according to some example embodiments. Detailed Implementation

[0012] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same components, and redundant descriptions are omitted. The embodiments described herein are exemplary embodiments, and therefore, the present disclosure is not limited thereto and can be implemented in various other forms.

[0013] As used in this article, expressions such as "at least one" modify the entire list of elements when they precede it, rather than modifying any individual element in the list. For example, the expression "at least one of a, b, or c" should be understood as only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0014] It will be understood that when a component or layer is referred to as being "above," "on top of," "above," "below," "under," "connected to," or "coupled to" another component or layer, it can be directly located on, directly connected to, or directly coupled to the other component or layer, or there can be intermediate components or layers. In contrast, when a component is referred to as being "directly located" "above," "on top of," "above," "below," "under," "under," "directly connected to," or "directly coupled to" another component or layer, there are no intermediate components or layers.

[0015] Terms such as "first" and "second" can be used to describe various components, but only for the purpose of distinguishing one component from another. These terms do not limit the differences in materials or structures of the components.

[0016] Unless otherwise stated, singular terms may include plural forms. Furthermore, when a part “includes” a component, it means that other components may be included rather than excluded, unless otherwise stated.

[0017] The use of the term "as stated" and similar designated terms can correspond to both singular and plural forms.

[0018] The operations of the method may be performed in a suitable order unless explicitly described in order. Furthermore, all illustrative terms (e.g., etc.) are used merely for the purpose of describing the technical idea in detail, and the scope is not limited by these examples or illustrative terms unless otherwise defined in the claims.

[0019] In the following description, exemplary embodiments of the present disclosure are illustrated with reference to the accompanying drawings.

[0020] Figure 1 This is a diagram illustrating a schematic layout of a semiconductor device according to some example embodiments. Figure 2 It shows along Figure 1 The diagram shows the cross-sections taken from AA and BB. Figure 3 It shows along Figure 1 A diagram of the cross sections taken from CC and DD. Figure 4 yes Figure 2 An enlarged view of part P in the image.

[0021] refer to Figures 1 to 4 The semiconductor device according to some example embodiments may include a bit line BL, multiple word lines WL1 and WL2, a back gate electrode structure BG, a shield line SL, multiple active patterns AP1 and AP2, and a data storage pattern DSP.

[0022] According to some example embodiments, substrate 100 may be, for example, a silicon substrate. As another example, substrate 100 may include, but is not limited to, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Substrate 100 may include a cell array region provided with a data storage pattern DSP, and a peripheral circuit region defined around the cell array region.

[0023] According to some example embodiments, a peripheral gate structure PG can be disposed on the substrate 100. The peripheral gate structure PG can be disposed across the cell array region and the peripheral circuit region. The peripheral gate structure PG can be included in a sensing transistor, a transmission transistor, and a driving transistor. For example, the peripheral gate structure PG included in the sensing transistor can be disposed on the cell array region of the substrate 100, but is not limited thereto. The type of transistor in the peripheral circuit disposed on the cell array region of the substrate 100 can vary depending on the design layout of the semiconductor device.

[0024] According to some example embodiments, the peripheral gate structure PG may include a peripheral gate insulating layer 215, a peripheral gate conductive pattern 223, and a peripheral gate mask pattern 225. The peripheral gate insulating layer 215 may include a silicon oxide layer, a silicon oxynitride layer, a high-dielectric-constant insulating layer with a dielectric constant higher than that of the silicon oxide layer, or combinations thereof. For example, the high-dielectric-constant insulating layer may include, but is not limited to, metal oxides, metal oxynitrides, metal silicon oxides, metal oxynitrides, or combinations thereof. The peripheral gate conductive pattern 223 may include a conductive material, such as a doped semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional (2D) material, a metal, or combinations thereof. The peripheral gate mask pattern 225 may include an insulating material.

[0025] In semiconductor devices according to some example embodiments, the 2D material may be a metallic material and / or a semiconductor material. The 2D material may include 2D allotropes or 2D compounds, and includes, for example, graphene, molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten diselenide (WSe2), tungsten disulfide (WS2), or combinations thereof, but is not limited thereto. Since the above-described 2D materials are merely examples, the 2D materials that may be included in the semiconductor devices of this disclosure are not limited to those described above.

[0026] According to some example embodiments, a first peripheral lower insulating layer 227 and a second peripheral lower insulating layer 228 may be disposed above the substrate 100. Each of the first peripheral lower insulating layer 227 and the second peripheral lower insulating layer 228 may include an insulating material. For example, each of the first peripheral lower insulating layer 227 and the second peripheral lower insulating layer 228 may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), and combinations thereof.

[0027] According to some example embodiments, peripheral wiring 241a and peripheral contact plug 241b may be disposed in a first peripheral lower insulating layer 227 and a second peripheral lower insulating layer 228. Peripheral wiring 241a and peripheral contact plug 241b are shown as different layers, but are not limited thereto. The boundary between peripheral wiring 241a and peripheral contact plug 241b may not be defined. Each of peripheral wiring 241a and peripheral contact plug 241b may include a conductive material.

[0028] According to some example embodiments, an outer peripheral insulating layer 265 may be disposed above the outer peripheral wiring line 241a and the outer peripheral contact plug 241b. The outer peripheral insulating layer 265 may include an insulating material. For example, the outer peripheral insulating layer 265 may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), and combinations thereof. A multilayer outer peripheral insulating layer may be disposed above the outer peripheral wiring line 241a and the outer peripheral contact plug 241b.

[0029] According to some example embodiments, a bonding insulating layer 263 may be disposed on a peripheral insulating layer 265. The bonding insulating layer 263 may be used for wafer bonding. The bonding insulating layer 263 may include, for example, silicon carbonitride (SiCN).

[0030] According to some example embodiments, the bit line BL may be disposed above the peripheral gate structure PG. For example, the bit line BL may be disposed on the bonding insulating layer 263.

[0031] According to some example embodiments, bit lines BL can extend along a first direction D1. Multiple bit lines BL can be configured. The multiple bit lines BL can be spaced apart from each other in a second direction D2. Bit lines BL may include long sidewalls extending along the first direction D1 and short sidewalls extending along the second direction D2. Bit lines BL can extend from the cell array region to the peripheral circuit region. The ends of bit lines BL can be positioned above the peripheral circuit region.

[0032] According to some example embodiments, the bit line BL may include a bit line mask pattern 165, a metal pattern 163, and a semiconductor pattern 161 sequentially stacked over the substrate 100. The bit line BL may include one of the semiconductor pattern 161 and the metal pattern 163.

[0033] According to some example embodiments, the bit line mask pattern 165 may contact the bonding insulating layer 263. The bit line mask pattern 165 may include insulating materials such as silicon nitride and silicon oxynitride.

[0034] According to some example embodiments, a metal pattern 163 may be disposed between a bit line mask pattern 165 and a semiconductor pattern 161. The metal pattern 163 may be disposed on the bit line mask pattern 165 and below the semiconductor pattern 161. The metal pattern 163 may include a conductive material comprising a metal. The metal pattern 163 may include at least one of, for example, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a 2D material, and a metal.

[0035] According to some example embodiments, a semiconductor pattern 161 may be disposed on a metal pattern 163. The semiconductor pattern 161 may be disposed below a plurality of active patterns AP1 and AP2. The semiconductor pattern 161 may be connected to the plurality of active patterns AP1 and AP2. The semiconductor pattern 161 may include a conductive semiconductor material. The semiconductor pattern 161 may include at least one of polycrystalline silicon, polycrystalline silicon germanium, polycrystalline germanium, amorphous silicon, amorphous silicon germanium, and amorphous germanium.

[0036] According to some example embodiments, bit line shielding structures 171, SL, and 175 may be disposed above substrate 100. Bit line shielding structures 171, SL, and 175 may be disposed on and in contact with bonding insulating layer 263. Bit line shielding structures 171, SL, and 175 may be disposed adjacent to bit lines BL. Bit line shielding structures 171, SL, and 175 may be disposed adjacent to bit lines BL in a second direction D2. For example, bit line shielding structures 171, SL, and 175 may be disposed between multiple bit lines BL along the second direction D2. Since bit line shielding structures 171, SL, and 175 are disposed between multiple adjacent bit lines BL along the second direction D2, coupling noise between bit lines BL can be reduced. Bit line shielding structures 171, SL, and 175 may be disposed below multiple word lines WL1 and WL2.

[0037] According to some example embodiments, bit line shielding structures 171, SL, and 175 may include a shielding wire SL and bit line shielding insulation layers 171 and 175. Bit line shielding insulation layers 171 and 175 may include a shielding insulation pad 171 and a shielding insulation cover layer 175. Bit line shielding insulation layers 171 and 175 may surround the periphery of the shielding wire SL. The shielding wire SL may be disposed within the bit line shielding insulation layers 171 and 175.

[0038] According to some example embodiments, the shielding line SL can extend from the cell array region to the peripheral circuit region. The end of the shielding line SL can be positioned above the peripheral circuit region. The shielding line SL can include a conductive material. The shielding line SL can include at least one of, for example, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, 2D materials, and metals.

[0039] According to some example embodiments, each of the shielding insulating pad 171 and the shielding insulating cover 175 may include an insulating material. If the shielding insulating pad 171 and the shielding insulating cover 175 comprise the same material, the boundary between the shielding insulating pad 171 and the shielding insulating cover 175 may not be defined.

[0040] According to some example embodiments, the heights of conductive bit lines 161 and 163 on the third direction D3 relative to the bonding insulating layer 263 are shown to be greater than the height of shielding line SL on the third direction D3, but are not limited thereto.

[0041] According to some example embodiments, the shielding line SL may include a first surface and a second surface disposed opposite to each other on a third direction D3. The first surface of the shielding line SL may be the surface facing the bonding insulation layer 263. The metal pattern 163 may include a first surface and a second surface disposed opposite to each other on a third direction D3. The first surface of the metal pattern 163 may be the surface facing the bonding insulation layer 263. The height of the second surface of the shielding line SL relative to the bonding insulation layer 263 is shown to be greater than the height of the second surface of the metal pattern 163, but is not limited thereto. The first surface of the shielding line SL is shown as a plane, but is not limited thereto. The first surface of the shielding line SL may be a concave surface.

[0042] According to some example embodiments, a plurality of active patterns AP1 and AP2 may include a first active pattern AP1 and a second active pattern AP2. The first active pattern AP1 and the second active pattern AP2 may be disposed on a bit line BL. The first active pattern AP1 and the second active pattern AP2 may be disposed alternately along a first direction D1.

[0043] According to some example embodiments, a first active pattern AP1 and a second active pattern AP2 can be respectively configured as a plurality of first active patterns AP1 and a plurality of second active patterns AP2. The plurality of first active patterns AP1 can be spaced apart from each other in a second direction D2. The plurality of first active patterns AP1 can be spaced apart at a predetermined interval. The plurality of second active patterns AP2 can be spaced apart from each other in the second direction D2. The plurality of second active patterns AP2 can be spaced apart at a predetermined interval. The plurality of first active patterns AP1 and the plurality of second active patterns AP2 can be arranged two-dimensionally relative to each other along the first direction D1 and the second direction D2. The first active patterns AP1 and the second active patterns AP2 can extend in a third direction D3. The third direction D3 can be a direction intersecting with the upper surface of the substrate 100. A semiconductor device according to an example embodiment of this disclosure may include a memory cell comprising a vertical channel transistor (VCT).

[0044] According to some example embodiments, a first active pattern AP1 and a second active pattern AP2 can be disposed between adjacent first word lines WL1 and WL2 along a first direction D1. The first active pattern AP1 can be disposed between the second portions WLb of the first word lines WL1 adjacent along a second direction D2, and is disposed on one side of the first portion Wla of the first word line WL1 in the first direction D1. The second active pattern AP2 can be disposed between the second portions WLb of the second word lines WL2 adjacent along the second direction D2, and is disposed on one side of the first portion Wla of the second word line WL2 in the first direction D1.

[0045] According to some example embodiments, the plurality of active patterns AP1 and AP2 may include, for example, a single-crystal semiconductor material. As an example, each of the first active pattern AP1 and the second active pattern AP2 may include single-crystal silicon.

[0046] According to some example embodiments, each of the first active pattern AP1 and the second active pattern AP2 may have a length along the second direction D2, a width along the first direction D1, and a height along the third direction D3. Each of the first active pattern AP1 and the second active pattern AP2 may have substantially the same width. The width of the first active pattern AP1 may be the same as the width of the second active pattern AP2.

[0047] According to some example embodiments, the width of the first active pattern AP1 and the width of the second active pattern AP2 can be in the range of several nanometers (nm) to tens of nanometers. For example, the width of the first active pattern AP1 and the width of the second active pattern AP2 can be in the range of 1 nm to 30 nm, or 1 nm to 10 nm, but are not limited thereto. The length of each of the plurality of active patterns AP1 and AP2 can be greater than the linewidth of the bit line BL. In other words, the length of each of the first active pattern AP1 and the second active pattern AP2 along the second direction D2 can be greater than the width of the bit line BL in the second direction D2.

[0048] refer to Figure 4 Each of the first active pattern AP1 and the second active pattern AP2 may include a first surface S1 and a second surface S2 disposed opposite to each other in a third direction D3. The first surface S1 of each of the first active pattern AP1 and the second active pattern AP2 may face the bit line BL. As used herein, "facing the bit line BL" may indicate that, among the surfaces of a component, the surface facing the bit line BL is the surface closest to the bit line BL in the third direction D3 (or other directions obvious from the figures). In a more general definition, as described herein, when a component includes multiple surfaces and one surface is described as facing another component (or another surface), it may indicate that the surface facing the other component is the surface among these surfaces that is closest to that other component when viewed in the relative directions. For example, the first surface S1 of each of the first active pattern AP1 and the second active pattern AP2 may contact the semiconductor pattern 161 of the bit line BL. If the semiconductor pattern 161 is omitted, the first surface S1 of each of the first active pattern AP1 and the second active pattern AP2 may contact the metal pattern 163.

[0049] According to some example embodiments, each of the first active pattern AP1 and the second active pattern AP2 may include a first side surface SS1 and a second side surface SS2 disposed opposite to each other in a first direction D1. The second side surface SS2 of the first active pattern AP1 may face the first side surface SS1 of the second active pattern AP2. The first side surface SS1 of the first active pattern AP1 may face the first word line WL1 along the first direction D1. The second side surface SS2 of the second active pattern AP2 may face the second word line WL2 along the first direction D1.

[0050] According to some example embodiments, each of the first active pattern AP1 and the second active pattern AP2 may include a first doped region adjacent to the bit line BL and a second doped region adjacent to the contact pattern BC. Each of the first active pattern AP1 and the second active pattern AP2 may include a channel region located between the first doped region and the second doped region. The first doped region and the second doped region may be regions within the first active pattern AP1 and the second active pattern AP2 that are doped with dopant. Each of the first active pattern AP1 and the second active pattern AP2 may not include at least one of the first doped region and the second doped region.

[0051] According to some example embodiments, when operating a semiconductor device, the channel regions of multiple active patterns AP1 and AP2 can be controlled by multiple word lines WL1 and WL2 and multiple back gate electrode structures BG. Since the multiple active patterns AP1 and AP2 comprise single-crystal semiconductor material, the leakage current characteristics of the semiconductor device can be improved.

[0052] According to some example embodiments, multiple word lines WL1 and WL2 can be disposed above bit line BL and shield line SL. The multiple word lines WL1 and WL2 may include a first word line WL1 and a second word line WL2. Each of the first word line WL1 and the second word line WL2 may extend in a second direction D2. The first word line WL1 and the second word line WL2 may be alternately disposed in a first direction D1.

[0053] According to some example embodiments, a first word line WL1 may be disposed on a first side surface SS1 of a first active pattern AP1. The first word line WL1 may be disposed between a gate separator pattern GSS and the first active pattern AP1. A second word line WL2 may be disposed on a second side surface SS2 of a second active pattern AP2. The second word line WL2 may be disposed between a gate separator pattern GSS and the second active pattern AP2.

[0054] According to some example embodiments, the first word line WL1 and the second word line WL2 may be spaced apart from the bit line BL and the contact pattern BC on a third-direction D3. The first word line WL1 and the second word line WL2 may be located between the bit line BL and the contact pattern BC. The first word line WL1 and the second word line WL2 may be disposed on the horizontal portion GSS_H of the gate separator pattern. The first word line WL1 and the second word line WL2 may be disposed between the horizontal portion GSS_H of the gate separator pattern and the contact pattern BC.

[0055] According to some example embodiments, each of the first word line WL1 and the second word line WL2 may have a width along the first direction D1. The width of the first word line WL1 above the bit line BL and the width of the second word line WL2 may differ from the width of the first word line WL1 above the shield line SL. For example, the width of the first word line WL1 above the bit line BL and the width of the second word line WL2 above the shield line SL may be smaller than the width of the first word line WL1 above the shield line SL.

[0056] According to some example embodiments, each of the first word line WL1 and the second word line WL2 may include a first portion WLa and a second portion WLb of the word line alternately arranged along the second portion D2. The width of the first portion WLa of the word line in the first direction D1 may be smaller than the width of the second portion WLb of the word line in the first direction D1. As an example, the first portion WLa of the word line may be disposed above the bit line BL. The second portion WLb of the word line may be disposed above the shield line SL.

[0057] According to some example embodiments, the first portion WLa of the word line may not overlap with the plurality of active patterns AP1 and AP2 in the second direction D2. The first portion WLa of the word line may be disposed on one side of each of the plurality of active patterns AP1 and AP2 in the first direction D1. The second portion WLb of the word line extends over the plurality of active patterns AP1 and AP2. At least a portion of the second portion WLb of the word line may be disposed on one side of each of the plurality of active patterns AP1 and AP2 in the second direction D2.

[0058] According to some example embodiments, each of the first word line WL1 and the second word line WL2 may include a first surface WL_S1 and a second surface WL_S2 disposed opposite to each other on a third direction D3. The first surface WL_S1 of each of the first word line WL1 and the second word line WL2 may face the bit line BL. The second surface WL_S2 of each of the first word line WL1 and the second word line WL2 may face the data storage pattern DSP.

[0059] According to some example embodiments, the description of the second word line WL2 is basically the same as that of the first word line WL1; therefore, the first word line WL1 will be mainly described below. The height of the first word line WL1 along the third direction D3 can be greater than the height of the back gate electrode structure BG along the third direction D3. However, the example embodiments are not limited to this. As an example, the height of the first word line WL1 along the third direction D3 can be the same as the height of the back gate electrode structure BG along the third direction D3. As another example, the height of the first word line WL1 along the third direction D3 can be less than the height of the back gate electrode structure BG along the third direction D3.

[0060] According to some example embodiments, the first surface WL_S1 of the first word line WL1 may be set below the first surface BG_S1 of the back gate electrode structure relative to the bit line BL. The height of the first surface WL_S1 of the first word line WL1 relative to the bit line BL may be less than the height of the first surface BG_S1 of the back gate electrode structure. However, the example embodiments are not limited to this. As an example, the first surface WL_S1 of the first word line WL1 may be set above the first surface BG_S1 of the back gate electrode structure. As another example, the first surface WL_S1 of the first word line WL1 may be located on the same plane as the first surface BG_S1 of the back gate electrode structure. As used herein, "on the same plane" can mean that the components or surfaces are substantially coplanar when viewed from a particular direction, where "substantially" allows for minor differences in surface height and uniformity.

[0061] According to some example embodiments, the second surface WL_S2 of the first word line WL1 can be configured to be higher than the second surface BG_S2 of the back gate electrode structure relative to the bit line BL. The height of the second surface WL_S2 of the first word line WL1 relative to the bit line BL can be greater than the height of the second surface BG_S2 of the back gate electrode structure. However, the example embodiments are not limited to this. As an example, the second surface WL_S2 of the first word line WL1 can be configured to be lower than the second surface BG_S2 of the back gate electrode structure. As another example, the second surface WL_S2 of the first word line WL1 can be disposed on the same plane as the second surface BG_S2 of the back gate electrode structure.

[0062] According to some example embodiments, the height of each of the first word line WL1 and the second word line WL2 along the third direction D3 can be greater than the height of the back gate electrode structure BG along the third direction D3. The height of each of the first word line WL1 and the second word line WL2 along the third direction D3 can be less than the height of the first active pattern AP1 and the second active pattern AP2 along the third direction D3.

[0063] According to some example embodiments, the first word line WL1 and the second word line WL2 may include a conductive material. The first word line WL1 and the second word line WL2 may include at least one of, for example, doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, 2D material, and metal.

[0064] According to some example embodiments, the first surface WL_S1 of each of the first word line WL1 and the second word line WL2 may be planar. As an example, the first surface WL_S1 of each of the first word line WL1 and the second word line WL2 may be circularly concave relative to the upper surface of the bit line BL. As another example, the first surface WL_S1 of each of the first word line WL1 and the second word line WL2 may be circularly convex towards the upper surface of the bit line BL.

[0065] According to some example embodiments, the second surface WL_S2 of each of the first word line WL1 and the second word line WL2 may be planar. The second surface WL_S2 of each of the first word line WL1 and the second word line WL2 may have a concave curved surface relative to the lower surface of the data storage pattern DSP.

[0066] According to some example embodiments, a gate insulating pattern GOX may be disposed between a first word line WL1 and a first active pattern AP1, and between a second word line WL2 and a second active pattern AP2. The gate insulating pattern GOX may extend in a second direction D2, parallel to the first word line WL1 and the second word line WL2.

[0067] According to some example embodiments, the gate insulating pattern GOX may include a silicon oxide layer, a silicon oxynitride layer, a high dielectric constant insulating layer with a dielectric constant higher than that of the silicon oxide layer, or a combination thereof.

[0068] According to some example embodiments, the gate insulating pattern GOX may extend along a first side surface SS1 of a first active pattern AP1 and along a second side surface SS2 of a second active pattern AP2. The gate insulating pattern GOX located between the first active pattern AP1 and the first word line WL1 may be separate from the gate insulating pattern GOX located between the second active pattern AP2 and the second word line WL2.

[0069] According to some example embodiments, a gate overlay pattern 143 may be disposed between a first word line WL1 and a contact pattern BC, and between a second word line WL2 and a contact pattern BC. The gate overlay pattern 143 may cover the second surface WL_S2 of each of the first word line WL1 and the second word line WL2. Figure 2The illustration shows a gate cover pattern 143 extending along a first direction D1 on a gate separator pattern GSS, such that a portion of the gate cover pattern 143 disposed on a first word line WL1 connects to a portion of the gate cover pattern 143 disposed on a second word line WL2. However, the example embodiment is not limited to this. For example, the gate cover pattern 143 on the first word line WL1 and the gate cover pattern 143 on the second word line WL2 may be spaced apart from each other in the first direction D1, with the gate separator pattern GSS located therebetween. In other words, the gate cover pattern 143 may not be disposed on the gate separator pattern GSS. In this case, the upper surface of the gate separator pattern GSS, the upper surface of the gate cover pattern 143 on the first word line WL1, and the upper surface of the gate cover pattern 143 on the second word line WL2 may be disposed on the same plane.

[0070] According to some example embodiments, the gate cover pattern 143 may include an insulating material. For example, the gate cover pattern 143 may include at least one of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and combinations thereof.

[0071] According to some example embodiments, a gate separator pattern GSS may be disposed on the bit line BL. The gate separator pattern GSS may be disposed between the bit line BL and the contact pattern BC. The gate separator pattern GSS may contact the bit line BL.

[0072] According to some example embodiments, a gate separator pattern GSS may be disposed between adjacent first word lines WL1 and WL2 along a first direction D1. The first word lines WL1 and WL2 may be separated from each other by the gate separator pattern GSS. The gate separator pattern GSS may extend along a second direction D2 between the first word lines WL1 and WL2.

[0073] According to some example embodiments, the gate separator pattern GSS may include a horizontal portion GSS_H and a protruding portion GSS_P. The protruding portion GSS_P of the gate separator pattern may protrude from the horizontal portion GSS_H of the gate separator pattern along a third direction D3.

[0074] According to some example embodiments, the horizontal portion GSS_H of the gate separator pattern may be closer to the bit line BL than the protruding portion GSS_P of the gate separator pattern. The horizontal portion GSS_H of the gate separator pattern may be disposed below multiple word lines WL1 and WL2. The horizontal portion GSS_H of the gate separator pattern may cover the first surface WL_S1 of each of the first word line WL1 and the second word line WL2. The horizontal portion GSS_H of the gate separator pattern may contact the bit line BL. The width of the horizontal portion GSS_H of the gate separator pattern in the first direction D1 may be greater than the width of the protruding portion GSS_P of the gate separator pattern in the first direction D1.

[0075] According to some example embodiments, the protruding portion GSS_P of the gate separator pattern can be disposed on one side of each of the plurality of word lines WL1 and WL2 in the first direction D1. The protruding portion GSS_P of the gate separator pattern can be disposed between the side surface of the first word line WL1 and the side surface of the second word line WL2, which face each other along the first direction D1.

[0076] According to some example embodiments, the gate separator pattern (GSS) may include an insulating material. For example, the gate separator pattern (GSS) may include at least one of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and combinations thereof. The gate separator pattern (GSS) may include multiple insulating layers.

[0077] According to some example embodiments, the contact pattern BC may penetrate the contact separator insulating pattern 231 and the contact etch stop layer 212. The contact pattern BC may be connected to each of the first active pattern AP1 and the second active pattern AP2. The contact pattern BC may be connected to the second surface S2 of each of the first active pattern AP1 and the second active pattern AP2. The contact pattern BC may have various shapes, such as circular, elliptical, rectangular, square, rhomboid and hexagonal, relative to the plane defined in the first direction D1 and the second direction D2.

[0078] According to some example embodiments, the contact pattern BC may include a conductive material. The contact pattern BC may include at least one of, for example, doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, 2D material, and metal.

[0079] According to some example embodiments, the contact etch stop layer 212 and the contact spacer insulating pattern 231 may be disposed over the gate cover pattern 143 and the back gate spacer pattern 111. The contact etch stop layer 212 and the contact spacer insulating pattern 231 may surround the side surface of the contact pattern BC. Each of the contact etch stop layer 212 and the contact spacer insulating pattern 231 may include an insulating material.

[0080] According to some example embodiments, landing pads LP can be disposed on contact patterns BC. Multiple landing pads LP can be configured. The multiple landing pads LP can be arranged in a matrix along the first direction D1 and the second direction D2, relative to a plane defined in the second direction D1. The upper surface of the landing pads LP can be disposed on a plane substantially the same as the upper surface of the pad separating insulating pattern 235. The landing pads LP can have various shapes relative to the plane defined in the first direction D1 and the second direction D2, such as circular, elliptical, rectangular, square, rhomboid, and hexagonal.

[0081] According to some example embodiments, a pad separator insulating pattern 235 may be disposed between a plurality of landing pads LP. The pad separator insulating pattern 235 may surround the side surfaces of the plurality of landing pads LP. The pad separator insulating pattern 235 may include an insulating material.

[0082] According to some example embodiments, the landing pad LP may include a conductive material. For example, the landing pad LP may include at least one of doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, 2D material, and metal.

[0083] According to some example embodiments, a data storage pattern DSP can be disposed on each landing pad LP. The data storage pattern DSP can be electrically connected to each of the multiple active patterns AP1 and AP2. For example... Figure 1 As shown, the data storage pattern DSP can be arranged in a matrix along the first direction D1 and the second direction D2. The data storage pattern DSP can completely or partially cover the landing pad LP on the third direction D3. The data storage pattern DSP can contact the entire or part of the upper surface of the landing pad LP.

[0084] According to some example embodiments, the data storage pattern DSP can be a capacitor. The data storage pattern DSP may include a first electrode 251, a second electrode 255, and a capacitor dielectric layer 253 between the first electrode 251 and the second electrode 255. The first electrode 251 may contact the landing pad LP. In a top view, the first electrode 251 may have various shapes, such as circular, elliptical, rectangular, square, rhomboid, and hexagonal. The data storage pattern DSP may completely or partially cover the landing pad LP. The data storage pattern DSP may contact all or part of the upper surface of the landing pad LP. The first electrode 251 may penetrate an upper etch stop layer 247. The upper etch stop layer 247 may include an insulating material.

[0085] According to some example embodiments, the data storage pattern DSP can be a variable resistance pattern that can switch between two resistance states due to an electrical pulse applied to the memory element. For example, the data storage pattern DSP can include phase change materials, perovskite compounds, transition metal oxides, magnetic materials, ferromagnetic materials, or antiferromagnetic materials whose crystallization state changes according to the amount of current.

[0086] According to some example embodiments, a back gate electrode structure BG can be disposed above the bit line BL and the shield line SL. Multiple back gate electrode structures BG can be configured. These multiple back gate electrode structures BG can be spaced apart from each other in a first direction D1. The multiple back gate electrode structures BG can be spaced apart at predetermined intervals. The back gate electrode structures BG can extend in a second direction D2. The back gate electrode structures BG can intersect with the bit line BL.

[0087] According to some example embodiments, the back gate electrode structure BG can be disposed between a first active pattern AP1 and a second active pattern AP2 that are adjacent to each other along a first direction D1. The first active pattern AP1 can be disposed on one side of the back gate electrode structure BG in the first direction D1, and the second active pattern AP2 can be disposed on the other side of the back gate electrode structure BG. The height of the back gate electrode structure BG in a third direction D3 can be less than the height of the plurality of active patterns AP1 and AP2 in the third direction D3. The height of the back gate electrode structure BG in the third direction D3 can be less than the height of the plurality of word lines WL1 and WL2 in the third direction D3.

[0088] According to some example embodiments, the back gate electrode structure BG can be spaced apart from multiple word lines WL1 and WL2 in the first direction D1. The back gate electrode structure BG can be disposed between the first word line WL1 and the second word line WL2.

[0089] According to some example embodiments, the back gate electrode structure BG can be disposed between the second side surface SS2 of the first active pattern AP1 and the first side surface SS1 of the second active pattern AP2. The first active pattern AP1 can be disposed between the first word line WL1 and the back gate electrode structure BG. The second active pattern AP2 can be disposed between the second word line WL2 and the back gate electrode structure BG. A pair of first word lines WL1 and second word lines WL2 can be disposed between adjacent back gate electrode structures BG along the first direction D1.

[0090] According to some example embodiments, the back gate electrode structure BG may include a first surface BG_S1 and a second surface BG_S2 disposed opposite to each other on a third direction D3. The first surface BG_S1 of the back gate electrode structure may face the bit line BL. The second surface BG_S2 of the back gate electrode structure may face the data storage pattern DSP. The first surface BG_S1 and the second surface BG_S2 of the back gate electrode structure are shown as planes, but are not limited thereto. For example, the first surface BG_S1 and the second surface BG_S2 of the back gate electrode structure may be curved surfaces.

[0091] According to some example embodiments, when viewed from the first direction D1 plane, the back gate electrode structure BG may overlap with multiple word lines WL1 and WL2. The first surface BG_S1 of the back gate electrode structure BG may be located on the third direction D3 between the first surfaces WL_S1 and second surfaces WL_S2 of the multiple word lines WL1 and WL2. The second surface BG_S2 of the back gate electrode structure BG may be located on the third direction D3 between the first surfaces WL_S1 and second surfaces WL_S2 of the multiple word lines WL1 and WL2. In other words, when viewed from the third direction D3, the first surface BG_S1 and the second surface BG_S2 of the back gate electrode structure BG may be located between the upper and lower surfaces of the word lines.

[0092] According to some example embodiments, the back-gate electrode structure BG may include a back-gate body pattern 310 and back-gate work function adjustment patterns 320 and 330. The back-gate body pattern 310 may be located between the back-gate work function adjustment patterns 320 and 330 in a third direction D3. That is, the back-gate body pattern 310 may be located above the first back-gate work function adjustment pattern 320 and below the second back-gate work function adjustment pattern 330 in the third direction D3, wherein each component has a substantially equal width in a first direction D1.

[0093] According to some example embodiments, the back gate main pattern 310 may be disposed between the first back gate work function adjustment pattern 320 and the second back gate work function adjustment pattern 330. When viewed from the first direction D1 plane, the back gate main pattern 310 may overlap with multiple word lines WL1 and WL2 and multiple active patterns AP1 and AP2. The back gate main pattern 310 may include at least one of, for example, titanium nitride (TiN), tungsten (W), and molybdenum (Mo).

[0094] According to some example embodiments, back-gate power function adjustment patterns 320 and 330 may include a first back-gate power function adjustment pattern 320 and a second back-gate power function adjustment pattern 330. The back-gate power function adjustment patterns 320 and 330 may be located above and below the back-gate main pattern 310, respectively, on a third-direction D3. The back-gate power function adjustment patterns 320 and 330 may contact the back-gate main pattern 310. The first back-gate power function adjustment pattern 320 and the second back-gate power function adjustment pattern 330 may be spaced apart from each other, with the back-gate main pattern 310 located between them. The first back-gate power function adjustment pattern 320 may be disposed between the back-gate main pattern 310 and the bit line BL. The second back-gate power function adjustment pattern 330 may be disposed between the back-gate main pattern 310 and the data storage pattern DSP.

[0095] According to some example embodiments, back-gate work function adjustment patterns 320 and 330 can be disposed at one or both ends of the back-gate electrode structure BG along the third direction D3. The two ends of the back-gate electrode structure BG along the third direction D3 can be a first surface BG_S1 and a second surface BG_S2 of the back-gate electrode structure. For example, the back-gate electrode structure BG can have a first end facing the alignment line BL on the third direction D3 and a second end disposed opposite to the first end. The first end of the back-gate electrode structure BG can be the first surface BG_S1 of the back-gate electrode structure. The second end of the back-gate electrode structure BG can be the second surface BG_S2 of the back-gate electrode structure. For example, a first back-gate work function adjustment pattern 320 can be disposed on the first end. A second back-gate work function adjustment pattern 330 can be disposed on the second end of the back-gate electrode structure BG.

[0096] According to some example embodiments, the back-gate work function adjustment patterns 320 and 330 may define one of a first surface BG_S1 and a second surface BG_S2 of the back-gate electrode structure. For example, the first back-gate work function adjustment pattern 320 may define the first surface BG_S1 of the back-gate electrode structure. The lower surface of the first back-gate work function adjustment pattern 320 may be the first surface BG_S1 of the back-gate electrode structure. The second back-gate work function adjustment pattern 330 may define the second surface BG_S2 of the back-gate electrode structure. The upper surface of the second back-gate work function adjustment pattern 330 may be the second surface BG_S2 of the back-gate electrode structure.

[0097] According to some example embodiments, when viewed from the first direction D1 plane, the back gate power function adjustment patterns 320 and 330 may overlap with multiple word lines WL1 and WL2 and multiple active patterns AP1 and AP2. Relative to the bit line BL, the lower surface of the first back gate power function adjustment pattern 320 may be configured to be higher than the first surface WL_S1 of each of the multiple word lines WL1 and WL2. Relative to the bit line BL, the height of the lower surface of the first back gate power function adjustment pattern 320 may be greater than the height of the first surface WL_S1 of each of the multiple word lines WL1 and WL2. Relative to the bit line BL, the upper surface of the second back gate power function adjustment pattern 330 may be configured to be lower than the second surface WL_S2 of each of the multiple word lines WL1 and WL2. Relative to the bit line BL, the height of the upper surface of the second back gate power function adjustment pattern 330 may be less than the height of the second surface WL_S2 of each of the multiple word lines WL1 and WL2.

[0098] According to some example embodiments, the first back-gate work function adjustment pattern 320 and the second back-gate work function adjustment pattern 330 may include materials different from those of the back-gate main pattern 310. The first back-gate work function adjustment pattern 320 and the second back-gate work function adjustment pattern 330 may include materials with a work function greater than that of the back-gate main pattern 310. The first back-gate work function adjustment pattern 320 and the second back-gate work function adjustment pattern 330 may include at least one of, for example, doped polycrystalline silicon, lanthanum oxide (LaO), and titanium aluminum carbide (TiAlC). However, the example embodiments are not limited thereto.

[0099] According to some example embodiments, the back gate electrode structure BG can block the electric field of the non-active word line to enhance the electrical reliability of the VCT. When operating the semiconductor device, a voltage can be applied to the back gate electrode structure BG, thereby adjusting the threshold voltage of the VCT. A negative voltage can be applied to the back gate electrode structure BG to adjust the threshold voltage of the VCT. When a negative voltage is applied to the back gate electrode structure BG, the gate-induced drain leakage (GIDL) of the VCT may deteriorate. Since the back gate electrode structure BG has a multilayer structure containing different materials, the GIDL characteristics of the VCT can be improved. Therefore, the electrical reliability of the semiconductor device according to some example embodiments of this disclosure can be enhanced.

[0100] According to some example embodiments, a first back-gate work function adjustment pattern 320 and a second back-gate work function adjustment pattern 330 can reduce dynamic leakage that may occur when a relatively low-amplitude voltage is applied to the back-gate electrode structure BG and the multiple word lines WL1 and WL2. When a relatively low-amplitude voltage is applied to the back-gate electrode structure BG and the multiple word lines WL1 and WL2, the occurrence of GIDL may be reduced, but the occurrence of dynamic leakage caused by the gate electrode may increase. Even when a relatively low-amplitude voltage is applied to the back-gate electrode structure BG and the multiple word lines WL1 and WL2, the occurrence of dynamic leakage caused by the gate electrode can be reduced by the first back-gate work function adjustment pattern 320 and the second back-gate work function adjustment pattern 330, which have relatively high work functions. Therefore, the risk of leakage current in semiconductor devices according to some example embodiments of the present disclosure can be reduced, and electrical reliability can be enhanced.

[0101] According to some example embodiments, the back-gate separation pattern 111 can be disposed between adjacent first active patterns AP1 and second active patterns AP2 in the first direction D1. The back-gate separation pattern 111 can extend in the second direction D2, parallel to the back-gate electrode structure BG. The back-gate separation pattern 111 can be disposed on the second surface BG_S2 of the back-gate electrode structure. The back-gate separation pattern 111 can be disposed on the second back-gate work function adjustment pattern 330.

[0102] According to some example embodiments, the back gate separation pattern 111 may include an insulating material. The back gate separation pattern 111 may include, for example, a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer, but is not limited thereto.

[0103] According to some example embodiments, the back gate side insulating pattern 113 can be disposed between the back gate electrode structure BG and the first active pattern AP1, and between the back gate electrode structure BG and the second active pattern AP2. The back gate side insulating pattern 113 can be disposed between the back gate separator pattern 111 and the first active pattern AP1, and between the back gate separator pattern 111 and the second active pattern AP2. The back gate side insulating pattern 113 can be disposed between the back gate cover pattern 115 and the first active pattern AP1, and between the back gate cover pattern 115 and the second active pattern AP2.

[0104] According to some example embodiments, the back gate-side insulating pattern 113 may include an insulating material. The back gate-side insulating pattern 113 may include, for example, a silicon oxide layer, a silicon oxynitride layer, a high dielectric constant insulating layer with a dielectric constant higher than that of the silicon oxide layer, or a combination thereof.

[0105] According to some example embodiments, the back gate cover pattern 115 can be disposed between the bit line BL and the back gate electrode structure BG. The back gate cover pattern 115 can be disposed between adjacent first active patterns AP1 and second active patterns AP2 along a first direction D. The back gate cover pattern 115 can be located below the back gate electrode structure BG in a third direction D3 and extend along a second direction D2. The back gate cover pattern 115 can be disposed on the first surface BG_S1 of the back gate electrode structure. The back gate cover pattern 115 can be disposed below the first back gate work function adjustment pattern 320. The thickness of the back gate cover pattern 115 located on the bit line shielding structures 171, SL, and 175 along the third direction D3 can be different from the thickness of the back gate cover pattern 115 located on the bit line BL along the third direction D3. For example, the thickness of the back gate cover pattern 115 located on the bit line shielding structures 171, SL, and 175 along the third direction D3 can be less than the thickness of the back gate cover pattern 115 located on the bit line BL along the third direction D3.

[0106] According to some example embodiments, the back gate cover pattern 115 may include an insulating material. The back gate cover pattern 115 may include, but is not limited to, at least one of, a silicon oxide layer, a silicon oxynitride layer, and a silicon nitride layer.

[0107] Figure 5 It is used to illustrate a semiconductor device according to an example embodiment. Figure 2 An enlarged view of part P in the diagram. For ease of understanding this disclosure, the main descriptions and references are as follows. Figures 1 to 4 The differences in description.

[0108] refer to Figure 5 The back-gate electrode structure BG may include a back-gate main body pattern 310 and a second back-gate work function adjustment pattern 330. Figure 4 Compared to the back gate electrode structure BG shown, Figure 5 The back-gate electrode structure BG shown may not include the first back-gate work function adjustment pattern 320. The back-gate body pattern 310 may contact the back-gate cover pattern 115. The back-gate body pattern 310 may define the first surface BG_S1 of the back-gate electrode structure. The lower surface of the back-gate body pattern 310 may be the first surface BG_S1 of the back-gate electrode structure.

[0109] According to some example embodiments, the back gate work function adjustment pattern may not be positioned between the back gate body pattern 310 and the bit line BL along the third direction D3. By changing the position of the work function adjustment pattern, leakage current (such as gate-induced dynamic leakage or GIDL) in the transistor composed of word lines WL1 and WL2, active patterns AP1 and AP2, bit line BL, and contact pattern BC can be effectively controlled.

[0110] Figure 6It is used to illustrate a semiconductor device according to an example embodiment. Figure 2 An enlarged view of part P in the diagram. For ease of understanding this disclosure, the main descriptions and references are as follows. Figures 1 to 4 The differences in description.

[0111] refer to Figure 6 The back-gate electrode structure BG may include a back-gate main body pattern 310 and a first back-gate work function adjustment pattern 320. Figure 4 Compared to the back gate electrode structure BG shown, Figure 6 The back-gate electrode structure BG shown may not include the second back-gate work function adjustment pattern 330. The back-gate main body pattern 310 may contact the back-gate separator pattern 111. The back-gate main body pattern 310 may define the second surface BG_S2 of the back-gate electrode structure. The upper surface of the back-gate main body pattern 310 may be the second surface BG_S2 of the back-gate electrode structure.

[0112] According to some example embodiments, the back gate power function adjustment pattern may not be positioned between the back gate body pattern 310 and the data storage pattern DSP along the third direction D3. By changing the position of the power function adjustment pattern, leakage current (such as gate-induced dynamic leakage or GIDL) in the transistor composed of word lines WL1 and WL2, active patterns AP1 and AP2, bit line BL, and contact pattern BC can be effectively controlled.

[0113] Figure 7 It is used to illustrate a semiconductor device according to an example embodiment. Figure 2 An enlarged view of part P in the diagram. For ease of understanding this disclosure, the main descriptions and references are as follows. Figures 1 to 4 The differences in description.

[0114] refer to Figure 7 The back grid work function adjustment patterns 320 and 330 can be spaced apart from the back grid main pattern 310. The back grid interlayer insulation pattern 114 can be disposed between the first back grid work function adjustment pattern 320 and the back grid main pattern 310, and between the second back grid work function adjustment pattern 330 and the back grid main pattern 310. The first back grid work function adjustment pattern 320, the back grid interlayer insulation pattern 114, the back grid main pattern 310, the back grid interlayer insulation pattern 114, and the second back grid work function adjustment pattern 330 can be sequentially stacked on the third direction D3.

[0115] According to some example embodiments, the back gate interlayer insulation pattern 114 may cover the upper and lower surfaces of the back gate body pattern 310. The back gate interlayer insulation pattern 114 may include an insulating material. For example, the back gate interlayer insulation pattern 114 may include at least one of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and combinations thereof.

[0116] According to some example embodiments, the back-gate work function adjustment patterns 320 and 330 may be physically spaced apart from the back-gate body pattern 310, such that the voltages applied to the back-gate work function adjustment patterns 320 and 330 and the voltage applied to the back-gate body pattern 310 can be controlled independently of each other. Therefore, by individually adjusting the individual voltages applied to the back-gate body pattern 310 and the back-gate work function adjustment patterns 320 and 330, transistor leakage currents (such as gate-induced dynamic leakage or GIDL) can be controlled more precisely.

[0117] Figure 8 It is used to illustrate a semiconductor device according to an example embodiment. Figure 2 An enlarged view of part P in the diagram. For ease of understanding this disclosure, the main descriptions and references are as follows. Figure 7 The differences in description.

[0118] refer to Figure 8 The back-gate electrode structure BG may include a back-gate main pattern 310 and a second back-gate work function adjustment pattern 330. The back-gate main pattern 310, the back-gate interlayer insulation pattern 114, and the second back-gate work function adjustment pattern 330 may be sequentially stacked on a third-direction D3. Figure 7 Compared to the back gate electrode structure BG shown, Figure 8 The back-gate electrode structure BG shown may not include the first back-gate work function adjustment pattern 320. The back-gate body pattern 310 may contact the back-gate cover pattern 115. The back-gate body pattern 310 may define the first surface BG_S1 of the back-gate electrode structure. The lower surface of the back-gate body pattern 310 may be the first surface BG_S1 of the back-gate electrode structure.

[0119] According to some example embodiments, the back-gate work function adjustment pattern may not be positioned between the back-gate body pattern 310 and the bit line BL along the third direction D3. By changing the position of the work function adjustment pattern, leakage current (such as gate-induced dynamic leakage or GIDL) in the transistor composed of word lines WL1 and WL2, active patterns AP1 and AP2, bit line BL, and contact pattern BC can be effectively controlled. Furthermore, transistor leakage current can be controlled more precisely by individually adjusting the voltages applied to the back-gate body pattern 310 and the second back-gate work function adjustment pattern 330.

[0120] Figure 9 It is used to illustrate a semiconductor device according to an example embodiment. Figure 2 An enlarged view of part P in the diagram. For ease of understanding this disclosure, the main descriptions and references are as follows. Figure 7 The differences in description.

[0121] refer to Figure 9The back-gate electrode structure BG may include a back-gate main body pattern 310 and a first back-gate work function adjustment pattern 320. The first back-gate work function adjustment pattern 320, the back-gate interlayer insulation pattern 114, and the back-gate main body pattern 310 may be sequentially stacked on a third-direction D3. Figure 7 Compared to the back gate electrode structure BG shown, Figure 9 The back-gate electrode structure BG shown may not include the second back-gate work function adjustment pattern 330. The back-gate main body pattern 310 may contact the back-gate separator pattern 111. The back-gate main body pattern 310 may define the second surface BG_S2 of the back-gate electrode structure. The upper surface of the back-gate main body pattern 310 may be the second surface BG_S2 of the back-gate electrode structure.

[0122] According to some example embodiments, the back-gate work function adjustment pattern may not be positioned between the back-gate body pattern 310 and the data storage pattern DSP along the third direction D3. By changing the position of the work function adjustment pattern, the leakage current in the transistor composed of word lines WL1 and WL2, active patterns AP1 and AP2, bit line BL, and contact pattern BC can be effectively controlled. Furthermore, by individually adjusting the voltages applied to the back-gate body pattern 310 and the first back-gate work function adjustment pattern 320, the transistor leakage current (such as gate-induced dynamic leakage or GIDL) can be controlled more finely.

[0123] Figure 10 It is used to illustrate a semiconductor device according to an example embodiment. Figure 2 An enlarged view of part P in the diagram. For ease of understanding this disclosure, the main descriptions and references are as follows. Figures 1 to 4 The differences in description.

[0124] refer to Figure 10 The second surface WL_S2 of each word line WL1 and WL2 can be disposed on the same plane as the second surface BG_S2 of the back gate electrode structure. Relative to the bit line BL, the height of the second surface WL_S2 of each word line WL1 and WL2 can be the same as the height of the second surface BG_S2 of the back gate electrode structure. The height of the back gate electrode structure BG along the third direction D3 can be less than the height of the word lines WL1 and WL2 along the third direction D3. Relative to the bit line BL, the first surface WL_S1 of each word line WL1 and WL2 can be set to be lower than the first surface BG_S1 of the back gate electrode structure. Relative to the bit line BL, the height of the first surface WL_S1 of each word line WL1 and WL2 can be less than the height of the first surface BG_S1 of the back gate electrode structure.

[0125] According to some example embodiments, when viewed from the first direction D1 plane, the back gate electrode structure BG can overlap with word lines WL1 and WL2 and active patterns AP1 and AP2. Specifically, on the third direction D3, the height of the back gate electrode structure BG can be less than the height of word lines WL1 and WL2 and active patterns AP1 and AP2, and the bottom surface BG_S1 of the back gate electrode structure BG can be above the bottom surfaces of word lines WL1 and WL2 and the bottom surfaces of active patterns AP1 and AP2, and the top surface BG_S2 of the back gate electrode structure BG can be substantially coplanar with the top surfaces of word lines WL1 and WL2 and located below the top surfaces of active patterns AP1 and AP2. By adjusting the portion where word lines WL1 and WL2 and active patterns AP1 and AP2 overlap with the back gate electrode structure BG when viewed along the first direction D1, transistor leakage current (such as gate-induced dynamic leakage or GIDL) can be effectively controlled.

[0126] Figure 11 It is used to illustrate a semiconductor device according to an example embodiment. Figure 2 An enlarged view of part P in the diagram. For ease of understanding this disclosure, the main descriptions and references are as follows. Figures 1 to 4 The differences in description.

[0127] refer to Figure 11 The first surface WL_S1 of each word line WL1 and WL2 can be disposed on the same plane as the first surface BG_S1 of the back gate electrode structure. Relative to the bit line BL, the height of the first surface WL_S1 of each word line WL1 and WL2 can be the same as the height of the first surface BG_S1 of the back gate electrode structure. The height of the back gate electrode structure BG along the third direction D3 can be less than the height of the word lines WL1 and WL2 along the third direction D3. Relative to the bit line BL, the second surface WL_S2 of each word line WL1 and WL2 can be set to be higher than the second surface BG_S2 of the back gate electrode structure. Relative to the bit line BL, the height of the second surface WL_S2 of each word line WL1 and WL2 can be greater than the height of the second surface BG_S2 of the back gate electrode structure.

[0128] According to some example embodiments, when viewed from the first direction D1 plane, the back gate electrode structure BG can overlap with word lines WL1 and WL2 and active patterns AP1 and AP2. Specifically, in the third direction D3, the height of the back gate electrode structure BG can be less than the height of word lines WL1 and WL2 and active patterns AP1 and AP2, and the bottom surface BG_S1 of the back gate electrode structure BG can be substantially coplanar with the bottom surfaces of word lines WL1 and WL2 and active patterns AP1 and AP2, and the top surface BG_S2 of the back gate electrode structure BG can be substantially coplanar with the top surfaces of word lines WL1 and WL2 and located below the top surfaces of active patterns AP1 and AP2. By adjusting the portion where word lines WL1 and WL2 and active patterns AP1 and AP2 overlap with the back gate electrode structure BG, transistor leakage current (such as gate-induced dynamic leakage or GIDL) can be effectively controlled.

[0129] Figure 12 It is used to illustrate a semiconductor device according to an example embodiment. Figure 2 An enlarged view of part P in the diagram. For ease of understanding this disclosure, the main descriptions and references are as follows. Figures 1 to 4 The differences in description.

[0130] refer to Figure 12 The thickness of the first back-gate work function adjustment pattern 320 along the third direction D3 and the thickness of the second back-gate work function adjustment pattern 330 along the third direction D3 can be different from each other. For example, the thickness of the first back-gate work function adjustment pattern 320 along the third direction D3 can be less than the thickness of the second back-gate work function adjustment pattern 330 along the third direction D3. However, the exemplary embodiment is not limited to this. For example, the thickness of the first back-gate work function adjustment pattern 320 along the third direction D3 can be greater than the thickness of the second back-gate work function adjustment pattern 330 along the third direction D3.

[0131] According to some example embodiments, transistor leakage current (such as gate-induced dynamic leakage or GIDL) can be effectively controlled by adjusting the area where each of the first back-gate work function adjustment pattern 320 and the second back-gate work function adjustment pattern 330 overlaps with word lines WL1 and WL2 and active patterns AP1 and AP2 when viewed along the first direction D1.

[0132] Figure 13 It is used to illustrate a semiconductor device according to an example embodiment. Figure 2 An enlarged view of part P in the diagram. For ease of understanding this disclosure, the main descriptions and references are as follows. Figures 1 to 4 The differences in description.

[0133] refer to Figure 13The word lines WL1 and WL2 may include a word line main pattern 410 and word line power function adjustment patterns 420 and 430. The word line main pattern 410 and the word line power function adjustment patterns 420 and 430 may overlap each other in the third direction D3. That is, the word line power function adjustment patterns 420 and 430 may have substantially equal widths in the first direction D1, while being located below and above the word line main pattern 410, respectively, in the third direction D3.

[0134] According to some example embodiments, the word line main body pattern 410 can be disposed between the first word line power function adjustment pattern 420 and the second word line power function adjustment pattern 430. When viewed from the first direction D1 plane, the word line main body pattern 410 can overlap with multiple active patterns AP1 and AP2 and the back gate electrode structure BG.

[0135] According to some example embodiments, word line power function adjustment patterns 420 and 430 may include a first word line power function adjustment pattern 420 and a second word line power function adjustment pattern 430. Word line power function adjustment patterns 420 and 430 may overlap with the word line body pattern 410 in a third direction D3. That is, word line power function adjustment patterns 420 and 430 may have substantially equal widths in a first direction D1, while being located below and above the word line body pattern 410, respectively, in the third direction D3. Word line power function adjustment patterns 420 and 430 may contact the word line body pattern 410. The first word line power function adjustment pattern 420 and the second word line power function adjustment pattern 430 may be spaced apart from each other, with the word line body pattern 410 located between them. The first word line power function adjustment pattern 420 may be disposed between the word line body pattern 410 and the bit line BL. The second word line power function adjustment pattern 430 may be disposed between the word line body pattern 410 and the data storage pattern DSP.

[0136] According to some example embodiments, word line power function adjustment patterns 420 and 430 can be disposed at one or both ends of each word line WL1 and WL2 along a third direction D3. The two ends of each word line WL1 and WL2 along the third direction D3 can be a first surface WL_S1 and a second surface WL_S2 of each word line WL1 and WL2. Word line power function adjustment patterns 420 and 430 can define one of the first surface WL_S1 and the second surface WL_S2 of each word line WL1 and WL2. For example, the first word line power function adjustment pattern 420 can define the first surface WL_S1 of each word line WL1 and WL2. The lower surface of the first word line power function adjustment pattern 420 can be the first surface WL_S1 of each word line WL1 and WL2. The second word line power function adjustment pattern 430 can define the second surface WL_S2 of each word line WL1 and WL2. The upper surface of the second character line function adjustment pattern 430 can be the second surface WL_S2 of each character line WL1 and WL2.

[0137] According to some example embodiments, the first word line work function adjustment pattern 420 and the second word line work function adjustment pattern 430 may include materials different from those of the main word line pattern 410. The first word line work function adjustment pattern 420 and the second word line work function adjustment pattern 430 may include materials with a work function lower than that of the main word line pattern 410. The first word line work function adjustment pattern 420 and the second word line work function adjustment pattern 430 may include at least one of, for example, doped polycrystalline silicon, lanthanum oxide (LaO), and titanium aluminum carbide (TiAlC). However, the example embodiments are not limited thereto.

[0138] According to some example embodiments, by adjusting the power functions of word lines WL1 and WL2 through the first word line power function adjustment pattern 420 and the second word line power function adjustment pattern 430, the threshold voltage of VCT can be effectively controlled.

[0139] Figure 14 It is used to illustrate a semiconductor device according to an example embodiment. Figure 2 An enlarged view of part P in the diagram. For ease of understanding this disclosure, the main descriptions and references are as follows. Figure 13 The differences in description.

[0140] refer to Figure 14The word line power function adjustment patterns 420 and 430 can be spaced apart from the word line main body pattern 410. The word line interlayer insulation pattern 116 can be disposed between the first word line power function adjustment pattern 420 and the word line main body pattern 410, and between the second word line power function adjustment pattern 430 and the word line main body pattern 410. The first word line power function adjustment pattern 420, the word line interlayer insulation pattern 116, the word line main body pattern 410, the word line interlayer insulation pattern 116, and the second word line power function adjustment pattern 430 can be sequentially stacked on the third direction D3.

[0141] According to some example embodiments, the interlayer insulation pattern 116 of the word lines may cover the upper and lower surfaces of the main word line pattern 410. The interlayer insulation pattern 116 of the word lines may include an insulating material. For example, the interlayer insulation pattern 116 of the word lines may include at least one of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and combinations thereof.

[0142] According to some example embodiments, word line power function adjustment patterns 420 and 430 can be physically spaced apart from word line body pattern 410, so that the voltages applied to word line power function adjustment patterns 420 and 430 and the voltage applied to word line body pattern 410 can be controlled independently of each other. Therefore, by individually adjusting the individual voltages applied to word line body pattern 410 and word line power function adjustment patterns 420 and 430, the threshold voltage of VCT can be controlled more precisely.

[0143] Figure 15 It is used to illustrate a semiconductor device according to an example embodiment. Figure 2 An enlarged view of part P in the diagram. For ease of understanding this disclosure, the main descriptions and references are as follows. Figures 1 to 4 The differences in description.

[0144] refer to Figure 15 The back grille body pattern 310 may include a back grille body center portion 310C, a first protruding portion 310P1, and a second protruding portion 310P2. The back grille body center portion 310C may be located on a third direction D3 between the first protruding portion 310P1 and the second protruding portion 310P2.

[0145] According to some example embodiments, the central portion 310C of the back grid body can be disposed between the first back grid work function adjustment pattern 320 and the second back grid work function adjustment pattern 330 along the third direction D3.

[0146] According to some example embodiments, each of the first protrusion 310P1 and the second protrusion 310P2 can protrude from the center portion 310C of the back gate body. The first protrusion 310P1 can protrude from the center portion 310C of the back gate body toward the bit line BL. The second protrusion 310P2 can protrude from the center portion 310C of the back gate body toward the data storage pattern DSP. The first protrusion 310P1 and the second protrusion 310P2 can be located on a third direction D3, respectively, below the second back gate work function adjustment pattern 330 and above the first back gate work function adjustment pattern 320.

[0147] According to some example embodiments, the first protrusion 310P1 may be surrounded (e.g., located within) the first back-gate work function adjustment pattern 320. The lower surface of the first protrusion 310P1 and the lower surface of the first back-gate work function adjustment pattern 320 may be disposed on the same plane. The lower surface of the first back-gate work function adjustment pattern 320 and the lower surface of the first protrusion 310P1 may be the first surface BG_S1 of the back-gate electrode structure.

[0148] According to some example embodiments, the second protrusion 310P2 may be surrounded (e.g., located within) by the second back-gate work function adjustment pattern 330. The upper surface of the second protrusion 310P2 and the upper surface of the second back-gate work function adjustment pattern 330 may be disposed on the same plane. The upper surface of the second back-gate work function adjustment pattern 330 and the upper surface of the second protrusion 310P2 may be the second surface BG_S2 of the back-gate electrode structure.

[0149] According to some example embodiments, by adjusting the area where the back gate main pattern 310 and the back gate work function adjustment patterns 320 and 330 overlap on the third direction D3, the resistance generated between the back gate main pattern 310 and the back gate work function adjustment patterns 320 and 330 can be reduced.

[0150] Figure 16 It is used to illustrate a semiconductor device according to an example embodiment. Figure 2 An enlarged view of part P in the diagram. For ease of understanding this disclosure, the main descriptions and references are as follows. Figures 1 to 4 The differences in description.

[0151] refer to Figure 16 The back-gate work function adjustment patterns 320 and 330 may each include horizontal portions 320H and 330H and vertical portions 320V and 330V, respectively. The first back-gate work function adjustment pattern 320 may include a first horizontal portion 320H and a first vertical portion 320V. The second back-gate work function adjustment pattern 330 may include a second horizontal portion 330H and a second vertical portion 330V.

[0152] According to some example embodiments, a first horizontal portion 320H may be disposed between the back gate body pattern 310 and the first buffer portion 310E1. A first vertical portion 320V may protrude from the first horizontal portion 320H toward the bit line BL. The first vertical portion 320V may be disposed on one side of the first buffer portion 310E1. A second horizontal portion 330H may be disposed between the back gate body pattern 310 and the second buffer portion 310E2. The second vertical portion 330V may protrude from the second horizontal portion 330H toward the data storage pattern DSP. The second vertical portion 330V may be disposed on one side of the second buffer portion 310E2.

[0153] According to some example embodiments, the back gate body pattern 310 may include a back gate body central portion 310C, a first buffer portion 310E1, and a second buffer portion 310E2. The back gate body central portion 310C is located between the first buffer portion 310E1 and the second buffer portion 310E2 in a third direction D3. The back gate body central portion 310C, the first buffer portion 310E1, and the second buffer portion 310E2 may be spaced apart from each other.

[0154] According to some example embodiments, the central portion 310C of the back grid body can be disposed between the first back grid work function adjustment pattern 320 and the second back grid work function adjustment pattern 330. The central portion 310C of the back grid body can be disposed between the first horizontal portion 320H and the second horizontal portion 330H.

[0155] According to some example embodiments, the first buffer portion 310E1 may be spaced apart from the central portion 310C of the back gate body, wherein the first back gate work function adjustment pattern 320 is located therebetween. The first buffer portion 310E1 may be surrounded by the first back gate work function adjustment pattern 320. For example, the upper surface and side surface of the first buffer portion 310E1 may be surrounded by the first back gate work function adjustment pattern 320 (e.g., located between them). The first buffer portion 310E1 may be surrounded by a first horizontal portion 320H and a first vertical portion 320V. The lower surface of the first buffer portion 310E1 and the lower surface of the first vertical portion 320V may be disposed on the same plane. The lower surface of the first buffer portion 310E1 and the lower surface of the first vertical portion 320V may be the first surface BG_S1 of the back gate electrode structure.

[0156] According to some example embodiments, the second buffer portion 310E2 may be spaced apart from the central portion 310C of the back gate body, wherein the second back gate work function adjustment pattern 330 is located therebetween. The second buffer portion 310E2 may be surrounded by the second back gate work function adjustment pattern 330. For example, the lower surface and side surface of the second buffer portion 310E2 may be surrounded by the second back gate work function adjustment pattern 330 (e.g., located between them). The second buffer portion 310E2 may be surrounded by a second horizontal portion 330H and a second vertical portion 330V. The upper surface of the second buffer portion 310E2 and the upper surface of the second vertical portion 330V may be disposed on the same plane. The upper surface of the second buffer portion 310E2 and the upper surface of the second vertical portion 330V may be the second surface BG_S2 of the back gate electrode structure.

[0157] According to some example embodiments, by adjusting the overlapping area of ​​the back gate main pattern 310 and the back gate work function adjustment patterns 320 and 330, the resistance generated between the back gate main pattern 310 and the back gate work function adjustment patterns 320 and 330 can be reduced.

[0158] Figure 17 It is used to illustrate a semiconductor device according to an example embodiment. Figure 2 An enlarged view of part P in the diagram. For ease of understanding this disclosure, the main descriptions and references are as follows. Figures 1 to 4 The differences in description.

[0159] refer to Figure 17 The back grid work function adjustment patterns 320 and 330 may include multiple layers. The first back grid work function adjustment pattern 320 may include a first sub-work function adjustment pattern 321 and a second sub-work function adjustment pattern 322. The second back grid work function adjustment pattern 330 may include a third sub-work function adjustment pattern 331 and a fourth sub-work function adjustment pattern 332.

[0160] According to some example embodiments, the first sub-work function adjustment pattern 321 may include a material different from the material included in the second sub-work function adjustment pattern 322. The work function of the material included in the first sub-work function adjustment pattern 321 may differ from the work function of the material included in the second sub-work function adjustment pattern 322. For example, the work function of the material included in the first sub-work function adjustment pattern 321 may be greater than the work function of the material included in the second sub-work function adjustment pattern 322.

[0161] According to some example embodiments, the third sub-work function adjustment pattern 331 may include a material different from the material included in the fourth sub-work function adjustment pattern 332. The work function of the material included in the third sub-work function adjustment pattern 331 may differ from the work function of the material included in the fourth sub-work function adjustment pattern 332. For example, the work function of the material included in the third sub-work function adjustment pattern 331 may be greater than the work function of the material included in the fourth sub-work function adjustment pattern 332.

[0162] Figure 17 The first back-gate work function adjustment pattern 320 and the second back-gate work function adjustment pattern 330 are shown to both include multiple layers, but the example embodiment is not limited thereto. For example, one of the first back-gate work function adjustment pattern 320 and the second back-gate work function adjustment pattern 330 may include multiple layers, while the other may include a single layer.

[0163] Figures 18 to 71 This is a diagram illustrating the operation of a method for manufacturing a semiconductor device according to some example embodiments.

[0164] refer to Figures 18 to 20 A buried insulating layer 201 and an active layer 202 can be formed above the sub-substrate 200.

[0165] According to some example embodiments, the buried insulating layer 201 and the active layer 202 may be disposed above the sub-substrate 200. The sub-substrate 200, the buried insulating layer 201, and the active layer 202 may be silicon-on-insulator (SOI) substrates. The sub-substrate 200 may be, for example, a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate.

[0166] According to some example embodiments, the buried insulating layer 201 may be a buried oxide (BOX) formed by an implanted oxygen separation (SIMOX) process or a bonding and layer transfer process. Alternatively, the buried insulating layer 201 may be an insulating layer formed by chemical vapor deposition. The buried insulating layer 201 may include, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and / or a low dielectric constant insulating layer.

[0167] According to some example embodiments, the active layer 202 may be a single-crystal semiconductor layer. The active layer 202 may be, for example, a single-crystal silicon substrate, a germanium substrate, and / or a silicon-germanium substrate. The active layer 202 may have a first surface 202S1 and a second surface 202S2 disposed opposite to each other on a third-direction D3, and the second surface 202S2 of the active layer 202 may contact the buried insulating layer 201.

[0168] refer to Figures 21 to 23 The first back gate trench BG_T1 can be formed using the back gate mask pattern MP1.

[0169] According to some example embodiments, a back gate mask pattern MP1 may be formed on the active layer 202. The back gate mask pattern MP1 may have a linear opening portion extending along a second direction D2. The back gate mask pattern MP1 may include a first lower mask layer 11 and a first upper mask layer 12 stacked sequentially. The first upper mask layer 12 may include a material with etch selectivity relative to the first lower mask layer 11. As an example, the first lower mask layer 11 may include silicon oxide and the first upper mask layer 12 may include silicon nitride, but the example embodiments are not limited thereto.

[0170] Subsequently, using the back gate mask pattern MP1 as an etching mask, the active layer 202 can be etched anisotropically. Therefore, a first back gate trench BG_T1 extending along the second direction D2 can be formed in the active layer 202. The first back gate trench BG_T1 can expose the buried insulating layer 201. The first back gate trench BG_T1 can be configured as a plurality of first back gate trenches BG_T1, and the plurality of first back gate trenches BG_T1 can be spaced apart from each other in the first direction D1.

[0171] refer to Figures 24 to 26 A back-gate side insulating pattern 113 and a pre-back-gate electrode BG_1 can be formed within the first back-gate trench BG_T1. In the following text, "pre" can refer to the element prior to completion.

[0172] According to some example embodiments, a back-gate side insulating pattern 113 can be formed along the sidewalls and bottom surface of the first back-gate trench BG_T1 and the upper surface of the back-gate mask pattern MP1. A back-gate body pattern 310 and a first back-gate work function adjustment pattern 320 can be formed on the back-gate side insulating pattern 113. The back-gate body pattern 310 and the first back-gate work function adjustment pattern 320 can fill the first back-gate trench BG_T1. Subsequently, by isotropically etching the back-gate body pattern 310 and the first back-gate work function adjustment pattern 320, a pre-back-gate electrode BG_1 extending along the second direction D2 can be formed. The pre-back-gate electrode BG_1 can fill a portion of the first back-gate trench BG_T1.

[0173] According to some example embodiments, a gas phase doping (GPD) process or a plasma doping (PLAD) process can be performed before forming the back gate side insulating pattern 113. Through these processes, the active layer 202 exposed by the first back gate trench BG_T1 can be doped with impurities.

[0174] refer to Figures 27 to 29 A back gate cover pattern 115 can be formed on the pre-back gate electrode BG_1.

[0175] According to some example embodiments, the back gate cover pattern 115 may fill the remaining portion of the first back gate trench BG_T1. If the back gate cover pattern 115 and the back gate side insulating pattern 113 comprise the same material (e.g., silicon oxide), the back gate side insulating pattern 113 on the upper surface of the back gate mask pattern MP1 may be removed while the back gate cover pattern 115 is being formed.

[0176] Before forming the back gate cover pattern 115, a GPD process or a PLAD process can be performed. Thus, the active layer 202 can be doped with impurities by forming the first back gate trench BG_T1 of the pre-back gate electrode BG_1.

[0177] According to some example embodiments, after forming the back grid cover pattern 115, it can be removed Figure 28 and Figure 29 The first upper mask layer 12. The back grid cover pattern 115 may have a form that protrudes above the upper surface of the first lower mask layer 11.

[0178] refer to Figures 30 to 32 A spacer layer 120 can be formed along the upper surface of the first lower mask layer 11, the sidewalls of the back gate side insulating pattern 113, and the upper surface of the back gate cover pattern 115. The spacer layer 120 can be formed with a uniform thickness. Based on the deposition thickness of the spacer layer 120, the width of the active pattern of the VCT can be determined. The spacer layer 120 may include an insulating material. The spacer layer 120 may include, for example, silicon oxide, silicon oxynitride, silicon carbide (SiC), silicon carbonitride (SiCN), and combinations thereof. The spacer layer 120 may extend along the surface profile of the back gate cover pattern 115, protruding above the upper surface of the first lower mask layer 11.

[0179] refer to Figures 33 to 35 When an anisotropic etching process is performed on the spacer layer 120, a pair of spacer patterns 121 can be formed on the sidewall of the back gate side insulating pattern 113.

[0180] According to some example embodiments, the spacer pattern 121 can be used as an etching mask to perform an anisotropic etching process on the active layer 202. This allows a pair of pre-active patterns PAPs, separated from each other, to be formed on opposite sides of the back gate-side insulating pattern 113. With the formation of the pre-active patterns PAPs, the buried insulating layer 201 can be exposed.

[0181] According to some example embodiments, when viewed from the first direction D1 plane, the pre-active pattern PAP may overlap with the first pre-back gate electrode BG_1. The pre-active pattern PAP may have the shape of a line extending in the second direction D2. Multiple pre-active pattern PAPs may be configured. Word line trenches WL_T may be formed between the multiple pre-active pattern PAPs spaced apart from each other along the first direction D1.

[0182] refer to Figures 36 to 38 An etch stop layer 31 can be formed along the sidewalls and bottom surface of the character line groove WL_T.

[0183] According to some example embodiments, an etch stop layer 31 and a sacrificial layer 33 may be formed within the word line trench WL_T. The sacrificial layer 33 may fill the word line trench WL_T. The sacrificial layer 33 may have a substantially flat upper surface.

[0184] According to some example embodiments, the etch stop layer 31 can be formed by depositing an insulating material (e.g., silicon oxide), but is not limited thereto. The sacrificial layer 33 can be formed of an insulating material that has etch selectivity relative to the etch stop layer 31. As an example, the sacrificial layer 33 can be one of an insulating material and a silicon oxide layer formed using spin-coated glass (SOG) technology, but is not limited thereto.

[0185] refer to Figures 39 to 41 A second mask pattern MP2 can be formed on the sacrificial layer 33.

[0186] According to some example embodiments, the second mask pattern MP2 may be formed of a material having etch selectivity relative to the sacrificial layer 33. The second mask pattern MP2 may be in the form of a line extending along a first direction D1. The second mask patterns MP2 may be configured as a plurality of second mask patterns MP2 spaced apart from each other along a second direction D2.

[0187] Subsequently, by etching the sacrificial layer 33 using the second mask pattern MP2 as an etch mask, an opening OP can be formed. The opening OP can expose the etch stop layer 31. The opening OP can penetrate the sacrificial layer 33 in the third direction D3.

[0188] refer to Figures 42 to 44 This can remove the etch stop layer 31 exposed by the opening OP.

[0189] According to some example embodiments, the opening OP can expose the upper surface of the buried insulation layer 201. Furthermore, the opening OP can expose a portion of the pre-existing active pattern PAP.

[0190] Subsequently, by etching the pre-active pattern PAP exposed by the opening OP, a first active pattern AP1 and a second active pattern AP2 can be formed on opposite sides of the first pre-back gate electrode BG_1. On the first sidewall of the first pre-back gate electrode BG_1, a plurality of first active patterns AP1 can be formed to be spaced apart from each other in the second direction D2. On the second sidewall of the first pre-back gate electrode BG_1, a plurality of second active patterns AP2 can be formed to be spaced apart from each other in the second direction D2. With the formation of the first active patterns AP1 and the second active patterns AP2, a portion of the back gate side insulating pattern 113 can be exposed by the opening OP.

[0191] refer to Figures 45 to 47 , can Figures 42 to 44 The opening OP is filled with a sacrificial layer 33. Filling Figures 42 to 44 The sacrificial layer 33 of the opening OP can have the same characteristics as the filling. Figure 34 and Figure 35 The sacrificial layer 33 of the character line groove WL_T is made of the same material.

[0192] According to some example embodiments, the sacrificial layer 33 is filled with Figures 42 to 44 After opening the OP, it can be removed. Figures 42 to 44 The second mask pattern MP2. To expose the upper surface of the back gate cover pattern 115, a planarization process can be performed on the sacrificial layer 33 and the etch stop layer 31. Subsequently, the mask pattern MP2 can be removed. Figure 43 The spacer pattern 121 and Figure 43 The first lower mask layer 11 is used. This exposes the first active pattern AP1 and the second active pattern AP2. A planarization process can be used to remove them. Figure 43 The spacer pattern 121 and Figure 43 The first lower mask layer 11, but not limited to this.

[0193] refer to Figures 48 to 50 It can remove Figures 45 to 47 Sacrificial layer 33 on buried insulation layer 201 and Figures 45 to 47 An etch stop layer 31 is embedded in the insulating layer 201. Thus, the embedded insulating layer 201 can be exposed.

[0194] refer to Figures 51 to 53 A gate insulation pattern GOX can be formed along the side surface of the first active pattern AP1, the side surface of the second active pattern AP2, the upper surface of the back gate cover pattern 115, and the upper surface of the buried insulating layer 201.

[0195] According to some example embodiments, at least one of physical vapor deposition (PVD), thermochemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), and atomic layer deposition (ALD) techniques can be used to form the gate insulating pattern GOX, but is not limited thereto.

[0196] Subsequently, a first word line WL1 and a second word line WL2 can be formed on the gate insulating pattern GOX. The first word line WL1 and the second word line WL2 can be formed on the side surfaces of the first active pattern AP1 and the second active pattern AP2. Forming the first word line WL1 and the second word line WL2 can include depositing a gate conductive layer on the gate insulating pattern GOX, and then performing an anisotropic etching process on the gate conductive layer. Here, the deposition thickness of the gate conductive layer can be less than [a certain value]. Figure 34 and Figure 35 The width of the character line groove WL_T along the first direction D1 is half.

[0197] According to some example embodiments, in an anisotropic etching process on the gate conductive layer, the gate insulating pattern GOX can be used as an etch stop layer. The gate insulating pattern GOX can be over-etched, and the buried insulating layer 201 can be exposed. Based on the anisotropic etching process of the gate conductive layer, the first word line WL1 and the second word line WL2 can have various shapes. The upper surface of the first word line WL1 and the upper surface of the second word line WL2 can be located at a lower height than the upper surface of the first active pattern AP1 and the second active pattern AP2.

[0198] As an example, after forming the first word line WL1 and the second word line WL2, a GPD process or a PLAD process can be performed. Thus, the first active pattern AP1 and the second active pattern AP2 can be doped with impurities through the gate insulating pattern GOX exposed by the first word line WL1 and the second word line WL2.

[0199] refer to Figures 54 to 56 A gate separator pattern GSS can be formed on the first word line WL1 and the second word line WL2. For example, the upper surface of the gate separator pattern GSS can be located on the same plane as the upper surface of the back gate cover pattern 115.

[0200] According to some example embodiments, a planarization process can be performed on the gate separator pattern GSS and the gate insulating pattern GOX to expose the upper surfaces of the first active pattern AP1 and the second active pattern AP2. For example, the planarization process may include, but is not limited to, a chemical mechanical polishing (CMP) process and may be modified in various ways.

[0201] refer to Figures 57 to 59Bit lines BL extending along the first direction D1 can be formed on the gate separator pattern GSS and the back gate cover pattern 115.

[0202] According to some example embodiments, the bit line BL may include a bit line mask pattern 165, a metal pattern 163, and a semiconductor pattern 161. While forming the bit line BL, a portion of the back gate cover pattern 115 and a portion of the gate separator pattern GSS may be etched. For example, a portion of the back gate cover pattern 115 and a portion of the gate separator pattern GSS on the third-direction D3 where the bit line BL is not formed may be etched more than a portion of the back gate cover pattern 115 and the gate separator pattern GSS on the third-direction D3 where the bit line BL is not formed. The upper surface of the back gate cover pattern 115 and the gate separator pattern GSS on the third-direction D3 where the bit line BL is not formed may be set lower than the upper surface of the back gate cover pattern 115 and the gate separator pattern GSS on the third-direction D3.

[0203] refer to Figures 60 to 62 A shielding line SL can be formed between adjacent bit lines along the second direction D2.

[0204] According to some example embodiments, a shielding insulating pad 171 may be formed on the upper surface of the bit lines BL spaced apart along the second direction D2, the upper surface of the back gate cover pattern 115, and the upper surface of the gate separator pattern GSS. The shielding insulating pad 171 may define a shielding region between adjacent bit lines BL along the second direction D2. A shielding line SL may be formed within the shielding region of the shielding insulating pad 171.

[0205] According to some example embodiments, a shielding line SL can be formed between bit lines BL. As an example, forming the shielding line SL may include forming a shielding conductive layer for filling a shielding region on the shielding insulating pad 171, and recessing the upper surface of the shielding conductive layer. Subsequently, a shielding insulating cover layer 175 can be formed on the shielding line SL. Further, shielding insulating cover layer 175, shielding insulating pad 171, and bit line BL may be formed. Figure 2 and Figure 3 The bonding insulation layer 263.

[0206] refer to Figures 63 to 65 A sub-substrate 200, having a pre-back gate electrode BG_1, multiple word lines WL1 and WL2, multiple active patterns AP1 and AP2, bit line BL, and shield line SL, can be bonded to the substrate 100. The substrate 100 and the sub-substrate 200 can be bonded using a bonding insulating layer 263.

[0207] According to some example embodiments, a peripheral gate structure PG can be pre-formed on the substrate 100. Peripheral wiring lines 241a and peripheral contact plugs 241b can be formed over the substrate 100. A peripheral upper insulating layer 265 can be sequentially formed over the peripheral wiring lines 241a and peripheral contact plugs 241b. A bonding insulating layer 263 can be formed on the peripheral upper insulating layer 265.

[0208] refer to Figures 66 to 68 ,exist Figures 63 to 65 After the substrate 100 and the sub-substrate 200 are bonded, a process for removing... Figures 63 to 65 The backside grinding process of the 200 sub-substrate. Removal Figures 63 to 65 The sub-substrate 200 may include sequentially performing a polishing process and a wet etching process to expose Figures 63 to 65 The buried insulation layer 201.

[0209] Subsequently, by removing Figures 63 to 65 The buried insulating layer 201 can expose the first active pattern AP1 and the second active pattern AP2. With... Figures 63 to 65 The buried insulating layer 201 is removed, which exposes a portion of the gate insulating pattern GOX and a portion of the back gate side insulating pattern 113.

[0210] Subsequently, the exposed portions of the gate insulating pattern GOX and the back gate side insulating pattern 113 can be removed. Thus, Figure 64 and Figure 65 The first pre-back gate electrode BG_1, the first word line WL1, and the second word line WL2 can be exposed.

[0211] Subsequently, by performing an etch-back process, a portion of the first word line WL1 and a portion of the second word line WL2 can be removed. A gate cover pattern 143 can then be formed on the recessed first word line WL1 and second word line WL2.

[0212] Subsequently, by performing a back etching process, the residue can be removed. Figure 64 and Figure 65 Part of the first pre-back gate electrode BG_1. Figure 64 and Figure 65 A portion of the first pre-back gate electrode BG_1 is removed, which can form the second pre-back gate electrode BG_2.

[0213] According to some example embodiments, a portion of the back gate body pattern 310 can be removed, and a second back gate trench BG_T2 can be formed. The bottom surface of the second back gate trench BG_T2 can be configured as a second surface WL_S2 lower than each of the first word line WL1 and the second word line WL2. After removing a portion of the back gate body pattern 310 by an etch-back process, the upper surface of the back gate body pattern 310 exposed within the second back gate trench BG_T2 can be configured as a second surface WL_S2 lower than each of the first word line WL1 and the second word line WL2.

[0214] refer to Figures 69 to 71 This can form a back gate electrode structure (BG). It can be used to... Figure 67 and Figure 68 A second back-gate work function adjustment pattern 330 and a back-gate separation pattern 111 are formed within the second back-gate trench BG_T2. The second back-gate work function adjustment pattern 330 can be formed on the back-gate body pattern 310. The back-gate body pattern 310 can have a first surface facing the bit line BL and a second surface disposed opposite to the first surface in a third direction D3. The second back-gate work function adjustment pattern 330 can be formed on the second surface of the back-gate body pattern 310. The second back-gate work function adjustment pattern 330 can be set to a second surface WL_S2 that is lower than each of the first word line WL1 and the second word line WL2.

[0215] Subsequently, reference Figure 2 and Figure 3 Contact holes for exposing the first active pattern AP1 and the second active pattern AP2 can be formed within the contact etch stop layer 212 and the contact separator insulating pattern 231. A contact pattern BC can be formed within the contact holes. The contact pattern BC can be formed on the first active pattern AP1 and the second active pattern AP2. The contact pattern BC can be connected to the first active pattern AP1 and the second active pattern AP2. A data storage pattern DSP can be formed above the contact pattern BC.

[0216] A method of manufacturing a semiconductor device may include: forming a plurality of back gate trenches within an active layer, the plurality of back gate trenches being spaced apart from each other in a first direction parallel to a first surface of the active layer, extending in a second direction intersecting the first direction, and penetrating at least a portion of the active layer in a third direction intersecting the first and second directions; sequentially forming a back gate body pattern and a first back gate work function adjustment pattern within the plurality of back gate trenches; forming a plurality of active patterns by patterning the active layer, the plurality of active patterns being disposed on the side of each of the back gate body pattern and the first back gate work function adjustment pattern in the first direction and being spaced apart from each other in the second direction; forming a plurality of word lines, each word line being disposed on the side of each of the plurality of active patterns along the first direction and extending in the second direction; forming a plurality of bit lines on a first surface of the plurality of active patterns, the plurality of bit lines extending in the first direction and being spaced apart from each other in the second direction; and forming a second back gate work function adjustment pattern on a second surface of the back gate body pattern, the second surface being disposed opposite to the first surface of the back gate body pattern facing the bit lines in a third direction.

[0217] Each embodiment described above is not excluded from being associated with one or more features of another example or another embodiment that are also provided herein or that are not provided herein but are consistent with this disclosure.

[0218] Although this disclosure has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: Bit lines, the bit lines extending in a first direction; The character line extends in a second direction intersecting the first direction, and is located above the bit line in a third direction intersecting the first and second directions; A back gate electrode structure, wherein the back gate electrode structure is located above the bit line in the third direction, is spaced apart from the word line in the first direction, and extends in the second direction; as well as An active pattern is located on the bit line, situated between the word line and the back gate electrode structure in the first direction, and extending upward in the third direction. Wherein, the height of the back gate electrode structure in the third direction is less than the height of the word line in the third direction, and The back gate electrode structure includes: At least one back grid work function adjusts the pattern; and The back grid main body pattern is in contact with the at least one back grid work function adjustment pattern in the third direction.

2. The semiconductor device according to claim 1, wherein, The work function of the material of the at least one back grid work function adjustment pattern is greater than the work function of the material of the back grid main pattern.

3. The semiconductor device according to claim 1, wherein, The at least one back grid work function adjustment pattern includes: A first back-gate work function adjustment pattern is located on the third-direction first surface of the back-gate main body pattern; and The second back grid work function adjustment pattern is located on the second surface of the back grid main pattern, which is opposite to the first surface of the back grid main pattern in the third direction.

4. The semiconductor device according to claim 3, wherein, The thickness of the first back grid work function adjustment pattern in the third direction is different from the thickness of the second back grid work function adjustment pattern in the third direction.

5. The semiconductor device according to claim 3, wherein, The back grille main body pattern includes: The central portion of the back grid body is located between the first back grid work function adjustment pattern and the second back grid work function adjustment pattern; A first buffer portion, spaced apart from the central portion of the back grid body and located within the first back grid work function adjustment pattern in the first direction; and The second buffer portion is spaced apart from the central portion of the back grid body and is located within the second back grid work function adjustment pattern in the first direction.

6. The semiconductor device according to claim 5, wherein, The first back grid work function adjustment pattern includes: A first horizontal portion, located on the third-order side between the center portion of the back grille body and the first buffer portion; and A first vertical portion protrudes from the first horizontal portion toward the bit line and is located on one side of the first buffer portion in the first direction.

7. The semiconductor device according to claim 3, wherein, The back grille main body pattern includes: The central portion of the back grid body is located between the first back grid work function adjustment pattern and the second back grid work function adjustment pattern in the third direction. A first protruding portion, the first protruding portion protruding from the center portion of the back grid body in the third direction, passing through the first back grid work function adjustment pattern; and The second protruding portion protrudes from the center portion of the back grid body in the third direction, passing through the second back grid work function adjustment pattern.

8. The semiconductor device according to claim 7, wherein, In the third direction, the lower surface of the first protruding portion and the lower surface of the first back grid work function adjustment pattern are substantially coplanar, and In the third direction, the upper surface of the second protruding portion and the upper surface of the second back grid work function adjustment pattern are substantially coplanar.

9. The semiconductor device according to claim 1, wherein, The back gate electrode structure has a first surface facing the bit line on a third-party upward direction that is substantially coplanar with the first surface facing the bit line on a third-party upward direction, or a first surface that is higher than the word line relative to the bit line.

10. The semiconductor device according to claim 1, wherein, The second surface of the back gate electrode structure is substantially coplanar with the second surface of the word line or is lower than the second surface of the word line relative to the bit line. The second surface of the back gate electrode structure is disposed opposite to the first surface of the back gate electrode structure facing the bit line in the third direction in the third direction. The second surface of the word line is disposed opposite to the first surface of the word line facing the bit line in the third direction in the third direction.

11. The semiconductor device according to claim 1, wherein, The back grid function adjustment pattern contacts the back grid main body pattern.

12. The semiconductor device according to claim 1, wherein, The at least one back grid work function adjustment pattern is spaced apart from the back grid main body pattern in the third direction, and The at least one back gate electrode structure further includes a back gate interlayer insulation pattern located in the third direction between the back gate work function adjustment pattern and the back gate body pattern.

13. The semiconductor device according to claim 1, wherein, The word lines include: The character line function adjusts the pattern; and The main pattern of the character line, wherein the main pattern of the character line contacts the character line function adjustment pattern in the third direction.

14. The semiconductor device according to claim 13, wherein, The work function of the material of the word line adjustment pattern is less than the work function of the material of the main word line pattern.

15. A semiconductor device, the semiconductor device comprising: Multiple bit lines, the multiple bit lines extending in a first direction and spaced apart from each other in a second direction intersecting the first direction; A back gate electrode structure, the back gate electrode structure extending in the second direction and located above the plurality of bit lines in a third direction intersecting the first direction and the second direction; A first active pattern is located on the plurality of bit lines, on a first side of the back gate electrode structure in the first direction, and extends upward in the third direction; The second active pattern is located on the plurality of bit lines, on the second side of the back gate electrode structure in the first direction, and extends upward in the third direction; The first word line is located above the plurality of bit lines in the third direction, on the first side of the back gate electrode structure, and spaced apart from the back gate electrode structure in the first direction; the first active pattern is located between the first word line and the back gate electrode structure in the first direction. as well as The second word line is located above the plurality of bit lines in the third direction, on the second side of the back gate electrode structure, and spaced apart from the back gate electrode structure in the first direction. The second active pattern is located between the second word line and the back gate electrode structure in the first direction. The back-gate electrode structure includes a first back-gate work function adjustment pattern, a back-gate main body pattern, and a second back-gate work function adjustment pattern, which are sequentially stacked in the third direction. Wherein, the work function of each of the first back grid work function adjustment pattern and the second back grid work function adjustment pattern is greater than the work function of the back grid main pattern.

16. The semiconductor device according to claim 15, wherein, The height of each of the first word line and the second word line in the third direction is greater than the height of the back gate electrode structure in the third direction, and less than the height of each of the first active pattern and the second active pattern in the third direction.

17. The semiconductor device according to claim 15, wherein, When viewed from the first direction, the first back grid power function adjustment pattern, the back grid main body pattern, and the second back grid power function adjustment pattern overlap with the first character line and the second character line.

18. The semiconductor device according to claim 15, wherein, At least one of the first back grid work function adjustment pattern and the second back grid work function adjustment pattern includes a multilayer structure.

19. The semiconductor device of claim 15, further comprising: A shielding line is located between the plurality of bit lines in the second direction and below the back gate electrode structure, the first word line, and the second word line in the third direction.

20. A semiconductor device, the semiconductor device comprising: Bit lines, the bit lines extending in a first direction; The character line extends in a second direction intersecting the first direction, and is located above the bit line in a third direction intersecting the first and second directions; A back gate electrode structure, wherein the back gate electrode structure is located above the bit line in the third direction, is spaced apart from the word line in the first direction, and extends in the second direction; An active pattern is located on the bit line, situated between the word line and the back gate electrode structure in the first direction, and extending upward in the third direction; as well as A data storage pattern, wherein the data storage pattern is positioned above the active pattern in a third-party orientation and is connected to the active pattern. The back gate electrode structure is located on the first and second surfaces in the third-direction orientation, between the word line and the first and second surfaces in the third-direction orientation. The back-gate electrode structure includes a first back-gate work function adjustment pattern, a back-gate main body pattern, and a second back-gate work function adjustment pattern, which are sequentially stacked in the third direction. Wherein, the work function of each of the first back grid work function adjustment pattern and the second back grid work function adjustment pattern is greater than the work function of the back grid main body pattern.

Images