A semiconductor structure and a method of fabricating the same

Abstract

The embodiment of the present disclosure provides a semiconductor structure and a preparation method thereof, wherein the semiconductor structure comprises: a plurality of active groups, any active group comprising a connecting part and two active columns extending in a vertical direction, the connecting part being located at the bottom of the two active columns and connecting the end portions of the two active columns on the same side in the vertical direction; a word line extending in a first direction and covering part of the surface of the active column; a bit line extending in a second direction and being located on the side of the connecting part away from the active column and connected with the connecting part; wherein the first direction, the second direction and the extending direction of the connecting part intersect with each other and are all parallel to the same plane, and the first direction, the second direction and the extending direction of the connecting part are all perpendicular to the vertical direction.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] With technological advancements, semiconductor devices are continuously evolving towards miniaturization and higher integration. Memory, as a crucial semiconductor device, is used to store data or programs during electronic device operations for data processing. However, with the ever-increasing demands for computing speed and capacity, applications are placing increasingly higher requirements on memory storage density. Summary of the Invention

[0003] This disclosure provides a semiconductor structure, including: Multiple active groups, each of the active groups includes a connecting portion and two active columns extending in a vertical direction, the connecting portion being located at the bottom of the two active columns and connecting the ends of the two active columns on the same side in the vertical direction; The character line extends along the first direction and covers a portion of the surface of the active column; The bit line extends along the second direction and is located on the side of the connection portion away from the active post and is connected to the connection portion; Wherein, the first direction, the second direction, and the extension direction of the connecting part intersect each other and are all parallel to the same plane, and the first direction, the second direction, and the extension direction of the connecting part are all perpendicular to the vertical direction.

[0004] In some embodiments, the center points of the plurality of connecting portions are arranged in an array in the first direction and the second direction; Among them, the orthographic projection of the multiple active columns in the vertical direction is arranged in a hexagonal close-packed pattern.

[0005] In some embodiments, the side of the connecting portion away from the word line includes a recessed portion, and the bit line is located in the recessed portion; Wherein, the surface of the bit line on the side away from the character line is flush with the top of the recessed portion on the side away from the character line; or, the surface of the bit line on the side away from the character line protrudes beyond the top of the recessed portion on the side away from the character line.

[0006] In some embodiments, along the direction in which the connection extends, the size of the bit line is greater than the spacing between two active posts in the same active group in that direction, and less than or equal to the size of the connection in that direction.

[0007] In some embodiments, the two active columns included in any active group are defined as a first active column and a second active column, respectively. Along the direction of extension of the connecting portion, the connecting portion includes a first sub-part, a second sub-part, and a third sub-part connected together. Along the vertical direction, the orthographic projection of the first sub-part overlaps with the orthographic projection of the first active column, and the orthographic projection of the second sub-part overlaps with the orthographic projection of the second active column. Along the direction of extension of the connecting portion, the third sub-part is located between the first sub-part and the second sub-part. The bit line is connected to at least one of the first sub-part, the second sub-part, and the third sub-part.

[0008] In some embodiments, the active pillar comprises monocrystalline silicon or a metal oxide semiconductor material.

[0009] In some embodiments, the semiconductor structure further includes: A capacitor structure is connected to the surface of the active post on the side away from the bit line; the orthographic projection of the plurality of capacitor structures in the vertical direction is arranged in a hexagonal close-packed pattern.

[0010] This disclosure also provides a method for fabricating a semiconductor structure, the method comprising: Multiple active groups are formed, and any active group includes a connecting part and two active columns extending in a vertical direction. The connecting part is located at the bottom of the two active columns and connects the ends of the two active columns on the same side in the vertical direction. A bit line is formed extending along a second direction; the bit line is located on the side of the connection portion away from the active post and is connected to the connection portion; A character line is formed, the character line extending along a first direction and covering a portion of the surface of the active pillar; Wherein, the first direction, the second direction, and the extension direction of the connecting part intersect each other and are all parallel to the same plane, and the first direction, the second direction, and the extension direction of the connecting part are all perpendicular to the vertical direction.

[0011] In some embodiments, the orthographic projections of the plurality of active columns in the vertical direction are arranged in a hexagonal close-packed pattern.

[0012] In some embodiments, the fabrication method includes: forming a plurality of active groups before forming the bit lines, specifically including: Provide substrate; A first etching process is performed to remove a portion of the substrate to form a plurality of initial active groups, the initial active groups being arranged along a first direction and a second direction; A second etching process is performed to remove a portion of each of the initial active groups, forming the active pillars.

[0013] In some embodiments, the fabrication method includes: after forming the bit lines, forming a plurality of the active groups, specifically including: A substrate is provided, the substrate including a first surface and a second surface disposed opposite to each other along a thickness direction; A plurality of bit lines extending along a second direction are formed on the second surface; an etching process is performed on the first surface to form a plurality of active blocks extending along a first direction; An etching process is performed on the active block to form multiple active pillars.

[0014] In some embodiments, the fabrication method includes: after forming the bit lines, forming a plurality of the active groups, specifically including: Provide substrate; A plurality of bit lines extending along the second direction are formed on the substrate; An isolation layer is formed covering the bit lines and the substrate surface; Part of the isolation layer is removed to form a multiple trench structure extending along the first direction. An active material layer is formed, the active material layer at least covering the sidewalls and bottom of the trench structure; Removing part of the active material layer and leaving the remaining active material layer covering the sidewalls of the trench structure constitutes a plurality of active pillars.

[0015] In some embodiments, forming the bit line includes: A thinning process is performed on the side of the substrate away from the active group to expose the surface of the connection portion away from the active pillar; A bit line is formed extending along the second direction, and the bit line is connected to the surface of the exposed connection portion.

[0016] In some embodiments, the preparation method further includes: A portion of the connecting portion is removed to form a recess extending along the second direction, and the bit line is formed in the recess; the surface of the bit line on the side away from the active post is flush with the top of the recess on the side away from the active post; or, the surface of the bit line on the side away from the active post protrudes beyond the top of the recess on the side away from the active post.

[0017] In some embodiments, the preparation method further includes: A capacitor structure is formed on the side of the active post away from the bit line. The capacitor structure is connected to the active post, and the orthographic projection of the plurality of capacitor structures in the vertical direction is arranged in a hexagonal close-packed pattern.

[0018] This disclosure provides a semiconductor structure and its fabrication method. In this disclosure, the vertically extending arrangement of the active pillars increases the number of transistors that can be placed on a single surface area, thereby increasing the number of memory cells per unit area based on the transistor structure and improving integration density. The connection between two active pillars saves material etching time when forming the active array, and the placement of the bit lines on the side of the connection away from the active pillars improves the flexibility of bit line placement, allowing for flexible adjustments in size and extension direction based on requirements.

[0019] Details of one or more embodiments of this disclosure will be set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the specification and drawings. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure; Figure 2 This is a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure; Figure 3 This is a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure; Figure 4 This is a top view schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure; Figure 5 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure; Figures 6 to 17 This is a schematic diagram of the semiconductor structure during the fabrication process according to an embodiment of the present disclosure; wherein, Figure 7 , Figure 9 This is a top view schematic diagram of the semiconductor structure during the fabrication process. Figure 8 Figure (1) shows the route along Figure 7 Detailed sectional view taken along the B1-B2 direction. Figure 8 Figure (2) is a three-dimensional structural diagram of the initial active group provided in the embodiments of this disclosure; Figure 10 Figure (1) shows the route along Figure 9 Detailed sectional view taken along the B1-B2 direction. Figure 10 Figure (2) is a three-dimensional structural diagram of the active group provided in the embodiment of this disclosure; Figures 18 to 21 This is a schematic diagram of the semiconductor structure during the fabrication process, provided in another embodiment of this disclosure; wherein, Figure 18 and Figure 19 This is a top view schematic diagram of the semiconductor structure during the fabrication process. Figure 20 Figure (1) is a top view of the semiconductor structure provided in the embodiment of this disclosure during the fabrication process; Figure 20 Figure (2) shows the route along Figure 20 (1) Detailed sectional view along the B1-B2 direction in the figure; Figures 22 to 32 This is a schematic diagram of the semiconductor structure during the fabrication process, provided in yet another embodiment of the present disclosure; wherein, Figure 23 , Figure 25 , Figure 27 as well as Figure 28 This is a top view schematic diagram of the semiconductor structure during the fabrication process. Figure 26 For along Figure 25 Detailed sectional view taken along the B1-B2 direction. Figure 29 For along Figure 28 Detailed sectional view taken along the B1-B2 direction. Detailed Implementation

[0022] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0023] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0024] In the accompanying drawings, for clarity, the dimensions of layers, areas, components, and their relative dimensions may be exaggerated. The same reference numerals denote the same components throughout.

[0025] It should be understood that when a component or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other components or layers, it may be directly on, adjacent to, connected to, or coupled to other components or layers, or there may be intervening components or layers. Conversely, when a component is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other components or layers, there are no intervening components or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various components, parts, areas, layers, and / or portions, these components, parts, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one component, part, area, layer, or portion from another component, part, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first component, part, area, layer, or portion discussed below may be referred to as a second component, part, area, layer, or portion. And the discussion of a second component, part, area, layer, or portion does not imply that the first component, part, area, layer, or portion necessarily exists in this disclosure.

[0026] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one component or feature shown in the figure and other components or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the component or feature described as “below,” “under,” or “below” other components or features will be oriented “above” other components or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0027] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “ / the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “compose” and / or “comprising,” when used in this specification, identify the presence of features, integers, steps, operations, components, and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, components, parts, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0028] In semiconductor structures, such as dynamic random access memory (DRAM) structures, bit lines, transistor structures, and capacitor structures are important components. The transistor structure can further include an active region structure, which in turn includes a channel region and two source / drain regions located on either side of the channel region. In some structures, the active region structure can be positioned parallel to the substrate surface. However, this is not a limitation; in other structures, to improve the utilization of the substrate area, the active region structure can also be positioned perpendicular to the substrate surface.

[0029] However, in semiconductor structures where the active region is positioned perpendicular to the substrate surface, there are still cases where the storage density is low.

[0030] Based on this, the technical solution of the present disclosure embodiment is proposed as follows: This disclosure provides a semiconductor structure, including: Multiple active groups, each active group includes a connecting part and two active columns extending in a vertical direction, the connecting part is located at the bottom of the two active columns and connects the ends of the two active columns on the same side in the vertical direction; The character line extends along the first direction and covers a portion of the surface of the source column; The bit line extends along the second direction and is located on the side of the connector away from the active post and is connected to the connector; The first direction, the second direction, and the extension direction of the connecting part intersect each other and are all parallel to the same plane, and the first direction, the second direction, and the extension direction of the connecting part are all perpendicular to the vertical direction.

[0031] In this embodiment, the vertically extending arrangement of the active pillars increases the number of transistors that can be placed on a single surface area, thereby increasing the number of memory cells per unit area based on the transistor structure and improving integration density. The connection between the two active pillars saves material etching time when forming the active array, and the fact that the bit lines are located on the side of the connection away from the active pillars improves the flexibility of bit line placement, allowing for adjustments in size and extension direction based on requirements.

[0032] To make the above-mentioned objects, features, and advantages of this disclosure more apparent and understandable, the specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to general proportions, and the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure.

[0033] Figure 1 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure; Figure 2 This is a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure; Figure 3 This is a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure; Figure 4 This is a top view schematic diagram of a semiconductor structure provided in an embodiment of this disclosure.

[0034] The semiconductor structure provided in the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings.

[0035] like Figures 1 to 4 As shown, the semiconductor structure includes: Multiple active groups AA, each active group AA includes a connecting part A1 and two active columns A2 extending in the vertical direction. The connecting part A1 is located at the bottom of the two active columns A2 and connects the ends of the two active columns A2 on the same side in the vertical direction. The character line WL extends along the first direction and covers a portion of the surface of the source column A2; Bit line BL extends along the second direction and is located on the side of the connector A1 away from the active post A2 and is connected to the connector A1; The extension direction of the connecting part A1 is defined as the third direction. The first direction, the second direction and the third direction intersect each other and are all parallel to the same plane. The first direction, the second direction and the extension direction of the connecting part A1 (the third direction) are all perpendicular to the vertical direction.

[0036] In some embodiments, such as Figure 3 As shown, the semiconductor structure also includes a substrate 10, with bit lines BL and active groups AA disposed on the substrate 10, which can provide support.

[0037] In this embodiment of the disclosure, in the structure including the substrate 10, the vertical direction is the direction perpendicular to the plane of the substrate 10, and the horizontal direction, the first direction, the second direction, and the third direction can be directions parallel to the plane of the substrate 10. In the structure without the substrate 10, the vertical direction corresponds to the direction in which the active pillar A2 extends, and the horizontal direction is the direction parallel to the surface where the connecting portion connects to the active pillar A2. In the structure without the substrate 10, the relationship between the first direction, the second direction, and the third direction and the planes parallel to them can also be understood as follows: Figure 3 The relationship between the first direction, the second direction, and the third direction and the substrate 10. In some embodiments, such as Figure 1 and Figure 2 As shown, the word line WL surrounds the middle area of ​​the active column A2.

[0038] In other embodiments, such as Figure 3 As shown, the word line WL covers the middle area of ​​the sidewalls of two active columns A2 in the same active group that are set opposite each other.

[0039] In some embodiments, the material of the word line WL and the bit line BL may include, but is not limited to, any suitable conductive material, such as tungsten (W), titanium nitride (TiN), or molybdenum (Mo).

[0040] Understandably, the portion of active pillar A2 covered by word line WL can be used as a channel region, while the portion of active pillar A2 used to connect to connection portion A1 can be used as a source / drain region, and the portion of active pillar A2 located on the opposite side of this source / drain region can be used as another source / drain region. The channel region, the two source / drain regions, and the portion of the channel region covered by word line WL can constitute a transistor structure.

[0041] In some embodiments, such as Figures 1 to 3 In any of the structures shown, the active group AA includes a connection portion A1 and an active pillar A2 made of either single-crystal silicon or a metal oxide semiconductor material.

[0042] In some embodiments, Figure 1 and Figure 2 In the structure shown, the material of the active group AA can be single-crystal silicon. Figure 3 In the structure shown, the material of the active group AA can include metal oxide semiconductor material.

[0043] This disclosure does not specifically limit the constituent materials of the active group AA. As an example, the active group AA can be a single-layer structure or a multi-layer structure.

[0044] In some embodiments, such as Figure 3 As shown, the materials for the active group AA include, but are not limited to, metal oxide semiconductor materials, such as indium gallium zinc oxide (IGZO). When the metal oxide material is IGZO, the transistor leakage current is relatively small (leakage current less than or equal to 10). -15 A), thus ensuring a low refresh rate for the dynamic memory.

[0045] It should be noted that the metal oxide material can also be ITO or InSnOx (Indium Tin Oxide), IWO or InWO (Indium Tungsten Oxide), or ZnO. x Zinc oxide (Zinc.Ox), Indium oxide (InOx), In₂O₃ (Indium oxide), Tin oxide (SnO₂), TiO₂ x (Tin Dioxide, Zn) x O yN z (Zinc. Nitride. Oxide, Mg) x Zn y O z (Magnesium Zinc Oxide), In x Zn y O z (Indium Zinc Oxide), In x Ga y Zn z O a (Indium gallium zinc oxide), Zr x In y Zn z O a (Zirconium Indium Zinc Oxide), Hf x In y Zn z O a (Hafnium Indium Zinc Oxide, Sn) x In y Zn z O a (Tin.Indium.Zinc.Oxide, Al) x Sn y In z Zn a O d (Aluminum, Tin, Indium, Zinc, Oxide), Si x In y Zn z O a (Silicon Indium Zinc Oxide, Zn) x Sn y O z (Zinc.Tin.Oxide, Al) x Zn y Sn z O a (Aluminum indium tin oxide), Ga x Zn y Sn z O a(Gallium Indium Tin Oxide), Zr x Zn y Sn z O a Materials such as Zirconium Indium Tin Oxide, InGaSiO (Indium Gallium Silicon Oxide), IAZO (Indium Aluminum Zinc Oxide), IGO (Indium Gallium Oxide), IZO (Indium Zinc Oxide), and IZOx (Indium Zinc Oxide) are all acceptable, as long as the leakage current of the transistor meets the requirements. Specific adjustments can be made based on the actual situation.

[0046] Understandably, the vertical extension of the active pillars helps to increase the number of transistors that can be placed on a single surface area, thereby increasing the number of memory cells per unit area based on the transistor structure and thus improving integration density.

[0047] In some embodiments, the connecting part A1 and the active column A2 are made of the same material and are an integral structure, and are formed in the same process step.

[0048] In some embodiments, such as Figure 4 As shown, the center points O3 of the multiple connecting parts A1 are arranged in an array in the first and second directions (see reference for details). Figure 4 ); Among them, the orthographic projections of multiple active columns A2 in the vertical direction are arranged in a hexagonal close-packed pattern.

[0049] In some embodiments, the semiconductor structure further includes: The capacitor structure C is connected to the surface of the active column A2 away from the bit line BL via the landing pad LP, and the orthographic projection of the plurality of capacitor structures C in the vertical direction is arranged in a hexagonal close arrangement. Thus, setting the capacitor structure C in a hexagonal close-packed manner helps to increase the number of capacitor structures that can be set per unit area, making the arrangement of the capacitor structure C compatible with the arrangement of the active pillar A2, and working together to improve the storage density of the semiconductor structure.

[0050] It is understandable that a capacitor structure (C) and a transistor structure can form a memory cell.

[0051] In some embodiments, the capacitor structure C may include at least one of a columnar capacitor, a cylindrical capacitor, or other capacitors, without specific limitations.

[0052] In some embodiments, the first central axis O1 of the capacitor structure C coincides with the second central axis O2 of the active pillar A2.

[0053] In a conventional architecture, dynamic random access memory (DRAM) typically uses a length of 4F. 2 The DRAM architecture uses a checkerboard layout for both transistors and capacitors, resulting in relatively low storage density. However, in this embodiment, the hexagonal close arrangement of multiple active pillars A2 in the vertical direction facilitates the formation of a 6F active pillar structure. 2 The layout can also be understood as the transistor structure provided in this embodiment of the present disclosure forming a hexagonal close-packed (6F) configuration. 2 The layout of transistors can increase the number of transistors that can be placed in a single-sided area, thereby enabling greater capacity and bit density, improving integration and reducing costs.

[0054] In some embodiments, the central axis of the landing pad LP also coincides with the first central axis O1 and the second central axis O2.

[0055] This arrangement allows the capacitor structure C, the landing pad LP, and the active pillar A2 to extend vertically, maximizing the concentration of multiple structures within the memory cell. Compared to arrangements where at least one of the multiple structures is offset from other structures, the individual memory cell in this embodiment achieves minimal area occupation, enabling a larger number of memory cells to be placed per unit area, thus achieving higher integration and bit density. It can be seen that the architecture design employing a hexagonal close-packed transistor and capacitor structure effectively improves memory density and capacity.

[0056] Furthermore, in conventional structures, such as DRAM structures using buried word lines, since the transistor structure, bit lines, and word lines are all located on the same side of the substrate, achieving a 6F capacitor structure is challenging. 2 The traditional arrangement requires a bent structure for the landing pad to be compatible with the existing layout of the structure below it, which easily increases the contact resistance between the capacitor structure and the source / drain regions and poses significant manufacturing challenges. However, in this embodiment, the structural layout in the memory cell is designed so that the transistor and capacitor structure C overlap in the vertical direction, significantly improving the connection contact between the transistor and capacitor structures and reducing the manufacturing difficulty of capacitor alignment.

[0057] Furthermore, in the semiconductor structure provided in this disclosure embodiment, the bit line BL is disposed on the side away from the memory cell. Regardless of whether the memory cell is disposed in any of the above embodiments, the bit line BL can have multiple selectivity in terms of position setting, size setting and relationship with other structures, and can maintain a high degree of independence in setting. It will not be affected by the memory cell layout and there will be no situation where the relevant settings are passively changed. Flexible setting can be achieved. The following will be further explained in conjunction with the accompanying drawings.

[0058] In some embodiments, such as Figure 2 As shown, the side of the connecting portion A1 away from the word line WL includes a recessed portion Q, and the bit line BL is located in the recessed portion Q; In this case, the surface of the bit line BL on the side away from the word line WL is flush with the top of the recessed portion Q on the side away from the word line WL; or, the surface of the bit line BL on the side away from the word line WL protrudes beyond the top of the recessed portion Q on the side away from the word line WL.

[0059] Understandably, in embodiments where the bit line BL is located in the recess Q, the semiconductor structure can have a lower height, which is beneficial for reducing weight and volume. This allows electronic devices using it as memory to achieve smaller size and promote miniaturization.

[0060] In some embodiments, when the surface of the bit line BL on the side away from the word line WL protrudes from the recess Q, the horizontal dimension (width) of the bit line BL can be smaller than the horizontal dimension of a conventional bit line. This is because the presence of the recess Q reduces the vertical dimension of the semiconductor structure. The design of the bit line BL protruding from the top of the recess Q is equivalent to obtaining a larger vertical dimension without increasing the height of the semiconductor structure. This allows the horizontal dimension to be appropriately reduced while meeting usage requirements, which is beneficial for increasing the spacing between adjacent bit lines BL in the horizontal direction, reducing parasitic capacitance between them, and reducing power consumption.

[0061] In some embodiments, when the surface of the bit line BL away from the word line WL is flush with the top of the recess Q away from the word line WL, the horizontal dimension of the bit line BL can be slightly larger than that of a conventional bit line. In this embodiment, in addition to further reducing the height, weight, and volume of the semiconductor structure, since an effective spacing distance has been provided between adjacent connection portions A1, even a slight increase in the horizontal dimension of the bit line BL will not cause interference or parasitic capacitance exceeding normal levels, and will not degrade the performance of the semiconductor structure.

[0062] In any of the above embodiments, along the direction of extension of the connecting portion A1 (third direction), the size of the bit line BL is greater than the distance between the two active pillars A2 in the same active group AA in that direction and less than or equal to the size of the connecting portion A1 in that direction.

[0063] Compared to the configuration where at least a portion of the structure in the bit line BL and the active pillar A2 is located at the same level, this embodiment allows the bit line BL to be larger than the spacing between the two active pillars A2 in the same active group AA in that direction. This is beneficial for increasing the contact area between the bit line BL and the connecting portion A1 and reducing the contact resistance.

[0064] In some embodiments, the width of the bit line BL located in the middle region of the semiconductor structure (equivalent to the middle region of the surface on the substrate (which can be understood as the middle region of the plane equivalent to the substrate function in a structure without a substrate) where the device layer is disposed can be larger, while the width of the bit line BL located in the edge region (equivalent to the edge region of the surface on the substrate (which can be understood as the edge region of the plane equivalent to the substrate function in a structure without a substrate) where the device layer is disposed) can be smaller, so that the area between the bit lines BL located at the edge can also serve as a accommodating area for disposing of other structures. Furthermore, since the bit line BL is located on the side away from the memory cell, even if its setting parameters differ in different regions, its simpler structure and material composition do not increase the difficulty of etching and other processes.

[0065] In some embodiments, the two active columns A2 included in any active group AA are defined as the first active column A21 and the second active column A22, respectively. Along the direction of extension of the connecting part A1, the connecting part A1 includes a first sub-part A11, a second sub-part A12 and a third sub-part A13 connected together. In the vertical direction, the orthographic projection of the first sub-part A11 overlaps with the orthographic projection of the first active column A21, and the orthographic projection of the second sub-part A12 overlaps with the orthographic projection of the second active column A22. Along the direction of extension of the connecting part A1 (third direction), the third sub-part A13 is located between the first sub-part A11 and the second sub-part A12. The bit line BL is connected to at least one of the first sub-part A11, the second sub-part A12, and the third sub-part A13. For example, the bit line BL is connected to at least one of the first sub-part A11 and the second sub-part A12, or to at least one of the first sub-part A11 and the second sub-part A12 and the third sub-part A13, etc.

[0066] In some embodiments, such as Figure 4 As shown, along the first direction, the perpendicular bisector O4 of the line segment formed by the center points of the two adjacent connecting parts A1 is symmetrically arranged.

[0067] In some embodiments, along the first direction, adjacent bit lines are asymmetrically arranged with respect to the perpendicular bisector O4 of the line segment formed by the center points of the two adjacent connecting parts A1. For example, any bit line connected to the two connecting parts A1 may be connected to the same sub-part contained in the connecting part A1 in the first direction, or one bit line may be connected to a single sub-part, and the other bit line may be connected to two or all three sub-parts. Alternatively, one bit line may be connected to two sub-parts, and the other bit line may be connected to all three sub-parts, etc.

[0068] In some embodiments, the extension direction of bit line BL, i.e., the second direction, is perpendicular to the extension direction of word line WL, i.e., the first direction.

[0069] This disclosure also provides a method for fabricating a semiconductor structure, such as... Figure 5 As shown, the preparation method includes the following steps: Step S101: Form multiple active groups, each active group including a connecting part and two active columns extending in the vertical direction, the connecting part being located at the bottom of the two active columns and connecting the ends of the two active columns on the same side in the vertical direction; Step S102: Form a bit line extending along the second direction, the bit line being located on the side of the connector away from the active post and connected to the connector. Step S103: Forming word lines, the word lines extending along the first direction and covering a portion of the surface of the source pillar; The first direction, the second direction, and the extension direction of the connecting part intersect each other and are all parallel to the same plane, and the first direction, the second direction, and the extension direction of the connecting part are all perpendicular to the vertical direction.

[0070] First, execute steps S101 and S102, as follows: Figures 6 to 10 , Figure 16 and Figure 17 , Figures 18 to 21 as well as Figures 22 to 32 As shown, multiple active groups AA are formed. Each active group AA includes a connecting portion A1 and two active pillars A2 extending in a vertical direction. The connecting portion A1 is located at the bottom of the two active pillars A2 and connects the ends of the two active pillars A2 on the same side in the vertical direction. Before or after the formation of multiple active groups AA, a bit line BL extending in a second direction is formed. In the embodiments of this disclosure, the formation of the active group AA can include various implementations. Furthermore, the timing of the formation of the bit line BL can also include various situations. In some embodiments, such as... Figures 6 to 10 as well as Figure 16 and Figure 17 In the illustrated embodiment, the active group AA is formed first, followed by the bit line BL. In other embodiments, such as... Figures 18 to 21 as well as Figures 22 to 32In the embodiment shown, the relevant content of forming the bit line BL first and then forming the active group AA will be further explained in conjunction with the accompanying drawings.

[0071] In some embodiments, such as Figures 6 to 10 As shown, before forming the bit line BL, multiple active groups AA are formed, specifically including: Substrate 10 is provided (please refer to the appendix for details). Figure 6 ); The first etching process is performed to remove a portion of the substrate 10 to form multiple initial active groups Aa. The initial active groups Aa are arranged along the first direction and the second direction (see appendix for details). Figure 7 and Figure 8 (Figures (1) and (2) in the text). A second etching process is performed to remove a portion of each initial active group Aa to obtain the first opening H1, forming an active pillar A2. The initial active groups Aa remaining below the active pillar A2 constitute the connecting portion A1. (Please refer to the appendix for details.) Figure 9 and Figure 10 (Figures (1) and (2) in the text).

[0072] Here, substrate 10 can be a single-crystal silicon substrate.

[0073] In this embodiment of the disclosure, the vertical direction is the direction perpendicular to the plane of the substrate 10, and the first direction, the second direction, and the third direction can be directions parallel to the plane of the substrate 10 and intersect each other.

[0074] Here, the substrate 10 is etched in two steps, that is, the initial active group Aa is formed first and then the active group AA is formed. This is beneficial to obtaining an integrated active group AA, which is beneficial to the current having a good flow path when flowing through the structure.

[0075] In some embodiments, after obtaining the initial active group Aa, the active group AA can be formed by first forming a mask layer (not shown in the figure) that exposes the area where the first opening H1 is located, and then etching it. In this embodiment of the present disclosure, the ends of the two active pillars A2 in the same active group AA adjacent to the bit line BL are connected by a connecting part A1. Compared with the setting of not setting a connecting part A1, but directly connecting the ends of the bit line BL and the active pillar BL, the former is beneficial to realize the sharing of bit line BL and reduce the number of bit lines BL.

[0076] In some embodiments, the orthographic projection of the active column A2 in the vertical direction is a hexagonal close-packed arrangement.

[0077] Understandably, a transistor structure can be obtained based on the active pillar A2. The hexagonal close-packed arrangement of the orthographic projection of the active pillar A2 in the vertical direction is beneficial for forming a 6F structure. 2The layout can also be understood as the transistor structure obtained in this embodiment of the present disclosure forming a hexagonal close-packed (6F) configuration. 2 The layout of transistors can increase the number of transistors that can be placed in a single-sided area, thereby enabling greater capacity and bit density, improving integration and reducing costs.

[0078] In some embodiments, such as Figure 15 , Figure 16 as well as Figure 17 As shown, forming the bit line BL includes: A thinning process is performed on the side of substrate 10 away from the active group AA to expose the surface of the connection portion A1 away from the active pillar A2 (see details). Figure 15 ); A bit line BL is formed extending along the second direction, and the bit line BL is connected to the surface of the exposed connection portion A1 (see details). Figure 16 or Figure 17 ).

[0079] In some embodiments, such as Figure 17 As shown, the preparation method also includes: After performing a thinning process on the side of the substrate 10 away from the active group AA, before forming the bit line BL extending in the second direction, a portion of the connection portion A1 is removed to form a recess portion Q extending in the second direction. Forming a bit line BL extending along the second direction includes: A bit line BL is formed in the recess Q; the surface of the bit line BL on the side away from the connecting part A1 is flush with the top of the recess Q on the side away from the connecting part A1; or, the surface of the bit line BL on the side away from the connecting part A1 protrudes from the top of the recess Q on the side away from the connecting part A1.

[0080] In some embodiments, before performing a thinning process on the side of the substrate 10 away from the active group AA, the side of the substrate 10 forming the active group AA can be fused-bonded to a support structure (not shown) before performing the thinning process.

[0081] Understandably, in embodiments where the bit line BL is located in the recess Q, the semiconductor structure can have a lower height, which is beneficial for reducing weight and volume. This allows electronic devices using it as memory to achieve smaller size and promote miniaturization.

[0082] In some embodiments, when the surface of the bit line BL on the side away from the word line WL protrudes from the recess Q, the horizontal dimension (width) of the bit line BL can be smaller than the horizontal dimension of a conventional bit line. This is because the presence of the recess Q reduces the vertical dimension of the semiconductor structure. The design of the bit line BL protruding from the top of the recess Q is equivalent to obtaining a larger vertical dimension without increasing the height of the semiconductor structure. This allows the horizontal dimension to be appropriately reduced while meeting usage requirements, which is beneficial for increasing the spacing between adjacent bit lines BL in the horizontal direction, reducing parasitic capacitance between them, and reducing power consumption.

[0083] In some embodiments, when the surface of the bit line BL away from the word line WL is flush with the top of the recess Q away from the word line WL, the horizontal dimension of the bit line BL can be slightly larger than that of a conventional bit line. In this embodiment, in addition to further reducing the height, weight, and volume of the semiconductor structure, since an effective spacing distance has been provided between adjacent connection portions A1, even a slight increase in the horizontal dimension of the bit line BL will not cause interference or parasitic capacitance exceeding normal levels, and will not degrade the performance of the semiconductor structure.

[0084] In other embodiments, such as Figure 6 as well as Figures 18 to 21 As shown, where, Figure 20 and Figure 21 Detailed cross-sectional views of the semiconductor structure fabrication process provided in different embodiments of this disclosure; the fabrication method includes: after forming the bit line BL, forming a plurality of active groups AA, specifically including: A substrate 10 is provided, the substrate 10 including a first surface S1 and a second surface S2 disposed opposite to each other along the thickness direction (see details). Figure 6 ); Multiple bit lines BL extending along the second direction are formed on the second surface S2 (see details). Figure 18 ); An etching process is performed on the first surface S1 to form multiple active blocks Ab extending along the first direction (see details). Figure 19 ); An etching process is performed on the active block Ab to form multiple active pillars A2. The active block Ab retained at the bottom of two adjacent active pillars A2 and connecting the two active pillars A2 constitutes the connecting part A1. (Please refer to [reference] for details) Figure 20 or Figure 21 );

[0085] In this embodiment, the orthographic projections of the multiple active columns A2 in the vertical direction are arranged in a hexagonal close-packed pattern. The effect can be referred to in any of the foregoing embodiments, and will not be repeated here.

[0086] In some embodiments, such as Figure 19 As shown, after forming the bit line BL and before forming the active group AA, the method further includes: filling the gap between adjacent bit lines BL with a dielectric material layer Lc.

[0087] In some embodiments, when the semiconductor structure includes, Figure 21 When constructing a bit line structure, a recess Q can be formed by etching the second surface of the substrate 10 before forming the bit line and then filling it with bit line material.

[0088] In this embodiment, after forming the bit line BL and before performing an etching process on the first surface of the substrate 10, a thinning process can be performed on the first surface S1 of the substrate, or the second surface S2 of the substrate 10 can be thinned before forming the bit line BL on the second surface of the substrate 10, so that the structures included in the resulting active group AA have suitable height-direction dimensions. Furthermore, the substrate thinning operation can be performed on any of multiple surfaces, offering high flexibility.

[0089] Furthermore, compared to the previous embodiment's method of forming AA, this embodiment first forms the active block Ab, which separates the original substrate material into multiple block-shaped structures distributed along the second direction. This helps reduce the etching time and difficulty of the subsequent etching step to form the active group AA. And in Figure 19 Based on the structure shown, Figure 20 In Figure (1), the multiple active groups AA obtained have two boundaries in the third direction that are parallel to the first direction, which helps to reduce the size occupied by the active groups in the second direction. This is because... Figure 9 Compared to the structure shown, Figure 9 The maximum dimension of the active group (assuming the connector is rectangular) in the second direction is the value obtained by multiplying the length of the diagonal (the diagonal in the projected shape of the connector in the direction perpendicular to the substrate plane) by the cosine of the angle between the diagonal and the second direction. Figure 20 In Figure (1), the maximum dimension of the active group in the second direction is the value obtained by multiplying the dimension of the long side (the side of the connection portion projected in the direction perpendicular to the substrate plane along the third direction) by the cosine of the angle between the long side and the second direction. Since the active pillar extends vertically, the orthographic projection of the active group in the direction perpendicular to the substrate plane can be approximately equal to the dimension of the orthographic projection of the connection portion in that direction. Assuming that the length of the long side of the connection portion (the boundary parallel to the third direction) is constant, the length of the diagonal is much greater than the dimension of the long side. Figure 20 The active group AA contained in Figure (1) can have a smaller size in the second direction, and the two adjacent active groups AA in this direction can have a larger spacing, reducing interference and improving the electrical performance of the final semiconductor structure.

[0090] In some other embodiments, such as Figures 22 to 32 As shown, where, Figure 23 for Figure 22 A top-view schematic diagram shows that after the bit lines are formed, multiple active groups are formed, specifically including: Substrate 10 is provided (see attached for details). Figure 22 ); Multiple bit lines BL extending along the second direction are formed on the substrate 10 (see attached diagram for details). Figure 22 and Figure 23 ); After the bit line BL is formed, multiple active groups AA are formed, including: An isolation layer L3 is formed on the surface of the substrate 10, covering the bit line BL (see attached diagram for details). Figure 24 ); Partial removal of the isolation layer L3 to form multiple trench structures T1 extending along the first direction (see appendix for details). Figure 25 and Figure 26 ), An active material layer AL is formed, which at least covers the sidewalls and bottom of the trench structure T1 (see appendix for details). Figure 27 ); Removing part of the active material layer AL, the remaining active material layer AL covering the sidewall of the trench structure T1 forms multiple active pillars A2 (see appendix for details). Figure 28 , Figure 29 as well as Figure 32 ).

[0091] In some embodiments, the active material layer AL further covers the surface of the isolation layer L3, and removing a portion of the active material layer AL includes: A portion of the active material layer AL is removed to form multiple openings H in a direction parallel to the surface of the substrate 10 and perpendicular to a third direction. The remaining active material layer AL is separated by the multiple opening structures H (see appendix for details). Figure 28 as well as Figure 29 ); The portion of the active material layer AL covering the surface of the isolation layer L3 is removed. The remaining active material layer AL located on the sidewall of the trench structure T1 forms active pillars A2. The active material layer AL retained on the substrate side of two adjacent active pillars A2 forms connecting portions A1. The two active pillars, A2, and connecting portions A1 form active group AA. The multiple active pillars A2 are arranged in a hexagonal close-packed pattern in the vertical orthographic projection. For details, please refer to the appendix. Figure 20 The setting of Figure (1) in the text, and the improvement effect that can be obtained by this structure can be referred to the relevant content in the foregoing, which will not be repeated here.

[0092] In this embodiment, the material of the active material layer AL may include a metal oxide semiconductor material, such as indium gallium zinc oxide (IGZO). However, it is not limited to this, and the material of the active material layer AL may include the metal oxide material of any of the foregoing embodiments, which will not be elaborated here.

[0093] In this embodiment, the substrate 10 may include any suitable substrate material, and no specific limitation is made herein.

[0094] In any of the above embodiments, the connecting portion A1 and the active pillar A2 are made of the same material and are an integral structure, formed in the same process step, which has the advantage of simplifying the process and can form a good current flow path in the working configuration. At the same time, the connecting portion A1 can also be used as a connection structure between the active pillar A2 and the bit line BL, thus having multiple functions.

[0095] This embodiment is similar to the arrangement of the active group AA in the previous embodiment in that it can also form a hexagonal close-packed arrangement, which can achieve the aforementioned effect, and will not be elaborated here.

[0096] In any of the above embodiments, such as Figure 4 As shown, the center points O3 of the multiple connecting parts A1 are arranged in an array in the first and second directions.

[0097] As can be seen, in this embodiment of the present disclosure, regardless of the formation order between the bit line BL and the active pillar A2, that is, regardless of the method used, the bit line BL is set on the side of the connection portion away from the active pillar A2. This allows the bit line BL to have multiple options in terms of position setting, size setting and relationship with other structures, regardless of the method used to form the active group AA. Moreover, it can maintain a high degree of independence in setting and will not be affected by the layout of the memory cells, thus avoiding the situation of passively changing related settings. Flexible setting can be achieved.

[0098] Furthermore, in this embodiment, the connection between the ends of two active pillars A2 in the same active group AA near the bit line BL via a connecting portion A1 is more advantageous than the direct connection between the bit line BL and the ends of the active pillars BL without a connecting portion A1, thus enabling the sharing of bit lines BL and reducing the number of bit lines BL. Simultaneously, sharing a single bit line BL between every two groups of transistors improves the process window for the bit line BL, reducing the process difficulty of forming the bit line BL.

[0099] Furthermore, since the bit line BL is located on the side of the connection portion A1 away from the active pillar A2, the bit line and transistors can be arranged vertically. However, if the bit line BL is positioned at the same level as the active pillar A2, they would be arranged horizontally, reducing the number of transistor structures that can be placed per unit area. Moreover, due to the minimum width requirement for the bit line to function, the spacing between adjacent active pillars cannot be arbitrarily reduced, which can easily lead to increased parasitic capacitance and significantly limit further improvements in storage density. In this embodiment, the presence of the bit line BL not only avoids occupying a unit area but also allows for a greater number of selectable positions during its placement. Furthermore, its extension direction can be adjusted without considering the arrangement of the active pillars, providing greater flexibility.

[0100] In any of the above embodiments, along the direction in which the connecting portion A1 extends, the size of the bit line BL is greater than the distance between the two active pillars A2 in the same active group AA in that direction and less than or equal to the size of the connecting portion A1 in that direction.

[0101] Understandably, compared to the configuration where at least a portion of the structure in the bit line BL and the active pillar A2 are located at the same level, this embodiment allows the bit line BL to be larger than the spacing between the two active pillars A2 in the same active group AA in that direction. This is beneficial for increasing the contact area between the bit line BL and the connecting portion A1 and reducing the contact resistance.

[0102] In some embodiments, the size of the bit lines BL located in the middle region of the semiconductor structure (also understood as substrate 10) can be larger, while the size of the bit lines BL located in the edge region can be smaller, so that the region between the bit lines BL located at the edge can also serve as a accommodating region for setting other structures. Furthermore, since the bit lines BL are located on the side away from the memory cell, even if their placement positions differ in different regions, their simpler structure and material composition do not increase the difficulty of etching and other processes.

[0103] Finally, proceed with step S103, as follows: Figures 11 to 13 , Figure 30 and Figure 31 as well as Figure 4 As shown, a word line WL is formed, which extends along a first direction and covers a portion of the surface of the active post A2; wherein, the bit line BL is located on the side of the connecting portion A1 away from the active post A2 and is connected to the connecting portion A1. The first direction, the second direction, and the extension direction of the connecting part A1 intersect each other and are all parallel to the same plane, and the first direction, the second direction, and the extension direction of the connecting part A1 are all perpendicular to the vertical direction.

[0104] In some embodiments, after obtaining such Figure 10 After the structure shown, or to obtain as follows Figure 20 and Figure 21 Following the structure shown, as Figures 11 to 13 As shown, before forming the character line WL, the preparation method also includes: A gate oxide material layer Lb is formed, covering the middle and upper regions of the active pillar A2. The portion of the gate oxide material layer Lb located in the middle region of the active pillar A2 is defined as the gate oxide layer La (see appendix for details). Figure 11 ); The word line WL includes: A word line material layer WLa is formed, which covers the surface of the gate oxide layer La and fills the gaps between adjacent gate oxide layers La (see appendix for details). Figure 12 ); A portion of the word line material layer WLa is removed to form a word line WL extending along the first direction, with the word line WL surrounding the central region of the active pillar A2 (see appendix for details). Figure 13 and Figure 4 ).

[0105] In some embodiments, such as Figure 30 , Figure 31 , Figure 3 as well as Figure 4 As shown, after forming the active material layer AL and before removing the portion of the active material layer AL covering the surface of the isolation layer L3, the fabrication method further includes: A gate oxide material layer Lb is formed, covering the middle and upper regions of the active pillar A2. The portion of the gate oxide material layer Lb located in the middle region of the active pillar A2 is defined as the gate oxide layer La (see appendix for details). Figure 30 ); The word line WL is formed, including: A word line material layer WLa is formed, which covers the surface of the gate oxide layer La and fills the gaps between adjacent gate oxide layers La (see appendix for details). Figure 30 ); Part of the word line material layer WLa is removed to form a word line WL extending along the first direction. The word line WL extends along the first direction and covers the middle area of ​​the sidewalls of two active pillars A2 adjacent to each other along the third direction in the same active group AA (see appendix for details). Figure 31 ).

[0106] In some embodiments, such as Figures 1 to 4 as well as Figure 14 As shown, after forming the word line WL, the preparation method further includes: A capacitor structure C is formed on the side of the active pillar A2 away from the bit line BL. The capacitor structure C is connected to the active pillar A2. The orthographic projection of the multiple capacitor structures C in the vertical direction is arranged in a hexagonal close-packed pattern.

[0107] In some embodiments, such as Figure 14 As shown, the first central axis O1 of the capacitor structure C coincides with the second central axis O2 of the active pillar A2.

[0108] In some embodiments, such as Figure 11 and Figure 30 As shown, the preparation method further includes the following steps before forming the gate oxide material layer Lb: A first dielectric layer L1 is formed, which covers the lower region of the active pillar A2 or the portion of the active material layer AL extending in the vertical direction.

[0109] In some embodiments, the material of the first dielectric layer L1 may include, but is not limited to, oxides, nitrides, or oxynitrides, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0110] In some embodiments, such as Figure 13 as well as Figure 14 As shown, after forming the word line WL and before forming the capacitor structure C, the fabrication method further includes: A second dielectric layer L2 is formed covering the surface of the word line WL, and a landing pad LP is formed.

[0111] In some embodiments, the material of the second dielectric layer L2 may be a nitride, such as silicon nitride.

[0112] In some embodiments, the central axis of the landing pad LP also coincides with the first central axis O1 and the second central axis O2.

[0113] In the embodiments related to the preparation method, the contents of the capacitor structure C, the relative positional relationship between the landing pad LP and the active column A2, and the effect of the first central axis O1 of the capacitor structure C coinciding with the second central axis O2 of the active column A2, or the central axis of the landing pad LP coinciding with both the first central axis O1 and the second central axis O2, can be referred to the relevant contents of the structure section, and will not be repeated here.

[0114] It should be noted that the technical features described in the embodiments provided in this disclosure can be combined arbitrarily without conflict.

[0115] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor structure, characterized in that, The semiconductor structure includes: Multiple active groups, each of the active groups includes a connecting portion and two active columns extending in a vertical direction, the connecting portion being located at the bottom of the two active columns and connecting the ends of the two active columns on the same side in the vertical direction; The character line extends along the first direction and covers a portion of the surface of the active column; The bit line extends along the second direction and is located on the side of the connection portion away from the active post and is connected to the connection portion; Wherein, the first direction, the second direction, and the extension direction of the connecting part intersect each other and are all parallel to the same plane, and the first direction, the second direction, and the extension direction of the connecting part are all perpendicular to the vertical direction.

2. The semiconductor structure according to claim 1, characterized in that, The center points of the plurality of connecting portions are arranged in an array in the first direction and the second direction; Among them, the orthographic projection of the multiple active columns in the vertical direction is arranged in a hexagonal close-packed pattern.

3. The semiconductor structure according to claim 1, characterized in that, The connecting portion includes a recess on the side away from the word line, and the bit line is located in the recess; Wherein, the surface of the bit line on the side away from the character line is flush with the top of the recessed portion on the side away from the character line; or, the surface of the bit line on the side away from the character line protrudes beyond the top of the recessed portion on the side away from the character line.

4. The semiconductor structure according to any one of claims 1-3, characterized in that, Along the direction in which the connecting portion extends, the size of the bit line is greater than the distance between two active posts in the same active group in that direction, and less than or equal to the size of the connecting portion in that direction.

5. The semiconductor structure according to claim 4, characterized in that, The two active columns included in any active group are defined as the first active column and the second active column, respectively. Along the direction of extension of the connecting part, the connecting part includes a first sub-part, a second sub-part, and a third sub-part connected together. Along the vertical direction, the orthographic projection of the first sub-part overlaps with the orthographic projection of the first active column, and the orthographic projection of the second sub-part overlaps with the orthographic projection of the second active column. Along the direction of extension of the connecting part, the third sub-part is located between the first sub-part and the second sub-part. The bit line is connected to at least one of the first sub-part, the second sub-part, and the third sub-part.

6. The semiconductor structure according to claim 5, characterized in that, The active pillar includes monocrystalline silicon or metal oxide semiconductor material.

7. The semiconductor structure according to claim 6, characterized in that, The semiconductor structure also includes: A capacitor structure is connected to the surface of the active post on the side away from the bit line; the orthographic projection of the plurality of capacitor structures in the vertical direction is arranged in a hexagonal close-packed pattern.

8. A method for fabricating a semiconductor structure, characterized in that, The preparation method includes: Multiple active groups are formed, and any active group includes a connecting part and two active columns extending in a vertical direction. The connecting part is located at the bottom of the two active columns and connects the ends of the two active columns on the same side in the vertical direction. A bit line is formed extending along a second direction; the bit line is located on the side of the connection portion away from the active post and is connected to the connection portion; A character line is formed, the character line extending along a first direction and covering a portion of the surface of the active pillar; Wherein, the first direction, the second direction, and the extension direction of the connecting part intersect each other and are all parallel to the same plane, and the first direction, the second direction, and the extension direction of the connecting part are all perpendicular to the vertical direction.

9. The preparation method according to claim 8, characterized in that, The orthographic projections of the multiple active columns in the vertical direction are arranged in a hexagonal close-packed pattern.

10. The preparation method according to claim 9, characterized in that, The preparation method includes: forming a plurality of active groups before forming the bit lines, specifically including: Provide substrate; A first etching process is performed to remove a portion of the substrate to form a plurality of initial active groups, the initial active groups being arranged along a first direction and a second direction; A second etching process is performed to remove a portion of each of the initial active groups, forming the active pillars.

11. The preparation method according to claim 9, characterized in that, The preparation method includes: after forming the bit line, forming a plurality of the active groups, specifically including: A substrate is provided, the substrate including a first surface and a second surface disposed opposite to each other along a thickness direction; A plurality of bit lines extending along a second direction are formed on the second surface; An etching process is performed on the first surface to form multiple active blocks extending along a first direction; An etching process is performed on the active block to form multiple active pillars.

12. The preparation method according to claim 9, characterized in that, The preparation method includes: after forming the bit line, forming a plurality of the active groups, specifically including: Provide substrate; A plurality of bit lines extending along the second direction are formed on the substrate; An isolation layer is formed covering the bit lines and the substrate surface; Part of the isolation layer is removed to form a multiple trench structure extending along the first direction. An active material layer is formed, the active material layer at least covering the sidewalls and bottom of the trench structure; Removing part of the active material layer and leaving the remaining active material layer covering the sidewalls of the trench structure constitutes a plurality of active pillars.

13. The preparation method according to claim 10, characterized in that, Forming the bit line includes: A thinning process is performed on the side of the substrate away from the active group to expose the surface of the connection portion away from the active pillar; A bit line is formed extending along the second direction, and the bit line is connected to the surface of the exposed connection portion.

14. The preparation method according to claim 13, characterized in that, The preparation method further includes: A portion of the connecting portion is removed to form a recess extending along the second direction, and the bit line is formed in the recess; the surface of the bit line on the side away from the active post is flush with the top of the recess on the side away from the active post; or, the surface of the bit line on the side away from the active post protrudes beyond the top of the recess on the side away from the active post.

15. The preparation method according to any one of claims 8-14, characterized in that, The preparation method further includes: A capacitor structure is formed on the side of the active post away from the bit line. The capacitor structure is connected to the active post, and the orthographic projection of the plurality of capacitor structures in the vertical direction is arranged in a hexagonal close-packed pattern.

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