Semiconductor device

Abstract

Semiconductor devices are disclosed, including a substrate, a plurality of bit lines, a composite spacer, and a plurality of insulating spacers. The bit lines are disposed on the substrate, and the composite spacer is disposed on two opposite sidewalls of each bit line and includes a first spacer and a second spacer disposed in sequence. The insulating spacers are disposed on the substrate and are arranged between the bit lines in a mutually spaced manner, and each insulating spacer is partially located in the composite spacer. Each insulating spacer includes a first portion disposed between the bit lines, a second portion disposed in the first spacer, and a third portion disposed in the second spacer. The second portion includes a recessed portion and the third portion includes a protruding portion, wherein an end point of the recessed portion and an end point of the protruding portion are not on the same straight line, thereby improving the structural reliability of the semiconductor devices and further improving their operational performance.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device comprising a storage node contact (SNC) and a spacer for the SNC, and a method for manufacturing the same. Background Technology

[0002] With the trend towards miniaturization in various electronic products, the design of dynamic random access memory (DRAM) cells must also meet the requirements of high integration and high density. For a DRAM cell with a recessed gate structure, because it can achieve a longer carrier channel length within the same semiconductor substrate, reducing leakage current caused by capacitor structures, it has gradually replaced DRAM cells with only planar gate structures under the current mainstream development trend. Generally, a DRAM cell with a recessed gate structure includes a transistor assembly and a charge storage device to receive voltage signals from bit lines and word lines. However, due to limitations in process technology, existing DRAM cells with recessed gate structures still have many shortcomings and require further improvement to effectively enhance the performance and reliability of related memory devices. Summary of the Invention

[0003] One objective of this invention is to provide a semiconductor device in which an insulating spacer is provided between adjacent memory plugs, partially extending into the bit line gap wall, to improve its structural reliability, thereby effectively isolating adjacent memory plugs and improving the overall operational performance of the semiconductor device.

[0004] To achieve the above objectives, one embodiment of the present invention provides a semiconductor device comprising a substrate, a plurality of bit lines, a composite spacer wall, and a plurality of insulating spacers. The plurality of bit lines are disposed on the substrate and extend along a first direction, spaced apart from each other. The composite spacer wall is disposed on two opposite sidewalls of each bit line and includes a first spacer wall and a second spacer wall disposed sequentially. The plurality of insulating spacers are disposed on the substrate and arranged sequentially between the bit lines, spaced apart from each other, along a second direction perpendicular to the first direction, and each insulating spacer is partially located within the composite spacer wall. Each insulating spacer includes a first portion disposed between the bit lines, a second portion disposed within the first spacer wall, and a third portion disposed within the second spacer wall. The second portion includes a recess located within the first spacer wall, and the third portion includes a protrusion located within the second spacer wall. The endpoints of the recess and the protrusion are not on the same straight line.

[0005] To achieve the above objectives, one embodiment of the present invention provides a semiconductor device comprising a substrate, a plurality of bit lines, a composite spacer wall, and a plurality of insulating spacers. The plurality of bit lines are disposed on the substrate and extend along a first direction, spaced apart from each other. The composite spacer wall is disposed on two opposite sidewalls of each bit line and includes a first spacer wall and a second spacer wall disposed sequentially. The plurality of insulating spacers are disposed on the substrate and arranged sequentially between the bit lines, spaced apart from each other, along a second direction perpendicular to the first direction, and each insulating spacer is partially located within the composite spacer wall. Each insulating spacer includes a first portion disposed between the bit lines, a second portion disposed within the first spacer wall, and a third portion disposed within the second spacer wall. The shortest distance between the third portions of two adjacent insulating spacers is less than the shortest distance between the ends of the second portions of two adjacent insulating spacers.

[0006] To achieve the above objectives, one embodiment of the present invention provides a semiconductor device comprising multiple bit lines, a composite spacer wall, multiple insulating spacers, and multiple contact structures. The multiple bit lines extend along a first direction and are disposed on a substrate, spaced apart from each other in a second direction perpendicular to the first direction. The composite spacer wall is disposed on two opposite sidewalls of each bit line, including a first spacer wall and a second spacer wall disposed sequentially. The insulating spacers and the contact structures are alternately disposed between the bit lines in the first direction. Each insulating spacer includes a first portion that is in physical contact with the contact structure, a second portion that is in physical contact with the first spacer wall, and a third portion that is in physical contact with the second spacer wall. Attached Figure Description

[0007] The accompanying drawings provide a more detailed understanding of embodiments of the invention and are incorporated herein by reference as a whole. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams, and for illustrative and drafting purposes, relative sizes and proportions have been adjusted. The same symbols represent corresponding or similar features in different embodiments.

[0008] Figures 1 to 2 A schematic diagram of a semiconductor device according to a first preferred embodiment of the present invention is shown; wherein:

[0009] Figure 1 This is a top view schematic diagram of the semiconductor device of the present invention; and

[0010] Figure 2 for Figure 1 An enlarged schematic diagram along rectangular frame A;

[0011] Figures 3 to 7 A schematic diagram illustrating a method for fabricating a semiconductor device according to a first preferred embodiment of the present invention is shown; wherein:

[0012] Figure 3 This is a top view of the semiconductor device of the present invention after the active region has been formed;

[0013] Figure 4 This is a top view of the semiconductor device of the present invention after word lines have been formed;

[0014] Figure 5 This is a top view of the semiconductor device of the present invention after the bit lines have been formed;

[0015] Figure 6 This is a top view of the semiconductor device of the present invention after the formation of the spacer hole; and

[0016] Figure 7 This is a top view of the semiconductor device of the present invention after the insulating spacer has been formed;

[0017] Figure 8 A top view schematic diagram of a semiconductor device according to a second preferred embodiment of the present invention is shown;

[0018] Figure 9 A top view schematic diagram of a semiconductor device in a third preferred embodiment of the present invention is shown. Detailed Implementation

[0019] To enable those skilled in the art to further understand this invention, preferred embodiments are described below, along with accompanying drawings, to explain in detail the structure and desired effects of the invention. It should be understood that the features described below can be substituted, rearranged, or combined to achieve other embodiments without departing from the spirit of the invention.

[0020] Please refer to the following: Figures 1 to 2 The illustration shown is a schematic diagram of the semiconductor device 10 in the first embodiment of the present invention, wherein, Figure 1 This is a top view schematic diagram of semiconductor device 10, and Figure 2This is a partially enlarged schematic diagram of semiconductor device 10. Semiconductor device 10 includes a substrate 100, multiple bit lines 130, composite spacers 140, and multiple insulating spacers 150. The substrate 100 includes, for example, a silicon substrate, a silicon-containing substrate (such as SiC, SiGe), an epitaxial silicon substrate, a silicon-on-insulator substrate, or a substrate made of other suitable materials, but is not limited thereto. At least one shallow trench isolation (not shown, for example, including silicon oxide) is further provided within the substrate 100 to define a plurality of active regions 102 extending in the same direction D1 within the substrate 100. In one embodiment, the active regions 102 are arranged, for example, sequentially along a first direction D2 and a second direction D3 that are mutually perpendicular, presenting as shown in the diagram. Figure 1 The array arrangement shown is an example, but not limited to it. Multiple bit lines 130 are disposed on the substrate 100 and extend along a first direction D2, spaced apart from each other, to simultaneously intersect with multiple active regions 102. Composite spacer walls 140 are disposed on two opposite sidewalls of each bit line 130 in the first direction D2, and further include a second spacer wall 144 and a first spacer wall 142 sequentially disposed on the two opposite sidewalls. In one embodiment, the first spacer wall 142 may include, for example, a nitrogen-containing silicide material such as silicon nitride or silicon carbonitride, while the second spacer wall 144 may include, for example, an insulating material etched with a different material than the first spacer wall 142, such as an oxygen-containing silicide material such as silicon oxide or silicon carbide, but is not limited thereto.

[0021] Multiple insulating spacers 150 and multiple contact structures 160 are alternately arranged on the substrate 100 along the first direction D2. Furthermore, the insulating spacers 150 are also sequentially arranged between adjacent bit lines 130 along the second direction D3, and partially located within the composite spacer wall 140. Figure 1 and Figure 2 As shown. It should be noted that each insulating spacer 150 further includes a first portion 152 disposed between adjacent contact structures 160, a second portion 154 disposed within the first gap wall 142, and a third portion 156 disposed within the second gap wall 144. The second portion 154 further includes a recess 154r located within the first gap wall 142, while the third portion 156 includes a protrusion 156p located within the second gap wall 144. The endpoint E1 of the recess 154r and the endpoint E3 of the protrusion 156p are not on the same straight line, as shown. Figure 2As shown. In this configuration, the insulating spacer 150 can have a relatively small extension range on the second portion 154 adjacent to the first portion 152, and a relatively large extension range on the third portion 156 far from the first portion 152. This allows the insulating spacer 150 to be positioned between adjacent bit lines 130 with a more stable topography, becoming a plug spacer with optimized structural reliability, and providing good insulation between adjacent contact structures 160.

[0022] Specifically, such as Figure 2 As shown, the first portion 152 of the insulating spacer 150 has, for example, a spindle-shaped structure and a centerline C1. In the first direction D2, the endpoint E1 of the recess 154r of the second portion 154 is closer to the centerline C1 of the first portion 152 than the endpoint E3 of the protrusion 156p of the third portion 156. On the other hand, on the first gap wall 142 of the composite gap wall 140, a protrusion 142p is provided relative to the second portion 154, while on the second gap wall 144 of the composite gap wall 140, a recess 144r is provided relative to the third portion 156. The endpoint E2 of the protrusion 142p is closer to the centerline C1 of the insulating spacer 150 than the endpoint E4 of the recess 144r. Thus, each insulating spacer 150 can be integrally formed as a rivet-like structure, with its second portion 154 and third portion 156 forming the rivet head of this structure, which is embedded within the composite gap wall 140, thereby achieving a stable installation. In one embodiment, the thickness T1 of the first portion 152 in the second direction D3 is, for example, about the thickness T2 of the second portion 154, or 5 to 10 times the thickness T3 of the third portion 156, but is not limited thereto.

[0023] In other words, the second portion 154 and the third portion 156 of the insulating spacer 150 have different extension lengths within the first gap wall 142 and the second gap wall 144, which have different etching selectivity ratios. Specifically, the maximum width W31 / W32 / W33 of the third portion 156 of the insulating spacer 150 is, for example, greater than the minimum width W2 of the second portion 154. Thus, the shortest distance L2 between the third portions 156 of two adjacent insulating spacers 150 can be less than the shortest distance L1 between the second portions 154 of two adjacent insulating spacers 150. Furthermore, the maximum width W33 of the third portion 156 is, for example, greater than the maximum width W1 of the first portion 152, but is not limited thereto. In other embodiments, the maximum width W32 of the third portion 156 may also be less than the maximum width W1 of the first portion 152, or the maximum width W31 of the third portion 156 may also be equal to the maximum width W1 of the first portion 152, such as... Figure 2 As shown, but not limited to.

[0024] For example Figure 1 As shown, the semiconductor device 10 also includes a plurality of word lines 110 disposed within the substrate 100, extending along a second direction D3 at intervals and located directly below the insulating spacer 150. The active regions 102, word lines 110, and bit lines 130 all have different extension directions, and the extension direction of the word lines 110 (second direction D3) is perpendicular to the extension direction of the bit lines 130 (first direction D2), while simultaneously intersecting with the plurality of active regions 102 and bit lines 130. In one embodiment, each word line 110 may include, for example, a dielectric layer (not shown), a gate dielectric layer (not shown, such as silicon oxide, silicon oxynitride, etc.), and a gate (not shown, such as polycrystalline silicon, doped amorphous silicon, etc.) sequentially stacked within the substrate 100, and a word line capping layer (not shown, such as silicon nitride, silicon carbonitride, or silicon oxynitride, etc., insulating material) covering the gate, but is not limited thereto. In this way, each word line 110 can serve as a buried word line (BWL) of the semiconductor device 10, and is isolated from the bit line 130 disposed on the substrate 100 by an insulating layer (not shown, for example, including a composite layer structure of oxide layer-nitride layer-oxide layer) disposed on the substrate 100.

[0025] Each bit line 130 is generally disposed on the insulating layer, and is electrically connected to the corresponding active region 102 by extending into the substrate 100 through an integrally formed bit line contact (BLC) 130a disposed below it. In one embodiment, each bit line 130 includes, for example, a semiconductor layer (not shown, such as containing doped polycrystalline silicon, doped amorphous silicon, etc.), a barrier layer (not shown, such as containing titanium and / or titanium nitride, tantalum and / or tantalum oxide, etc.), a metal layer (not shown, such as containing tungsten, aluminum, or copper, etc., with low resistance) and a bit line capping layer (not shown, such as containing silicon oxide, silicon nitride, or silicon oxynitride, etc., with insulating material) stacked sequentially on the substrate 100. In addition, the semiconductor device 10 also includes a plurality of contact structures 160 disposed on the substrate 100, spaced apart from each other between the bit lines 130, and arranged alternately with insulating spacers 150 in the first direction D2, such as Figure 1 As shown. Each contact structure 160 comprises, for example, a semiconductor material such as doped polycrystalline silicon or doped amorphous silicon, or a low-resistivity metal material such as aluminum, titanium, copper, or tungsten, and is electrically connected to the corresponding active region 102. Thus, the bottom of each contact structure 160 can also extend into the substrate 100 and be electrically connected to the corresponding active region 102, serving as a storage node contact (SNC) of the semiconductor device 10, and electrically connected to the storage node (SN) subsequently disposed above it.

[0026] According to the semiconductor device 10 of this embodiment, by providing insulating spacers 150 between adjacent contact structures 160 and partially extending into the composite spacer wall 140, each insulating spacer 150 simultaneously includes a first portion 152 that can physically contact the contact structure 160, a second portion 154 that can physically contact the first spacer wall 142, and a third portion 156 that can physically contact the second spacer wall 144, forming a more reinforced and stable plug spacer. Thus, the insulating spacers 150 are more securely disposed in the storage plug (i.e., contact structure 160), becoming a plug spacer with optimized structural reliability and providing good insulation. The semiconductor device 10 can then serve as a dynamic random access memory (DRAM) device, and is composed of at least one capacitor (not shown) subsequently disposed above the contact structure 160 and at least one transistor assembly (not shown) disposed within the substrate 100, forming the smallest unit of a memory cell in a DRAM array, receiving voltage information from the bit line 130 and word line 110.

[0027] To enable those skilled in the art to easily understand the semiconductor device 10 of the present invention, the manufacturing method of the semiconductor device 10 of the present invention will be further described below.

[0028] Please see Figures 3 to 7 The diagram shown is a schematic representation of a method for fabricating a semiconductor device 10 according to a preferred embodiment of the present invention.

[0029] First, such as Figure 3 As shown, a substrate 100 is provided, and shallow trench isolation 104 is formed within the substrate 100, defining a plurality of active regions 102 within the substrate 100. Specifically, the active regions 102 extend in the same direction D1, for example, spaced apart from each other, and are arranged sequentially along a first direction D2 and a second direction D3 that are perpendicular to each other. Figure 3 The array arrangement shown is not limited to this. In one embodiment, the shallow trench isolation 104 is formed, for example, by including but not limited to the following steps: first, forming at least one trench (not shown) in the substrate 100 using an etching process; then, filling the trench with at least one insulating material (such as silicon oxide) to form a shallow trench isolation 104 with a surface flush with the top surface of the substrate 100, and simultaneously defining the active region 102.

[0030] like Figure 4As shown, multiple word lines 110 extending along the second direction D3 are formed within the substrate 100. In one embodiment, the word lines 110 are fabricated in a manner including, but not limited to, the following steps: for example, first forming multiple trenches (not shown) that can simultaneously pass through multiple active regions 102 and shallow trench isolation 104; then, sequentially forming within the trenches a dielectric layer (not shown) covering the entire surface of the trench, a gate dielectric layer (not shown, such as silicon oxide, silicon oxynitride, etc.) covering the lower half of the trench surface, a gate (not shown, such as doped polysilicon, etc.) filling the lower half of the trench, and a word line capping layer (not shown, such as silicon nitride, silicon carbonitride, or silicon oxynitride, etc., insulating material) filling the upper half of the trench, but not limited thereto.

[0031] Next, an insulating layer (not shown, for example, a composite layer structure including an oxide layer-nitride layer-oxide layer) is formed on the substrate 100, covering the top surface of the substrate 100 and the word lines 110 disposed therein. Figure 5 As shown, multiple bit lines 130 extending along a first direction D2 and bit line plugs 130a below them are formed on a substrate 100. In one embodiment, the fabrication process of the bit lines 130 and bit line plugs 130a includes, but is not limited to, the following steps. First, an opening (not shown) is formed through a mask layer (not shown) that penetrates the insulating layer and partially exposes the top surface of the substrate 100. Then, a semiconductor material (not shown, such as polycrystalline silicon, doped amorphous silicon, etc.) is formed on the substrate 100 to fill the opening. Next, a barrier material layer (not shown, such as titanium and / or titanium nitride, tantalum and / or tantalum oxide, etc.), a metal material layer (not shown, such as tungsten, aluminum, or copper, etc., low-resistance metals), and a capping material layer (not shown, such as silicon nitride, silicon carbonitride, or silicon oxynitride, etc., insulating materials) are formed sequentially. Finally, the bit lines 130 and the integrally formed bit line plugs 130a below them are formed simultaneously through a patterning fabrication process. Thus, after removing the mask layer, bit lines 130 can be formed on the substrate 100, which intersect with multiple active regions 102 and word lines 110. Each bit line 130 can be electrically connected to the corresponding active region 102 by extending into the substrate 100 through an integrally formed bit line plug 130a.

[0032] Then, a composite gap wall 140 is formed on the two opposite sidewalls of each bit line 130 in the first direction D2, for example, including in detail a second gap wall 144 arranged in sequence. Figure 5 (not shown) and the first gap wall 142 ( Figure 5(Not shown). In one embodiment, the first gap wall 142 and the second gap wall 144 preferably include different etched insulating materials. For example, the first gap wall 142 may be selected to include nitrogen-containing silicon compounds such as silicon nitride and silicon carbonitride, while the second gap wall 144 may include oxygen-containing silicon compounds such as silicon oxide and silicon carbide, but is not limited thereto.

[0033] like Figure 6 As shown, a deposition and etch-back fabrication process is performed sequentially to form an insulating sacrificial layer 170 between adjacent bit lines 130, filling the remaining space between adjacent bit lines 130. In one embodiment, the insulating sacrificial layer 170 includes, for example, an insulating material with an etching selection different from that of the first spacer wall 142 and the second spacer wall 144, such as silicon oxide, silicon nitride, or silicon oxynitride, but is not limited thereto. Then, an etching process is performed through a mask layer (not shown) to form a plurality of spacer holes 172 in the insulating sacrificial layer 170, exposing the corresponding active regions 102 underneath. It should be noted that during the etching process, a portion of the first spacer wall 142 and the second spacer wall 144 is intentionally removed simultaneously by taking advantage of the difference in etching selection. Since there is also a difference in etching selection between the first spacer wall 142 and the second spacer wall 144, the area R2 of the removed second spacer wall 144 is larger than the area R1 of the removed first spacer wall 142, such as... Figure 6 As shown. Furthermore, the second gap wall 144 has recesses 144r formed adjacent to each gap hole 172, while the first gap wall 142 has protrusions 142p adjacent to each gap hole 172. The endpoint E2 of the protrusion 142p is closer to the centerline of the gap hole 172 than the endpoint E4 of the recess 144r. Figure 6 As shown. Then, the mask layer is completely removed.

[0034] like Figure 7As shown, a deposition and etch-back fabrication process is performed sequentially to form insulating spacers 150 within each spacer hole 172. Thus, multiple insulating spacers 150 are sequentially arranged along the second direction D3 between adjacent bit lines 130, partially located within the composite spacer wall 140. Specifically, each insulating spacer 150 further includes a first portion 152 disposed between adjacent bit lines 130 and directly contacting the insulating sacrificial layer 170, a second portion 154 disposed within the first spacer wall 142 and directly contacting the first spacer wall 142, and a third portion 156 disposed within the second spacer wall 144 and directly contacting the second spacer wall 144. The second portion 154 of each insulating spacer 150 forms a recess 154r corresponding to the protrusion 142p, while the third portion 156 forms a protrusion 156p corresponding to the recess 144r. Thus, the maximum width W3 of the third portion 156 is greater than the minimum width W2 of the second portion 154. Figure 7 As shown. Furthermore, the maximum width W3 of the third part 156 can be selectively greater than, equal to or less than the maximum width W1 of the first part 152, depending on the actual device requirements.

[0035] In this operation, the insulating spacer 150 can have a relatively small extension range on the second portion 154 adjacent to the first portion 152, and a relatively large extension range on the third portion 156 away from the first portion 152. This allows each insulating spacer 150 to form a rivet-like structure as a whole, with the second portion 154 and the third portion 156 together forming the head of this rivet-like structure, which is embedded within the composite spacer wall 140, thereby achieving a stable setting and providing good insulation between the subsequently formed plugs. In one embodiment, the thickness T1 of the first portion 152 in the second direction D3 is, for example, greater than the thickness T2 of the second portion 154 and the thickness T3 of the third portion 156, for example, approximately 5 to 10 times the thickness T2 of the second portion 154 or the thickness T3 of the third portion 156, but is not limited thereto.

[0036] Then, the insulating sacrificial layer 170 between the insulating spacers 150 is completely removed to form a plurality of plug holes (not shown). These plug holes are then filled with semiconductor materials such as doped polycrystalline silicon or doped amorphous silicon, or low-resistivity metal materials such as aluminum, titanium, copper, or tungsten, to form a plurality of contact structures 160. Specifically, the contact structures 160 are formed, for example, between adjacent bit lines 130, and are arranged alternately with the insulating spacers 150 in the first direction D2, such that the first portion 152 of each insulating spacer 150 directly contacts its adjacent contact structure 160. Furthermore, the bottom of the contact structure 160 also extends into the substrate 100 and is electrically connected to the corresponding active region 102 to serve as a storage plug for the semiconductor device 10, and continues to be electrically connected to the storage nodes subsequently formed on top of it.

[0037] The aforementioned operations complete the fabrication process of the semiconductor device 10 of this embodiment. According to the fabrication method of this embodiment, when forming insulating spacers 150 between adjacent contact structures 160, the etching selectivity difference between different film layers in the composite spacer wall 140 is utilized so that each insulating spacer 150 simultaneously includes a first portion 152 that can physically contact the contact structure 160, a second portion 154 that can physically contact the first spacer wall 142, and a third portion 156 that can physically contact the second spacer wall 144. In this way, the insulating spacers 150 can partially extend into the composite spacer wall 140 on the sidewall of the bit line 130, forming a more reinforced and stable plug spacing structure located between the storage plugs (i.e., contact structures 160), providing good insulation. The semiconductor device 10 formed by the manufacturing method of this embodiment can serve as a dynamic random access memory (DRAM) device. It consists of at least one capacitor (not shown) subsequently formed above the contact structure 160 and at least one transistor assembly (not shown) formed in the substrate 100, forming the smallest memory cell in the DRAM array, which receives voltage information from the bit line 130 and the word line 110.

[0038] Those skilled in the art will readily understand that, to meet actual product requirements, the semiconductor device and its fabrication method of this invention may have other forms and are not limited to those described above. The following will further describe other embodiments or variations of the semiconductor device and its fabrication method of this invention. For the sake of simplicity, the following description focuses on the differences between the embodiments, without repeating the similarities. Furthermore, identical components in the embodiments of this invention are designated with the same reference numerals to facilitate comparison between embodiments.

[0039] Please refer to Figure 8The illustration shown is a top view of the semiconductor device 20 in the second embodiment of the present invention. The structure of the semiconductor device 20 in this embodiment is largely the same as that of the semiconductor device 10 in the previous embodiment, and the similarities will not be described again here. The main difference between the semiconductor device 20 in this embodiment and the previous embodiment is that the composite spacer wall 240 further includes a third spacer wall 246, and each insulating spacer 250 further includes a fourth portion 258 located within the third spacer wall 246.

[0040] In detail, the composite spacer wall 240 further includes a third spacer wall 246, a second spacer wall 144, and a first spacer wall 142 sequentially disposed on the sidewalls of each bit line 130. The first spacer wall 142 and the third spacer wall 246 include etched with similar silicon nitride materials (e.g., silicon nitride, silicon carbonitride, etc.), while the second spacer wall 144 includes etched with oxygen-containing silicon nitride materials (e.g., silicon oxide, silicon carbide, etc.) that are different from those of the first spacer wall 142 and the third spacer wall 246, but is not limited thereto. The insulating spacer 250 disposed between adjacent position lines 130 is also partially located within the composite gap wall 240, and includes a first portion 152 disposed between the contact structures 160 and in direct contact with the contact structures 160, a second portion 154 disposed within the first gap wall 142 and in direct contact with the first gap wall 142, a third portion 256 disposed within the second gap wall 144 and in direct contact with the second gap wall 144, and a fourth portion 258 disposed within the third gap wall 246 and in direct contact with the third gap wall 246.

[0041] In this design, the maximum width W4 of the third portion 256 of the insulating spacer 250 is, for example, greater than the minimum width W2 of the second portion 154 and the minimum width W5 of the fourth portion 258. Thus, the shortest distance L2 between the third portions 256 of two adjacent insulating spacers 250 can be less than the shortest distance L1 between the second portions 154 of two adjacent insulating spacers 250, and less than the shortest distance L3 between the fourth portions 258 of two adjacent insulating spacers 250. Furthermore, the maximum width W4 of the third portion 256 is, for example, not greater than (for example, less than or equal to) the maximum width W1 of the first portion 152, while the minimum width W5 of the fourth portion 258 is, for example, not greater than (for example, less than or equal to) the minimum width W2 of the second portion 154. In this way, each insulating spacer 250 can still present an overall rivet-like structure, with its second portion 154, third portion 256, and fourth portion 258 collectively forming the rivet head of this rivet-like structure, which is embedded within the composite spacer wall 240, thereby achieving a stable installation.

[0042] The semiconductor device 20 of this embodiment also provides insulating spacers 250 between adjacent contact structures 160, which partially extend into the composite gap wall 240. Each insulating spacer 250 simultaneously includes a first portion 152, a second portion 154, a third portion 256, and a fourth portion 258 that physically contact the contact structure 160, the first gap wall 142, the second gap wall 144, and the third gap wall 246, respectively, thereby forming a more reinforced and stable plug spacing. Thus, the insulating spacers 250 of this embodiment are more securely disposed in the storage plug (i.e., contact structure 160) and effectively isolate adjacent storage plugs.

[0043] Please refer to Figure 9 The illustration shown is a top view of the semiconductor device 30 in the third embodiment of the present invention. The structure of the semiconductor device 30 in this embodiment is largely the same as that of the semiconductor device 20 in the previous embodiment, and the similarities will not be described again here. The main difference between the semiconductor device 30 in this embodiment and the previous embodiment is that the maximum width W6 of the third portion 356 of each insulating spacer 350 disposed within the second gap wall 144 is greater than the maximum width W1 of the first portion 152 disposed between the contact structures 160.

[0044] In this embodiment, the maximum width W6 of the third portion 356 of the insulating spacer 350 is also greater than the minimum width W2 of the second portion 154 and the minimum width W5 of the fourth portion 258, such that the shortest distance L2 between the third portions 356 of two adjacent insulating spacers 350 is still less than the shortest distance L1 between the second portions 154 of two adjacent insulating spacers 350 and less than the shortest distance L3 between the fourth portions 258 of two adjacent insulating spacers 350. Furthermore, the maximum width W6 of the third portion 356 is, for example, further greater than the maximum width W1 of the first portion 152, so that each insulating spacer 350 as a whole presents a rivet-like structure, and its second portion 154, third portion 356, and fourth portion 258 together form the head of this rivet-like structure, which is embedded in the composite spacer wall 240, thereby achieving a stable installation effect. Thus, the semiconductor device 30 of this embodiment also provides insulating spacers 350 between adjacent contact structures 160, which partially extend into the composite gap wall 240. Each insulating spacer 350 simultaneously includes a first portion 152, a second portion 154, a third portion 356, and a fourth portion 258 that physically contact the contact structure 160, the first gap wall 142, the second gap wall 144, and the third gap wall 246, thereby forming a more reinforced and stable plug spacing structure. This allows it to be more securely disposed in the storage plug (i.e., contact structure 160) and effectively isolates the adjacent storage plugs.

[0045] Overall, the semiconductor device of the present invention has an insulating spacer that extends partially into the bit line gap wall between adjacent memory plugs to improve its structural reliability, thereby effectively isolating adjacent contact plugs and improving the overall operating performance of the semiconductor device.

[0046] The foregoing has outlined the features of several embodiments, enabling those skilled in the art to fully understand various aspects of the invention. Those skilled in the art should recognize that the invention provides a basis for designing or modifying other processes and structures to achieve substantially the same functionality and / or substantially the same results as the embodiments described above. Furthermore, such equivalent configurations do not depart from the spirit and scope of the invention, and various changes, substitutions, and modifications can be made without departing from that spirit and scope.

Claims

1. A semiconductor device, characterized in that, include: Substrate; Multiple bit lines are disposed on the substrate and extend along a first direction, spaced apart from each other; A composite gap wall is disposed on two opposite side walls of each of the said position lines, including a second gap wall and a first gap wall disposed in sequence; as well as A plurality of insulating spacers are disposed on the substrate and sequentially arranged between the bit lines along a second direction perpendicular to the first direction, with each insulating spacer partially located within the composite gap wall, wherein each insulating spacer comprises: The first part is disposed between the bit lines; The second part is disposed within the first gap wall, and the second part includes a recess located within the first gap wall; and The third part is disposed within the second gap wall, and the third part includes a protrusion located within the second gap wall; The endpoints of the recessed portion and the protruding portion are not on the same straight line.

2. The semiconductor device according to claim 1, characterized in that, The maximum width of the third part is greater than the minimum width of the second part 4.

3. The semiconductor device according to claim 1, characterized in that, The maximum width of the third part is less than the maximum width of the first part.

4. The semiconductor device according to claim 1, characterized in that, The maximum width of the third part is greater than the maximum width of the first part.

5. The semiconductor device according to claim 1, characterized in that, The endpoint of the recess is closer to the centerline of the first portion in the first direction than the endpoint of the protrusion.

6. The semiconductor device according to claim 2, characterized in that, The composite spacer wall also includes a third spacer wall, and each of the insulating spacers also includes a fourth portion located within the third spacer wall.

7. The semiconductor device according to claim 6, characterized in that, The minimum width of the fourth part is less than the maximum width of the third part.

8. The semiconductor device according to claim 6, characterized in that, The minimum width of the fourth part is less than the minimum width of the second part.

9. The semiconductor device according to claim 6, characterized in that, The materials of the first and third spacer walls include nitrogen-containing silicides, and the material of the second spacer wall includes oxygen-containing silicides.

10. The semiconductor device according to claim 1, characterized in that, The first part has a spindle-shaped structure.

11. The semiconductor device according to claim 1, characterized in that, The thickness of the first portion in the second direction is 5 to 10 times the thickness of the second portion or the thickness of the third portion.

12. The semiconductor device according to claim 1, characterized in that, Also includes: Multiple word lines are disposed within the substrate, extending along the second direction and spaced apart from each other, located below the insulating spacer; as well as Multiple contact structures are disposed on the substrate and spaced apart between the bit lines, the contact structures and the insulating spacers being arranged alternately in the first direction.

13. A semiconductor device, characterized in that, include: Substrate; Multiple bit lines are disposed on the substrate and extend along a first direction, spaced apart from each other; A composite gap wall is disposed on two opposite side walls of each of the said position lines, including a second gap wall and a first gap wall disposed in sequence; as well as Multiple insulating spacers are disposed on the substrate and are arranged sequentially between the bit lines along a second direction perpendicular to the first direction, and are partially disposed in the composite gap wall. Each insulating spacer includes a first portion disposed between the bit lines, a second portion disposed in the first gap wall, and a third portion disposed in the second gap wall. The shortest distance between the third portions of two adjacent insulating spacers is less than the shortest distance between the second portions of two adjacent insulating spacers.

14. The semiconductor device according to claim 13, characterized in that, The first gap wall has a protrusion, and the second gap wall has a recess, wherein the end point of the protrusion is closer to the centerline of the insulating spacer than the end point of the recess.

15. The semiconductor device according to claim 13, characterized in that, The maximum width of the third part is less than the maximum width of the first part.

16. The semiconductor device according to claim 13, characterized in that, The maximum width of the third part is equal to the maximum width of the first part.

17. The semiconductor device according to claim 13, characterized in that, The maximum width of the third part is greater than the maximum width of the first part.

18. The semiconductor device according to any one of claims 14 to 17, characterized in that, The composite spacer wall also includes a third spacer wall, and each of the insulating spacers also includes a fourth portion located within the third spacer wall.

19. The semiconductor device according to claim 18, characterized in that, The minimum width of the fourth part is less than the minimum width of the second part.

20. The semiconductor device according to claim 18, characterized in that, The minimum width of the fourth part is less than the maximum width of the third part.

21. A semiconductor device, characterized in that, include: Multiple bit lines extend along a first direction and are disposed on a substrate in a second direction perpendicular to the first direction, which are spaced apart from each other. A composite gap wall is disposed on two opposite side walls of each of the said position lines, including a second gap wall and a first gap wall disposed in sequence; as well as Multiple insulating spacers and multiple contact structures are alternately disposed between the bit lines in the first direction, wherein each of the insulating spacers comprises: The first part is in physical contact with the contact structure. The second part is in physical contact with the first spacer wall; and The third part is in physical contact with the second spacer wall.

22. The semiconductor device according to claim 21, characterized in that, The maximum width of the third part is greater than the minimum width of the second part.

23. The semiconductor device according to claim 21, characterized in that, The maximum width of the third part is less than the maximum width of the first part.

24. The semiconductor device according to claim 21, characterized in that, The maximum width of the third part is greater than the maximum width of the first part.

25. The semiconductor device according to claim 21, characterized in that, The endpoint of the second part is closer to the centerline of the first part in the first direction than the endpoint of the third part.

26. The semiconductor device according to claim 22, characterized in that, The composite spacer wall also includes a third spacer wall, and each of the insulating spacers also includes a fourth portion located within the third spacer wall.

27. The semiconductor device according to claim 26, characterized in that, The minimum width of the fourth part is less than the maximum width of the third part.

28. The semiconductor device according to claim 26, characterized in that, The minimum width of the fourth part is less than the minimum width of the second part.

29. The semiconductor device according to claim 26, characterized in that, The materials of the first and third spacer walls include nitrogen-containing silicides, and the material of the second spacer wall includes oxygen-containing silicides.

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