Method of manufacturing embedded flash memory devices
Patent Information
- Application Number
- CN202610975402.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-01
- Publication Date
- 2026-11-03
AI Technical Summary
In the semiconductor embedded flash memory manufacturing process, during the etching of contact holes between the storage area and the peripheral logic area, uneven etching can easily occur due to the difference in step height, which can lead to open circuits in the contact holes and affect product yield and reliability.
By adjusting the mask pattern in the photolithography process, a second polysilicon layer is simultaneously formed in the opening of the gate oxide layer as a padding layer while the first polysilicon layer is formed in the storage area using the same deposition and etching process, thereby reducing the step height difference.
It effectively alleviates the contact hole etching shrinkage phenomenon, reduces the risk of contact hole open circuit failure, improves device yield and reliability, and maintains process compatibility and cost-effectiveness.
Smart Images
Figure CN123035677A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor devices and integrated circuit technology, and in particular to a method for manufacturing an embedded flash memory device. Background Technology
[0002] Embedded flash memory (eFlash), as a type of non-volatile memory (NVM), is widely used in integrated circuits such as microcontrollers and system-on-a-chip (SoC) to store firmware, code, or configuration data.
[0003] In semiconductor embedded flash memory manufacturing processes, to meet the flatness requirements of High-k Metal Gate (HKMG) Chemical Mechanical Planarization (CMP), the memory cell area (Cell area) generally needs to be recessed relative to the surrounding logic area. However, this recessed design can cause significant structural height differences in subsequent contact etching (CT ET) processes. Taking fourth-generation embedded super flash memory (ESF4) as an example, its memory cells typically employ a split-gate (SG) structure, which includes a first gate structure consisting of a floating gate and an erase gate, as well as a select gate. In the relevant manufacturing process, after forming the first gate structure, a select gate oxide layer and a select gate polysilicon layer are deposited sequentially, and then the select gate polysilicon in the bit line region is completely removed by photolithography and etching. Due to the sinking and superposition of the Cell region, a step height difference of approximately 1000 Å will be formed between the Contact Etch Stop Layer (CESL) above the Bit Line (BL) region at the bottom of the Cell region and the Contact Etch Stop Layer above the Metal Gate (MG) region in the peripheral logic region.
[0004] This significant height difference creates a noticeable "step" in the CESL between the BL and MG regions. During subsequent contact hole etching, the etched holes are prone to "closing" at this step, resulting in uneven etching or opening contraction due to abrupt morphological changes. Furthermore, with the continuous miniaturization of devices, the critical dimension (CD) of contact holes has shrunk to 60 nm or even smaller. Excessive etching depth can easily lead to the contact holes failing to penetrate the target conductive interconnect layer effectively, resulting in open contact holes and electrical connection failure. This issue not only poses a severe challenge to optical proximity correction (OPC) simulation and contact hole etching processes but also seriously restricts product yield and reliability. Summary of the Invention
[0005] This application provides a method for manufacturing an embedded flash memory device. This method helps to reduce the step height difference between the bit line region of the storage area and the metal gate region of the peripheral logic area, and the contact hole etching stop layer above them. This effectively alleviates the "closing" phenomenon at the step during subsequent contact hole etching, reduces the risk of open circuit failure of the contact hole, and improves the device yield and reliability.
[0006] In view of this, this application provides a method for manufacturing an embedded flash memory device, comprising:
[0007] S1, a semiconductor substrate is provided, the substrate including a memory region and a logic region, the substrate surface of the memory region is lower than the substrate surface of the logic region, a first gate structure is formed on the memory region, and a first gate oxide film covering the substrate surface is formed in the memory region;
[0008] S2, photolithography is performed using a mask to form a photoresist pattern on the first gate oxide film and the first gate structure, so that the first gate oxide film in the target bit line region is exposed.
[0009] S3, etch away the first gate oxide film in the target bit line region to form a first gate oxide layer with an opening in the storage region;
[0010] S4, a polysilicon thin film is formed in the storage region, the polysilicon thin film covering the surface of the first gate oxide layer and the substrate surface exposed by the opening, and the top of the first gate structure is exposed;
[0011] S5, etch away part of the polysilicon thin film of the storage area, form a first polysilicon layer on the non-opening portion of the first gate oxide layer, and simultaneously form a second polysilicon layer in the opening.
[0012] Optionally, the first polysilicon layer is formed on the outer sidewall of the first gate structure to serve as the select gate of the memory region.
[0013] Optionally, the first gate structure includes a first floating gate, a second floating gate, a floating gate oxide layer located between each floating gate and the substrate, and an erase gate located between the first floating gate and the second floating gate.
[0014] Optionally, the first gate structure includes a first floating gate, a second floating gate, a floating gate oxide layer located between each floating gate and the substrate, a control gate located above the first floating gate and the second floating gate respectively, and an erase gate located between the first floating gate and the second floating gate.
[0015] Optionally, the first gate structure further includes a dielectric isolation structure that covers the exposed surfaces of each gate in the first gate structure.
[0016] Optionally, the first gate oxide film is a silicon oxide film.
[0017] Optionally, step S4 includes: depositing a polysilicon thin film in the storage region, the polysilicon thin film covering the surface of the gate oxide layer, the substrate surface exposed by the opening, and the first gate structure; and removing a portion of the polysilicon thin film by chemical mechanical planarization until the top of the first gate structure is exposed.
[0018] Optionally, after performing step S5, the method further includes the step of forming a metal gate structure in the logic region.
[0019] Optionally, after forming the metal gate structure, the method further includes the step of forming a contact hole etch stop layer in the memory region and the logic region.
[0020] The technical solution of this application has at least the following advantages:
[0021] This application ingeniously utilizes the same deposition and etching process for forming the first polysilicon layer. With only appropriate adjustments to the mask pattern and an additional photolithography step, a second polysilicon layer can be simultaneously formed within the opening of the gate oxide layer, serving as a padding layer for the bit line region of the memory area. This significantly reduces the step height difference between the bit line region and the surrounding logic gate region, as well as the contact hole etching stop layer above them. This effectively alleviates the "closing" phenomenon at the step during subsequent contact hole etching, reduces the risk of open-circuit failure, and improves device yield and reliability. Furthermore, this application boasts high process compatibility and has minimal impact on manufacturing costs and process complexity. Attached Figure Description
[0022] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0023] Figure 1 This is a process flow diagram of a method for manufacturing an embedded flash memory device provided in an exemplary embodiment of this application;
[0024] Figure 2 This is a schematic cross-sectional view of a semiconductor substrate provided in a method for manufacturing an embedded flash memory device according to an exemplary embodiment of this application;
[0025] Figure 3 This is a schematic cross-sectional view of the storage region after forming a first gate oxide film in a manufacturing method of an embedded flash memory device provided in an exemplary embodiment of this application;
[0026] Figure 4 This is a cross-sectional schematic diagram of the storage area after forming a photoresist pattern in a manufacturing method of an embedded flash memory device provided in an exemplary embodiment of this application;
[0027] Figure 5 This is a schematic cross-sectional view of the storage region after the formation of the first gate oxide layer in a manufacturing method of an embedded flash memory device provided in an exemplary embodiment of this application;
[0028] Figure 6 This is a schematic cross-sectional view of the storage region after forming a polycrystalline silicon thin film in a manufacturing method of an embedded flash memory device provided in an exemplary embodiment of this application;
[0029] Figure 7 This is a schematic cross-sectional view of the storage region after forming the first polysilicon layer and the second polysilicon layer in a manufacturing method of an embedded flash memory device provided in an exemplary embodiment of this application;
[0030] Figure 8 This is a schematic cross-sectional view of the embedded flash memory device manufacturing method provided in an exemplary embodiment of this application after forming a metal gate structure;
[0031] Figure 9 This is a cross-sectional schematic diagram showing the step height difference formed in the fourth-generation embedded super flash memory (ESF4) manufacturing process provided by related technologies;
[0032] Figure label:
[0033] 11. Storage area; 12. Logical area;
[0034] 20. First gate structure; 21. First floating gate; 22. Second floating gate; 23. Erase gate; 24. Dielectric isolation structure;
[0035] 30. First gate oxide film; 31. First gate oxide layer; 32. Opening;
[0036] 40. Photoresist pattern;
[0037] 50. Polycrystalline silicon thin film; 51. Select gate; 52. Second polycrystalline silicon layer;
[0038] 60. Metal gate structure Detailed Implementation
[0039] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0040] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0041] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0042] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0043] The following is combined Figures 1 to 8 This describes an embodiment of the present application.
[0044] refer to Figure 1The illustration shows an embodiment of this application, providing a method for manufacturing an embedded flash memory device, comprising:
[0045] S1, a semiconductor substrate is provided, the substrate includes a storage region 11 and a logic region, the substrate surface of the storage region 11 is lower than the substrate surface of the logic region 12, a first gate structure 20 is formed on the storage region 11, and a first gate oxide thin film 30 covering the substrate surface is formed on the storage region 11.
[0046] It should be noted that the first gate structure 20 is a gate stack combination structure formed on the memory region 11 before the formation of the first polysilicon layer of this application. Depending on the flash memory architecture, the first gate structure 20 may include different structures.
[0047] In some embodiments, the first gate structure 20 includes a first floating gate 21, a second floating gate 22, a floating gate oxide layer located between each floating gate and the substrate, and an erase gate 23 located between the first floating gate 21 and the second floating gate 22.
[0048] In some embodiments, the first gate structure 20 further includes a dielectric isolation structure 25, which covers the exposed surfaces of each gate in the first gate structure 20. It should be noted that the exposed surface of each gate refers to the outer surface of each gate that was not covered by other material layers before the dielectric isolation structure 25 was formed.
[0049] For example, see the fourth-generation embedded super flash memory (ESF4). Figure 2 The first gate structure 20 includes a first floating gate 21, a second floating gate 22, an erase gate 23 located between the first floating gate 21 and the second floating gate 22, and a dielectric isolation structure 24 covering the exposed surfaces of each floating gate and the erase gate 23. The dielectric isolation structure 24 includes: a first cap layer formed on top of each floating gate for protecting the top of the floating gate during subsequent etching and implantation processes; a first sidewall formed between the inner sidewall of the floating gate facing the erase gate 23 and the erase gate 23 for serving as a dielectric layer for erase tunneling; a second sidewall formed on the outer sidewall of the floating gate away from the erase gate 23 for isolating it from a subsequently formed first polysilicon layer serving as a select gate; and a protective layer formed on top of the erase gate 23. It should be noted that... Figure 2 In this structure, the first cap layer, the first sidewall, the second sidewall, and the protective layer appear as a continuous, integrated structure due to the use of the same or similar insulating materials. However, those skilled in the art should understand that even if they appear to be continuous, this does not affect the fact that they can be distinguished as different structural regions based on different forming processes, spatial locations, and device functions.
[0050] In some embodiments, the first gate structure 20 includes a first floating gate 21, a second floating gate 22, a floating gate oxide layer located between each floating gate and the substrate, a control gate located above the first floating gate 21 and the second floating gate 22 respectively, and an erase gate 23 located between the first floating gate 21 and the second floating gate 22.
[0051] For example, taking a third-generation embedded super flash memory (ESF3) as an example, the first gate structure 20 includes a first floating gate 21, a second floating gate 22, a control gate located above the first floating gate 21 and the second floating gate 22 respectively, an erase gate 23 located between the first floating gate 21 and the second floating gate 22, and a dielectric isolation structure 24 covering the exposed surfaces of each floating gate, the control gate and the erase gate 23. The dielectric isolation structure 24 includes: an inter-gate dielectric layer formed between each floating gate and the control gate above it; a second cap layer formed on top of each control gate; a third sidewall formed between the inner sidewall of the stacked structure composed of the floating gate, the inter-gate dielectric layer and the control gate and the erase gate 23; a fourth sidewall formed on the outer sidewall of the stacked structure composed of the floating gate, the inter-gate dielectric layer and the control gate; and a protective layer formed on top of the erase gate 23.
[0052] S2, a photolithography is performed using a mask to form a photoresist pattern 40 on the first gate oxide film 30 and the first gate structure 20, thereby exposing the first gate oxide film 30 in the target bit line region.
[0053] For example, the first gate oxide film 30 is a silicon oxide film.
[0054] It should be noted that the target bit line region is the region where bit line contacts need to be formed subsequently, and its location corresponds to the substrate surface above the drain doped region in the memory region 11.
[0055] S3, etch away the first gate oxide film 30 in the target bit line region, and form a first gate oxide layer 31 with an opening 32 in the storage region 11.
[0056] For example, the first gate oxide film 30 of the target bit line region can be removed by dry etching or wet etching, thereby forming a first gate oxide layer 31 with an opening 32 in the storage region 11. The opening 32 exposes the substrate surface of the target bit line region, and the non-opening portion of the first gate oxide layer 31 is composed of the retained first gate oxide film 30.
[0057] S4, a polysilicon thin film 50 is formed in the storage region 11. The polysilicon thin film 50 covers the surface of the first gate oxide layer 31 and the substrate surface exposed by the opening 32, and the top of the first gate structure 20 is exposed.
[0058] In some embodiments, step S4 includes: depositing a polysilicon thin film 50 in the storage region 11, the polysilicon thin film 50 covering the surface of the gate oxide layer, the substrate surface exposed by the opening 32, and the first gate structure 20; and removing a portion of the polysilicon thin film 50 by chemical mechanical planarization until the top of the first gate structure 20 is exposed.
[0059] For example, chemical vapor deposition (CVD), such as low-pressure chemical vapor deposition (LPCVD), can be used to deposit a polycrystalline silicon thin film 50 in the storage region 11.
[0060] S5, etch away part of the polysilicon thin film 50 in the storage region 11, form a first polysilicon layer on the non-opening 32 portion of the first gate oxide layer 31, and simultaneously form a second polysilicon layer 52 in the opening 32.
[0061] For example, photolithography and dry etching can be used to selectively remove a portion of the polysilicon thin film 50 in the storage region 11 to form a first polysilicon layer on the non-opening 32 portion of the first gate oxide layer 31, while simultaneously forming a second polysilicon layer 52 within the opening 32.
[0062] In some embodiments, see Figure 7 A first polysilicon layer is formed on the outer sidewall of the first gate structure 20 to serve as the select gate 51 of the memory region 11.
[0063] In some embodiments, after performing step S5, the step of forming a metal gate structure 60 in the logic region 12 is further included.
[0064] For example, the metal gate structure 60 can be formed using a post-gate process. Benefiting from the sinking design of the substrate surface of the memory region 11 relative to the logic region 12 in step S1, the chemical mechanical planarization step in the post-gate process can effectively compensate for the pattern density difference between the memory region 11 and the logic region 12, and obtain the required flatness.
[0065] In some embodiments, after forming the metal gate structure 60, the step of forming contact hole etch stop layers in the memory region 11 and the logic region 12 is further included. Due to the boosting effect of the second polysilicon layer 52 formed within the opening 32 in step S5, the step height difference between the contact hole etch stop layer above the bit line region of the memory region 11 and the contact hole etch stop layer above the metal gate region of the logic region 12 is significantly reduced. Exemplarily, the step height difference is reduced to 400 Å.
[0066] In semiconductor embedded flash memory manufacturing processes, to meet the flatness requirements of High-k Metal Gate (HKMG) Chemical Mechanical Planarization (CMP), the memory cell area (Cell area) generally needs to be recessed relative to the surrounding logic area. However, this recessed design can cause significant structural height differences in subsequent contact etching (CT ET) processes. For example, see the fourth-generation embedded super flash memory (ESF4). Figure 9 Its memory cells typically employ a split-gate (SG) structure, which includes a first gate structure 20 consisting of a floating gate and an erase gate 23, and a select gate 51. In the relevant manufacturing process, after forming the first gate structure 20, a select gate oxide layer and a select gate polysilicon layer are deposited sequentially, and then the select gate polysilicon in the bit line region is completely removed by photolithography and etching. Due to the sinking and stacking effect of the Cell region 11, a step height difference of approximately 1000 angstroms (Å) is formed between the contact etch stop layer (CESL) above the bit line (BL) region at the bottom of the Cell region and the contact etch stop layer above the metal gate (MG) region in the peripheral logic region 12. This significant height difference creates a noticeable "step" in the CESL between the BL and MG regions. During subsequent contact hole etching, the etched holes are prone to "closing" at this step, resulting in uneven etching or opening contraction due to abrupt morphological changes. Furthermore, with the continuous miniaturization of devices, the critical dimension (CD) of contact holes has shrunk to 60 nm or even smaller. Excessive etching depth can easily lead to the contact holes failing to penetrate the target conductive interconnect layer effectively, resulting in open contact holes and electrical connection failure. This issue not only poses a severe challenge to optical proximity correction (OPC) simulation and contact hole etching processes but also seriously restricts product yield and reliability.
[0067] This application ingeniously utilizes the same deposition and etching process for forming the first polysilicon layer. With only appropriate adjustments to the mask pattern and an additional photolithography step, a second polysilicon layer 52 can be simultaneously formed within the opening 32 of the gate oxide layer, serving as a padding layer for the 11-bit line region of the memory area. This significantly reduces the step height difference between the bit line region and the surrounding logic area 12 metal gate region, effectively mitigating the "closing" phenomenon at the step during subsequent contact hole etching, reducing the risk of open-circuit failure, and improving device yield and reliability. Furthermore, this application exhibits high process compatibility and has minimal impact on manufacturing costs and process complexity.
[0068] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A method for manufacturing an embedded flash memory device, comprising: S1, a semiconductor substrate is provided, the substrate including a memory region and a logic region, the substrate surface of the memory region is lower than the substrate surface of the logic region, a first gate structure is formed on the memory region, and a first gate oxide film covering the substrate surface is formed in the memory region; S2, photolithography is performed using a mask to form a photoresist pattern on the first gate oxide film and the first gate structure, so that the first gate oxide film in the target bit line region is exposed. S3, etch away the first gate oxide film in the target bit line region to form a first gate oxide layer with an opening in the storage region; S4, a polysilicon thin film is formed in the storage region, the polysilicon thin film covering the surface of the first gate oxide layer and the substrate surface exposed by the opening, and the top of the first gate structure is exposed; S5, etch away part of the polysilicon thin film of the storage area, form a first polysilicon layer on the non-opening portion of the first gate oxide layer, and simultaneously form a second polysilicon layer in the opening.
2. The method according to claim 1, characterized in that, The first polysilicon layer is formed on the outer wall of the first gate structure to serve as the select gate of the memory region.
3. The method according to claim 1, characterized in that, The first gate structure includes a first floating gate, a second floating gate, a floating gate oxide layer located between each floating gate and the substrate, and an erase gate located between the first floating gate and the second floating gate.
4. The method according to claim 1, characterized in that, The first gate structure includes a first floating gate, a second floating gate, a floating gate oxide layer located between each floating gate and the substrate, a control gate located above the first floating gate and the second floating gate respectively, and an erase gate located between the first floating gate and the second floating gate.
5. The method according to claim 3 or 4, characterized in that, The first gate structure further includes a dielectric isolation structure that covers the exposed surfaces of each gate in the first gate structure.
6. The method according to claim 1, characterized in that, The first gate oxide film is a silicon oxide film.
7. The method according to claim 1, characterized in that, Step S4 includes: depositing a polysilicon thin film in the storage region, the polysilicon thin film covering the surface of the gate oxide layer, the substrate surface exposed by the opening, and the first gate structure; and removing a portion of the polysilicon thin film by chemical mechanical planarization until the top of the first gate structure is exposed.
8. The method according to claim 1, characterized in that, After performing step S5, the process also includes the step of forming a metal gate structure in the logic region.
9. The method according to claim 8, characterized in that, After forming the metal gate structure, the process also includes forming a contact hole etch stop layer in the memory region and logic region.