Semiconductor device with double-layer bit line

Abstract

A semiconductor device includes a substrate including a first region having a second region and a third region; a peripheral circuit pattern on the substrate; a gate electrode structure on each of the second region of the substrate; a memory channel structure each extending through the gate electrode structure; a first bit line and a second bit line on the gate electrode structure; a third bit line on the first bit line; and a through-connection on the third region of the substrate. A third primary region of the third region is closer to a first edge of the first region in a first direction than a third secondary region of the third region. The first bit line is electrically connected to the peripheral circuit pattern through a first through-connection, and the second bit line is electrically connected to the peripheral circuit pattern through a second through-connection.

Description

Cross-reference of related applications

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2025-0058542, filed with the Korean Intellectual Property Office (KIPO) on May 2, 2025, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The exemplary embodiments of the present invention relate to a semiconductor device. More specifically, the exemplary embodiments of the present invention relate to a vertical memory device. Background Technology

[0003] In electronic systems that include data storage units, semiconductor devices capable of storing large amounts of data are desired. Therefore, solutions to increase the data storage capacity of semiconductor devices are being researched. For example, as a method for increasing the data storage capacity of semiconductor devices, a semiconductor device comprising memory cells arranged in three dimensions instead of two dimensions has been proposed.

[0004] In semiconductor devices, there is a desired process for efficiently forming contact plugs for sending electrical signals to memory cells. Summary of the Invention

[0005] An exemplary embodiment of the present invention provides a semiconductor device with enhanced electrical characteristics.

[0006] According to an exemplary embodiment of the present invention, a semiconductor device is provided. The semiconductor device may include: a substrate including a first region having second and third regions alternately and repeatedly arranged in a first direction; a peripheral circuit pattern on the substrate; a gate electrode structure on each of the second regions of the substrate; a memory channel structure extending through the gate electrode structure; a first bit line and a second bit line on the gate electrode structure in the first region of the substrate, each of the first bit line and the second bit line extending in a first direction and spaced apart from each other in a second direction intersecting the first direction; a third bit line extending on the first bit line in the first direction; and a through-hole on the third region of the substrate. The third region may include a third main region and a third secondary region. The third main region may be closer to a first edge of the first region in the first direction than the third secondary region. The first bit line may be electrically connected to the peripheral circuit pattern via a first through-hole disposed on the third main region, and the second bit line may be electrically connected to the peripheral circuit pattern via a second through-hole disposed on the third secondary region of the substrate.

[0007] According to an exemplary embodiment of the present invention, a semiconductor device is provided. The semiconductor device may include: a peripheral circuit pattern on a substrate including a first region; a bonding pattern structure on the peripheral circuit pattern; a first bit structure on the bonding pattern structure, the first bit structure including a first bit line extending in a first direction parallel to an upper surface of the substrate and a second bit line contacting the upper surface of the first bit line, the second bit line extending in the first direction on the upper surface of the first bit line; a third bit line extending in the first direction, the third bit line being spaced apart from the second bit line in a second direction parallel to the upper surface of the substrate and intersecting the first direction; gate electrode structures on the first bit structure and the third bit line; and a memory channel structure extending through the gate electrode structure on the first region of the substrate. The bonding pattern structure may include a first bonding pattern structure closer to a first edge of the first region in the first direction than a second bonding pattern structure. The first bit structure can be electrically connected to the peripheral circuit pattern via the first bonding pattern structure, and the third bit line can be electrically connected to the peripheral circuit pattern via the second bonding pattern structure.

[0008] According to an exemplary embodiment of the present invention, a semiconductor device is provided. The semiconductor device may include: a substrate including a first region having a second region and a third region alternately and repeatedly arranged in a first direction; a peripheral circuit pattern on the substrate; and a first bonding pattern structure, a first unit structure, a second bonding pattern structure, and a second unit structure sequentially stacked in a vertical direction on the peripheral circuit pattern. The first unit structure may include a first bit line group on the first bonding pattern structure, a first gate electrode structure on the first bit line group in the second region of the substrate, first memory channel structures extending through the first gate electrode structure, and through-holes in the third region of the substrate. The second unit structure may include a second bit line group on the second bonding pattern structure, a second gate electrode structure on the second bit line group in the second region of the substrate, and second memory channel structures extending through the second gate electrode structure. The second bit line group may include a first bit line structure on the second bonding pattern structure, the first bit line structure including a first bit line extending in a first direction, a second bit line extending in the first direction on the upper surface of the first bit line, and a third bit line extending in the first direction, the third bit line being spaced apart from the second bit line in a second direction parallel to the upper surface of the substrate and intersecting the first direction. The third region may include a third main region and a third secondary region. The third primary region may be closer to the first edge of the first region in the first direction than the third secondary region. The first bit line structure can be electrically connected to the peripheral circuit pattern through the first through-hole disposed on the third primary region of the substrate, and the third bit line can be electrically connected to the peripheral circuit pattern through the second through-hole disposed on the third secondary region of the substrate.

[0009] The semiconductor device according to the example embodiment can incorporate a two-layer structure in which a second layer of bit lines is additionally disposed on the bit lines connected to the page buffer via edge through-holes, thereby increasing the effective cross-sectional area and reducing resistance. Therefore, RC delay can be reduced, precharge current can propagate quickly, and thus overall memory operating speed can be improved. Attached Figure Description

[0010] Figure 1 This is a plan view of a semiconductor device according to an exemplary embodiment of the present disclosure.

[0011] Figure 2 This illustrates an example embodiment according to the present disclosure. Figure 1 A plan view of the layout of elements in region X.

[0012] Figure 3 yes Figure 2 A magnified plan view of a portion of the image.

[0013] Figure 4 The example embodiment shows the following: Figure 3 The cross-sectional view of the semiconductor device taken by lines A-A' and B-B'.

[0014] Figure 5 According to the example embodiment, along Figure 3 A cross-sectional view of a portion of a semiconductor device taken by line C-C'.

[0015] Figure 6 This is a plan view showing the layout of the elements of a semiconductor device according to an example embodiment.

[0016] Figure 7 This is a cross-sectional view of a semiconductor device according to an example embodiment.

[0017] Figure 8 This illustrates the layout of a semiconductor device according to an example embodiment.

[0018] Figure 9 This is a cross-sectional view of a semiconductor device according to an example embodiment.

[0019] Figure 10 and Figure 11 This is a cross-sectional view of a semiconductor device according to an example embodiment.

[0020] Figure 12 and Figure 13 These are layout and cross-sectional views of a semiconductor device according to an example embodiment.

[0021] Figure 14 This illustrates the layout of a semiconductor device according to an example embodiment.

[0022] Figure 15 This illustrates the layout of a semiconductor device according to an example embodiment.

[0023] Figure 16 This is a cross-sectional view of a semiconductor device according to an example embodiment.

[0024] Figure 17 This is a cross-sectional view of a semiconductor device according to an example embodiment.

[0025] Figure 18 , Figure 21 , Figure 23 , Figure 25 and Figure 27 This illustrates the manufacturing process according to an example embodiment. Figures 1 to 5 A plan view of the method for the semiconductor device, and Figure 19 , Figure 20 , Figure 22 , Figure 24 , Figure 26 , Figure 28 and Figure 29 This illustrates the manufacturing process according to an example embodiment. Figures 1 to 5 A cross-sectional view of a method for constructing a semiconductor device.

[0026] Figures 30 to 32 This illustrates the manufacturing process according to an example embodiment. Figure 12 and Figure 13 A cross-sectional view of a method for constructing a semiconductor device.

[0027] Figure 33 This is a block diagram illustrating a semiconductor device according to an example embodiment. Detailed Implementation

[0028] The above and other aspects and features of the semiconductor device and the method of manufacturing the semiconductor device according to the example embodiments will become readily apparent from the following detailed description with reference to the accompanying drawings. It will be understood that although ordinal numbers such as “first,” “second,” “third,” etc., may be used herein to describe various materials, layers, regions, pads, electrodes, patterns, structures, and / or processes, these various materials, layers, regions, pads, electrodes, patterns, structures, and / or processes should not be limited by these terms. Ordinal numbers are used only to distinguish one material, layer, region, pad, electrode, pattern, structure, or process from another. Therefore, “first,” “second,” “third,” etc., may be used selectively or interchangeably for each material, layer, region, electrode, pad, pattern, structure, or process.

[0029] The direction perpendicular to the upper surface of the substrate may be referred to as the first direction D1, and the two intersecting horizontal directions parallel to the upper surface of the substrate may be referred to as the second direction D2 and the third direction D3, respectively. In the example embodiment, the second direction D2 and the third direction D3 may be perpendicular to each other. The first direction D1 may be a vertical direction.

[0030] The first direction to the third direction D1, D2 and D3 may include not only the direction indicated by the arrows in the figures, but also the opposite direction.

[0031] As used herein, terms such as “identical,” “equal,” “planar,” “coplanar,” “parallel,” and “perpendicular” encompass identity or include near-identity, including variations that may occur, for example, due to manufacturing processes. The term “substantially” may be used herein to emphasize this meaning unless the context or other statement indicates otherwise.

[0032] Throughout this specification, when a component is described as “comprising” a particular element or group of elements, it will be understood that the component is formed solely by that element or group of elements, or that the element or group of elements may be combined with other elements to form the component, unless the context clearly and / or explicitly describes the opposite.

[0033] For ease of description, spatial relative terms such as “lower,” “below,” “down,” “above,” “top,” “bottom,” “front,” “back,” “horizontal,” and “vertical” may be used to describe, for example, the positional relationships shown in the figure. It will be understood that spatial relative terms encompass different orientations of the device other than those shown in the figure.

[0034] It will be understood that when an element is referred to as “connected” or “coupled” to or “on another element”, the element may be directly connected to or coupled to or on the other element, or there may be intermediate elements present. Conversely, when an element is referred to as “directly connected” or “directly coupled” to another element, or referred to as “in contact with another element” or “in contact with another element” (or using any form of the word “in contact”), there are no intermediate elements at the point of contact.

[0035] As used herein, components described as “electrical connections” are configured to enable electrical signals to be transmitted from one component to another (although such electrical signals may be attenuated in strength and may be selectively transmitted during transmission).

[0036] As used herein, the singular forms of “a,” “one,” and “the” are intended to include both the plural and singular forms, unless the context clearly indicates otherwise.

[0037] Figures 1 to 5 A semiconductor device according to an example embodiment is shown. Specifically, Figure 1 It's a floor plan. Figure 2 It is a planar layout (or plan view) of bit lines and some other components. Figure 3 yes Figure 2 An enlarged plan view (or floor plan) of a portion of the layout. Figure 4 Including along respectively Figure 3 The cross-sectional view taken from lines A-A' and B-B'. Figure 5 It is along Figure 3 A cross-sectional view of a portion of a semiconductor device taken by line C-C'. Figures 2 to 5 yes Figure 1 The graph of region X.

[0038] Reference Figures 1 to 5 Semiconductor devices can have a COP (cell on peripheral) structure. For example, the cell structure CS, which includes memory cells, can be disposed on the peripheral circuit structure PS.

[0039] The peripheral circuit structure PS may include a peripheral circuit pattern disposed on the first substrate 100 and a first insulating intermediate layer 150.

[0040] The unit structure CS may include a first common source plate (CSP) 200 disposed on the peripheral circuit structure PS, a gate electrode structure, a memory channel structure MC, a molded structure MS, a through member 725, a first via member 755, a first bit line structure 797 including a 1-1 bit line (which may be referred to as a bit line of the first primary bit line) and a 2-1 bit line (which may be referred to as a bit line of the second primary bit line), a 1-2 bit line (which may be referred to as a bit line of the first secondary bit line) 775-2, a third bit line structure 799 including a 1-3 bit line (which may be referred to as a bit line of the first tertiary bit line) and a 2-2 bit line (which may be referred to as a bit line of the second secondary bit line), and a first insulating intermediate layer 150, a second insulating intermediate layer 290, a third insulating intermediate layer 620, a fourth insulating intermediate layer 630, a fifth insulating intermediate layer 750, a sixth insulating intermediate layer 770 and a seventh insulating intermediate layer 790. For example, the 1-1 bit line, the 1-2 bit line, and the 1-3 bit line can be the first bit line 775 (not shown), and the 2-1 bit line and the 2-2 bit line can be the second bit line 795 (not shown).

[0041] In addition, the unit structure CS may include a sacrificial layer structure 250, a support layer 260, a support pattern 265, a channel connection pattern 580, a first insulating pattern 275, a first separation pattern 610 and a second separation pattern 660, and a second barrier pattern 590.

[0042] The first substrate 100 may include semiconductor materials (such as silicon, germanium, or silicon-germanium) or III-V compounds (such as GaP, GaAs, GaSb). In an example embodiment, the first substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0043] The first substrate 100 may include a first region I and a second region II surrounding the first region I. In an example embodiment, the first region I of the first substrate 100 may be a cell array region in which memory cells are disposed, and the second region II of the first substrate 100 may be an extension region in which contact plugs for transmitting signals to memory cells are disposed. The first region I and the second region II of the first substrate 100 may together form a cell region. Figure 1 The second region II is shown to completely surround the first region I. For example, the second region II may form a closed loop along the edge of the first region I. However, the embodiments are not limited to this. For example, in some embodiments, the second region II may be located only on one side of the first region I in the second direction D2.

[0044] A first region I of the first substrate 100 may include a third region III and a fourth region IV. The third region III may be an active memory region on which a memory channel structure MC is disposed, and the fourth region IV may be a through-hole region on which through-holes 725 are disposed for providing electrical connections between peripheral circuit patterns and bit lines disposed at different vertical horizontal positions. In an example embodiment, a plurality of third regions III and a plurality of fourth regions IV may be arranged alternately and repeatedly along a third direction D3. For example, each of the third regions III may be disposed between a corresponding pair of fourth regions IV adjacent to each other along the third direction D3.

[0045] In an example embodiment, a pair of fourth regions IV that are set adjacent to the opposite ends of the first region I on the third direction D3 (i.e., the first edge portion (or edge) E1 and the second edge portion (or edge) E2 of the first region I) may be referred to as 4-1 region (e.g., fourth main region) IV-1 and 4-3 region (e.g., fourth tertiary region) IV-3, respectively, and one of the fourth regions IV set between 4-1 region IV-1 and 4-3 region IV-3 may be referred to as 4-2 region (e.g., fourth secondary region) IV-2.

[0046] In the example embodiment, the difference between the two distances measured from region IV-2 of 4-2 to the first edge portion (or edge) E1 and the second edge portion (or edge) E2 of the first region I can be less than the difference between the two distances measured from region IV-1 of 4-1 or region IV-3 of 4-3 to the first edge portion (or edge) E1 and the second edge portion (or edge) E2 of the first region I (see reference). Figure 3 (The difference in length of the middle arrow). For example, region IV-2 of 4-2 may be located at the center of the first region I on the third direction D3, while regions IV-1 of 4-1 and IV-3 of 4-3 may be located at the side portions of the first region I on the third direction D3.

[0047] The first substrate 100 may include a field region thereon having an isolation pattern 110 and an active region 101 thereon not having an isolation pattern. The isolation pattern 110 may include, for example, an oxide, such as silicon oxide.

[0048] The peripheral circuit pattern may include a transistor TR and a wiring structure WS electrically connected to the transistor TR. The transistor TR may be disposed on the active region 101. Each component of the wiring structure WS may be formed by a patterning process or a damascene process.

[0049] A first insulating interlayer 150 may be disposed on the first substrate 100 and may cover the transistor TR and the wiring structure WS. The first insulating interlayer 150 may include, for example, an oxide, such as silicon oxide.

[0050] A first CSP 200 may be disposed on a first insulating intermediate layer 150. The first CSP 200 may include, for example, polysilicon doped with n-type impurities. Alternatively, the first CSP 200 may include sequentially stacked metal silicide layers and polysilicon layers doped with n-type impurities. The metal silicide layer may include, for example, tungsten silicide.

[0051] The sacrificial layer structure 250, the channel connection pattern 580, the support layer 260, and the support pattern 265 may be formed on the first CSP 200. For example, the support layer 260 may be formed on and in contact with the sacrificial layer structure 250 and the channel connection pattern 580.

[0052] A channel connection pattern 580 may be disposed on a third region III of the first substrate 100, and may include an air gap. A sacrificial layer structure 250 may be disposed on a second region II and a fourth region IV of the first substrate 100.

[0053] The channel connection pattern 580 may include, for example, polysilicon doped with n-type impurities or undoped polysilicon. The sacrificial layer structure 250 may include first sacrificial layers 220, 230 and 240 sequentially stacked in the first direction D1. The first sacrificial layer 220 and the third sacrificial layer 240 may include, for example, oxides, such as silicon oxide, and the second sacrificial layer 230 may include, for example, nitrides, such as silicon nitride.

[0054] Also refer to Figure 10 A support layer 260 may be disposed on the channel connection pattern 580 and the sacrificial layer structure 250. In an example embodiment, the support layer 260 may also be disposed in a first opening that extends through the channel connection pattern 580 and the sacrificial layer structure 250 and exposes the upper surface of the first CSP 200. For example, the support layer 260 may contact the upper surface of the first CSP 200 exposed by the first opening. The support layer 260 may include a support pattern 265 as part of the support layer 260 disposed in the first opening. The support pattern 265 may be disposed in various layouts in a plan view. In an example embodiment, in a plan view, the support pattern 265 may surround a third region III of the first substrate 100.

[0055] Each of the support layer 260 and the support pattern 265 may include a material that has etch selectivity relative to the first sacrificial layer 220, the second sacrificial layer 230 and the third sacrificial layer 240, such as polysilicon doped with n-type impurities.

[0056] The gate electrode structure may be disposed on the first CSP 200 and the sacrificial layer structure 250 on the second region II and the third region III of the first substrate 100. The gate electrode structure may include gate electrodes that may be disposed at multiple horizontal locations, spaced apart from each other in a first direction D1, and extending, for example, longitudinally in a second direction D2. In an example embodiment, multiple gate electrode structures may be disposed on a third direction D3 and separated from each other by a first separation pattern 610.

[0057] In an example embodiment, the gate electrode structure may include a first gate electrode 600 and a second gate electrode 650 stacked in a first direction D1. The first gate electrode 600 may be disposed at multiple horizontal locations, and the second gate electrode 650 may be disposed at one or more horizontal locations on the first gate electrode 600.

[0058] In an example embodiment, the first plurality of first gate electrodes 600 disposed at the lowest horizontal level and at a second horizontal level from the bottom of the first gate electrode 600 may be gate-sensed drain-leak (GIDL) gate electrodes. In an example embodiment, the second first gate electrode 600 disposed at a third horizontal level from the bottom of the first gate electrode 600 may be used as a ground select line (GSL). In an example embodiment, the third plurality of first gate electrodes 600 disposed at the highest horizontal level and at a second horizontal level from the top of the first gate electrode 600 may be GIDL gate electrodes. In an example embodiment, the fourth plurality of first gate electrodes 600 disposed at other horizontal levels of the first gate electrode 600 may be used as word lines. In an example embodiment, the second gate electrode 650 may be used as a string select line (SSL).

[0059] The first gate electrode 600 may include a gate conductive pattern and a gate blocking pattern that at least partially covers the surface of the gate conductive pattern. The gate conductive pattern may include, for example, a metal with low resistance, such as tungsten, titanium, tantalum, platinum, etc., and the gate blocking pattern may include, for example, a metal nitride, such as titanium nitride, tantalum nitride, etc.

[0060] In an example embodiment, the second gate electrode 650 may include, for example, polysilicon doped with n-type impurities.

[0061] In an example embodiment, a plurality of first insulating patterns 275 may be disposed / stacked along a first direction D1, and each of the first insulating patterns 275 may be disposed between the first gate electrodes 600 or between the first gate electrode 600 disposed at the lowest horizontal position and the first CSP 200. The first insulating pattern 275 may include, for example, an oxide, such as silicon oxide.

[0062] In an example embodiment, a first separation pattern 610 may be disposed between first gate electrodes 600 included in a gate electrode structure adjacent to each other along a third direction D3, and may extend on the first CSP 200 on the third region III and the second region II of the first substrate 100 to separate the first gate electrodes 600 from each other.

[0063] In an example embodiment, the first separation pattern 610 may extend through the upper portion of the second insulating intermediate layer 290, the first gate electrode 600, the first insulating pattern 275, and the first CSP 200. In an example embodiment, the first separation pattern 610 may extend in a second direction D2 (e.g., longitudinally), and a plurality of first separation patterns 610 may be spaced apart from each other in a third direction D3.

[0064] In an example embodiment, a gate electrode structure disposed on a third region III of the first substrate 100 and a memory channel structure MC extending through the gate electrode structure can together form a memory block. In an example embodiment, multiple memory blocks can be spaced apart from each other on the third region III in a third direction D3.

[0065] The second separation pattern 660 may extend along a second direction D2 (e.g., longitudinally) on the third region III of the first substrate 100 and the portion of the second region II of the first substrate 100 adjacent to the third region III, and may extend through the second gate electrode 650 and the etch stop layer 640 to contact the upper surface of the fourth insulating intermediate layer 630. In an example embodiment, for example in a plan view, the second separation pattern 660 may be disposed between a pair of first separation patterns 610 adjacent to each other along a third direction D3.

[0066] Each of the first separation pattern 610 and the second separation pattern 660 may include, for example, an oxide (such as silicon oxide) or, for example, an insulating nitride (such as silicon nitride).

[0067] The cell structure CS may include multiple memory channel structures MC that include a first memory channel structure 550 and a second memory channel structure 720.

[0068] Reference Figure 10 and Figure 20 The first memory channel structure 550 may be disposed on the third region III of the first substrate 100, may contact the upper surface of the first CSP 200, and may extend through the second insulating intermediate layer 290, the first gate electrode 600 and the first insulating pattern 275 in the corresponding memory block.

[0069] In an example embodiment, the first memory channel structure 550 may include a cylindrical first filling pattern 530 extending longitudinally in a first direction D1, a cup-shaped first channel 520 covering the sidewalls and lower surface of the first filling pattern 530, a first charge storage structure 510 on the outer sidewalls and lower surface of the first channel 520, and a first capping pattern 540 contacting the upper surfaces of the first filling pattern 530, the first channel 520, and the first charge storage structure 510.

[0070] The first charge storage structure 510 may include a first tunnel insulation pattern 500, a first charge storage pattern 490, and a first barrier pattern 480 that are sequentially stacked in a horizontal or radial direction from the outer sidewall of the first channel 520.

[0071] The second memory channel structure 720 may include a second fill pattern 700, a second channel 690, a second charge storage structure 680, and a second capping pattern 710 corresponding to the first memory channel structure 550. In an example embodiment, the second memory channel structure 720 may extend through the fourth insulating interlayer 630, the etch stop layer 640, and the second gate electrode 650, and may contact the upper surface of the first memory channel structure 550.

[0072] In an example embodiment, the second channel 690 may include a lower portion extending through and horizontally overlapping the fourth insulating intermediate layer 630 and having a first width, a middle portion extending through and horizontally overlapping the etch stop layer 640 and having a second width, and an upper portion extending through a portion of the second gate electrode 650 and horizontally overlapping that portion of the second gate electrode 650 and having a third width. Each of the first width and the third width may be greater than the second width. In an example embodiment, the upper portion of the second channel 690 may have a cup shape, and the second fill pattern 700 may fill the internal space defined or closed by the cup-shaped upper portion of the second channel 690.

[0073] The second charge storage structure 680 may extend vertically through the second gate electrode 650 and may cover / contact the upper sidewall of the second channel 690, the edge portion of the lower surface of the upper part of the second channel 690, and the sidewall of the second capping pattern 710. The lower surface of the upper part of the second channel 690 may be the downward-facing portion of the upper surface of the second channel 690. The second charge storage structure 680 may include a second tunnel insulating pattern, a second charge storage pattern, and a third blocking pattern corresponding to the first tunnel insulating pattern 500, the first charge storage pattern 490, and the first blocking pattern 480 of the first charge storage structure 510, respectively, and these second tunnel insulating patterns, second charge storage patterns, and third blocking patterns are sequentially stacked horizontally or radially from the outer sidewall of the second channel 690.

[0074] The second capping pattern 710 can contact the upper surface of the second filling pattern 700 and the upper part of the second channel 690, and also contact the inner wall of the second charge storage structure 680.

[0075] In an example embodiment, a plurality of memory channel structures MC may be spaced apart from each other along each of the second direction D2 and the third direction D3 within each memory block to form a memory channel structure array MCA. A plurality of first memory channel structures 550 included in the memory channel structure array MCA may be electrically connected to each other via corresponding channel connection patterns 580. For example, a first charge storage structure 510 may not be disposed on a portion of the outer wall of each first channel 520, and the channel connection pattern 580 may contact the outer wall of the first channel 520 to electrically connect the first channels 520 to each other.

[0076] The memory channel structure array (MCA) may include memory channel structure rows (MCRs) spaced apart from each other in the second direction D2. Each of the memory channel structure rows (MCRs) may include multiple memory channel structures (MCs) disposed on or arranged along the third direction D3.

[0077] The first channel 520 and the second channel 690 may comprise, for example, undoped polysilicon. The first fill pattern 530 and the second fill pattern 700 may comprise, for example, oxides, such as silicon oxide. The first capping pattern 540 and the second capping pattern 710 may comprise, for example, polysilicon doped with n-type impurities.

[0078] The first tunnel insulating pattern 500 and the second tunnel insulating pattern may include, for example, oxides, such as silicon oxide. The first charge storage pattern 490 and the second charge storage pattern may include, for example, nitrides, such as silicon nitride. The first barrier pattern 480 and the third barrier pattern may include, for example, oxides, such as silicon oxide.

[0079] The second barrier pattern 590 may cover the upper and lower surfaces of each of the first gate electrodes 600 and a portion of the sidewall of the gate electrode 600 facing the first memory channel structure 550. The second barrier pattern 590 may include, for example, a metal oxide, such as aluminum oxide or hafnium oxide.

[0080] The molded structure MS may be disposed on the sacrificial layer structure 250 in the fourth region IV of the first substrate 100. The molded structure MS may include a first insulating pattern 275 and a fourth sacrificial pattern 285 alternately stacked along the first direction D1 on the sacrificial layer structure 250. The fourth sacrificial pattern 285 may include, for example, a nitride, such as silicon nitride.

[0081] A second insulating interlayer 290 may be disposed on the uppermost of the first insulating pattern 275. A third insulating interlayer 620 may be disposed on the second insulating interlayer 290. The third insulating interlayer 620 may cover / contact the fourth insulating interlayer 630, the etch stop layer 640, and the sidewalls of the second gate electrode 650. The second insulating interlayer 290 and the third insulating interlayer 620 may comprise, for example, oxides, such as silicon oxide.

[0082] The through-hole 725 may extend longitudinally in the fourth region IV of the first substrate 100 through the second insulating interlayer 290 and the third insulating interlayer 620, the molding structure MS, the support layer 260, the sacrificial layer structure 250, the first CSP 200, and the upper part of the first insulating interlayer 150, and may contact the wiring structure WS for electrical connection to the transistor TR. For example, the through-hole 725 may provide an electrical connection between a corresponding one of the first bit line structure 797, the 1-2 bit lines 775-2, and the third bit line structure 799 and a corresponding one of the transistor TRs in the peripheral circuit structure PS.

[0083] In an example embodiment, a plurality of through-holes 725 may be spaced apart from each other in each of the second direction D2 and the third direction D3 on a fourth region IV of the first substrate 100.

[0084] A fifth insulating interlayer 750 may be disposed on the second memory channel structure 720, the through-hole 725, and the third insulating interlayer 620. A first via 755 may extend vertically through the fifth insulating interlayer 750 to contact the upper surface of the second memory channel structure 720. The first via 755 provides electrical connection between the memory channel structure MC and the bit lines.

[0085] In an example embodiment, a plurality of first vias 755 may be spaced apart from each other in each of the second direction D2 and the third direction D3, corresponding to the second memory channel structure 720.

[0086] Figure 4 The illustration shows a memory channel structure MC and bit lines electrically connected to each other via a single via; however, the embodiments are not limited to this. For example, the memory channel structure MC and bit lines may be electrically connected to each other via multiple vias, multiple wirings, and / or multiple pads. In the following explanation, for ease of description, the illustration assumes that the bit lines are electrically connected to the memory channel structure MC via a single via (e.g., a first via 755).

[0087] The first bit line structure 797 may include 1-1 bit lines 775-1 and 2-1 bit lines 795-1 stacked sequentially in the first direction D1. The third bit line structure 799 may include 1-3 bit lines 775-3 and 2-2 bit lines 795-2 stacked sequentially in the first direction D1.

[0088] In an example embodiment, a plurality of first basic units RU1 may be disposed in a semiconductor device along a second direction D2. Each of the plurality of first basic units RU1 may include two 1-2 bit lines 775-2, a first bit line structure 797, and a third bit line structure 799. The two 1-2 bit lines 775-2, the first bit line structure 797, and the third bit line structure 799 are arranged in the order of one 1-2 bit line 775-2, the first bit line structure 797, the other 1-2 bit line 775-2, and the third bit line structure 799. In an example embodiment, the first bit line structure 797, the 1-2 bit lines 775-2, and the third bit line structure 799 may be commonly connected to a memory channel structure MC in a corresponding one of the memory channel rows MCR.

[0089] In an example embodiment, the first bit line structure 797 can be electrically connected to the transistor TR of the peripheral circuit structure PS via a through-hole 725 disposed in region IV-1 of the first substrate 100. In an example embodiment, the 1-2 bit line 775-2 can be electrically connected to the transistor TR of the peripheral circuit structure PS via a through-hole 725 disposed in region IV-2 of the first substrate 100. In an example embodiment, the third bit line structure 799 can be electrically connected to the transistor TR of the peripheral circuit structure PS via a through-hole 725 disposed in region IV-3 of the first substrate 100.

[0090] In an example embodiment, the transistor TR, which is electrically connected to the peripheral circuit structure PS of the first bit line structure 797, the 1-2 bit lines 775-2 and the third bit line structure 799, can form a page buffer circuit.

[0091] Each of the 1-1 bit line 775-1, 1-2 bit line 775-2, and 1-3 bit line 775-3 may extend through the sixth insulating interlayer 770 and extend longitudinally along the third direction D3 in the third region III and the fourth region IV of the first substrate 100. The 1-1 bit line 775-1, 1-2 bit line 775-2, and 1-3 bit line 775-3 may be spaced apart from each other in the second direction D2. In the example embodiment, a plurality of basic units may be arranged along the second direction D2. Each of the plurality of basic units may include a 1-1 bit line 775-1, two 1-2 bit lines 775-2 and a 1-3 bit line 775-3. The 1-1 bit line 775-1, the two 1-2 bit lines 775-2 and the 1-3 bit line 775-3 are arranged in the order of one 1-2 bit line 775-2, one 1-1 bit line 775-1, another 1-2 bit line 775-2 and the 1-3 bit line 775-3.

[0092] In the example embodiment, the widths of bit line 775-1, bit line 775-2, and bit line 775-3 in the second direction D2 may be substantially the same as each other.

[0093] Each of the 2-1 bit line 795-1 and the 2-2 bit line 795-2 may extend through the seventh insulating interlayer 790 in a first direction D1, and may extend longitudinally in a third direction D3 on the third region III and the fourth region IV of the first substrate 100. The 2-1 bit line 795-1 and the 2-2 bit line 795-2 may be spaced apart from each other in a second direction D2. The 2-1 bit line 795-1 may contact the upper surface of the 1-1 bit line 775-1 and may extend longitudinally in a third direction D3. The 2-2 bit line 795-2 may contact the upper surface of the 1-3 bit line 775-3 and may extend longitudinally in a third direction D3. For example, compared to the 1-2 bit line 775-2, the first bit line structure 797 and the third bit line structure 799, which are electrically connected to the peripheral circuit structure PS by means of the through-piece 725 disposed on the first edge portion (or edge) E1 and the second edge portion (or edge) E2 of the first region I of the first substrate 100, may also include the 2-1 bit line 795-1 and the 2-2 bit line 795-2, respectively.

[0094] In the following text, for ease of description, the 1-1 bit line 775-1, the 1-2 bit line 775-2 and the 1-3 bit line 775-3 can be collectively referred to as the first bit line 775, and the 2-1 bit line 795-1 and the 2-2 bit line 795-2 can be collectively referred to as the second bit line 795.

[0095] A sixth insulating intermediate layer 770 may be disposed on the fifth insulating intermediate layer 750 and the first via 755. A seventh insulating intermediate layer 790 may be disposed on the sixth insulating intermediate layer 770 and the first line 775. The sixth insulating intermediate layer 770 and the seventh insulating intermediate layer 790 may comprise, for example, oxides, such as silicon oxide.

[0096] In an example embodiment, the upper surface of the first bit line 775 may have a first width W1 in the second direction D2, the lower surface of the second bit line 795 may have a second width W2 in the second direction D2, and the upper surface of the second bit line 795 may have a third width W3 in the second direction D2. In an example embodiment, the third width W3 may be greater than the first width W1. In an example embodiment, the third width W3 may be greater than the second width W2. In an example embodiment, the second width W2 may be less than the first width W1.

[0097] In an example embodiment, the upper ends of bit lines 1-2 and 775-2 and 1-3 (or the upper ends of bit lines 1-2 and 775-3, or 1-1 and 775-1) may be spaced apart by a first distance d1 in the second direction D2. For example, the upper end of a bit line may be the top surface / upper surface of the bit line. In an example embodiment, the upper ends of bit lines 1-2 and 775-2 and the lower ends or lower surfaces / bottom surfaces of bit lines 795 may be spaced apart by a second distance d2 in the second direction D2.

[0098] In the example embodiment, as described above, since the second width W2 of the lower surface of the second bit line 795 is smaller than the first width W1 of the upper surface of the first bit line 775, the second distance d2 between the 1-2 bit line 775-2 and the second bit line 795 can be greater than the first distance d1 between the 1-2 bit line 775-2 and the 1-3 bit line 775-3 (or between the 1-2 bit line 775-2 and the 1-1 bit line 775-1). Therefore, the 1-2 bit line 775-2 and the second bit line 795 can be sufficiently spaced apart from each other to reduce and / or prevent electrical short circuits between the 1-2 bit line 775-2 and the second bit line 795.

[0099] In an example embodiment, the upper ends of adjacent bit lines in the first bit line 775 may be spaced apart from each other by a first distance d1. Therefore, for example in a plan view, the first-second bit line 775-2, the first bit line structure 797, the first-second bit line 775-2, and the third bit line structure 799 may be arranged sequentially at a constant distance in the second direction D2.

[0100] Each of the first line 775 and the second line 795 may include, for example, a metal (such as copper (Cu), aluminum (Al), tungsten (W) or titanium (Ti)), a metal nitride (such as titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN) and aluminum titanium nitride (TiAlN)) or a combination thereof.

[0101] During read operations, the page buffer precharges the bit lines to a specific voltage (typically from about 0.7 V to about 1.0 V) and detects whether the bit line voltage is held or discharged based on the state of the selected memory cell, thereby reading the data. Furthermore, during program verification operations, the page buffer precharges the bit lines to accurately check the programming state of the memory cell. Therefore, the connection structure between the page buffer and the bit lines directly affects precharge performance, which in turn affects the read and write speeds, power consumption, and reliability of the memory device.

[0102] Specifically, the connection position between the bit line and the page buffer has a significant impact on the precharge operation speed. Specifically, the precharge efficiency of the bit line can vary depending on the position of the pass-through. In a bit line electrically connected to the first bit line of the page buffer via a first pass-through that contacts the center portion of the first bit line, the precharge current can flow in both directions from the position of the first pass-through, resulting in a relatively fast precharge speed. In a bit line electrically connected to the second bit line of the page buffer via a second pass-through that contacts the edge portion of the second bit line, the precharge current can flow in one direction from the second pass-through, resulting in a relatively slow precharge speed. This difference in precharge speed can affect the timing margin during read and program verification operations of the memory device (see [link to documentation]). Figure 2 (arrow length).

[0103] According to an example embodiment, the second bit line 795 may be additionally disposed on the 1-1 bit line 775-1 and the 1-3 bit line 775-3, for example, without an intermediate layer. The 1-1 bit line 775-1 and the 1-3 bit line 775-3 can be connected to the page buffer circuit via through-holes 725 disposed on the 4-1 regions IV-1 and IV-3 regions IV-3 of the first substrate 100, which are located at opposite ends of the first region I of the first substrate 100 in the second direction D2. For example, unlike a conventional single-layer bit line structure, the bit line structure according to the example embodiment may have a stacked structure comprising two bit lines stacked vertically at two horizontal locations with respect to the same electrical connection path. The bit line structure with the stacked structure may have an increased cross-sectional area of ​​the bit line structure, resulting in reduced resistance and reduced RC delay. Therefore, the precharge current can propagate rapidly throughout the entire bit line structure, and the precharge speed of the bit line structure can be improved, thereby increasing the overall operating speed of the memory cell. Since the overall operating speed of a memory device is limited by the precharge speed of the bitline structure when the precharge speed of the bitline structure is the slowest speed in the memory device, this improvement may directly affect / improve the overall system performance.

[0104] Figure 6 and Figure 7 The plan view and cross-sectional view of the layout are shown respectively, illustrating what can be corresponding to... Figure 2 and Figure 5 A semiconductor device according to an example embodiment. Except for the bit line layout, this semiconductor device is similar to a reference... Figures 1 to 5 The semiconductor devices described are essentially the same, and therefore redundant descriptions are omitted here.

[0105] Reference Figure 6 and Figure 7Multiple second basic units RU2 can be arranged / repeated in a semiconductor device along a second direction D2, and each second basic unit RU2 may include a first bit line structure 797, a 1-2 bit line 775-2 and a third bit line structure 799 arranged sequentially.

[0106] In an example embodiment, multiple basic units may be arranged along the second direction D2, and each basic unit may include a 1-1 bit line 775-1, a 1-2 bit line 775-2, and a 1-3 bit line 775-3.

[0107] In the example embodiment, the upper surface / end of bit line 775-1 and the upper surface / end of bit line 775-3 can be spaced apart from each other by a third distance d3 in the second direction D2.

[0108] In the example embodiment, the third distance d3 between 1-1 bit line 775-1 and 1-3 bit line 775-3 can be greater than the first distance d1 between 1-2 bit line 775-2 and 1-3 bit line 775-3 (or between 1-2 bit line 775-2 and 1-1 bit line 775-1). Therefore, adjacent bit line structures in the first bit line structure 797 and the third bit line structure 799 can be spaced apart from each other by a sufficiently large distance in the second direction D2.

[0109] Figure 8 This illustrates a possible correspondence with the example embodiment. Figure 2 A planar layout or plan view of a semiconductor device. Except for the layout of the third region III and the fourth region IV of the first substrate 100, the semiconductor device is similar to a reference... Figures 1 to 5 The semiconductor devices described are essentially the same, so redundant descriptions are omitted here.

[0110] Reference Figure 8 The first region I of the first substrate 100 may further include a fifth region V adjacent to the first edge portion (or edge) E1 and the second edge portion (or edge) E2, respectively. Each of the fifth regions V may be a pseudo memory region.

[0111] In an example embodiment, the third region III adjacent to the first edge portion E1 can be a 3-1 region (e.g., a third main region) III-1, and the other third regions III in the third region III can be 3-2 regions (e.g., third secondary regions) III-2. In an example embodiment, the first region I may include a fifth region V, a 3-1 region III-1, a 4-2 region IV-2, a 3-2 region III-2, a 4-1 region IV-1, a 3-2 region III-2, a 4-3 region IV-3, a 3-2 region III-2, and a fifth region V, arranged sequentially from the first edge portion E1 along a third direction D3.

[0112] In the example embodiment, the difference between the two distances measured from region IV-2 of 4-2 to the first edge portion (or edge) E1 and the second edge portion (or edge) E2 of the first region I in the third direction D3 can be less than the difference between the two distances measured from region IV-1 of 4-1 or region IV-3 of 4-3 to the first edge portion (or edge) E1 and the second edge portion (or edge) E2 of the first region I in the third direction D3 (refer to...) Figure 8 (Difference in the length of the middle arrow). For example, region IV-2 of 4-2 may be closer to the center portion of the first region I on the third direction D3 than region IV-1 of 4-1 and region IV-3 of 4-3.

[0113] In the example embodiment, the widths of regions III-2 in the third direction D3 may be substantially the same as each other, or may differ within a range of approximately ±20%. In the example embodiment, the width of region III-1 in the third direction D3 may be greater than the sum of the widths of regions III-2 in the third direction.

[0114] For example, compared to the 1-2 bit line 775-2, the first bit line structure 797 and the second bit line structure 799, which are electrically connected to the peripheral circuit structure PS by means of the through member 725 disposed on the 4-1 region IV-1 and the 4-3 region IV-3, which are relatively close to / adjacent to the second edge portion (or second edge) E2 of the first region I, may also include a second bit line 795.

[0115] Figure 9 This illustrates a possible correspondence with the example embodiment. Figure 4 A cross-sectional view of a semiconductor device. Except that the first gate electrode 600 and the second insulating pattern 727 and the third insulating pattern 729 are disposed on the fourth region IV of the first substrate 100 instead of on the fourth sacrificial pattern 285 of the molded structure MS, this semiconductor device is similar to the reference... Figures 1 to 5 The semiconductor devices described are essentially the same, so redundant descriptions are omitted here.

[0116] Reference Figure 9 The first gate electrode 600 may be sequentially stacked along the first direction D1 on the sacrificial layer structure 250 on the fourth region IV of the first substrate 100.

[0117] Each of the through-holes 725 may extend through the upper portion of the second insulating intermediate layer 290, the third insulating intermediate layer 620, the fifth insulating intermediate layer 750, the first insulating pattern 275, the first gate electrode 600, the support layer 260, the sacrificial layer structure 250, the first CSP 200, and the first insulating intermediate layer 150 on the fourth region IV of the first substrate 100 to contact the wiring structure WS of the peripheral circuit pattern. In an example embodiment, each of the through-holes 725 may be spaced apart from and insulated from the first gate electrode 600 by the second insulating pattern 727, and may be spaced apart from and insulated from the sacrificial layer structure 250 by the third insulating pattern 729. Each of the second insulating pattern 727 and the third insulating pattern 729 may include, for example, an oxide, such as silicon oxide.

[0118] Figure 10 and Figure 11 This is a cross-sectional view illustrating a semiconductor device according to an example embodiment. Specifically, Figure 10 It is along Figure 1 A cross-sectional view taken from line D-D'. Figure 11 yes Figure 10 An enlarged cross-sectional view of region Y. In addition to including the first contact plug 735, this semiconductor device is compared with a reference... Figures 1 to 5 The semiconductor devices described are essentially the same, so redundant descriptions are omitted here.

[0119] Reference Figure 10 and Figure 11 The gate electrode structure may have a stepped shape, wherein the length of the gate electrode in the second direction D2 decreases in the first direction D1, starting from the lowest level and approaching the highest level, and thus a step disposed (rising / falling) along the second direction D2 may be included in the second region II of the first substrate 100. Furthermore, the gate electrode structure may also include a step disposed (rising / falling) along the third direction D3 in the second region II of the first substrate 100.

[0120] In the following text, the end of each of the first gate electrodes 600 corresponding to the step of the gate electrode structure (e.g., the portion of each of the first gate electrodes 600 not covered by other first gate electrodes 600 thereon) is referred to as a pad. Therefore, the pad of each of the first gate electrodes 600 may be disposed on the second region II of the substrate 100. In an exemplary embodiment, the pad of each of the first gate electrodes 600 may have a greater thickness than other portions of the same / corresponding first gate electrodes 600.

[0121] Each of the first contact plugs 735 may extend through the upper portion of the second insulating intermediate layer 290, the third insulating intermediate layer 620, the first gate electrode 600, the first insulating pattern 275, the support layer 260, the sacrificial layer structure 250, the first CSP 200, and the first insulating intermediate layer 150 to contact the wiring structure WS.

[0122] In an exemplary embodiment, each of the first contact plugs 735 may extend through a pad of a first gate electrode 600 and through a second plurality of first gate electrodes 600 below it. In an exemplary embodiment, each of the first contact plugs 735 may be spaced apart from and insulated from the second plurality of first gate electrodes 600 by a fourth insulating pattern 737, and may be spaced apart from and insulated from the sacrificial layer structure 250 by a fifth insulating pattern 739. In an exemplary embodiment, the fourth insulating pattern 737 may not be provided between each of the first contact plugs 735 and the corresponding first gate electrode 600. For example, each of the first contact plugs 735 may contact a corresponding pad of the first gate electrode 600.

[0123] In an example embodiment, each of the first contact plugs 735 may have a horizontally projecting protrusion on the sidewall at the level where the first of the first gate electrodes 600 is located, the protrusion being able to contact the first of the first gate electrodes 600.

[0124] Each of the fourth insulating pattern 737 and the fifth insulating pattern 739 may include, for example, an oxide, such as silicon oxide.

[0125] Figure 12 and Figure 13 These are a plan view and a cross-sectional view of a semiconductor device according to an example embodiment. Except that the cell structure CS and the peripheral circuit structure PS are joined together by a bonding structure, this semiconductor device is related to the reference... Figures 1 to 5 The semiconductor devices described are essentially the same, so redundant descriptions are omitted here.

[0126] Reference Figure 12 and Figure 13 The bonding structure can be disposed between the peripheral circuit structure PS and the unit structure CS. For example, the peripheral circuit structure PS, the bonding structure and the unit structure CS can be stacked sequentially in the first direction D1.

[0127] The bonding structure may include a first bonding layer 160 disposed on the peripheral circuit structure PS and a first bonding pattern 165 disposed in the first bonding layer 160, and a second bonding layer 810 disposed below the unit structure CS and a second bonding pattern 815 disposed in the second bonding layer 810 and contacting the first bonding pattern 165. The first bonding pattern 165 and the second bonding pattern 815 may together form a bonding pattern structure BS, and a plurality of bonding pattern structures BS may be spaced apart from each other in each of the second direction D2 and the third direction D3. In an example embodiment, the bonding pattern structure BS may include a first bonding pattern structure BS-1, a second bonding pattern structure BS-2, and a third bonding pattern structure BS-3.

[0128] The first bonding pattern structure BS-1 may be adjacent to the first edge portion E1 of the first region I of the first substrate 100 and may be spaced apart from each other in the second direction D2. The third bonding pattern structure BS-3 may be adjacent to the second edge portion E2 of the first region I of the first substrate 100 and may be spaced apart from each other in the second direction D2. The second bonding pattern structure BS-2 may be disposed between the first bonding pattern structure BS-1 and the third bonding pattern structure BS-3, and may be adjacent to the center portion of the first region I of the first substrate 100 in the third direction D3 and may be spaced apart from each other in the second direction D2.

[0129] In an example embodiment, multiple basic units may be arranged or configured along the second direction D2. Each basic unit may include a first second bonding pattern structure BS-2 in the second bonding pattern structure BS-2 in the central portion of the first region I, a first bonding pattern structure BS-1 adjacent to the first edge portion E1, a second second bonding pattern structure BS-2 in the second bonding pattern structure BS-2 in the central portion of the first region I, and a third bonding pattern structure BS-3 adjacent to the second edge portion E2. For example, the bonding pattern structures BS may be sequentially arranged along the second direction D2 to be adjacent to the central portion of the first region I, the first edge portion E1 of the first region I, the central portion of the first region I, and the second edge portion E2 of the first region I.

[0130] With reference Figures 1 to 5 Compared to the described semiconductor device cell structure CS, the cell structure CS can have an inverted structure. Furthermore, compared to the reference... Figures 1 to 5 Compared to the described semiconductor device cell structure CS, the cell structure CS may not include the first CSP 200, the channel connection pattern 580, the support layer 260, and the support pattern 265. Furthermore, compared to the reference... Figures 1 to 5 Compared to the described semiconductor device cell structure CS, the cell structure CS may further include an eighth insulating intermediate layer 800, a second via 805, a second CSP 980, and a ninth insulating intermediate layer 990.

[0131] The following describes each component of the cell structure CS with an inverted structure.

[0132] An eighth insulating interlayer 800 may be disposed on the bonding structure. The eighth insulating interlayer 800 may include, for example, an oxide, such as silicon oxide.

[0133] Each of the second vias 805 may extend through the eighth insulating intermediate layer 800 to electrically connect each of the bit lines and the corresponding bonding pattern structure BS in the bonding pattern structure BS. Figure 13 The diagram shows that each bit line is electrically connected to its corresponding bonding pattern structure BS in the bonding pattern structure BS via a single via. However, the embodiment is not limited to this, but rather each bit line and its corresponding bonding pattern structure BS in the bonding pattern structure BS can be electrically connected to each other via multiple vias, multiple wirings, and / or multiple pads.

[0134] The first line structure 797, the first and second line structures 775-2 and the third line structure 799 can be set on the eighth insulating intermediate layer 800.

[0135] In an example embodiment, a plurality of first basic units RU1 may be arranged along the second direction D2, and each first basic unit RU1 may include an arrangement of 1-2 bit lines 775-2, a first bit line structure 797, 1-2 bit lines 775-2, and a third bit line structure 799 (e.g., as shown in the example). Figure 12 (As shown).

[0136] Compared to the 1-2 bit line 775-2, the first bit line structure 797 and the second bit line structure 799, which are electrically connected to the peripheral circuit structure PS through the first bonding pattern structure BS-1 and the third bonding pattern structure BS-3 adjacent to the first edge portion E1 and the second edge portion E2 of the first region I of the first substrate 100, respectively, may also include a second bit line 795.

[0137] In an example embodiment, the first bit line structure 797 can be electrically connected to the transistor TR of the peripheral circuit structure PS via the first bonding pattern structure BS-1. In an example embodiment, the 1-2 bit line 775-2 can be electrically connected to the transistor TR of the peripheral circuit structure PS via the second bonding pattern structure BS-2. In an example embodiment, the third bit line structure 799 can be electrically connected to the transistor TR of the peripheral circuit structure PS via the third bonding pattern structure BS-3.

[0138] The gate electrode structure and the memory channel structure MC extending through the gate electrode structure can be set on the first bit line structure 797, the 1-2 bit lines 775-2 and the third bit line structure 799.

[0139] Multiple first memory channel structures 550 included in the memory channel structure array MCA can be electrically connected to each other via corresponding second CSP 980s in the second CSP 980. Specifically, the first charge storage structure 510 may not be disposed on the upper outer wall and upper surface of the first channel 520, and each of the second CSPs 980 may contact the upper outer wall and upper surface of the first channel 520 to electrically connect the first channels 520 to each other.

[0140] The second CSP 980 may include, for example, polysilicon doped with n-type impurities. Alternatively, the second CSP 980 may include sequentially stacked metal silicide layers and polysilicon layers doped with n-type impurities. In an example embodiment, the metal silicide layer may include, for example, tungsten silicide.

[0141] A ninth insulating intermediate layer 990 may be disposed on the gate electrode structure and may cover the sidewalls of the second CSP 980. The ninth insulating intermediate layer 990 may include, for example, an oxide, such as silicon oxide.

[0142] In an example embodiment, for example in a plan view, the 1-2 bit line 775-2, the first bit line structure 797, the 1-2 bit line 775-2 and the third bit line structure 799 may be arranged sequentially along the second direction D2 at a constant distance.

[0143] Figure 14 This is a planar layout diagram illustrating a semiconductor device according to an example embodiment. Except for the layout of the bonding pattern structure BS and bit lines, this semiconductor device is similar to the reference... Figure 12 and Figure 13 The semiconductor devices described are essentially the same, so redundant descriptions are omitted here.

[0144] Reference Figure 14 The first bonding pattern structure BS-1, the second bonding pattern structure BS-2, and the third bonding pattern structure BS-3 may be arranged alternately and / or repeatedly along the second direction D2. For example, multiple basic units may be arranged or configured along the second direction D2, and each basic unit may include the first bonding pattern structure BS-1, the second bonding pattern structure BS-2, and the third bonding pattern structure BS-3.

[0145] In the example embodiment, multiple second basic units RU2, each including a first bit line structure 797, a 1-2 bit line 775-2 and a third bit line structure 799, may be arranged along the second direction D2.

[0146] In the example embodiment, compared with the reference Figure 6 and Figure 7 Similar to the described semiconductor device, the upper ends of the 1-1 bit line 775-1 and the 1-3 bit line 775-3 may be spaced apart from each other by a third distance d3 in the second direction D2. In the example embodiment, compared with the reference... Figure 6 and Figure 7 Similarly, in the described semiconductor device, the third distance d3 between 1-1 bit line 775-1 and 1-3 bit line 775-3 can be greater than the first distance d1 between 1-2 bit line 775-2 and 1-3 bit line 775-3 (or between 1-2 bit line 775-2 and 1-1 bit line 775-1). Therefore, adjacent bit line structures in the first bit line structure 797 and the third bit line structure 799 can be spaced apart from each other by a sufficiently large distance in the second direction D2.

[0147] Figure 15 This is a planar layout diagram illustrating a semiconductor device according to an example embodiment. Except for the layout of the bonding pattern structure BS and bit lines, this semiconductor device is similar to the reference... Figure 12 and Figure 13 The semiconductor devices described are essentially the same, so redundant descriptions are omitted here.

[0148] Reference Figure 15 The joining pattern structure BS can be arranged along the diagonal of the first region I (e.g., from the lower left corner to the upper right corner). The first joining pattern structure BS-1 can be located at the first corner C1 of the first region I. The second joining pattern structure BS-2 can be located at the center of the first region I. The third joining pattern structure BS-3 can be located at the second corner C2 opposite to the first corner C1 in the first region I.

[0149] In an example embodiment, the semiconductor device may have a layout in which a first bit line structure 797 electrically connected to a first bonding pattern structure BS-1 disposed at a first corner C1 is disposed on a first side of a 1-2 bit line 775-2 disposed side by side in a second direction D2, and a third bit line structure 799 electrically connected to a third bonding pattern structure BS-3 disposed at a second corner C2 is disposed on a second side of a 1-2 bit line 775-2.

[0150] In an example embodiment, a plurality of 1-2 bit lines 775-2 may be spaced apart from each other in the second direction by a distance smaller than the distance between the first bit line structures 797 or between the third bit line structures 799 in the second direction D2.

[0151] Figure 16 This is a cross-sectional view illustrating a semiconductor device according to an example embodiment. In addition to including a second contact plug 745, the semiconductor device is similar to the reference... Figures 12 to 13 The semiconductor devices described are essentially the same, so redundant descriptions are omitted here.

[0152] Reference Figure 16Multiple second contact plugs 745 may be disposed along the second direction D2. Each of the second contact plugs 745 may extend through the third insulating intermediate layer 620 and the second insulating intermediate layer 290, the first gate electrode 600 and the second blocking pattern 590 on the second region II of the first substrate 100, and may contact the lower surface of the corresponding first gate electrode 600 (hereinafter referred to as the selected gate electrode) in the first gate electrode 600 to be electrically connected to the lower surface.

[0153] The spacer 747 may cover the sidewall of each of the second contact plugs 745. For example, the spacer 747 may include an oxide such as silicon oxide or a nitride such as silicon nitride.

[0154] For example, each of the second contact plugs 745 is accessible to the lower surface of the selected gate electrode and can extend through the first gate electrode 600 disposed below it (hereinafter referred to as the unselected (one or more) gate electrodes) and can be electrically insulated from the unselected (one or more) gate electrodes by spacer 747.

[0155] Since the first gate electrode 600 included in the gate electrode structure has the same extension length in the second direction D2, each of the second contact plugs 745 can contact the upper surface of the corresponding first gate electrode 600, for example, the portion other than the end of the selected gate electrode in the second direction D2.

[0156] Figure 17 This is a cross-sectional view illustrating a semiconductor device according to an example embodiment. Except for the structure having multiple unit structures CS1, CS2... and CSn stacked on a peripheral circuit structure PS, this semiconductor device is similar to the reference... Figures 12 to 13 The semiconductor devices described are essentially the same, so redundant descriptions are omitted here.

[0157] Reference Figure 17 The semiconductor device may include a first unit structure CS1, a second unit structure CS2, ..., and an nth unit structure CSn (not shown) sequentially stacked on a peripheral circuit structure PS. In the following description, only the first unit structure CS1 and the second unit structure CS2 will be described for ease of explanation.

[0158] The semiconductor device may include a peripheral circuit structure PS, a first unit bonding pattern structure CBS1, a first unit structure CS1, a second unit bonding pattern structure CBS2, and a second unit structure CS2, which are sequentially stacked in a first direction D1.

[0159] Each of the first unit structure CS1 and the second unit structure CS2 can be referenced. Figures 12 to 16The cell structures CS of one of the described semiconductor devices are substantially the same. In the example embodiment, each of the first cell structure CS1 and the second cell structure CS2 may further include a reference... Figures 1 to 5 The molded structure MS and the through-hole component 725 are described.

[0160] The first unit structure CS1 may include a first bit line group BLG1 having bit lines spaced apart from each other in a second direction D2 and extending longitudinally in a third direction D3. The second unit structure CS2 may include a second bit line group BLG2 having bit lines spaced apart from each other in a second direction D2 and extending longitudinally in a third direction D3.

[0161] The bit line of the first unit structure CS1, the bit line of the first bit line group BLG1, can be electrically connected to the transistor TR of the peripheral circuit structure PS through the first unit bonding pattern structure CBS1.

[0162] In an example embodiment, the bit lines of the first unit structure CS1 may have different thicknesses at the locations where they connect / contact with the bit lines of the first unit bonding pattern structure CBS1 in the first direction D1. For example, the bit lines of the first unit bonding pattern structure CBS1 electrically connected to and / or contacting the center of the first region I may have the same thickness as the reference bit lines. Figures 12 to 15 The 1-2 bit lines 775-2 of the described semiconductor device have essentially the same structure, for example, a single-layer structure. The bit lines electrically connected to and / or contacting each of the first cell bonding pattern structure CBS1 adjacent to each of the first edge portions (or edges) E1 and the second edge portions (or edges) E2 of the first region I may have the same structure as the referenced... Figures 12 to 15 The first bit line structure 797 and the third bit line structure 799 of the described semiconductor device have essentially the same structure, for example, a double-layer structure.

[0163] In the example embodiment, the bit lines of the first unit structure CS1 may have the same characteristics as the reference. Figures 12 to 15 The bit lines of the described semiconductor devices have essentially the same layout.

[0164] The bit lines of the second bit line group BLG2 of the second unit structure CS2 can be electrically connected to the transistor TR of the peripheral circuit structure PS through the second unit bonding pattern structure CBS2 of the first unit structure CS1 and the through-hole 725.

[0165] In an example embodiment, depending on the position of the bit line connected to the through-piece 725 of the first unit structure CS1, the bit line of the second unit structure CS2 may have different thicknesses in the first direction D1. For example, the bit line electrically connected to the through-piece 725 of the first unit structure CS1 disposed in the center of the first region I may have a thickness similar to that of the reference bit line. Figures 1 to 8The 1-2 bit line 775-2 of the described semiconductor device has a substantially the same structure, for example, a single-layer structure. The second bit line BL2, electrically connected to the through-piece 725 of the first cell structure CS1 disposed adjacent to each of the first edge portions E1 and second edge portions E2 of the first region I, may have the same structure as the referenced... Figures 1 to 8 The first bit line structure 797 and the third bit line structure 799 of the described semiconductor device have substantially the same or similar structures, for example, a double-layer structure.

[0166] In the example embodiment, the bit lines of the second unit structure CS2 may have the same characteristics as the reference. Figures 1 to 8 The bit lines of the described semiconductor devices have essentially the same layout.

[0167] Figures 18 to 29 These are plan and cross-sectional views illustrating a method of manufacturing a semiconductor device according to an example embodiment, the semiconductor device being, for example, Figures 1 to 5 Semiconductor devices. Specifically, Figure 18 , Figure 21 , Figure 23 , Figure 25 and Figure 27 It's a floor plan. Figure 19 , Figure 22 , Figure 24 , Figure 26 and Figure 28 Each of them includes cross-sectional views taken along lines A-A' and B-B' of the corresponding plan view, respectively. Figure 20 yes Figure 19 A magnified cross-sectional view of region Z. Figure 29 It is along Figure 27 A partial cross-sectional view taken from line C-C'.

[0168] Reference Figures 18 to 20 A peripheral circuit pattern and a first insulating intermediate layer 150 covering the peripheral circuit pattern can be formed on the first substrate 100.

[0169] The first substrate 100 may include a semiconductor material (such as silicon, germanium, or silicon-germanium) or a III-V compound (such as GaP, GaAs, or GaSb). In embodiments, the first substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. The first substrate 100 may include a first region I, a second region II, a third region III, and a fourth region IV.

[0170] The peripheral circuit pattern may include a transistor TR and a wiring structure WS electrically connected to the transistor TR. Each component of the wiring structure WS may be formed by a patterning process or a damascene process.

[0171] A first CSP 200 and a sacrificial layer structure 250 may be formed on the first insulating intermediate layer 150. The sacrificial layer structure 250 may be partially removed to form a first opening exposing the upper surface of the first CSP 200, and a support layer 260 may be formed on the upper surface of the sacrificial layer structure 250 and the exposed upper surface of the first CSP 200.

[0172] The sacrificial layer structure 250 may include first sacrificial layers 220, 230 and 240 sequentially stacked in a first direction D1. Each of the first sacrificial layer 220 and the third sacrificial layer 240 may include, for example, an oxide (such as silicon oxide), and the second sacrificial layer 230 may include, for example, a nitride (such as silicon nitride).

[0173] The support layer 260 can be formed to have a uniform thickness, therefore, a first recess can be formed on the portion of the support layer 260 located in the first opening (see reference). Figure 10 In the following text, the portion of the support layer 260 formed in the first opening and in contact with the upper surface of the first CSP 200 is referred to as the support pattern 265.

[0174] The first insulating layer 270 and the fourth sacrificial layer 280 may be stacked alternately and repeatedly along the first direction D1 on the support layer 260 and the support pattern 265. Thus, a molded layer structure including the first insulating layer 270 and the fourth sacrificial layer 280 can be formed. The first insulating layer 270 may include, for example, an oxide (such as silicon oxide), and the fourth sacrificial layer 280 may include a material having etch selectivity relative to the first insulating layer 270, such as a nitride (such as silicon nitride).

[0175] A second insulating intermediate layer 290 may be formed on the uppermost first insulating layer 270 in the first insulating layer 270. A first channel hole may be formed through the second insulating intermediate layer 290, the molding layer structure, the support layer 260, the sacrificial layer structure 250 on the third region III of the first substrate 100, and the upper part of the first CSP 200, and a first memory channel structure 550 may be formed in the first channel hole.

[0176] In an example embodiment, each of the first memory channel structures 550 may include a first fill pattern 530 having a columnar shape extending longitudinally in a first direction D1, a first channel 520 covering the sidewalls and lower surface of the first fill pattern 530, a first charge storage structure 510 covering the sidewalls and lower surface of the first channel 520, and a first capping pattern 540 including the upper surfaces of the first fill pattern 530, the first channel 520, and the first charge storage structure 510. The first charge storage structure 510 may include a first tunnel insulation pattern 500, a first charge storage pattern 490, and a first barrier pattern 480 sequentially stacked on the sidewalls and lower surface of the first channel 520.

[0177] Reference Figure 21 and Figure 22 An etching process can be performed on the second insulating intermediate layer 290 and the molding layer structure on the second region II and the third region III of the first substrate 100 to form an exposed support layer 260 or a support pattern 265. Figure 10 The upper surface (shown in the figure) and the second opening 570 extending in the second direction D2.

[0178] In an example embodiment, on the second region II and the third region III of the first substrate 100, the second opening 570 may extend along the second direction D2, and a plurality of second openings 570 may be formed to be spaced apart from each other in the third direction D3. Therefore, the molding layer structure may be divided by the first opening 570 into a plurality of molding structures MS spaced apart from each other in the third direction D3, and the first insulating layer 270 and the fourth sacrificial layer 280 included in the molding layer structure may be divided into a first insulating pattern 275 and a fourth sacrificial pattern 285 extending in the second direction D2, respectively.

[0179] Although the molded structure MS extends in the second direction D2 and is spaced apart from each other in the third direction D3 by an etching process to form the second opening 570, the molded structure MS will not collapse because the first memory channel structure 550 penetrates the molded structure MS.

[0180] A spacer layer (not shown) may be formed on the sidewall of the second opening 570, the exposed upper surface (not shown) of the support layer 260 or support pattern 265, and the upper surface of the second insulating intermediate layer 290, and an anisotropic etching process may be performed on the spacer layer. Therefore, portions of the spacer layer on the upper surface of the support layer 260 or support pattern 265 and the upper surface of the second insulating intermediate layer 290 may be removed to form spacers.

[0181] The spacer layer may include, for example, polysilicon.

[0182] The portions of the support layer 260 and support pattern 265 that are not covered by the spacers and are exposed, as well as the portion of the sacrificial layer structure 250 below the spacers, can be removed, allowing the second opening 570 to widen downwards. Therefore, the second opening 570 can expose the upper surface of the first CSP 200 and can further extend through the upper portion of the first CSP 200.

[0183] When the sacrificial layer structure 250 is partially removed, the sidewall of the second opening 570 can be covered by a spacer, and since the spacer may include a material different from the sacrificial layer structure 250, the first insulating pattern 275 and the fourth sacrificial pattern 285 included in the molded structure MS may not be removed.

[0184] A wet etching process can be performed through the second opening 570, thereby removing the sacrificial layer structure 250 exposed by the second opening 570, thus forming a first gap between the first CSP 200 and the support layer 260 on the third region III of the first substrate 100. Etching agents such as hydrofluoric acid (HF) and / or phosphoric acid (H3PO4) can be used to perform the wet etching process.

[0185] In the example embodiment, due to the support layer 260, the etchant may not reach portions of the sacrificial layer structure 250 on the second region II and the fourth region IV of the first substrate 100. Therefore, portions of the sacrificial layer structure 250 on the second region II and the fourth region IV may not be removed but are retained.

[0186] When the first gap is formed, a portion of the sidewall of the first charge storage structure 510 (not shown) can be exposed, and the exposed sidewall of the first charge storage structure 510 can be removed during a wet etching process, thereby exposing the outer sidewall of the first channel 520. Therefore, the first charge storage structure 510 can be divided into an upper and a lower portion, the upper portion penetrating the molding structure MS to cover most (e.g., more than half) of the outer sidewall of the first channel 520, and the lower portion covering the bottom of the first channel 510 and formed on the upper portion of the first CSP 200, as shown. Figure 22 As shown.

[0187] The spacer can be removed, and a channel connection layer (not shown) can be formed on the sidewall of the second opening 570 and in the first gap. For example, an etch-back process can be performed to remove a portion of the channel connection layer in the second opening 570, thereby forming a channel connection pattern 580 in the first gap.

[0188] When the channel connection pattern 580 is formed, adjacent first channels 520 in the first channels 520 between the second openings 570 in the memory block region can be connected to each other.

[0189] In an embodiment, an air gap may be formed in the channel connection pattern 580.

[0190] Reference Figure 23 and Figure 24 The fourth sacrificial pattern 285 exposed by the second opening 570 can be removed to form a second gap between adjacent first insulating patterns 275 along the first direction D1, and a portion of the outer wall of the first charge storage structure 510 included in the first memory channel structure 550 can be exposed in each of the second gaps.

[0191] According to an example embodiment, the fourth sacrificial pattern 285 can be removed by a wet etching process using an etchant including phosphoric acid (H3PO4) or sulfuric acid (H2SO4).

[0192] A wet etching process can be performed through the second opening 570, and the portion of the fourth sacrificial pattern 285 between the second openings 570 can be removed by etchant introduced horizontally through the second openings 570 on the second region II and the third region III of the first substrate 100, respectively.

[0193] In an embodiment, the etchant may not reach the portion of the fourth sacrificial pattern 285 on the fourth region IV of the first substrate 100; therefore, the portion of the fourth sacrificial pattern 285 on the fourth region IV of the first substrate 100 may not be removed but retained. For example, the molded structure MS may remain on the fourth region IV of the first substrate 100.

[0194] A second barrier layer may be formed on the outer wall of the first charge storage structure 510 exposed by the second gap, the inner wall of the second gap, the surface of the first insulating pattern 275, the side wall of the second insulating intermediate layer 290, and the upper surface of the second insulating intermediate layer 290, and a first gate electrode layer may be formed on the second barrier layer.

[0195] The first gate electrode layer can be partially removed to form the first gate electrode 600 in each of the second gaps. According to an example embodiment, the first gate electrode layer can be partially removed by a wet etching process.

[0196] In an example embodiment, the first gate electrode 600 may extend longitudinally along a second direction D2, and a plurality of first gate electrodes 600 may be formed to be spaced apart from each other in a first direction D1 to form a first gate electrode structure. In an example embodiment, a plurality of first gate electrode structures may be spaced apart from each other in a third direction D3 through a first opening 570.

[0197] A first separation layer may be formed on the second barrier layer to fill each of the second openings 570, and the first separation layer may be planarized until the upper surface of the second insulating intermediate layer 290 is exposed.

[0198] Therefore, the second barrier layer can be divided into multiple second barrier patterns 590, and the first separation layer can be divided into multiple first separation patterns 610.

[0199] Reference Figure 25 and Figure 26 A third insulating intermediate layer 620 can be formed on the upper surface of the second insulating intermediate layer 290.

[0200] A third opening exposing the upper surface of the second insulating intermediate layer 290 can be formed by partially removing the third insulating intermediate layer 620 on the third region III of the first substrate 100, and a fourth insulating intermediate layer 630, an etch stop layer 640, and a second gate electrode layer can be sequentially stacked on the exposed upper surface of the second insulating intermediate layer 290 to fill the third opening.

[0201] The fourth insulating intermediate layer 630 may include an insulating nitride such as silicon nitride, the etch stop layer 640 may include an oxide such as silicon oxide, and the second gate electrode layer may include polysilicon doped with impurities.

[0202] A fourth opening may be formed through the second gate electrode layer and the etch stop layer 640 to expose the upper surface of the fourth insulating intermediate layer 630, and a second separation pattern 660 may be formed in the fourth opening. In an example embodiment, the second separation pattern 660 may extend, for example, longitudinally in the second direction D2, and a plurality of second separation patterns 660 may be formed to be spaced apart from each other in the third direction D3. For example, in a plan view, each of the second separation patterns 660 may be formed between first separation patterns 610 that are adjacent to each other along the third direction D3.

[0203] When the second separation pattern 660 is formed, the second gate electrode layer can be separated into second gate electrodes 650, each extending, for example, longitudinally in the second direction D2. The second gate electrodes 650 can form a gate electrode structure together with the first gate electrode structure below them, which includes the first gate electrode 600.

[0204] A second channel via can be formed through the second gate electrode 650 to expose the upper surface of the etch stop layer 640. The second channel via may partially overlap with the first memory channel structure 550 in the first direction D1. In an example embodiment, a plurality of second channel vias may be formed in each of the second direction D2 and the third direction D3.

[0205] A second charge storage structure layer may be formed on the sidewalls and bottom of the second channel hole, as well as on the second gate electrode 650, the first separation pattern 610, the second separation pattern 660, and the third insulating intermediate layer 620. An etch-back process may be performed on the second charge storage structure layer to form a second charge storage structure 680 on the sidewalls and edge portions of the bottom of the second channel hole. The second charge storage structure 680 may include a third barrier pattern, a second charge storage pattern, and a second tunnel insulating pattern sequentially stacked from the sidewalls of the second channel hole.

[0206] The portion of the etch stop layer 640 exposed by the second charge storage structure 680 and the portion of the fourth insulating intermediate layer 630 below that portion can be removed to enlarge / expand the second channel via in the first direction D1. Furthermore, the portion of the fourth insulating intermediate layer 630 adjacent to the enlarged second channel via can be removed to enlarge / expand the second channel via in the horizontal direction, for example, as... Figure 26 As shown. Therefore, the second channel hole can expose at least a portion of the upper surface of the first memory channel structure 550. The second channel hole can also expose the upper surface of the portion of the second insulating intermediate layer 290 adjacent to the first memory channel structure 550.

[0207] A second channel 690, a second filling pattern 700, and a second capping pattern 710 may be formed in each of the second channel holes.

[0208] In an example embodiment, the second channel 690 may include a lower portion surrounded and horizontally overlapping with the fourth insulating intermediate layer 630, a middle portion surrounded and horizontally overlapping with the etch stop layer 640, and an upper portion surrounded and horizontally overlapping with the second charge storage structure 680. The second fill pattern 700 may have a lower surface and sidewalls covered by the upper portion of the second channel 690, and a second capping pattern 710 may be formed on the second channel 690 and the second fill pattern 700 and may be surrounded by the second charge storage structure 680.

[0209] The second charge storage structure 680, the second channel 690, the second filling pattern 700, and the second capping pattern 710 can together form a second memory channel structure 720 that is accessible to and connected to the upper surface of the first memory channel structure 550.

[0210] The first memory channel structure 550 and the second memory channel structure 720 can together form a memory channel structure MS.

[0211] A through-hole 725 extending through the upper portion of the third insulating interlayer 620, the molding structure MS, the sacrificial layer structure 250, the first CSP 200, and the first insulating interlayer 150 can be formed on the fourth region IV of the first substrate 100. The through-hole 725 can be electrically connected to the transistor TR of the peripheral circuit pattern via the wiring structure WS.

[0212] Reference Figures 27 to 29 A fifth insulating intermediate layer 750 may be formed on the second gate electrode 650, the second separation pattern 660, the memory channel structure MS and the third insulating intermediate layer 620, and a first via 755 may be formed extending through the fifth insulating intermediate layer 750 and contacting the upper surface of the memory channel structure MS.

[0213] A sixth insulating intermediate layer 770 may be formed on the fifth insulating intermediate layer 750 and the first via 755, and a first line 775 may be formed extending through the sixth insulating intermediate layer 770 and contacting the upper surface of the first via 755.

[0214] In an example embodiment, the first first line 775 may extend longitudinally along a third direction D3 on the third region III and the fourth region IV of the first substrate 100, and the plurality of first first lines 775 may be spaced apart from each other in the second direction D2. In an example embodiment, the width of the first first lines 775 in the second direction D2 may be substantially the same.

[0215] In an example embodiment, the first bit line 775 includes a 1-1 bit line 775-1, a 1-2 bit line 775-2, and a 1-3 bit line 775-3. In the example embodiment, the 1-1 bit line 775-1 can be electrically connected to the transistor TR of the peripheral circuit structure PS via a through-hole 725 disposed in region IV-1 of the first substrate 100. The 1-2 bit line 775-2 can be electrically connected to the transistor TR of the peripheral circuit structure PS via a through-hole 725 disposed in region IV-2 of the first substrate 100. The 1-3 bit line 775-3 can be electrically connected to the transistor TR of the peripheral circuit structure PS via a through-hole 725 disposed in region IV-3 of the first substrate 100.

[0216] Return to reference Figures 1 to 5 A seventh insulating intermediate layer 790 can be formed on the sixth insulating intermediate layer 770 and the first line 775.

[0217] A second bit line 795 can be formed through the seventh insulating intermediate layer 790 to extend longitudinally along the third direction D3 on the third region III and the fourth region IV of the first substrate 100, and a plurality of second bit lines 795 can be spaced apart from each other in the second direction D2. Each of the second bit lines 795 can contact the upper surface of the corresponding 1-1 bit line 775-1 or the corresponding 1-3 bit line 775-3, and can extend longitudinally in the third direction D3. For example, the second bit line 795 can be formed on the 1-1 bit line 775-1 and the 1-3 bit line 775-3, which are electrically connected to the peripheral circuit structure PS through through-holes 725 respectively provided on the opposite ends of the first region I in the third direction D3 of the first region IV-1 and the 4-3 region IV-3.

[0218] By performing the above process, semiconductor devices can be manufactured.

[0219] Figures 30 to 32 This illustrates the manufacturing process according to an example embodiment. Figure 12 and Figure 13 A cross-sectional view of a method for using a semiconductor device. The method may include, with reference to... Figures 18 to 29 and Figures 1 to 5 The processes described are essentially the same, so redundant descriptions are omitted here.

[0220] Reference Figure 30 A first bonding layer 160, including a first bonding pattern 165 electrically connected to a wiring structure WS, can be formed on the peripheral circuit structure PS.

[0221] Reference Figure 31 Through execution and reference Figures 18 to 29 and Figures 1 to 5 The described process is substantially the same or similar, and can form on the second substrate 120 a cell structure including a gate electrode structure, a first insulating pattern 275, a memory channel structure MC, a first separation pattern 610, a second separation pattern 660, and a bit line structure CS. (Refer to reference...) Figures 18 to 29 and Figures 1 to 5 The process described is different; in this embodiment, the process of forming the sacrificial layer structure 250, the support layer 260, the support pattern 265, and the channel connection pattern 580 may not be performed.

[0222] An eighth insulating intermediate layer 800 may be formed on the bit line, and a second via 805 may be formed extending through the eighth insulating intermediate layer 800 in the first direction D1 and contacting the upper surface of the bit line.

[0223] A second bonding layer 810 may be formed on the eighth insulating intermediate layer 800, including a second bonding pattern 815 on the upper surface of the contact second through hole 805.

[0224] Reference Figure 32 After flipping the cell structure CS, the cell structure CS and the peripheral circuit structure PS can be bonded to each other, so that the second bonding layer 810 contacts the first bonding layer 160. The first bonding pattern 815 and the second bonding pattern 165 can contact each other, and the first bonding pattern 815 and the second bonding pattern 165 can together form the bonding pattern structure BS.

[0225] Return to reference Figure 12 and Figure 13 For example, the second substrate 120 can be removed by a polishing process, thereby exposing the upper part of the first charge storage structure 510 and the upper surface of the uppermost first insulating pattern 275 in the first insulating pattern 275. The exposed upper part of the first charge storage structure 510 can be removed, thereby exposing the outer sidewall and upper surface of the upper part of the first channel 520.

[0226] A second CSP layer may be formed on the outer sidewall and upper surface of the upper portion of the first channel 520 and on the upper surface of the uppermost first insulating pattern 275 in the first insulating pattern 275, and the second CSP layer may be patterned to form a second CSP 980. A ninth insulating intermediate layer 990 may be formed covering the second CSP 980, and a planarization process may be performed on the upper portion of the ninth insulating intermediate layer 990 until the upper surface of the second CSP 980 is exposed.

[0227] By performing the above process, semiconductor devices can be manufactured.

[0228] Figure 33 This is a block diagram illustrating a semiconductor device according to an example embodiment.

[0229] Reference Figure 33 The semiconductor device 10 may include a memory cell array 11 and peripheral circuitry PECT, and the peripheral circuitry PECT may include a page buffer circuit 12, a control logic circuit 13, a voltage generator 14, and a line decoder 15. Although in Figure 33 Not shown, but the peripheral circuitry PECT may also include data input / output circuitry or input / output interfaces. Furthermore, the peripheral circuitry PECT may also include temperature sensors, command decoders, address decoders, etc.

[0230] The memory cell array 11 may include multiple memory blocks BLK1 to BLKz (where z is a positive integer), and each of the multiple memory blocks BLK1 to BLKz may include multiple memory cells. The memory cell array 11 is electrically connected to the page buffer circuit 12 via the bit line BL, and is electrically connected to the row decoder 15 via the word line WL, the serial select line SSL, and the ground select line GSL. For example, the memory cells may be flash memory cells.

[0231] Page buffer circuit 12 may include multiple page buffers PB. Each of the multiple page buffers PB is electrically connected to a memory cell of memory cell array 11 via a corresponding bit line. Page buffer circuit 12 may select at least one of the bit lines BL under the control of control logic circuit 13. For example, page buffer circuit 12 may select some of the bit lines BL in response to a column address Y_ADDR received from control logic circuit 13. Each of the multiple page buffers PB may operate as a write driver or a sense amplifier. For example, in a programming operation, each of the multiple page buffers PB may apply a voltage corresponding to the programming data DATA to the bit line to store the data DATA in the memory cell. For example, in a programming verification operation or a read operation, each of the multiple page buffers PB may read current or voltage via the bit line to detect the programmed data DATA.

[0232] The control logic circuit 13 can output various control signals for programming data into the memory cell array 11, reading data from the memory cell array 11, or erasing data stored in the memory cell array 11, based on the command CMD, the address ADDR, and the control signal CTRL. Such control signals may include, for example, the voltage control signal CTRL_vol, the row address X_ADDR, and the column address Y_ADDR. Therefore, the control logic circuit 13 can generally control various operations in the semiconductor device 10. For example, the control logic circuit 13 can receive the command CMD, the address ADDR, and the control signal CTRL from the memory controller.

[0233] Voltage generator 14 can generate various types of voltages for performing programming, reading, and erasing operations on memory cell array 11 based on the voltage control signal CTRL_vol. Specifically, voltage generator 14 can generate word line voltages VWL, such as programming voltage, read voltage, pass voltage, erase verification voltage, or programming verification voltage. Furthermore, voltage generator 14 can also generate serial select line voltages and ground select line voltages based on the voltage control signal CTRL_vol.

[0234] The row decoder 15 can select one of a plurality of memory blocks BLK1 to BLKz in response to the row address X_ADDR received from the control logic circuit 13, can select one of the word lines WL of the selected memory block, and can select one of the string select lines SSL. For example, during a programming operation, the row decoder 15 can apply a programming voltage and a programming verification voltage to the selected word line, and during a read operation, the row decoder 15 can apply a read voltage to the selected word line.

[0235] Although the different figures illustrate variations of the exemplary embodiments, and the different embodiments disclose features that differ from each other, these figures and embodiments are not necessarily intended to be mutually exclusive. Rather, features depicted in different figures and / or described above in different embodiments may be combined with other features from other figures / embodiments to produce additional variations of the embodiments when the related descriptions of the figures and embodiments are considered as a whole. For example, unless the context clearly indicates otherwise, components and / or features of the different embodiments described above can be combined interchangeably or additionally with components and / or features of other embodiments to form additional embodiments, and this disclosure includes additional embodiments.

[0236] Although the inventive concept has been shown and described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various modifications in form and detail may be made to the inventive concept without departing from its spirit and scope.

Claims

1. A semiconductor device, comprising: A substrate comprising a first region having a second region and a third region arranged alternately and repeatedly in a first direction; Peripheral circuit patterns on the substrate; A gate electrode structure, on each of the second regions of the substrate; A memory channel structure, each extending through the gate electrode structure; A first bit line and a second bit line on the gate electrode structure on the first region of the substrate, each of the first bit line and the second bit line extending in the first direction, and the first bit line and the second bit line being spaced apart from each other in a second direction intersecting the first direction; The third line extends along the first direction on the first line; as well as A through-hole, located in the third region of the substrate, The third region includes a third main region and a third secondary region. The third primary region is closer to the first edge of the first region in the first direction than the third secondary region. The first bit line is electrically connected to the peripheral circuit pattern through a first through-hole member disposed on the third main region of the substrate, and the second bit line is electrically connected to the peripheral circuit pattern through a second through-hole member disposed on the third secondary region of the substrate.

2. The semiconductor device according to claim 1, wherein, The upper surface of the first bit line has a first width in the second direction, and the upper surface of the third bit line has a second width in the second direction, wherein the second width is greater than the first width.

3. The semiconductor device according to claim 2, wherein, The lower surface of the third bit line has a third width in the second direction, and the third width is smaller than the first width.

4. The semiconductor device according to claim 1, further comprising: A fourth bit line extends in the first direction, and the fourth bit line is spaced apart from the second bit line in the second direction; as well as A fifth bit line extends along the first direction from the fourth bit line, and the fifth bit line is spaced apart from the third bit line in the second direction. The third region includes a third-level region. Wherein, the third-level region is closer to the second edge of the first region in the first direction than the third-level region, and The fourth bit line is electrically connected to the third through-piece disposed on the third third-level region of the substrate.

5. The semiconductor device according to claim 4, wherein, The first bit line and the third bit line together form the first bit line structure, and the fourth bit line and the fifth bit line together form the second bit line structure. The basic unit formed by the first bit line structure, the second bit line structure, and the two second bit lines is periodically disposed on the first region of the substrate in the second direction. The first bit line structure, the second bit line structure, and the two second bit lines are arranged in the second direction in the order of one second bit line, the first bit line structure, the other second bit line, and the second bit line structure.

6. The semiconductor device according to claim 4, wherein, The first bit line and the third bit line together form the first bit line structure, and the fourth bit line and the fifth bit line together form the second bit line structure. The basic unit formed by the first bit line structure, the second bit line and the second bit line structure arranged in sequence in the second direction is periodically disposed on the first region of the substrate in the second direction.

7. The semiconductor device according to claim 6, wherein, The first distance between the upper surface of the first bit line and the upper surface of the second bit line in the second direction is less than the second distance between the upper surface of the first bit line and the upper surface of the fourth bit line in the second direction.

8. The semiconductor device according to claim 1, further comprising: A molded structure, which is located on the third region of the substrate. Each of the through-pieces extends through the molded structure.

9. The semiconductor device according to claim 1, in, The gate electrode structure is disposed on the third region of the substrate, and each of the through-members extends through the gate electrode structure and is insulated from the gate electrode structure. Each of the through-hole members is electrically insulated from the gate electrode structure by an insulating pattern.

10. The semiconductor device of claim 1, further comprising: A channel connection pattern is provided between the peripheral circuit pattern and the gate electrode structure, which electrically connects the memory channel structures to each other.

11. A semiconductor device, comprising: Peripheral circuit patterns are on a substrate, the substrate including a first region; A bonding pattern structure is formed on the peripheral circuit pattern; The first bit line structure, on the bonding pattern structure, includes a first bit line extending in a first direction parallel to the upper surface of the substrate, and a second bit line contacting the upper surface of the first bit line, the second bit line extending in the first direction on the upper surface of the first bit line. A third bit line extends in the first direction and is spaced apart from the second bit line in a second direction that is parallel to the upper surface of the substrate and intersects the first direction. A gate electrode structure, which is located on the first bit line structure and the third bit line; as well as Memory channel structures, each extending through the gate electrode structure in the first region of the substrate. The joining pattern structure includes a first joining pattern structure and a second joining pattern structure, wherein the first joining pattern structure is closer to the first edge of the first region in the first direction than the second joining pattern structure, and The first bit line structure is electrically connected to the peripheral circuit pattern through the first bonding pattern structure, and the third bit line is electrically connected to the peripheral circuit pattern through the second bonding pattern structure.

12. The semiconductor device according to claim 11, wherein, The lower surface of the second bit line has a first width in the second direction, and the lower surface of the first bit line has a second width in the second direction, wherein the second width is greater than the first width.

13. The semiconductor device of claim 11, further comprising: The second bit line structure includes a fourth bit line spaced apart from the first bit line in the second direction, and a fifth bit line contacting the upper surface of the fourth bit line, the fifth bit line extending in the first direction on the upper surface of the fourth bit line, and the fourth bit line spaced apart from the third bit line in the second direction. The joining pattern structure further includes a third joining pattern structure that is closer to the second edge of the first region in the first direction than the second joining pattern structure, and The second bit line structure is electrically connected to the peripheral circuit pattern through the third bonding pattern structure.

14. The semiconductor device according to claim 13, wherein, The basic unit formed by the first bit line structure, the second bit line structure, and two third bit lines is periodically disposed on the first region of the substrate in the second direction. The first bit line structure, the second bit line structure, and the two third bit lines are arranged in the second direction in the order of one third bit line, the first bit line structure, the other third bit line, and the second bit line structure.

15. The semiconductor device according to claim 13, wherein, The basic unit formed by the first bit line structure, the third bit line and the second bit line structure arranged in sequence in the second direction is periodically disposed on the first region of the substrate in the second direction.

16. The semiconductor device of claim 11, further comprising: A common source plate is disposed on the gate electrode structure, and the common source plate electrically connects the memory channel structures to each other.

17. A semiconductor device, comprising: A substrate comprising a first region having a second region and a third region arranged alternately and repeatedly in a first direction; Peripheral circuit patterns on the substrate; as well as A first bonding pattern structure, a first unit structure, a second bonding pattern structure, and a second unit structure are sequentially stacked vertically on the peripheral circuit pattern. The first unit structure includes: The first line group is located on the first joining pattern structure. A first gate electrode structure is provided on the second region of the substrate, on the first line group. The first memory channel structure, each extending through the first gate electrode structure, and A through-hole, located in the third region of the substrate, The second unit structure includes: The second line group, which is on the second joining pattern structure. The second gate electrode structure is located on the second bit line group in the second region of the substrate, and The second memory channel structure extends through the second gate electrode structure. The second bit line group includes: The first bit line structure, on the second bonding pattern structure, includes a first bit line extending in the first direction and a second bit line extending in the first direction on the upper surface of the first bit line. A third bit line extends in the first direction and is spaced apart from the second bit line in a second direction parallel to the upper surface of the substrate and intersecting the first direction. The third region includes a third main region and a third secondary region. Wherein, the third primary region is closer to the first edge of the first region in the first direction than the third secondary region, and The first bit line structure is electrically connected to the peripheral circuit pattern through a first through-hole member disposed on the third main region of the substrate, and the third bit line is electrically connected to the peripheral circuit pattern through a second through-hole member disposed on the third secondary region of the substrate.

18. The semiconductor device according to claim 17, wherein, The lower surface of the second bit line has a first width in the second direction, and the lower surface of the first bit line has a second width in the second direction, wherein the second width is greater than the first width.

19. The semiconductor device according to claim 17, wherein, The first bit line group includes: A second bit line structure, which is on the first bonding pattern structure, includes a fourth bit line extending in the first direction and a fifth bit line extending in the first direction on the upper surface of the third bit line; and The sixth bit line extends in the first direction and is spaced apart from the fifth bit line in the second direction. The semiconductor device includes a plurality of first bonding pattern structures, each comprising a first primary bonding pattern structure and a first secondary bonding pattern structure. Wherein, the first primary bonding pattern structure is closer to the first edge of the first region of the substrate in the first direction than the first secondary bonding pattern structure, and The second bit line structure is electrically connected to the peripheral circuit pattern through the first primary bonding pattern structure, and the sixth bit line is electrically connected to the peripheral circuit pattern through the first secondary bonding pattern structure.

20. The semiconductor device of claim 17, further comprising: A first common source plate is disposed on the first gate electrode structure and connects the first memory channel structures to each other. as well as The second common source plate is disposed on the second gate electrode structure and connects the second memory channel structures to each other.

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