Semiconductor structure in a memory device

Abstract

Memory devices having semiconductor structures and memory systems are provided. In one aspect, a memory device includes a first semiconductor structure and a second semiconductor structure stacked with the first semiconductor structure. The first semiconductor structure has a memory array including a plurality of memory banks. The second semiconductor structure includes a control circuit. The control circuit includes a plurality of memory bank circuits corresponding to the plurality of memory banks and a peripheral circuit arranged to a side of the plurality of memory bank circuits. The peripheral circuit includes a first regulator coupled to a bit line in a first memory bank of the plurality of memory banks. A first memory bank circuit corresponding to the first memory bank includes a second regulator coupled to the bit line in the first memory bank.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, such as memory devices. Background Technology

[0002] Semiconductor devices (e.g., memory devices) can have various structures to increase the density of memory cells and lines on a chip. Memory devices typically include a memory array of memory cells and control circuitry for facilitating the operation of the memory array. Summary of the Invention

[0003] This disclosure describes a semiconductor structure for managing memory devices.

[0004] One aspect of this disclosure features a memory device. The memory device includes a memory array comprising a plurality of memory banks. The memory device also includes control circuitry. The control circuitry includes a first regulator coupled to bit lines in a first memory bank of the plurality of memory banks. The control circuitry also includes a second regulator coupled to bit lines in the first memory bank. The output of the first regulator is coupled to the output of the second regulator.

[0005] In some implementations, the second regulator is closer to the first storage unit than the first regulator.

[0006] In some embodiments, the control circuitry further includes a third regulator coupled to bit lines in a second memory bank of a plurality of memory banks. Bit lines in the second memory bank are also coupled to a first regulator. The output of the third regulator is coupled to the output of the first regulator.

[0007] In some embodiments, the control circuitry includes a plurality of memory bank circuits corresponding to a plurality of memory banks. The control circuitry also includes peripheral circuitry disposed on one side of the plurality of memory bank circuits. A second regulator is included in a first memory bank circuit corresponding to a first memory bank, and a first regulator is included in the peripheral circuitry.

[0008] In some implementations, each of the plurality of memory bank circuits includes a corresponding second regulator coupled to a bit line in the corresponding memory bank of the plurality of memory banks.

[0009] In some embodiments, the first memory bank circuitry further includes one or more sense amplifiers for bit lines coupled to the first memory bank, and one or more word line drivers for word lines coupled to the first memory bank. Peripheral circuitry includes input / output circuitry for the memory device.

[0010] In some implementations, the second regulator is located at the edge of the first memory circuit.

[0011] In some embodiments, a first output of the first regulator is coupled to a first output of a second regulator in the first memory circuit. A second output of the first regulator is coupled to a second output of the second regulator in the first memory circuit.

[0012] In some embodiments, the bit lines in the first memory are numbered sequentially. The first output of the first regulator and the first output of the second regulator are coupled to the odd-numbered bit lines in the first memory. The second output of the first regulator and the second output of the second regulator are coupled to the even-numbered bit lines in the first memory.

[0013] In some embodiments, the first regulator includes one or more first operational amplifiers, one or more first transistors, and one or more capacitors. The second regulator includes one or more second operational amplifiers and one or more second transistors.

[0014] In some implementations, the transistors included in one or more second operational amplifiers are smaller in size than the transistors included in one or more first operational amplifiers.

[0015] In some implementations, the first regulator is configured to operate when the first memory is in an inactive mode and when the first memory is in an active mode. The second regulator is configured to operate when the first memory is in an active mode and to be disabled when the first memory is in an inactive mode.

[0016] In some implementations, the second regulator is configured to be disabled by an internal switch in the corresponding second operational amplifier within the second regulator.

[0017] Another aspect of this disclosure features a memory device. The memory device includes a first semiconductor structure and a second semiconductor structure stacked with the first semiconductor structure. The first semiconductor structure has a memory array including a plurality of memory cells. The second semiconductor structure includes control circuitry. The control circuitry includes a plurality of memory cell circuits corresponding to the plurality of memory cells, and peripheral circuitry disposed on one side of the plurality of memory cells. The peripheral circuitry includes a first regulator coupled to a bit line in the first memory cell. The first memory cell circuitry corresponding to the first memory cell includes a second regulator coupled to a bit line in the first memory cell.

[0018] In some embodiments, the first semiconductor structure includes a first contact structure isolated by a first insulating material, and the second semiconductor structure includes a second contact structure isolated by a second insulating material. The first semiconductor structure and the second semiconductor structure are bonded together through contact between the first contact structure and the second contact structure.

[0019] In some implementations, multiple memory bank circuits are arranged in two rows. The output of a first regulator is coupled to the output of a second regulator in the memory bank circuits in the first row. The peripheral circuitry also includes an additional first regulator, wherein the output of the additional first regulator is coupled to the output of a second regulator in the memory bank circuits in the second row.

[0020] In some embodiments, the control circuitry includes a plurality of memory bank circuits corresponding to a plurality of memory banks. The control circuitry also includes peripheral circuitry disposed on one side of the plurality of memory bank circuits. A second regulator is included in a first memory bank circuit corresponding to a first memory bank, and a first regulator is included in the peripheral circuitry.

[0021] In some implementations, each of the plurality of memory bank circuits includes a corresponding second regulator coupled to a bit line in the corresponding memory bank of the plurality of memory banks.

[0022] In some implementations, the second regulator is located at the edge of the first memory circuit.

[0023] Another aspect of this disclosure features a memory system. The memory system includes a memory device and a memory controller, the memory controller being coupled to the memory device and configured to control the memory device. The memory device includes a memory array comprising a plurality of memory banks. The memory device also includes control circuitry. The control circuitry includes: a first regulator coupled to bit lines in a first memory bank of the plurality of memory banks, and a second regulator coupled to bit lines in the first memory bank. The output of the first regulator is coupled to the output of the second regulator.

[0024] Details of one or more embodiments of the subject matter of this disclosure are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of this subject matter will become apparent from the specification, drawings, and claims. Attached Figure Description

[0025] The accompanying drawings, which are incorporated herein and form part of this disclosure, illustrate various aspects of this disclosure and, together with the description, further serve to explain the principles of this disclosure and enable those skilled in the art to implement and use this disclosure.

[0026] Figure 1 A schematic diagram of an exemplary memory device is shown, including control circuitry and an array of memory cells, each having a vertical transistor.

[0027] Figure 2 An exemplary memory device with a storage array and exemplary control circuitry is shown.

[0028] Figure 3 A layout diagram of an exemplary control circuit is shown.

[0029] Figure 4 An exemplary memory device is shown, wherein the memory array and control circuitry are formed on the same wafer.

[0030] Figure 5A A schematic diagram of a cross-section of an exemplary memory device is shown, in which the memory array and control circuitry are formed on different wafers.

[0031] Figure 5B A schematic diagram of a cross-section of another exemplary memory device is shown, in which the memory array and control circuitry are formed on different wafers.

[0032] Figure 6 An exemplary control circuit including a global bitline regulator is shown.

[0033] Figure 7 Another exemplary control circuit including a global bit line modulator and a local bit line modulator is shown.

[0034] Figure 8 An exemplary connection between the memory bank circuitry, the local bit line modulator, and the global bit line modulator is shown.

[0035] Figure 9 A schematic diagram of an exemplary local bitline modulator is shown.

[0036] Figure 10 A schematic diagram of an exemplary global bitline regulator is shown.

[0037] Figure 11 A schematic diagram of an exemplary sensing amplifier is shown.

[0038] Figure 12 The performance of memory devices with and without local bit line adjusters is shown.

[0039] Figure 13 A block diagram of an exemplary system having one or more memory devices is shown.

[0040] The same reference numerals and names in the various figures denote the same elements. It should also be understood that the various exemplary embodiments shown in the figures are merely illustrative and are not necessarily drawn to scale. Detailed Implementation

[0041] A dynamic random access memory (DRAM) device may include a memory array and control circuitry coupled to the memory array. In some embodiments, the memory array is formed on a first semiconductor structure (e.g., a first wafer), and the control circuitry is formed on a second semiconductor structure (e.g., a second wafer). The first and second semiconductor structures may be bonded together to form the memory device.

[0042] The control circuitry may include multiple memory bank circuits, each corresponding to (e.g., controlling) a specific memory bank in the memory array. The control circuitry may also include peripheral circuitry disposed to one side of the memory bank circuitry. The peripheral circuitry may include circuitry configured to control more than one memory bank.

[0043] The control circuitry may include bit line conditioners configured to provide bias voltages to bit lines in the memory bank. In some cases, the bit line conditioner is placed in peripheral circuitry and configured to provide bias voltages to bit lines in more than one memory bank. In this disclosure, the bit line conditioner in the peripheral circuitry is referred to as a global bit line conditioner. The wiring between the global bit line conditioner and the bit lines may be long. Therefore, the transient response may be slow when the global bit line conditioner provides bias voltages to the bit lines. A large voltage drop may also exist due to the continuous large current in the wiring.

[0044] This disclosure provides techniques for improving the voltage supply of bit lines in a memory device. In some embodiments, in addition to a global bit line regulator in the peripheral circuitry, the control circuitry may also include a bit line regulator in each memory bank circuit. In this disclosure, the bit line regulator in the memory bank circuitry may be referred to as a local bit line regulator. The local bit line regulator may be configured to provide a bias voltage to the bit line in the memory bank corresponding to the memory bank circuit that includes the local bit line regulator. In some embodiments, the local bit line regulator may be enabled or disabled by a corresponding memory bank control logic unit. For example, the local bit line regulator may be enabled when the corresponding memory bank is in an active mode (e.g., when reading data from or writing data to the memory bank), and disabled when the corresponding memory bank is in an inactive mode.

[0045] Embodiments of this disclosure may provide one or more of the following technical benefits and / or advantages. For example, by including a local bit line conditioner, the wiring between the bit line conditioner and the bit line can be shortened. Transient response can be improved, and the bias voltage supplied to the bit line can be more stable. For example, variations in the bias voltage supplied to the bit line can be smaller during operation (e.g., refresh operation with continuous high current in the wiring between the bit line conditioner and the bit line). Furthermore, the local bit line conditioner can be housed in a spare area of ​​the control circuitry. Embodiments of this disclosure can be implemented cost-effectively without increasing die size. In some embodiments, different or additional technical advantages can be achieved.

[0046] Figure 1 A schematic diagram of a memory device 100 according to some aspects of the present disclosure is shown. The memory device 100 includes control circuitry and an array of memory cells, each having a vertical transistor. The memory device 100 may include a memory array 101 and control circuitry 102 coupled to the memory array 101. The memory array 101 may be any suitable memory cell array, wherein each memory cell 108 includes a vertical transistor 110 and a storage element 112 coupled to the vertical transistor 110. In some embodiments, the memory array 101 is a DRAM cell array, and the storage element 112 is a capacitor for storing charge as binary information stored by the respective DRAM cells. In some embodiments, the memory array 101 is a PCM cell array, and the storage element 112 is a PCM element (e.g., including a chalcogenide alloy) for storing the binary information of the respective PCM cells based on the different resistivities of the PCM element in the amorphous and crystalline phases. In some implementations, the storage array 101 is an FRAM cell array, and the storage device 112 is a ferroelectric capacitor for storing binary information of each FRAM cell based on the switching between two polarization states of the ferroelectric material under an external electric field.

[0047] like Figure 1 As shown, the memory cells 108 can be arranged as a two-dimensional (2D) array with rows and columns. The memory device 100 may include word lines 104 that couple control circuitry 102 to the memory array 101 for controlling the switching of vertical transistors 110 in a row of memory cells 108. The memory device 100 may include bit lines 106 that couple control circuitry 102 to the memory array 101 for sending and / or receiving data from memory cells 108 in a column. That is, each word line 104 is coupled to a memory cell 108 in a corresponding row of the memory array 101, and each bit line is coupled to a memory cell 108 in a corresponding column of the memory array 101 (e.g., a string of memory cells 108).

[0048] In some implementations, memory cell 108 may include a vertical transistor 110 (e.g., a vertical metal-oxide-semiconductor field-effect transistor (MOSFET) instead of a planar transistor) as a transfer transistor to reduce the area occupied by the transfer transistor of memory cell 108, reduce coupling capacitance, and reduce interconnect wiring complexity. Figure 1 As shown, in some embodiments, unlike planar transistors where the active region is formed in a substrate, the vertical transistor 110 includes a semiconductor body 114 extending vertically (along the z-direction) above a substrate (not shown). That is, the semiconductor body 114 may extend above the top surface of the substrate, thereby exposing not only the top surface of the semiconductor body 114 but also one or more of its side surfaces. Figure 1 As shown, for example, the semiconductor body 114 may have a cuboid shape to expose its four sides. It should be understood that the semiconductor body 114 may have any suitable 3D shape, such as a polyhedral shape or a cylindrical shape. That is, the cross-section of the semiconductor body 114 in a planar view (e.g., in the xy plane) may have a square, rectangular (or trapezoidal), circular (or elliptical) or any other suitable shape.

[0049] like Figure 1 As shown, the vertical transistor 110 may further include a gate structure 116 (e.g., in one or more planes of the active region(s) side surfaces) that contacts one or more sides of the semiconductor body 114. In other words, the active region (e.g., the semiconductor body 114) of the vertical transistor 110 may be at least partially surrounded by the gate structure 116. The gate structure 116 may include a gate dielectric 118 (e.g., as shown in the figure) located on one or more sides of the semiconductor body 114. Figure 1As shown, it contacts the four sides of the semiconductor body 114. The gate structure 116 may also include a gate electrode 120 located on and in contact with the gate dielectric 118. The gate dielectric 118 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the gate dielectric 118 may include a gate oxide (e.g., silicon oxide). The gate electrode 120 may include any suitable conductive material, such as polysilicon, a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), a metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or a silicide. For example, the gate electrode 120 may include doped polysilicon, i.e., gate polysilicon. In some embodiments, the gate electrode 120 includes multiple conductive layers, such as a W layer over a TiN layer. It should be understood that in some examples, the gate electrode 120 and the word line 104 may be a continuous conductive structure. In other words, the gate electrode 120 can be considered as part of the word line 104 forming the gate structure 116, or the word line 104 can be considered as an extension of the gate electrode 120 for coupling to the control circuit 102.

[0050] like Figure 1 As shown, the vertical transistor 110 may further include a pair of source and drain electrodes (also referred to as source and drain electrodes) formed respectively at both ends of the semiconductor body 114 in the vertical direction (z-direction). The source and drain electrodes may be doped with any suitable P-type dopant (e.g., boron (B) or gallium (Ga)) or any suitable N-type dopant (e.g., phosphorus (P) or arsenic (As)). The source and drain electrodes may be separated in the vertical direction (z-direction) by a gate structure 116. In other words, the gate structure 116 is formed vertically between the source and drain electrodes. As a result, when the gate voltage applied to the gate electrode 120 of the gate structure 116 is higher than the threshold voltage of the vertical transistor 110, one or more channels (not shown) of the vertical transistor 110 may be formed vertically in the semiconductor body 114 between the source and drain electrodes. That is, according to some embodiments, each channel of the vertical transistor 110 is also formed in the vertical direction along which the semiconductor body 114 extends.

[0051] In some implementations, such as Figure 1 As shown, the vertical transistor 110 is a multi-gate transistor. That is, the gate structure 116 can be connected to more than one side of the semiconductor body 114 (e.g., Figure 1 The four sides of the semiconductor body 114 are contacted to form more than one gate, which allows more than one channel to be formed between the source and drain during operation. That is, unlike planar transistors that only include a single planar gate (and create a single planar channel), the 3D structure of the semiconductor body 114 and the gate structure 116 surrounding the multiple sides of the semiconductor body 114 enable the formation of more than one gate. Figure 1 The vertical transistor 110 shown may include multiple vertical gates on multiple sides of a semiconductor body 114. As a result, compared to planar transistors, Figure 1 The illustrated vertical transistor 110 can have a larger gate control area, achieving better channel control with a smaller subthreshold swing. During the off-state, the leakage current of the vertical transistor 110 can also be significantly reduced because the channel is fully depleted. Multi-gate vertical transistors can include dual-gate vertical transistors (e.g., dual-side-gate vertical transistors), tri-gate vertical transistors (e.g., tri-side-gate vertical transistors), and GAA vertical transistors.

[0052] It should be understood that, despite Figure 1 The vertical transistor 110 is shown as a multi-gate transistor, but as described in detail below, the vertical transistor disclosed herein may also include a single-gate transistor. That is, for example, to increase transistor and memory cell density, the gate structure 116 may contact a single side of the semiconductor body 114. It should also be understood that although the gate dielectric 118 is shown separated from other gate dielectrics of adjacent vertical transistors (not shown) (e.g., as a separate structure), the gate dielectric 118 may be part of a continuous dielectric layer of multiple gate dielectrics having vertical transistors.

[0053] In planar transistors and some lateral multi-gate transistors (e.g., FinFETs), the active region (e.g., the semiconductor body (e.g., a fin)) extends laterally (in the xy plane), and the source and drain are located at different positions in the same lateral plane (xy plane). In contrast, according to some embodiments, in the vertical transistor 110, the semiconductor body 114 extends vertically (in the z direction), and the source and drain are located in different lateral planes. In some embodiments, the source and drain are formed at opposite ends of the semiconductor body 114 in the vertical direction (z direction), thus overlapping in a planar view. As a result, the area occupied by the vertical transistor 110 (in the xy plane) can be reduced compared to planar transistors and lateral multi-gate transistors. Furthermore, since interconnects can be wired in different planes, the metal wiring coupled to the vertical transistor 110 can be simplified. For example, bit line 106 and memory device 112 can be formed on opposite sides of the vertical transistor 110. In one example, bit line 106 may be coupled to a source or drain at the upper end of semiconductor body 114, and memory device 112 may be coupled to another source or drain at the lower end of semiconductor body 114.

[0054] Figure 2An exemplary memory device 100 having a memory array 101 and exemplary control circuitry 102 according to some aspects of this disclosure is shown. Control circuitry 102 can be coupled to memory array 101 via bit line 106 and word line 104. Control circuitry 102 may include any suitable analog, digital, and mixed-signal circuitry to facilitate operation of memory array 101. Control circuitry 102 may include various types of circuitry formed using metal-oxide-semiconductor (MOS) technology. Exemplary control circuitry 102 includes control logic unit 202, address and bank decoder 204, row address decoder and latch 206, bank control logic unit 208, sense amplifier 210, data input / output (I / O) circuitry 212, column address decoder and latch 214, and voltage generator 226. In some examples, Figure 2 Additional circuitry, not shown, may also be included in control circuitry 102.

[0055] In some implementations, the storage array 101 may include a plurality of storage banks 211. Each storage bank 211 may include storage cells 108 arranged in rows and columns. The storage banks 211 can be accessed and operated independently of each other. Figure 2 In the example shown, memory array 101 includes memory banks 211a, 211b, and 211c (collectively referred to as 211). In other examples, memory array 101 may include any suitable number of memory banks 211. For example, memory array 101 may include memory banks 211 arranged in two rows, with each row having eight memory banks 211. In some implementations, each memory bank 211a, 211b, and 211c may be controlled by a corresponding row address decoder and latch 208a, 208b, and 208c (collectively referred to as 208), a corresponding sense amplifier 210a, 210b, and 210c (collectively referred to as 210), and a corresponding column address decoder and latch 214a, 214b, and 214c (collectively referred to as 214).

[0056] Control logic unit 202 can be configured to control the operation of other circuits in control circuitry 102. Control logic unit 202 may include command decoder 222, configured to decode commands received from memory device 100 (e.g., from a memory controller coupled to memory device 100) and generate instructions to be sent to other circuits (e.g., memory bank control logic unit 208 and row address decoder and latch 206). Control logic unit may also include multiple registers, such as mode register 224 storing configuration parameters, circuit states, preset data modes, etc. Different mode registers 224 or different groups of mode registers 224 can be designated for different purposes.

[0057] Address and memory bank decoder 204 can be configured to decode address signals received by memory device 100. Address and memory bank decoder 204 can send row address, column address, and signals indicating the selected memory bank 211 (e.g., decoded from address signals) to row address decoder and latch 206, column address decoder and latch 214, and memory bank control logic unit 208, respectively.

[0058] The row address decoder and latch 206 can be configured to decode the row address received from the address and memory decoder 204 and enable the word line 104 connected to a row memory cell 108 for writing or reading data based on the decoded row address.

[0059] The column address decoder and latch 214 can be configured to decode the column address received from the address and memory decoder 204 and enable the bit line 106 connected to a column memory cell 108 for writing or reading data based on the decoded column address.

[0060] The sense amplifier 210 can sense and amplify data in the memory cell and store the data in the memory cell. The sense amplifier 210 can be implemented using a cross-coupled amplifier connected between bit lines and complementary bit lines included in the memory array 101. See below for reference. Figure 11 A schematic diagram of an exemplary sensing amplifier is discussed in more detail.

[0061] The memory bank control logic unit 208 can be configured, for example, to control the operation of the selected memory bank 211 by controlling the row address decoders and latches 206a, 206b, 206c, column address decoders and latches 214a, 214b, 214c and / or sense amplifiers 210a, 210b, 210c corresponding to the selected memory banks 211a, 211b, 211c.

[0062] Data I / O circuitry 212 can write input data to memory array 101 and read output data from memory array 101. Data I / O circuitry 212 may include a read latch for temporarily holding data to be sent to the memory controller and a write latch for temporarily holding data received from the memory controller. In some embodiments, data input / output circuitry 212 may include a data masking logic unit configured to select portions of data, for example, by masking invalid data bits and holding valid data bits during read or write operations.

[0063] Voltage generator 226 can be configured to be controlled by control logic unit 202 and generate word line voltages (e.g., read voltage, programming voltage, pass voltage, verification voltage, etc.) and bit line voltages to be supplied to memory array 101. Voltage generator 226 may include regulator 228, which includes a word line regulator configured to supply power to word line 104 during read and write operations to activate or deactivate memory cells 108 coupled to word line 104. Regulator 228 may also include a bit line regulator configured to supply power to bit line 106 during data sensing. In some embodiments, bit line 106 in a memory bank 211 is coupled to at least one bit line regulator that can provide a bias voltage (e.g., at half the supply voltage) to bit line 106 via sense amplifier 210. The bit line regulator can charge the bit line to the bias voltage during a precharge phase, and the bias voltage can be used as a reference voltage during a sensing phase after the precharge phase. For example, during the sensing phase, the sensing amplifier 210 can amplify a small voltage difference between the bit line 106 and the reference voltage to determine whether the data stored in the memory cell 108 coupled to the bit line 106 is a logic "1" or a "0". This allows data to be read from the memory cell.

[0064] Figure 3 A layout diagram of an exemplary control circuit 102 is shown. The control circuit 102 may include peripheral circuitry 302 and memory circuitry 304.

[0065] Each memory bank circuit 304 can be coupled to a specific memory bank of the memory array (e.g., Figure 2 (Memory bank 211 in the memory). In some embodiments, memory bank circuitry 304 may include circuitry configured to control a particular memory bank. For example, memory bank circuitry 0 may include a row address decoder and latch 206a, a word line driver, a column address decoder and latch 214a, and a sense amplifier 210a coupled to the corresponding memory bank 211a; memory bank circuitry 1 may include a row address decoder and latch 208b, a word line driver, a column address decoder and latch 214b, and a sense amplifier 210b coupled to the corresponding memory bank 211b; and so on.

[0066] Peripheral circuitry 302 may include circuitry configured to control more than one memory bank. For example, peripheral circuitry 302 may include control logic unit 202, address and memory bank decoder 204, and data I / O circuitry 212.

[0067] In some embodiments, peripheral circuitry 302 may include one or more global bit line adjusters 312. Furthermore, in some embodiments, each bank circuit 304 may include a local bit line adjuster 314. The global bit line adjuster 312 is coupled to bit lines in more than one bank via a sense amplifier of the corresponding bank circuit 304. For example, peripheral circuitry 302 may include one global bit line adjuster 312 coupled to bit lines in all banks of the memory array and configured to power those bit lines. As another example, peripheral circuitry 302 may include two global bit line adjusters 312, each coupled to bit lines in a row of banks of the memory array and configured to power those bit lines. Local bit line adjusters 314 are coupled to bit lines in a specific bank (i.e., the bank corresponding to the bank circuit 304 that includes the local bit line adjuster 314) and configured to power those bit lines.

[0068] In some implementations, such as Figure 3 As shown, the peripheral circuitry 302 is arranged on one side of the memory circuitry. In some other embodiments, such as Figure 4 As shown, the peripheral circuit 302 may include a side peripheral circuit 402 disposed on one side of the memory bank circuit 304 and an intermediate peripheral circuit 404 disposed between the two rows of memory bank circuits 304.

[0069] Figure 4 An exemplary memory device 400 is shown (e.g., Figures 1-2 Memory device 100 in the memory array (e.g., memory array) Figure 1 The storage array 101 in the memory and the control circuit (e.g., Figure 1 The control circuitry 102 is formed on the same wafer. For example, the memory array of the memory device 400 includes 16 memory banks 406 (memory banks 0 to 15) arranged in two rows. Figure 2 The memory bank 211 can be an example of memory bank 406. The control circuitry of the memory device 400 may include 16 memory bank circuits 408 (e.g., Figure 3 The memory circuit 304 in the memory and the peripheral circuits (e.g., Figure 3 (External circuit 302 in the memory bank circuit). The peripheral circuit may include a side peripheral circuit 402 disposed on one side of the memory bank circuit 408 and an intermediate peripheral circuit 404 disposed between the two rows of memory bank circuits 408.

[0070] like Figure 4 As shown, the control circuitry for the memory array and memory device 400 can be formed on the same wafer. Coupled to each memory bank circuit 408 (e.g., Figure 3The memory circuit 304 and the memory cell 406 controlled by it can be integrally formed with the memory circuit 408 and arranged in the same region. For example, the memory circuit 408 can be formed around the corresponding memory cell 406.

[0071] In some implementations, the row address decoder (e.g., Figure 2 The row address decoder and latch 206 in the memory can be shared and arranged between two adjacent memory bank circuits 408. For example... Figure 4 As shown, the memory circuit coupled to memory bank 0 and the memory circuit coupled to memory bank 2 share a row address decoder arranged between the two memory bank circuits; the memory circuit coupled to memory bank 1 and the memory circuit coupled to memory bank 3 share a row address decoder arranged between the two memory bank circuits; and so on.

[0072] Figure 5A A schematic cross-sectional view of an exemplary memory device 500 is shown, wherein the memory array and control circuitry are formed on different wafers. Figures 1-2 The memory device 100 in the memory device 500 can be an example of the memory device 500.

[0073] Memory device 500 represents an example of a bonded chip. Components of memory device 500 (e.g., memory array and control circuitry) may be formed separately on different wafers and then bonded to form a bonded chip. Memory device 500 may include a first semiconductor structure 502, which includes a memory array (e.g., Figures 1-2 The memory device 500 may further include a second semiconductor structure 504, which includes control circuitry (e.g., memory array 101). Figures 1-3 The control circuit 102 in the second semiconductor structure 504 may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of the memory array. For example, the control circuitry may include one or more of the following: decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or voltage generators, current or voltage references, any portion (e.g., sub-circuits) of the aforementioned functional circuitry, or any active or passive component of the circuitry (e.g., transistors, diodes, resistors, or capacitors). According to some embodiments, the control circuitry in the second semiconductor structure 504 utilizes complementary metal-oxide-semiconductor (CMOS) technology, which may be implemented, for example, using logic processes (e.g., technology nodes such as 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, 22nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.).

[0074] like Figure 5A As shown, the memory device 500 may further include a first semiconductor structure 502, which includes a memory cell array (memory array) that can use transistors as switching and selection devices. In some embodiments, the memory array includes a DRAM cell array. For ease of description, a DRAM cell array may be used as an example for describing the memory array in this disclosure. However, it should be understood that the memory array is not limited to a DRAM cell array and may include any other suitable type of memory array that can use transistors as switching and selection devices, such as a PCM cell array, a static random access memory (SRAM) cell array, an FRAM cell array, a resistive memory array, a magnetic memory array, a spin-transfer torque (STT) memory array, or any combination thereof, to name just a few examples.

[0075] like Figure 5A As shown, the memory device 500 also includes a portion vertically located between the first semiconductor structure 502 and the second semiconductor structure 504 (in the vertical direction, for example, Figure 5A The bonding interface 506 is located in the z-direction of the semiconductor structure. As described in detail below, the first semiconductor structure 502 and the second semiconductor structure 504 can be manufactured separately (and in some embodiments in parallel), such that the thermal budget for manufacturing one of the first semiconductor structure 502 and the second semiconductor structure 504 does not limit the process for manufacturing the other of the first semiconductor structure 502 and the second semiconductor structure 504.

[0076] Furthermore, in contrast to long-distance (e.g., millimeter or centimeter-scale) chip-to-chip data buses on circuit boards (e.g., printed circuit boards (PCBs)), a large number of interconnects (e.g., contact structures) can be formed through bonding interface 506 to achieve direct, short-distance (e.g., micrometer-scale) electrical connections between the first semiconductor structure 502 and the second semiconductor structure 504, thereby eliminating chip interface latency and achieving high-speed I / O throughput with reduced power consumption. Data transfer between the memory array in the first semiconductor structure 502 and the control circuitry in the second semiconductor structure 504 can be performed through interconnects (e.g., contact structures) on bonding interface 506. For example, the first semiconductor structure 502 may include a first contact structure isolated by a first insulating material (e.g., silicon oxide) (e.g., made of a conductive material such as W and / or TiN), and the second semiconductor structure 504 may include a second contact structure isolated by a second insulating material (e.g., silicon oxide) (e.g., made of a conductive material such as W and / or TiN). The first semiconductor structure 502 and the second semiconductor structure 504 can be bonded together through contact between the first contact structure and the second contact structure. By vertically integrating the first semiconductor structure 502 and the second semiconductor structure 504, the chip size can be reduced and the memory cell density can be increased.

[0077] In some embodiments, when the first semiconductor structure 502 and the second semiconductor structure 504 are stacked and bonded together, each memory cell of the memory array in the first semiconductor structure 504 corresponds to a memory cell circuit of the control circuit in the xy plane (e.g., Figure 3 The memory circuitry 304 in the first semiconductor structure 502 overlaps or partially overlaps. This allows for high-speed data transmission between the memory array included in the first semiconductor structure 502 and the control circuitry included in the second semiconductor structure 504.

[0078] It should be understood that the relative positions of the stacked first semiconductor structure 502 and the second semiconductor structure 504 are not restricted. Figure 5B A schematic cross-sectional view of another exemplary memory device 501 is shown. Figure 5A The memory device 500 (which includes a first semiconductor structure 502 of a memory array situated on a second semiconductor structure 504 including control circuitry) differs from the memory device 500 in that... Figure 5BIn the memory device 501, a second semiconductor structure 504, including peripheral circuitry, is situated above a first semiconductor structure 502, including a memory array. Nevertheless, a bonding interface 506 is vertically formed between the first semiconductor structure 502 and the second semiconductor structure 504 in the memory device 501, and according to some embodiments, the first semiconductor structure 502 and the second semiconductor structure 504 are vertically joined by bonding (e.g., hybrid bonding). Hybrid bonding (also known as “metal / dielectric hybrid bonding”) is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer (e.g., solder or adhesive)) and can simultaneously achieve metal-to-metal (e.g., copper-to-copper) bonding and dielectric-to-dielectric (e.g., silicon oxide-to-silicon oxide) bonding. Data transfer between the memory array in the first semiconductor structure 502 and the control circuitry in the second semiconductor structure 504 can be performed via interconnects (e.g., contact structures) on the bonding interface 506.

[0079] Notice, Figure 5A and Figure 5B The x, y, and z axes are included to further illustrate the spatial relationships of components in memory devices 500 and 501. The substrate of the memory device may include two lateral surfaces extending laterally in the XY plane: a top surface on the front side of the substrate on which the memory device may be formed; and a bottom surface on the back side opposite the front side of the substrate. The Z direction is perpendicular to both the X and Y directions. As used in this disclosure, when the substrate is located in the lowest plane of the memory device in the Z direction, whether a component (e.g., a layer or device) of the semiconductor device is “on,” “above,” or “below” another component (e.g., a layer or device) is determined relative to the substrate of the memory device in the Z direction (a vertical direction perpendicular to the XY plane, such as the thickness direction of the substrate). The same concepts used to describe spatial relationships are applied throughout this disclosure.

[0080] Figure 6 An exemplary control circuit 600 including a global bit line adjuster is shown. The control circuit 600 includes a plurality of memory bank circuits 604 (including 604a and 604b) and peripheral circuitry 602 disposed on one side of the plurality of memory bank circuits 604. The control circuit 600 includes at least one global bit line adjuster 612 (including 612a and 612b) in the peripheral circuitry 602, while the memory bank circuits 604 do not include a bit line adjuster.

[0081] As an example, the peripheral circuitry 602 may include a global bit line modulator 612, which is sensed by a corresponding memory bank circuitry 604 (e.g., Figure 2 The sensing amplifier 210 in the memory is coupled to the bit line in the corresponding memory bank. For example... Figure 6In another example shown, the control circuitry 600 includes two rows of memory bank circuitry 604. A global bit line adjuster 612a (e.g., arranged in the upper portion of the peripheral circuitry 602) is coupled to a bit line in the memory bank corresponding to the memory bank circuitry 602a in the first row via a corresponding sense amplifier. A global bit line adjuster 612b (e.g., arranged in the lower portion of the peripheral circuitry 602) is coupled to a bit line in the memory bank corresponding to the memory bank circuitry 602b in the second row via a corresponding sense amplifier. It should be noted that the memory bank circuitry 604 can be arranged in any suitable number of rows, each row can include any suitable number of memory bank circuitry 604, and the peripheral circuitry 602 can include any suitable number of global bit line adjusters 612.

[0082] In some cases, due to some memory circuits (e.g., Figure 3 The memory circuits 14 and 15 in the memory bank circuits are different from other memory circuits (e.g., Figure 3 The memory bank circuits 0 and 1 in the memory bank circuits are further away from the peripheral circuit 602, therefore the sense amplifiers in these memory bank circuits (e.g., Figure 3 The metal wiring between the memory bank circuits 14 and 15 and the global bit line adjuster 612 may be longer. Therefore, when connecting to the memory bank corresponding to these memory bank circuits (e.g., ... Figure 4 When the bit lines in memory cells 14 and 15 are powered, there may be delayed transient response and large voltage drop.

[0083] Figure 7 An exemplary control circuit 700 including global bit line conditioners and local bit line conditioners is shown. The control circuit 700 includes a plurality of memory bank circuits 704 (including 704a and 704b) and peripheral circuitry 702 disposed on one side of the plurality of memory bank circuits 704. In addition to one or more global bit line conditioners 712 (including 712a and 712b) in the peripheral circuitry 702, the control circuit 700 also includes local bit line conditioners 714 (including 714a and 714b) in the memory bank circuits 704. The global bit line conditioners 712 and the local bit line conditioners 714 can form a power grid, wherein the bit lines in each memory bank are powered by both the global bit line conditioner 712 in the peripheral circuitry 702 and the local bit line conditioner 714 in the corresponding memory bank circuitry 704.

[0084] like Figure 7As shown, both the global bit line modulator 712a (e.g., in the upper portion of the peripheral circuit 702) and the local bit line modulator 714a in the memory bank circuit 704a are coupled to the bit lines in the memory bank corresponding to the memory bank circuit 704a and are configured to supply power to these bit lines. In some embodiments, the outputs of the global bit line modulator 712a and the local bit line modulator 714a are coupled together and then further coupled to a sense amplifier in the memory bank circuit 704a to supply power to the bit lines via the sense amplifier.

[0085] In some implementations, the global bit line modulator 712a is configured to power bit lines in more than one memory bank. For example, the global bit line modulator 712a may be configured to power all memory bank circuits in the first row (e.g., ...). Figure 3 The bit lines in the memory banks corresponding to memory bank circuits 1, ..., 13 and 15 in the first row are powered. The output of the global bit line adjuster 712a is coupled to the output of each local bit line adjuster in the memory bank circuits in the first row, and also coupled to the bit lines in the memory bank corresponding to the memory bank circuits in the first row. The global bit line adjuster 712a is configured to always operate, regardless of whether the memory bank corresponding to memory bank circuit 704a is in an active or inactive mode. The local bit line adjuster 714a is configured to power the bit lines in a specific memory bank (i.e., the memory bank corresponding to memory bank circuit 704a). Thus, the local bit line adjuster 714a can be configured to operate when the memory bank is in an active mode and be disabled when the memory bank is in an inactive mode.

[0086] Similarly, both the global bit line modulator 712b (e.g., in the lower portion of the peripheral circuitry 702) and the local bit line modulator 714b in the memory bank circuitry 704b are coupled to the bit lines in the memory bank corresponding to the memory bank circuitry 704b and are configured to supply power to these bit lines. In some embodiments, the outputs of the global bit line modulator 712b and the local bit line modulator 714b are coupled together and then further coupled to a sense amplifier in the memory bank circuitry 704b to supply power to the bit lines via the sense amplifier.

[0087] In some implementations, the global bit line modulator 712b is configured to power bit lines in more than one memory bank. For example, the global bit line modulator 712b may be configured to power all memory bank circuits in the second row (e.g., Figure 3The bit lines in the memory banks corresponding to memory bank circuits 0, ..., 12 and 14 in the second row are powered. The output of the global bit line adjuster 712b is coupled to the output of each local bit line adjuster in the memory bank circuit 704 in the second row, and also coupled to the bit lines in the memory bank corresponding to the memory bank circuit 704 in the second row. The global bit line adjuster 712b is configured to always operate, regardless of whether the memory bank corresponding to memory bank circuit 704b is in an active mode (e.g., when data is written to or read from the memory bank) or in an inactive mode. The local bit line adjuster 714b is configured to power the bit lines in a specific memory bank (i.e., the memory bank corresponding to memory bank circuit 704b). Therefore, the local bit line adjuster 714b can be configured to operate when the memory bank is in an active mode and be disabled when the memory bank is in an inactive mode.

[0088] In some implementations, the local bit line adjuster 714 may be arranged on the edge of the respective memory bank circuit 704. For example, the local bit line adjuster 714a may be arranged on one side (e.g., to the left, right, top, or bottom) of all block circuits 720a of the memory bank circuit 704a (e.g., circuits configured to control a particular memory block of the memory bank).

[0089] like Figure 7 As shown, the local bit line conditioner 714 is closer to the corresponding sense amplifier than the global bit line conditioner 712. Therefore, the power grid including the local bit line conditioner 714 and the global bit line conditioner 712 can improve transient response and reduce voltage drop when powering the bit line, making the bias voltage supplied to the bit line more stable.

[0090] Figure 8 An exemplary connection between memory bank circuit 704, local bit line adjuster 714 and global bit line adjuster 712 is shown.

[0091] Each global bitline regulator 712 (including 712a and 712b) has a first output (vblp1) and a second output (vb1p2). Each local bitline regulator 714 (including 714a and 714b) has a first output (vblp1) and a second output (vblp2). In some embodiments, the first outputs of all bitline regulators 712, 714 are coupled together and output the same voltage, and the second outputs of all bitline regulators 712, 714 are coupled together and output the same voltage. For example, as... Figure 8As shown, the first output of the global bit line regulator 712a is coupled to the first output of the local bit line regulator 714a; the second output of the global bit line regulator 712a is coupled to the second output of the local bit line regulator 714a; the first output of the global bit line regulator 712b is coupled to the first output of the local bit line regulator 714b; and the second output of the global bit line regulator 712b is coupled to the second output of the local bit line regulator 714b.

[0092] Furthermore, the first output of the local bit line modulator 714 can be coupled to the input of the local bit line modulator 714 to provide a feedback signal. The first output of the global bit line modulator 712 can be coupled to the input of the global bit line modulator 712 to provide a feedback signal.

[0093] In some implementations, the voltages from the first output (vblp1) and the second output (vblp2) have the same voltage value but opposite voltage phases. Furthermore, the bit lines in the memory can be numbered sequentially (e.g., from 0 to n). The first output (vb1p1) of the global bit line adjuster 712 and the first output (vb1p1) of the local bit line adjuster 714 can be coupled to the odd-numbered bit lines in the memory, for example, via sense amplifiers coupled to the odd-numbered bit lines. The second output (vblp2) of the global bit line adjuster 712 and the second output of the local bit line adjuster 714 can be coupled to the even-numbered bit lines in the memory, for example, via sense amplifiers coupled to the even-numbered bit lines.

[0094] Figure 9 A schematic diagram of an exemplary local bitline modulator 900 is shown. The local bitline modulator 900 can be... Figure 3 Local bitline modulator 314 and Figure 7 An example of a local bit line modulator 714. A local bit line modulator 900 may include one or more operational amplifiers 902 (including 902a and 902b).

[0095] like Figure 9As shown, operational amplifier 902a receives voltage (v3) as its first input and receives a first output (vblp1) as its second input. The output of operational amplifier 902a is coupled to the gate of one or more transistors 904a and 904b (e.g., P-MOS transistors). Operational amplifier 902b receives voltage (v1) as its first input and receives a first output (vblp1) as its second input. The output of operational amplifier 902b is coupled to the gate of one or more transistors 906a and 906b (e.g., N-MOS transistors). A transistor pair including transistors 904a and 906a is coupled between a power supply voltage (vdd2h) and a ground voltage and can output a first output (vblp1). A transistor pair including transistors 904b and 906b is coupled between a power supply voltage (vdd2h) and a ground voltage and can output a second output (vblp2).

[0096] In some implementations, each operational amplifier 902 may include an enable pin as an internal switch. The enable pin may receive a control signal indicating whether the operational amplifier 902 is enabled or disabled. For example, when the memory bank corresponding to the memory bank circuitry including the local bit line adjuster 900 is in an inactive mode, the operational amplifier 902 may be disabled, thereby disabling the local bit line adjuster 900.

[0097] Figure 10 A schematic diagram of an exemplary global bit line modulator 1000 is shown. The global bit line modulator 1000 can be... Figure 3 Global bitline regulator 312 and Figure 7 An example of the global bitline regulator 712 in the example.

[0098] Similar to the local bitline modulator 900, the global bitline modulator 1000 includes one or more operational amplifiers 1002 (including 1002a and 1002b). Operational amplifier 1002a receives a voltage (v3) as its first input and receives a first output (vblp1) as its second input. The output of operational amplifier 1002a is coupled to the gate of one or more transistors 1004a and 1004b (e.g., P-MOS transistors). Operational amplifier 1002b receives a voltage (v1) as its first input and receives a first output (vblp1) as its second input. The output of operational amplifier 1002b is coupled to the gate of one or more transistors 1006a and 1006b (e.g., N-MOS transistors). The transistor pair including transistors 1004a and 1006a is coupled between a power supply voltage (vdd2h) and a ground voltage and can output the first output (vblp1). The transistor pair, including transistors 1004b and 1006b, is coupled between the power supply voltage (vdd2h) and the ground voltage and can output a second output (vblp2).

[0099] In some implementations, unlike the local bit line regulator 900, the global bit line regulator 1000 may also include one or more capacitor-inductor pairs 1008. For example, the global bit line regulator 1000 may include a capacitor-inductor pair 1008 located between the output of each operational amplifier 1002 and a first / second output (vblp1 or vblp2). By having capacitor-inductor pairs 1008, the global bit line regulator 1000 can stabilize the voltage during transient load changes (e.g., by reducing oscillations). In contrast, by not having capacitor-inductor pairs, the local bit line regulator 900 can respond more quickly (e.g., by directly responding to changes without charging or discharging the capacitor-inductor pairs).

[0100] In some embodiments, the transistors in the local bit line adjuster 900 (including transistors 904, 906 and / or the transistors included in operational amplifier 902) may be smaller in size than the transistors in the global bit line adjuster 1000 (including transistors 1004, 1006 and / or the transistors included in operational amplifier 1002). Therefore, the area occupied by the local bit line adjuster 900 on the wafer may be smaller than that of the global bit line adjuster 1000, thereby allowing the local bit line adjuster 900 to be easily accommodated in the memory circuitry.

[0101] Figure 11 A schematic diagram of an exemplary sense amplifier 1100 is shown. The sense amplifier 210 may include a plurality of sense amplifiers 1100, wherein each sense amplifier 1100 may be coupled to a bit line in the memory bank (e.g., Figure 1Bit line 106 in the middle.

[0102] like Figure 11 As shown, the sense amplifier 1100 may include a cross-coupled amplifier between a bit line (bl) and a complementary bit line (blb). The cross-coupled amplifier may include two transistors 1102a and 1102b (e.g., P-MOS transistors). In some embodiments, the cross-coupled amplifier may include two N-MOS transistors. The cross-coupled amplifier may be controlled by two power supply signals (sp / sn), which can drive the bit line voltage to a higher or lower voltage.

[0103] For example, during the precharge phase, both the bit line (bl) and the complementary bit line (blb) can be precharged to the bias voltage, with the output (vblp) of the bit line regulator 900 or 1000 serving as the precharge power supply. During the sensing phase, the voltage of the bit line (bl) may change due to a small amount of charge from the memory cell connected to the bit line, while the voltage of the complementary bit line (blb) remains at the bias voltage. A cross-coupled amplifier can amplify the small voltage difference between the bit line (bl) and the complementary bit line (blb), making it possible to read data (e.g., logic "0" or logic "1") from the memory cell.

[0104] In some implementations, additional control signals (e.g., "sab" and "saa") can enable specific read / write functions of the sense amplifier during memory operation, thereby ensuring proper data flow to and from the memory array.

[0105] Figure 12 The performance of memory devices with and without local bit line adjusters is shown.

[0106] like Figure 12 As shown, in a circuit with control circuitry (e.g., Figure 6 In a memory device with a control circuit 600 (which has a global bit line conditioner but no local bit line conditioner), a large voltage drop may exist from the bit line conditioner to the bit line due to the long wiring between the global bit line conditioner and the bit line. For example, refer to... Figure 3 With the output voltage (vblp) of the bit line regulator approximately 500mV, the bit line voltage in memory bank 0 (e.g., the memory bank corresponding to memory bank circuit 0, which is closer to the global bit line regulator) can be supplied to 82% of the output voltage (vb1p), with a voltage drop of 18%. The bit line voltage in memory bank 15 (e.g., the memory bank corresponding to memory bank circuit 15, which is further away from the global bit line regulator) can be supplied to 79% of the output voltage (vblp), with a voltage drop exceeding 20%.

[0107] In contrast, in systems with control circuitry (e.g., Figure 7 In a memory device with a control circuit 700 (which includes both a global bit line regulator and a local bit line regulator), bit lines in the memory bank can respond to any bit line regulator closer to the memory bank. Therefore, the voltage drop from the bit line regulator to the bit line can be reduced. For example, refer to... Figure 3 With the output voltage (vblp) of the bit line regulator approximately 500mV, the bit line voltage in memory bank 0 (e.g., the memory bank corresponding to memory bank circuit 0, which is closer to the global bit line regulator) can be supplied to 99% of the output voltage (vb1p). The bit line voltage in memory bank 15 (e.g., the memory bank corresponding to memory bank circuit 15, which is further away from the global bit line regulator) can be supplied to 98% of the output voltage (vblp), where the voltage drop is only 2% or less.

[0108] Figure 13 A block diagram of a system 1300 having one or more memory devices according to one or more embodiments of the present disclosure is shown. System 1300 may be a mobile phone, desktop computer, laptop computer, tablet computer, server, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 13 As shown, system 1300 may include a host device 1308 and a memory system 1302, the memory system 1302 having one or more memory devices 1304 and a memory controller 1306. Host device 1308 may include a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). Host device 1308 may be configured to send data to or receive data from one or more memory devices 1304.

[0109] Memory device 1304 can be any memory device disclosed herein, such as Figures 1-12The memory device 1304 is shown in any of the embodiments described herein. In some embodiments, the memory device 1304 includes DRAM memory. A memory controller 1306 (also referred to as controller circuitry) is coupled to the memory device 1304 and the host device 1308. Consistent with embodiments of this disclosure, the memory device 1304 may include a plurality of conductive interconnects through a cover layer that contact conductive pads in a conductive pad layer, and the memory controller 1306 may be coupled to the memory device 1304 through at least one of the plurality of conductive interconnects. The memory controller 1306 is configured to control the memory device 1304. The memory controller 1306 may manage data stored in the memory device 1304 and communicate with the host device 1308.

[0110] In some embodiments, the memory controller 1306 is designed / configured to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones. In some embodiments, the memory controller 1306 is designed / configured to operate in a high duty cycle environment, such as a memory card, graphics memory, or SSD used as data storage for mobile devices (e.g., smartphones, tablets, laptops, etc.), and enterprise storage arrays. The memory controller 1306 may be configured to control the operation of the memory device 1304, such as read, program (or write) operations. The memory controller 1306 may also be configured to manage various functions associated with data stored or to be stored in the memory device 1304, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 1306 is also configured to process error correction codes (ECC) associated with reading or writing data from or to the memory device 1304. The memory controller 1306 may also perform any other appropriate function, such as formatting the memory device 1304.

[0111] The memory controller 1306 can communicate with external devices (e.g., host device 1308) according to a specific communication protocol. For example, the memory controller 1306 can communicate with external devices through at least one of various interface protocols, such as USB protocol, Peripheral Component Interconnect (PCI) protocol, High Speed ​​PCI (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, FireWire protocol, etc.

[0112] This disclosure describes a semiconductor structure for managing a memory device. One aspect of this disclosure features a memory device. The memory device includes a memory array (e.g., Figures 1-3 The storage array 101 in the memory includes multiple memory banks (e.g., Figure 2 Storage 211 in Figure 4 The memory device also includes control circuitry (e.g., storage 406). Figure 7 The control circuit 700 includes a first regulator (e.g., a bit line regulator coupled to a first memory bank (e.g., the memory bank corresponding to memory bank circuit 704a) among a plurality of memory banks. Figure 7 Global bit line modulator 712a in Figure 10 The global bit line regulator 1000 in the first memory bank). The control circuit also includes a second regulator (e.g., a global bit line regulator 1000) coupled to the bit lines in the first memory bank. Figure 7 Local bit line adjuster 714a in Figure 9 (Local bitline regulator 900 in the middle). The output of the first regulator is coupled to the output of the second regulator.

[0113] In some implementations, the second regulator is closer to the first storage unit than the first regulator.

[0114] In some implementations, the control circuitry also includes a third regulator (e.g., with...). Figure 7 The memory bank circuit 704a in the memory bank circuit is located in the same row as the local bit line regulator included in the memory bank circuit. The third regulator is coupled to the second memory bank in the plurality of memory banks (e.g., and with). Figure 7 The bit lines in the memory bank 704 (located in the corresponding memory bank of the memory bank circuit in the same row) are also coupled to the first regulator. The output of the third regulator is coupled to the output of the first regulator.

[0115] In some embodiments, the control circuitry includes multiple memory bank circuits corresponding to multiple memory banks (e.g., Figure 7 The memory bank circuit 704 is included in the control circuit. The control circuit also includes peripheral circuitry (e.g., arranged on one side of the plurality of memory bank circuits) Figure 7 (External circuit 702). The second regulator is included in the first memory circuit corresponding to the first memory, and the first regulator is included in the peripheral circuit.

[0116] In some implementations, each of the plurality of memory bank circuits includes a corresponding second regulator (e.g., a local bit line regulator) coupled to a bit line in the corresponding memory bank of the plurality of memory banks.

[0117] In some embodiments, the first memory bank circuitry further includes one or more sense amplifiers (e.g., ) coupled to bit lines in the first memory bank. Figure 11 The sense amplifier 1100 in the memory, and one or more word line drivers coupled to word lines in the first memory bank. Peripheral circuitry includes input / output circuitry for the memory device (e.g., ...). Figure 2 (Data I / O circuit 212 in the middle).

[0118] In some implementations, the second regulator is located at the edge of the first memory circuit.

[0119] In some implementations, a first output (e.g., vblp1) of the first regulator is coupled to a first output (e.g., vblp1) of the second regulator in the first memory circuit. A second output (e.g., vblp2) of the first regulator is coupled to a second output (e.g., vblp2) of the second regulator in the first memory circuit.

[0120] In some embodiments, the bit lines in the first memory are numbered sequentially. The first output of the first regulator and the first output of the second regulator are coupled to the odd-numbered bit lines in the first memory. The second output of the first regulator and the second output of the second regulator are coupled to the even-numbered bit lines in the first memory.

[0121] In some embodiments, the first regulator includes one or more first operational amplifiers, one or more first transistors, and one or more capacitors. The second regulator includes one or more second operational amplifiers and one or more second transistors.

[0122] In some implementations, the transistors included in one or more second operational amplifiers are smaller in size than the transistors included in one or more first operational amplifiers.

[0123] In some implementations, the first regulator is configured to operate when the first memory is in an inactive mode and when the first memory is in an active mode. The second regulator is configured to operate when the first memory is in an active mode and to be disabled when the first memory is in an inactive mode.

[0124] In some implementations, the second regulator is configured to be disabled by an internal switch in the corresponding second operational amplifier within the second regulator.

[0125] Another aspect of this disclosure features a memory device. The memory device includes a first semiconductor structure and a second semiconductor structure stacked with the first semiconductor structure. The first semiconductor structure has a memory array including a plurality of memory cells. The second semiconductor structure includes control circuitry. The control circuitry includes a plurality of memory cell circuits corresponding to the plurality of memory cells, and peripheral circuitry disposed on one side of the plurality of memory cells. The peripheral circuitry includes a first regulator coupled to a bit line in the first memory cell. The first memory cell circuitry corresponding to the first memory cell includes a second regulator coupled to a bit line in the first memory cell.

[0126] In some embodiments, the first semiconductor structure includes a first contact structure isolated by a first insulating material, and the second semiconductor structure includes a second contact structure isolated by a second insulating material. The first semiconductor structure and the second semiconductor structure are bonded together through contact between the first contact structure and the second contact structure.

[0127] In some implementations, multiple memory bank circuits are arranged in two rows. The first regulator (e.g., Figure 7 The output of the global bit-line regulator 712a in the first row is coupled to the output of the second regulator in the memory bank circuitry in the first row. The peripheral circuitry also includes an additional first regulator (e.g., Figure 7 The global bit line regulator 712b in the second row is coupled to the output of the second regulator in the memory bank circuit in the second row.

[0128] In some embodiments, the control circuitry includes multiple memory bank circuits corresponding to multiple memory banks (e.g., Figure 7 The memory bank circuit 704 is included in the control circuit. The control circuit also includes peripheral circuitry (e.g., arranged on one side of the plurality of memory bank circuits) Figure 7 (External circuit 702). The second regulator is included in the first memory circuit corresponding to the first memory, and the first regulator is included in the peripheral circuit.

[0129] In some implementations, each of the plurality of memory bank circuits includes a corresponding second regulator coupled to a bit line in the corresponding memory bank of the plurality of memory banks.

[0130] In some implementations, the second regulator is located at the edge of the first memory circuit.

[0131] Another aspect of this disclosure features a memory system. The memory system includes a memory device and a memory controller, the memory controller being coupled to the memory device and configured to control the memory device. The memory device includes a memory array comprising a plurality of memory banks. The memory device also includes control circuitry. The control circuitry includes: a first regulator coupled to bit lines in a first memory bank of the plurality of memory banks, and a second regulator coupled to bit lines in the first memory bank. The output of the first regulator is coupled to the output of the second regulator.

[0132] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some implementations," etc., in this disclosure indicate that the described embodiments may include specific features, structures, or characteristics, but not every embodiment must include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other implementations is within the knowledge of those skilled in the art.

[0133] Generally, terms can be understood at least partly from their usage in context. For example, depending at least partly on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least partly on the context, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage. Additionally, again depending at least partly on the context, the term "based on" can be understood to not necessarily convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described.

[0134] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” not only means “directly on something,” but also includes the meaning of “on something” with an intermediate feature or layer between them. Furthermore, “above” or “on top of” not only means “above something” or “on top of something,” but can also include the meaning of “above something” or “on top of something” without an intermediate feature or layer between them (i.e., directly on something).

[0135] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or feature and another (or more) elements or features as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the apparatus during use or process steps. The apparatus may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0136] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. A substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where semiconductor devices are formed, and therefore, unless otherwise stated, semiconductor devices are formed on the top side of the substrate. The bottom surface is opposite to the top surface, and therefore, the bottom side of the substrate is opposite to the top side of the substrate. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.

[0137] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer may extend over the entire lower or upper overlay structure, or may have a range smaller than that of the lower or upper overlay structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure having a thickness smaller than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive and contact layers (where contacts, interconnect lines, and / or vertical interconnect channels (VIAs) are formed) and one or more dielectric layers.

[0138] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter set for a component or process step during the design phase of a product or process, and the range of values ​​higher and / or lower than the expected value. As used herein, the range of values ​​may be due to minor variations in manufacturing processes or tolerances. As used herein, the term "about" indicates the value of a given quantity that may vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" may indicate the value of a given quantity that varies within, for example, 10-30% of that value (e.g., ±10%, ±20%, or ±30% of the value).

[0139] In this disclosure, the terms "horizontal / horizontally / laterally" mean nominally parallel to the lateral surface of the substrate, and the term "vertical / vertically" means nominally perpendicular to the lateral surface of the substrate.

[0140] This disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features can be in direct contact, and may also include embodiments where an additional feature can be formed between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or constructions discussed.

[0141] The descriptions of specific implementation methods described above can be easily modified and / or adjusted for various applications. Therefore, based on the teachings and guidance provided herein, such adjustments and modifications are intended to fall within the meaning and scope of equivalents of the disclosed implementation methods.

[0142] While this disclosure contains numerous specific implementation details, these should not be construed as limiting the scope of the claims as defined by the claims themselves, but rather as descriptions of features that may be implemented for specific embodiments of a particular invention. In the context of individual embodiments, certain features described in this disclosure may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations and even initially claimed in this way, one or more features from the claimed combination may be removed from the combination in some cases, and the claims may be for sub-combinations or variations thereof.

[0143] Similarly, although operations are depicted in the accompanying drawings in a specific order and referenced in the claims, this should not be construed as requiring the operations to be performed in the specific order or sequence shown, or requiring all shown operations to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0144] Specific embodiments of the subject matter have been described. Other embodiments are also within the scope of the following claims. For example, the actions cited in the claims can be performed in a different order and still achieve the desired result. As an example, the process depicted in the drawings does not necessarily require the specific order or sequence shown to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous.

[0145] The breadth and scope of this disclosure should not be limited to any of the embodiments described above, but should be defined solely by the following claims and their equivalents.

Claims

1. A memory device, comprising: A storage array, comprising multiple storage units; as well as Control circuit, including: A first regulator, the first regulator being coupled to a bit line in a first memory bank of the plurality of memory banks; and A second regulator is coupled to the bit line in the first memory bank, wherein the output of the first regulator is coupled to the output of the second regulator.

2. The memory device according to claim 1, wherein, The second regulator is closer to the first storage unit than the first regulator.

3. The memory device according to claim 1, wherein, The control circuit also includes: A third regulator is coupled to a bit line in a second memory bank of the plurality of memory banks, wherein the bit line in the second memory bank is also coupled to the first regulator, and wherein the output of the third regulator is coupled to the output of the first regulator.

4. The memory device according to claim 1 or 2, wherein, The control circuit includes: Multiple memory bank circuits corresponding to the plurality of memory banks; and Peripheral circuitry arranged on one side of the plurality of memory bank circuits. The second regulator is included in a first memory circuit corresponding to the first memory, and the first regulator is included in the peripheral circuit.

5. The memory device according to claim 4, wherein, Each of the plurality of memory bank circuits includes a corresponding second regulator coupled to a bit line in the corresponding memory bank.

6. The memory device according to claim 4 or 5, wherein, The first memory circuit also includes: One or more sense amplifiers coupled to the bit lines in the first memory bank; and One or more word line drivers coupled to word lines in the first memory bank, and wherein the peripheral circuitry further includes: The input / output circuit of the memory device.

7. The memory device according to any one of claims 4 to 6, wherein, The second regulator is located at the edge of the first memory circuit.

8. The memory device according to any one of claims 4 to 7, wherein, The first output of the first regulator is coupled to the first output of the second regulator in the first memory circuit, and The second output of the first regulator is coupled to the second output of the second regulator in the first storage circuit.

9. The memory device according to claim 8, wherein, The bit lines in the first memory bank are numbered sequentially. Wherein, the first output of the first regulator and the first output of the second regulator are coupled to odd-numbered bit lines in the bit lines of the first memory bank, and The second output of the first regulator and the second output of the second regulator are coupled to even-numbered bit lines in the bit lines of the first memory bank.

10. The memory device according to any one of claims 1 to 9, wherein, The first regulator includes one or more first operational amplifiers, one or more first transistors, and one or more capacitors, and The second regulator includes one or more second operational amplifiers and one or more second transistors.

11. The memory device according to claim 10, wherein, The transistors included in the one or more second operational amplifiers are smaller in size than the transistors included in the one or more first operational amplifiers.

12. The memory device according to any one of claims 1 to 11, wherein, The first regulator is configured to operate when the first memory is in an inactive mode and when the first memory is in an active mode, and The second regulator is configured to operate when the first storage is in the active mode and to be disabled when the first storage is in the inactive mode.

13. The memory device according to claim 12, wherein, The second regulator is configured to be disabled by an internal switch in the corresponding second operational amplifier within the second regulator.

14. A memory device, comprising: A first semiconductor structure, the first semiconductor structure including a memory array, the memory array including a plurality of memory cells; as well as A second semiconductor structure stacked with the first semiconductor structure, wherein the second semiconductor structure includes a control circuit, the control circuit comprising: Multiple memory bank circuits corresponding to the plurality of memory banks; and Peripheral circuitry arranged on one side of the plurality of memory bank circuits. The peripheral circuitry includes a first regulator, which is coupled to a bit line in a first memory bank among the plurality of memory banks. The first memory bank circuit corresponding to the first memory bank includes a second regulator, wherein the second regulator is coupled to the bit line in the first memory bank.

15. The memory device according to claim 14, wherein, The first semiconductor structure includes a first contact structure isolated by a first insulating material. The second semiconductor structure includes a second contact structure isolated by a second insulating material, and The first semiconductor structure and the second semiconductor structure are bonded together through the contact between the first contact structure and the second contact structure.

16. The memory device according to claim 14 or 15, wherein, The plurality of memory bank circuits are arranged in two rows. The output of the first regulator is coupled to the output of the second regulator in the memory circuit of the first row, and The peripheral circuitry further includes an additional first regulator, the output of which is coupled to the output of a second regulator in the memory circuitry of the second row.

17. The memory device according to any one of claims 14 to 16, wherein, The control circuit includes: Multiple memory bank circuits corresponding to the plurality of memory banks; and Peripheral circuitry arranged on one side of the plurality of memory bank circuits. The second regulator is included in a first memory circuit corresponding to the first memory, and the first regulator is included in the peripheral circuit.

18. The memory device according to claim 17, wherein, Each of the plurality of memory bank circuits includes a corresponding second regulator coupled to a bit line in the corresponding memory bank.

19. The memory device according to claim 17 or 18, wherein, The second regulator is located at the edge of the first memory circuit.

20. A memory system, comprising: A memory device, the memory device comprising: A storage array, comprising a plurality of storage cells; and Control circuit, the control circuit comprising: A first regulator, the first regulator being coupled to a bit line in a first memory bank of the plurality of memory banks; and A second regulator, coupled to the bit line in the first memory bank, wherein the output of the first regulator is coupled to the output of the second regulator; and A memory controller, which is coupled to the memory device and configured to control the memory device.

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