Pixel circuit and display device including same

Abstract

The utility model relates to a pixel circuit and a display device comprising the same. The pixel circuit includes a driving transistor, a first capacitor including a first electrode and a second electrode, a write transistor writing a data voltage to a control electrode of the driving transistor in response to a write gate signal, a first emission transistor supplying a first power supply voltage to a second electrode of the first capacitor in response to a first emission signal, and a second emission transistor supplying a second power supply voltage to the second electrode of the second capacitor. A first initialization transistor that supplies a first initialization voltage to a control electrode of the driving transistor in response to an initialization gate signal; a second initialization transistor that supplies a second initialization voltage to a second electrode of the driving transistor in response to a bias gate signal; and a light emitting element that emits light.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a pixel circuit capable of compensating for a threshold voltage of a driving transistor and a display device including the pixel circuit. Background Art

[0002] Typically, a display device may include a display panel, a gate driver, a data driver, and a timing controller. The display panel may include a plurality of gate lines, a plurality of data lines, and a plurality of pixels electrically connected to the gate lines and the data lines. The gate driver may provide a gate signal to the gate line, the data driver may provide a data voltage to the data line, and the timing controller may control the gate driver and the data driver.

[0003] The display device may differ in characteristics such as a threshold voltage of a driving transistor of each pixel due to process variations, etc. Therefore, in order to improve display quality, the threshold voltage of the driving transistor may be compensated in each pixel. Utility Model Content

[0004] An object of the present disclosure is to provide a pixel circuit capable of compensating for a threshold voltage of a driving transistor by using capacitor coupling.

[0005] Another object of the present disclosure is to provide a display device including the pixel circuit.

[0006] However, the purpose of the present disclosure may not be limited thereto. Therefore, the purpose of the present disclosure may be expanded without departing from the spirit and scope of the present disclosure.

[0007] According to an embodiment, a pixel circuit may include: a driving transistor configured to generate a driving current; a first capacitor including a first electrode and a second electrode; a write transistor configured to write a data voltage to a control electrode of the driving transistor in response to a write gate signal; a first emission transistor configured to provide a first power supply voltage to the second electrode of the first capacitor in response to a first emission signal; a first initialization transistor configured to provide a first initialization voltage to the control electrode of the driving transistor in response to an initialization gate signal; a second initialization transistor configured to provide a second initialization voltage to the second electrode of the driving transistor in response to a bias gate signal; and a light-emitting element receiving the driving current to emit light.

[0008] In an embodiment, the pixel circuit may further include: a second capacitor including a first electrode receiving the first power supply voltage and a second electrode electrically connected to the second electrode of the first capacitor, and the first electrode of the first capacitor may be electrically connected to the control electrode of the driving transistor.

[0009] In an embodiment, the initialization gate signal and the bias gate signal may have an active period in a first period, the write gate signal may have an active period in a second period after the first period, and the first emission signal may have an active period in a third period after the second period.

[0010] In an embodiment, the pixel circuit may further include: a second emission transistor configured to electrically connect the first electrode of the driving transistor to the second electrode of the first capacitor in response to the second emission signal, and the first electrode of the first capacitor may be electrically connected to the control electrode of the driving transistor.

[0011] In an embodiment, the pixel circuit may further include: a third capacitor including a first electrode configured to receive the second emission signal and a second electrode electrically connected to the second electrode of the first capacitor.

[0012] In an embodiment, the initialization gate signal, the bias gate signal, and the second emission signal may have an activation period in a first period, the write gate signal may have an activation period in a second period after the first period, the first emission signal may have an activation period in a third period after the second period, and the first emission signal and the second emission signal may have an activation period in a fourth period after the third period.

[0013] In an embodiment, the pixel circuit may further include: a second emission transistor configured to electrically connect the control electrode of the driving transistor to the first electrode of the first capacitor in response to the first emission signal.

[0014] In an embodiment, the pixel circuit may further include: a third capacitor including a first electrode receiving the first power supply voltage and a second electrode connected to the control electrode of the driving transistor.

[0015] In an embodiment, the pixel circuit may further include: a compensation reference transistor configured to provide the first power supply voltage to the first electrode of the first capacitor in response to the write gate signal.

[0016] In an embodiment, the initialization gate signal and the bias gate signal may have an active period in a first period, the bias gate signal and the write gate signal may have an active period in a second period after the first period, and the first emission signal may have an active period in a third period after the second period.

[0017] According to an embodiment, the first initialization voltage may be equal to the second initialization voltage.

[0018] According to an embodiment, a display device may include: a display panel including a pixel circuit; a gate driver configured to provide a write gate signal, an initialization gate signal and a bias gate signal to the pixel circuit; an emission driver configured to provide a first emission signal to the pixel circuit; a data driver configured to provide a data voltage to the pixel circuit; and a timing controller configured to control the gate driver, the emission driver and the data driver, where the pixel circuit may include: a driving transistor configured to generate a driving current; a first capacitor including a first electrode and a second electrode; a write transistor configured to write a data voltage to a control electrode of the driving transistor in response to the write gate signal; a first emission transistor configured to provide a first power supply voltage to the second electrode of the first capacitor in response to the first emission signal; a first initialization transistor configured to provide a first initialization voltage to the control electrode of the driving transistor in response to the initialization gate signal; a second initialization transistor configured to provide a second initialization voltage to the second electrode of the driving transistor in response to the bias gate signal; and a light-emitting element configured to receive the driving current to emit light.

[0019] In an embodiment, the pixel circuit may further include: a second capacitor including a first electrode configured to receive the first power supply voltage and a second electrode electrically connected to the second electrode of the first capacitor, and the first electrode of the first capacitor may be electrically connected to the control electrode of the driving transistor.

[0020] In an embodiment, the initialization gate signal and the bias gate signal may have an active period in a first period, the write gate signal may have an active period in a second period after the first period, and the first emission signal may have an active period in a third period after the second period.

[0021] In an embodiment, the emission driver may be configured to further provide a second emission signal to the pixel circuit, and in addition, the pixel circuit may further include: a second emission transistor, configured to electrically connect the first electrode of the driving transistor to the second electrode of the first capacitor in response to the second emission signal, and the first electrode of the first capacitor may be electrically connected to the control electrode of the driving transistor.

[0022] In an embodiment, the pixel circuit may further include: a third capacitor including a first electrode configured to receive the second emission signal and a second electrode electrically connected to the second electrode of the first capacitor.

[0023] In an embodiment, the initialization gate signal, the bias gate signal, and the second emission signal may have an activation period in a first period, the write gate signal may have an activation period in a second period after the first period, the first emission signal may have an activation period in a third period after the second period, and the first emission signal and the second emission signal may have an activation period in a fourth period after the third period.

[0024] In an embodiment, the pixel circuit may further include: a second emission transistor configured to electrically connect the control electrode of the driving transistor to the first electrode of the first capacitor in response to the first emission signal.

[0025] In an embodiment, the pixel circuit may further include: a third capacitor including a first electrode receiving the first power supply voltage and a second electrode connected to the control electrode of the driving transistor.

[0026] According to an embodiment, the pixel circuit may further include: a compensation reference transistor configured to provide the first power supply voltage to the first electrode of the first capacitor in response to the write gate signal.

[0027] Therefore, according to an embodiment, a pixel circuit may include: a driving transistor configured to generate a driving current; a first capacitor including a first electrode and a second electrode; a write transistor configured to write a data voltage to a control electrode of the driving transistor in response to a write gate signal; a first emission transistor configured to provide a first power supply voltage to the second electrode of the first capacitor in response to a first emission signal; a first initialization transistor configured to provide a first initialization voltage to the control electrode of the driving transistor in response to an initialization gate signal; a second initialization transistor configured to provide a second initialization voltage to the second electrode of the driving transistor in response to a bias gate signal; and a light-emitting element configured to receive the driving current to emit light, so that threshold voltage compensation using capacitor coupling can be performed with a small number of transistors.

[0028] In addition, the display device according to the embodiment may include a pixel circuit capable of compensating for the threshold voltage of the driving transistor by using a capacitor coupling, so that the display device can be advantageous for high-speed driving in terms of compensation time compared to a case in which the driving transistor can be diode-connected to compensate for the threshold voltage.

[0029] However, the effects of the present disclosure may not be limited thereto. Therefore, the effects of the present disclosure may be expanded without departing from the spirit and scope of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects and features of the present disclosure will become more apparent by describing the embodiments of the present disclosure in detail with reference to the accompanying drawings, in which:

[0031] Figure 1 is a schematic block diagram showing a display device according to an embodiment of the present disclosure;

[0032] Figure 2 yes Figure 1 A schematic diagram of an equivalent circuit of a pixel circuit of a display device;

[0033] Figure 3 Is shown driving Figure 2 A schematic timing diagram of an example of a pixel circuit;

[0034] Figure 4 is a schematic diagram of an equivalent circuit of a pixel circuit according to an embodiment of the present disclosure;

[0035] Figure 5 Is shown driving Figure 4 A schematic timing diagram of an example of a pixel circuit;

[0036] Figure 6 It shows that the first period of driving Figure 4 A schematic diagram of an example of a pixel circuit;

[0037] Figure 7 It shows that the drive Figure 4 A schematic diagram of an example of a pixel circuit;

[0038] Figure 8 It is shown that the drive Figure 4 A schematic diagram of an example of a pixel circuit;

[0039] Fig. 9 It is shown that the drive Figure 4 A schematic diagram of an example of a pixel circuit;

[0040] Fig.10 is a schematic timing diagram showing an example of a driving pixel circuit according to an embodiment of the present disclosure;

[0041] Fig.11 is a schematic diagram of an equivalent circuit of a pixel circuit according to an embodiment of the present disclosure;

[0042] Fig.12 Is shown driving Fig.11 A schematic timing diagram of an example of a pixel circuit;

[0043] Fig.13 It shows that the first period of driving Fig.11 A schematic diagram of an example of a pixel circuit;

[0044] Fig.14 It shows that the drive Fig.11A schematic diagram of an example of a pixel circuit;

[0045] Fig.15 It is shown that the drive Fig.11 A schematic diagram of an example of a pixel circuit;

[0046] Fig.16 is a schematic block diagram showing an electronic device according to an embodiment of the present disclosure; and

[0047] Fig.17 It shows that Fig.16 A schematic diagram of an example in which the electronic device is implemented as a smart phone. DETAILED DESCRIPTION

[0048] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the utility model. As used herein, "embodiment" and "implementation" are interchangeable words as non-limiting examples of the device or method disclosed herein. However, it is apparent that various embodiments can be practiced without these specific details or with one or more equivalent arrangements. Here, various embodiments do not have to be exclusive, nor do they have to limit the present disclosure. For example, the specific shape, configuration and characteristics of an embodiment can be used or implemented in another embodiment.

[0049] Unless otherwise specified, the illustrated embodiments should be understood to provide exemplary features of the present invention. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects of various embodiments (hereinafter individually or collectively referred to as "elements") may be combined, separated, interchanged and / or rearranged in other ways without departing from the concept of the present invention.

[0050] When an element or layer is referred to as being "on" another element or layer, "connected to" or "coupled to" another element or layer, the element or layer may be directly on another element or layer, directly connected to or coupled to another element or layer, or there may be an intervening element or layer. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there is no intervening element or layer. For this reason, the term "connection" may refer to a physical, electrical and / or fluid connection with or without an intervening element. Further, the X-axis, Y-axis and Z-axis are not limited to the three axes of a rectangular coordinate system, such as an x-axis, a y-axis and a z-axis, and may be interpreted in a broader sense. For example, the X-axis, the Y-axis and the Z-axis may be perpendicular to each other, or may be different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of A and B" may be interpreted as only A, only B, or any combination of A and B. Furthermore, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as any combination of only X, only Y, only Z, or two or more of X, Y, and Z. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0051] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0052] The terms used herein are used for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, the singular forms "a" and "the (said)" are intended to also include plural forms, unless the context clearly indicates otherwise. In addition, when used in this specification, the terms "include" and / or "comprise" indicate the existence of stated features, wholes, steps, operations, elements, parts and / or their groups, but do not exclude the existence or addition of one or more other features, wholes, steps, operations, elements, parts or their groups.

[0053] Various embodiments are described herein with reference to cross-sectional illustrations and / or exploded illustrations that are schematic illustrations of embodiments and / or intermediate structures. As such, variations in the illustrated shapes as a result of, for example, manufacturing techniques and / or tolerances, may be expected. Therefore, the embodiments disclosed herein need not be construed as limited to the specific illustrated shapes of the regions, but rather should include deviations in shape resulting from, for example, manufacturing. In this manner, the regions illustrated in the accompanying drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and therefore need not be intended to be limiting.

[0054] Hereinafter, embodiments of the present disclosure will be explained in detail with reference to the accompanying drawings.

[0055] Figure 1 is a schematic block diagram illustrating a display device according to an embodiment of the present disclosure.

[0056] refer to Figure 1 , the display device may include a display panel 100, a timing controller 200, a gate driver 300, a data driver 400, and an emission driver 500. According to an embodiment, the timing controller 200 and the data driver 400 may be integrated on one chip.

[0057] The display panel 100 may include a display portion AA configured to display an image and a peripheral portion PA that may be adjacent to the display portion AA. According to one embodiment, the gate driver 300 and the emission driver 500 may be mounted on the peripheral portion PA.

[0058] The display panel 100 may include a plurality of gate lines GL, a plurality of data lines DL, a plurality of emission lines EL, and a plurality of pixel circuits P electrically connected to the gate lines GL, the data lines DL, and the emission lines EL. The gate lines GL and the emission lines EL may extend in a first direction D1, and the data lines DL may extend in a second direction D2 crossing the first direction D1.

[0059] The timing controller 200 may receive input image data IMG and an input control signal CONT from a main processor (e.g., a graphics processing unit (GPU), etc.). For example, the input image data IMG may include red image data, green image data, and blue image data. According to one embodiment, the input image data IMG may further include white image data. As another example, the input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a main clock signal and a data enable signal. The input control signal CONT may further include a vertical synchronization signal and a horizontal synchronization signal.

[0060] The timing controller 200 may generate a first control signal CONT1 , a second control signal CONT2 , a third control signal CONT3 , and a data signal DATA based on input image data IMG and an input control signal CONT.

[0061] The timing controller 200 may generate a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT to output the generated first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0062] The timing controller 200 may generate a second control signal CONT2 for controlling the operation of the data driver 400 based on the input control signal CONT to output the generated second control signal CONT2 to the data driver 400. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0063] The timing controller 200 may receive input image data IMG and an input control signal CONT to generate a data signal DATA. The timing controller 200 may output the data signal DATA to the data driver 400.

[0064] The timing controller 200 may generate a third control signal CONT3 for controlling the operation of the emission driver 500 based on the input control signal CONT to output the generated third control signal CONT3 to the emission driver 500. The third control signal CONT3 may include a vertical start signal and an emission clock signal.

[0065] The gate driver 300 may generate a gate signal for driving the gate line GL in response to the first control signal CONT1 received from the timing controller 200. The gate driver 300 may output the gate signal to the gate line GL. For example, the gate driver 300 may sequentially output the gate signal to the gate line GL.

[0066] The data driver 400 may receive the second control signal CONT2 and the data signal DATA from the timing controller 200. The data driver 400 may generate a data voltage obtained by converting the data signal DATA into an analog voltage. The data driver 400 may output the data voltage to the data line DL.

[0067] The emission driver 500 may generate emission signals for driving the emission lines EL in response to the third control signal CONT3 received from the timing controller 200. The emission driver 500 may output the emission signals to the emission lines EL. For example, the emission driver 500 may sequentially output the emission signals to the emission lines EL.

[0068] Figure 2 yes Figure 1 Schematic diagram of an equivalent circuit of an example of a pixel circuit P of a display device.

[0069] refer to Figure 2, the pixel circuit P may include a driving transistor T1 configured to generate (or transmit) a driving current, a first capacitor C1 including a first electrode electrically connected to a control electrode of the driving transistor T1 and a second electrode electrically connected to the first electrode of the driving transistor T1, a write transistor T2 configured to write a data voltage VDATA to the first capacitor C1 in response to a write gate signal GW, a first emission transistor T3 configured to provide a first power supply voltage ELVDD (e.g., a high power supply voltage) to the second electrode of the first capacitor C1 in response to a first emission signal EM1, a first initialization transistor T4 configured to provide a first initialization voltage VINT to the first electrode of the first capacitor C1 in response to an initialization gate signal GI, a second initialization transistor T5 configured to provide a second initialization voltage VAINT to the second electrode of the driving transistor T1 in response to a bias gate signal GB, and a light emitting element EE configured to receive the driving current to emit light. According to an embodiment, the pixel circuit P may further include a second capacitor C2 including a first electrode configured to receive the first power supply voltage ELVDD and a second electrode electrically connected to the second electrode of the first capacitor C1.

[0070] For example, the driving transistor T1 may include a control electrode connected to the first node N1, a first electrode connected to the second node N2, and a second electrode connected to the third node N3. The write transistor T2 may include a control electrode configured to receive a write gate signal GW, a first electrode configured to receive a data voltage VDATA, and a second electrode connected to the first node N1. The first emission transistor T3 may include a control electrode configured to receive a first emission signal EM1, a first electrode configured to receive a first power supply voltage ELVDD, and a second electrode connected to the second node N2. The first initialization transistor T4 may include a control electrode configured to receive an initialization gate signal GI, a first electrode configured to receive a first initialization voltage VINT, and a second electrode connected to the first node N1. The second initialization transistor T5 may include a control electrode configured to receive a bias gate signal GB, a first electrode configured to receive a second initialization voltage VAINT, and a second electrode connected to the third node N3. The first capacitor C1 may include a first electrode connected to the first node N1 and a second electrode connected to the second node N2. The second capacitor C2 may include a first electrode configured to receive a first power supply voltage ELVDD and a second electrode connected to the second node N2. The light emitting element EE may include a first electrode connected to the third node N3 and a second electrode configured to receive a second power voltage ELVSS (eg, a low power voltage).

[0071] According to one embodiment, the first initialization voltage VINT may be equal to the second initialization voltage VAINT. According to one embodiment, the second initialization voltage VAINT may be equal to the second power supply voltage ELVSS.

[0072] The driving transistor T1, the writing transistor T2, the first emission transistor T3, the first initialization transistor T4 and the second initialization transistor T5 may be implemented as p-channel metal oxide semiconductor (PMOS) transistors. Figure 3 VL) can be an activation level, and a high voltage level (e.g., Figure 3 The VH of the PMOS transistor may be a deactivation level. For example, when the signal applied to the control electrode of the PMOS transistor has a low voltage level, the PMOS transistor may be turned on. For example, when the signal applied to the control electrode of the PMOS transistor has a high voltage level, the PMOS transistor may be turned off. The activation period may be a period with an activation level when the transistor is turned on, and the deactivation period may be a period with a deactivation level when the transistor is turned off.

[0073] However, the present disclosure may not be limited thereto. For example, the driving transistor T1 , the writing transistor T2 , the first emission transistor T3 , the first initialization transistor T4 , and the second initialization transistor T5 may be implemented as n-channel metal oxide semiconductor (NMOS) transistors.

[0074] Figure 3 Is shown driving Figure 2 A schematic timing diagram of an example of a pixel circuit P is shown in FIG.

[0075] refer to Figure 2 and Figure 3 , in the first period P1, the initialization gate signal GI and the bias gate signal GB may have an activation period, and the write gate signal GW and the first emission signal EM1 may have a deactivation period. Accordingly, the first initialization transistor T4 and the second initialization transistor T5 may be turned on, the first initialization voltage VINT may be applied to the first node N1, and the second initialization voltage VAINT may be applied to the third node N3. Therefore, the voltage of the first node N1 may be VINT, and the voltage of the second node N2 may be VAINT-VTH, where VINT may be the first initialization voltage, VAINT may be the second initialization voltage, and VTH may be the threshold voltage of the driving transistor T1.

[0076] In the second period P2 after the first period P1, the write gate signal GW may have an activation period, and the initialization gate signal GI, the bias gate signal GB, and the first emission signal EM1 may have a deactivation period. Accordingly, the write transistor T2 may be turned on, and the data voltage VDATA may be applied to the first node N1. In addition, according to the coupling of the first capacitor C1, the voltage of the second node N2 may increase by (C_C1 / (C_C1+C_C2))×(VDATA-VINT). Therefore, the voltage of the first node N1 may be VDATA, and the voltage of the second node N2 may be VAINT-VTH+(C_C1 / (C_C1+C_C2))×(VDATA-VINT), where VDATA may be the data voltage, VAINT may be the second initialization voltage, VTH may be the threshold voltage of the driving transistor T1, C_C1 may be the capacitance of the first capacitor C1, and C_C2 may be the capacitance of the second capacitor C2.

[0077] In a third period P3 after the second period P2, the first emission signal EM1 may have an activation period, and the initialization gate signal GI, the bias gate signal GB, and the write gate signal GW may have a deactivation period. Accordingly, the first emission transistor T3 may be turned on, and the first power supply voltage ELVDD may be applied to the second node N2. In addition, according to the coupling of the first capacitor C1, the voltage of the first node N1 may increase by ELVDD-(VAINT-VTH+(C_C1 / (C_C1+C_C2))×(VDATA-VINT)). Therefore, the voltage of the first node N1 can be VDATA+ELVDD-(VAINT-VTH+(C_C1 / (C_C1+C_C2))×(VDATA-VINT)), and the voltage of the second node N2 can be ELVDD, where VDATA can be the data voltage, ELVDD can be the first power supply voltage, VAINT can be the second initialization voltage, VTH can be the threshold voltage of the driving transistor T1, C_C1 can be the capacitance of the first capacitor C1, and C_C2 can be the capacitance of the second capacitor C2.

[0078] In the third period P3 in which the light emitting element EE emits light, the driving transistor T1 may generate a driving current corresponding to the gate-source voltage, and the gate-source voltage may be VDATA-(VAINT-VTH+(C_C1 / (C_C1+C_C2))×(VDATA-VINT)). Since the gate-source voltage of the driving transistor T1 includes a data voltage component and a threshold voltage component, the driving current may include a data voltage component but not a threshold voltage component. In other words, the threshold voltage of the driving transistor T1 may be compensated.

[0079] Figure 4is a schematic diagram of an equivalent circuit of a pixel circuit P′ according to an embodiment of the present disclosure.

[0080] refer to Figure 4 , the pixel circuit P' may include a driving transistor T1 configured to generate a driving current, a first capacitor C1 including a first electrode electrically connected to a control electrode of the driving transistor T1 and a second electrode electrically connected to a second node N2, a write transistor T2 configured to write a data voltage VDATA to the first capacitor C1 in response to a write gate signal GW, a first emission transistor T3 configured to provide a first power supply voltage ELVDD to the second electrode of the first capacitor C1 in response to a first emission signal EM1, a first initialization transistor T4 configured to provide a first initialization voltage VINT to the first electrode of the first capacitor C1 in response to an initialization gate signal GI, a second initialization transistor T5 configured to provide a second initialization voltage VAINT to the second electrode of the driving transistor T1 in response to a bias gate signal GB, and a light emitting element EE configured to receive the driving current to emit light. The second electrode of the first capacitor C1 may also be electrically connected to the first electrode of the driving transistor T1 through the second emission transistor T6 when the second emission transistor T6 is activated. According to one embodiment, the pixel circuit P' may further include a second capacitor C2 including a first electrode configured to receive the first power supply voltage ELVDD and a second electrode electrically connected to the second electrode of the first capacitor C1.

[0081] According to one embodiment, the pixel circuit P' may further include a second emission transistor T6 configured to electrically connect the first electrode of the driving transistor T1 to the second electrode of the first capacitor C1 in response to the second emission signal EM2. According to one embodiment, the pixel circuit P' may further include a third capacitor C3 including a first electrode configured to receive the second emission signal EM2 and a second electrode electrically connected to the second electrode of the first capacitor C1.

[0082] For example, the driving transistor T1 may include a control electrode connected to the first node N1, a first electrode connected to the second electrode of the second emission transistor T6, and a second electrode connected to the third node N3. The write transistor T2 may include a control electrode configured to receive a write gate signal GW, a first electrode configured to receive a data voltage VDATA, and a second electrode connected to the first node N1. The first emission transistor T3 may include a control electrode configured to receive a first emission signal EM1, a first electrode configured to receive a first power supply voltage ELVDD, and a second electrode connected to the second node N2. The first initialization transistor T4 may include a control electrode configured to receive an initialization gate signal GI, a first electrode configured to receive a first initialization voltage VINT, and a second electrode connected to the first node N1. The second initialization transistor T5 may include a control electrode configured to receive a bias gate signal GB, a first electrode configured to receive a second initialization voltage VAINT, and a second electrode connected to the third node N3. The first capacitor C1 may include a first electrode connected to the first node N1 and a second electrode connected to the second node N2. The second capacitor C2 may include a first electrode configured to receive a first power supply voltage ELVDD and a second electrode connected to the second node N2. The light emitting element EE may include a first electrode connected to the third node N3 and a second electrode configured to receive the second power supply voltage ELVSS. The second emission transistor T6 may include a control electrode configured to receive the second emission signal EM2, a first electrode connected to the second node N2, and a second electrode connected to the first electrode of the driving transistor T1. The third capacitor C3 may include a first electrode configured to receive the second emission signal EM2 and a second electrode connected to the second node N2.

[0083] According to one embodiment, the first initialization voltage VINT may be equal to the second initialization voltage VAINT. According to one embodiment, the second initialization voltage VAINT may be equal to the second power supply voltage ELVSS.

[0084] The driving transistor T1, the writing transistor T2, the first emission transistor T3, the first initialization transistor T4, the second initialization transistor T5, and the second emission transistor T6 may be implemented as PMOS transistors. The low voltage level may be an activation level, and the high voltage level may be a deactivation level. For example, in the case where the signal applied to the control electrode of the PMOS transistor has a low voltage level, the PMOS transistor may be turned on. For example, in the case where the signal applied to the control electrode of the PMOS transistor has a high voltage level, the PMOS transistor may be turned off.

[0085] However, the present disclosure may not be limited thereto. For example, the driving transistor T1 , the writing transistor T2 , the first emission transistor T3 , the first initialization transistor T4 , the second initialization transistor T5 , and the second emission transistor T6 may be implemented as NMOS transistors.

[0086] Figure 5 Is shown driving Figure 4 A schematic timing diagram of an example of a pixel circuit P', Figure 6 It shows that the first period P1 is driven Figure 4 A schematic diagram of an example of a pixel circuit P', Figure 7 It shows that the driving Figure 4 A schematic diagram of an example of a pixel circuit P', Figure 8 It shows that the driving Figure 4 A schematic diagram of an example of a pixel circuit P', and Fig. 9 It shows that the drive Figure 4 Schematic diagram of an example of a pixel circuit P'.

[0087] refer to Figure 5 and Figure 6 , in the first period P1, the initialization gate signal GI, the bias gate signal GB, and the second emission signal EM2 may have an activation period, and the write gate signal GW and the first emission signal EM1 may have a deactivation period. Accordingly, the first initialization transistor T4, the second initialization transistor T5, and the second emission transistor T6 may be turned on, the first initialization voltage VINT may be applied to the first node N1, and the second initialization voltage VAINT may be applied to the third node N3. Therefore, the voltage of the first node N1 may be VINT, and the voltage of the second node N2 may be VAINT-VTH, where VINT may be the first initialization voltage, VAINT may be the second initialization voltage, and VTH may be the threshold voltage of the driving transistor T1.

[0088] refer to Figure 5 and Figure 7In the second period P2 after the first period P1, the write gate signal GW may have an activation period, and the initialization gate signal GI, the bias gate signal GB, the first emission signal EM1 and the second emission signal EM2 may have a deactivation period. Accordingly, the write transistor T2 may be turned on, and the data voltage VDATA may be applied to the first node N1. In addition, the voltage of the second node N2 may increase by (C_C1 / (C_C1+C_C2+C_C3))×(VDATA-VINT) according to the coupling of the first capacitor C1, and may increase by (C_C3 / (C_Cl+C_C2+C_C3))×(VH-VL) according to the coupling of the third capacitor C3. Therefore, the voltage of the first node N1 can be VDATA, and the voltage of the second node N2 can be VAINT-VTH+(C_C1 / (C_C1+C_C2+C_C3))×(VDATA-VINT)+(C_C3 / (C_Cl+C_C2+C_C3))×(VH-VL), where VDATA can be the data voltage, VAINT can be the second initialization voltage, VTH can be the threshold voltage of the driving transistor T1, C_C1 can be the capacitance of the first capacitor C1, C_C2 can be the capacitance of the second capacitor C2, C_C3 can be the capacitance of the third capacitor C3, VH can be the high voltage level, and VL can be the low voltage level.

[0089] refer to Figure 5 and Figure 8, in a third period P3 after the second period P2, the first emission signal EM1 may have an activation period, and the initialization gate signal GI, the bias gate signal GB, the write gate signal GW and the second emission signal EM2 may have a deactivation period. Accordingly, the first emission transistor T3 may be turned on, and the first power supply voltage ELVDD may be applied to the second node N2. In addition, according to the coupling of the first capacitor C1, the voltage of the first node N1 may increase by ELVDD-(VAINT-VTH+(C_C1 / (C_C1+C_C2+C_C3))×(VDATA-VINT)+(C_C3 / (C_Cl+C_C2+C_C3))×(VH-VL)). Therefore, the voltage of the first node N1 can be VDATA+ELVDD-(VAINT-VTH+(C_C1 / (C_C1+C_C2+C_C3))×(VDATA-VINT)+(C_C3 / (C_Cl+C_C2+C_C3))×(VH-VL)), and the voltage of the second node N2 can be ELVDD, where VDATA can be the data voltage, ELVDD can be the first power supply voltage, VAINT can be the second initialization voltage, VTH can be the threshold voltage of the driving transistor T1, C_C1 can be the capacitance of the first capacitor C1, C_C2 can be the capacitance of the second capacitor C2, C_C3 can be the capacitance of the third capacitor C3, VH can be the high voltage level, and VL can be the low voltage level.

[0090] refer to Figure 5 and Fig. 9 , in a fourth period P4 after the third period P3, the driving transistor T1 may generate a driving current corresponding to the gate-source voltage, and the gate-source voltage may be ELVDD-(VAINT-VTH+(C_C1 / (C_C1+C_C2+C_C3))×(VDATA-VINT)+(C_C3 / (C_Cl+C_C2+C_C3))×(VH-VL)). Since the gate-source voltage of the driving transistor T1 includes a data voltage component and a threshold voltage component, the driving current may include a data voltage component but not a threshold voltage component. In other words, the threshold voltage of the driving transistor T1 may be compensated.

[0091] Fig.10 1 is a schematic timing diagram showing an example of a driving pixel circuit according to an embodiment of the present disclosure.

[0092] Since the pixel circuit according to the embodiment may have the same Figure 4 The configuration of the pixel circuit P′ is substantially the same as the configuration of EMBODIMENT 2, so the same reference numerals and reference signs will be used for the same or similar components, and redundant description will be omitted.

[0093] refer to Fig.10 , the length of the activation period of the bias gate signal GB may be longer than the length of the activation period of the initialization gate signal GI. In order to ensure the time when the voltage corresponding to the second initialization voltage VAINT is charged in all the capacitors of the first capacitor C1, the second capacitor C2 and the third capacitor C3, the length of the activation period of the bias gate signal GB may be increased.

[0094] Fig.11 is a schematic diagram showing an equivalent circuit of a pixel circuit P″ according to an embodiment of the present disclosure.

[0095] refer to Fig.11 , the pixel circuit P″ may include a driving transistor T1 configured to generate a driving current, a first capacitor C1 including a first electrode electrically connected to a fourth node N4 and a second electrode electrically connected to the first electrode of the driving transistor T1, a write transistor T2 configured to write a data voltage VDATA to a control electrode of the driving transistor T1 in response to a write gate signal GW, a first emission transistor T3 configured to provide a first power supply voltage ELVDD to the second electrode of the first capacitor C1 in response to a first emission signal EM1, a first initialization transistor T4 configured to provide a first initialization voltage VINT to the control electrode of the driving transistor T1 and the first node N1 in response to an initialization gate signal GI, a second initialization transistor T5 configured to provide a second initialization voltage VAINT to the second electrode of the driving transistor T1 in response to a bias gate signal GB, and a light emitting element EE configured to receive the driving current to emit light. According to one embodiment, the pixel circuit P″ may further include a second capacitor C2 including a first electrode configured to receive the first power supply voltage ELVDD and a second electrode electrically connected to the second electrode of the first capacitor C1.

[0096] According to one embodiment, the pixel circuit P" may further include a second emission transistor T6 configured to electrically connect the control electrode of the driving transistor T1 to the first electrode of the first capacitor C1 in response to the first emission signal EM1. According to one embodiment, the pixel circuit P" may further include a third capacitor C3 including a first electrode configured to receive the first power supply voltage ELVDD and a second electrode connected to the control electrode of the driving transistor T1. According to one embodiment, the pixel circuit P" may further include a compensation reference transistor T7 configured to provide the first power supply voltage ELVDD to the first electrode of the first capacitor C1 in response to the write gate signal GW.

[0097] For example, the driving transistor T1 may include a control electrode connected to the first node N1, a first electrode connected to the second node N2, and a second electrode connected to the third node N3. The write transistor T2 may include a control electrode configured to receive a write gate signal GW, a first electrode configured to receive a data voltage VDATA, and a second electrode connected to the first node N1. The first emission transistor T3 may include a control electrode configured to receive a first emission signal EM1, a first electrode configured to receive a first power supply voltage ELVDD, and a second electrode connected to the second node N2. The first initialization transistor T4 may include a control electrode configured to receive an initialization gate signal GI, a first electrode configured to receive a first initialization voltage VINT, and a second electrode connected to the first node N1. The second initialization transistor T5 may include a control electrode configured to receive a bias gate signal GB, a first electrode configured to receive a second initialization voltage VAINT, and a second electrode connected to the third node N3. The first capacitor C1 may include a first electrode connected to the fourth node N4 and a second electrode connected to the second node N2. The second capacitor C2 may include a first electrode configured to receive a first power supply voltage ELVDD and a second electrode connected to the second node N2. The light emitting element EE may include a first electrode connected to the third node N3 and a second electrode configured to receive the second power supply voltage ELVSS. The second emission transistor T6 may include a control electrode configured to receive the first emission signal EM1, a first electrode connected to the first node N1, and a second electrode connected to the fourth node N4. The third capacitor C3 may include a first electrode configured to receive the first power supply voltage ELVDD and a second electrode connected to the control electrode of the driving transistor T1. The compensation reference transistor T7 may include a control electrode configured to receive the write gate signal GW, a first electrode configured to receive the first power supply voltage ELVDD, and a second electrode connected to the fourth node N4.

[0098] According to one embodiment, the first initialization voltage VINT may be equal to the second initialization voltage VAINT. According to one embodiment, the second initialization voltage VAINT may be equal to the second power supply voltage ELVSS.

[0099] The driving transistor T1, the writing transistor T2, the first emission transistor T3, the first initialization transistor T4, the second initialization transistor T5, the second emission transistor T6 and the compensation reference transistor T7 may be implemented as PMOS transistors. The low voltage level may be an activation level, and the high voltage level may be a deactivation level. For example, in the case where the signal applied to the control electrode of the PMOS transistor has a low voltage level, the PMOS transistor may be turned on. For example, in the case where the signal applied to the control electrode of the PMOS transistor has a high voltage level, the PMOS transistor may be turned off.

[0100] However, the present disclosure may not be limited thereto. For example, the driving transistor T1 , the writing transistor T2 , the first emission transistor T3 , the first initialization transistor T4 , the second initialization transistor T5 , the second emission transistor T6 , and the compensation reference transistor T7 may be implemented as NMOS transistors.

[0101] Fig.12 Is shown driving Fig.11 A schematic timing diagram of an example of a pixel circuit P" is shown in FIG. Fig.13 It shows that the first period P1 is driven Fig.11 A schematic diagram of an example of a pixel circuit P" is shown in FIG. Fig.14 It shows that the driving Fig.11 A schematic diagram of an example of a pixel circuit P" is shown in FIG. Fig.15 It shows that the driving Fig.11 Schematic diagram of an example of a pixel circuit P".

[0102] refer to Fig.12 and Fig.13 , in the first period P1, the initialization gate signal GI and the bias gate signal GB may have an activation period, and the write gate signal GW and the first emission signal EM1 may have a deactivation period. Accordingly, the first initialization transistor T4 and the second initialization transistor T5 may be turned on, the first initialization voltage VINT may be applied to the first node N1, and the second initialization voltage VAINT may be applied to the third node N3. Therefore, the voltage of the first node N1 may be VINT, and the voltage of the second node N2 may be VAINT-VTH, where VINT may be the first initialization voltage, VAINT may be the second initialization voltage, and VTH may be the threshold voltage of the driving transistor T1.

[0103] refer to Fig.12 and Fig.14, in the second period P2 after the first period P1, the bias gate signal GB and the write gate signal GW may have an activation period, and the initialization gate signal GI and the first emission signal EM1 may have a deactivation period. Accordingly, the write transistor T2, the second initialization transistor T5, and the compensation reference transistor T7 may be turned on, the data voltage VDATA may be applied to the first node N1, the second initialization voltage VAINT may be applied to the third node N3, and the first power supply voltage ELVDD may be applied to the fourth node N4. In addition, the voltage of the first node N1 may be VDATA, and due to the current path formed by the driving transistor T1, the voltage of the second node N2 may be VDATA-VTH, where VDATA may be the data voltage, VTH may be the threshold voltage of the driving transistor T1, and ELVDD may be the first power supply voltage.

[0104] refer to Fig.12 and Fig.15 In the third period P3 after the second period P2, the first emission signal EM1 may have an activation period, and the initialization gate signal GI, the bias gate signal GB and the write gate signal GW may have a deactivation period. Accordingly, the first emission transistor T3 and the second emission transistor T6 may be turned on.

[0105] In the second period P2, the charge amount of the first capacitor C1 may be C_C1×(ELVDD-(VDATA-VTH)), and the charge amount of the third capacitor C3 may be C_C3×(VDATA-ELVDD). In addition, without considering the coupling of the first capacitor C1, in the third period P3, the charge amount of the first capacitor C1 may be C_C1×(V_N1-ELVDD), and the charge amount of the third capacitor C3 may be C_C3×(V_N1-ELVDD). In addition, since the sum of the charge amounts of the first capacitor C1 and the third capacitor C3 in the second period P2 may be equal to the sum of the charge amounts of the first capacitor C1 and the third capacitor C3 in the third period P3 before considering the coupling of the first capacitor C1, V_N1 may be (2×C_C1×ELVDD+(C_C3-C_C1)×VDATA+C_C1×VTH) / (C_C1+C_C3). In addition, according to the coupling of the first capacitor C1, the voltage of the first node N1 may increase by (C_C1 / (C_C1+C_C3))×(ELVDD-(VDATA-VTH)). Therefore, the voltage of the first node N1 may be (2×C_C1×ELVDD+(C_C3-C_C1)×VDATA+C_C1×VTH) / (C_C1+C_C3)+(C_C1 / (C_Cl+C_C3))×(ELVDD-(VDATA-VTH)), and the voltage of the second node N2 may be ELVDD. In summary, the voltage of the first node N1 can be ((3×C_C1) / (C_C1+C_C3))×ELVDD+((C_C3-2×C_C1) / (C_C1+C_C3))×VDATA+((2×C_C1) / (C_C1+C_C3))×VTH, where V_N1 can be the voltage of the first node N1 in the third period P3 before considering the coupling of the first capacitor C1, C_C1 can be the capacitance of the first capacitor C1, C_C3 can be the capacitance of the third capacitor C3, ELVDD can be the first power supply voltage, and VTH can be the threshold voltage of the driving transistor T1.

[0106] In the third period P3 when the light emitting element EE emits light, the driving transistor T1 may generate a driving current corresponding to the gate-source voltage, and the gate-source voltage may be ((3×C_C1) / (C_C1+C_C3)-1)×ELVDD+((C_C3-2×C_C1) / (C_C1+C_C3))×VDATA+((2×C_C1) / (C_C1+C_C3))×VTH. Since the gate-source voltage of the driving transistor T1 includes a data voltage component and a threshold voltage component, the driving current may include a data voltage component and a threshold voltage component having a value less than the threshold voltage. In other words, a portion of the threshold voltage of the driving transistor T1 may be compensated.

[0107] Fig.16 is a schematic block diagram showing an electronic device 1000 according to an embodiment of the present disclosure, and Fig.17 It shows that Fig.16 The electronic device 1000 is a schematic diagram of an example in which the electronic device 1000 may be implemented as a smart phone.

[0108] refer to Fig.16 and Fig.17 , the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. Here, the display device 1060 may be Figure 1 In addition, the electronic device 1000 may further include a plurality of ports for communicating with a graphics card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, etc. In an embodiment, as Fig.17 As shown in , the electronic device 1000 may be implemented as a smart phone. However, the electronic device 1000 may not be limited thereto. For example, the electronic device 1000 may be implemented as a cellular phone, a video phone, a smart tablet, a smart watch, a tablet PC, a car navigation system, a computer monitor, a notebook computer, a head mounted display (HMD) device, etc.

[0109] The processor 1010 may perform various computing functions. The processor 1010 may be a microprocessor, a central processing unit (CPU), an application processor (AP), etc. The processor 1010 may be coupled to other components via an address bus, a control bus, a data bus, etc. In addition, the processor 1010 may be coupled to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0110] The memory device 1020 may store data for operation of the electronic device 1000. For example, the memory device 1020 may include at least one nonvolatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc. and / or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, etc.

[0111] The storage device 1030 may include a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, or the like.

[0112] I / O devices 1040 may include input devices such as a keyboard, a keypad, a mouse device, a touch pad, a touch screen, etc. and output devices such as a printer, a speaker, etc. In some embodiments, I / O devices 1040 may include a display device 1060 .

[0113] The power supply 1050 may provide power for the operation of the electronic device 1000. For example, the power supply 1050 may be a power management integrated circuit (PMIC).

[0114] The display device 1060 may display an image corresponding to the visual information of the electronic device 1000. In some embodiments, the display device 1060 may be an organic light emitting display device or a quantum dot light emitting display device, but may not be limited thereto. The display device 1060 may be connected to other components via a bus or other communication links.

[0115] The present disclosure may be applied to a display device and an electronic device including the display device. For example, the present disclosure may be applied to a digital television, a 3D television, a smart phone, a cellular phone, a personal computer (PC) (e.g., a tablet PC or a laptop computer), a virtual reality (VR) device, a home appliance, a personal digital assistant (PDA), a portable media player (PMP), a digital camera, a music player, a portable game console, a car navigation system, etc.

[0116] The foregoing may be illustrative of embodiments and may not be construed as limiting the embodiments. Although several embodiments have been described, it will be readily appreciated by those skilled in the art that many modifications may be possible in the embodiments without substantially departing from the novel teachings and advantages of the present disclosure. Accordingly, all such modifications may be intended to be included within the scope of the present disclosure as defined in the claims. Therefore, it will be appreciated that the foregoing may be illustrative of various embodiments and may not be construed as being limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments may be intended to be included within the scope of the claims.

Claims

1. A pixel circuit, include: a drive transistor configured to transmit a drive current; a write transistor configured to write a data voltage to a control electrode of the drive transistor in response to a write gate signal; a light emitting element, receiving the driving current to emit light, Characterized in that the pixel circuit further comprises: A first capacitor including a first electrode and a second electrode; a first emission transistor configured to provide a first power supply voltage to the second electrode of the first capacitor in response to a first emission signal; a first initialization transistor configured to provide a first initialization voltage to the control electrode of the driving transistor in response to an initialization gate signal; and The second initialization transistor is configured to provide a second initialization voltage to the second electrode of the driving transistor in response to a bias gate signal.

2. The pixel circuit according to claim 1, It is characterized in that The pixel circuit further comprises: a second capacitor including a first electrode receiving the first power supply voltage and a second electrode electrically connected to the second electrode of the first capacitor, The first electrode of the first capacitor is electrically connected to the control electrode of the driving transistor.

3. The pixel circuit according to claim 1, in, The initialization gate signal and the bias gate signal have an active period in a first period, The write gate signal has an active period in a second period after the first period, and The first transmission signal has an activation period in a third period after the second period.

4. The pixel circuit according to claim 1, It is characterized in that The pixel circuit further comprises: a second emission transistor configured to electrically connect the first electrode of the driving transistor to the second electrode of the first capacitor in response to a second emission signal, The first electrode of the first capacitor is electrically connected to the control electrode of the driving transistor.

5. The pixel circuit according to claim 4, It is characterized in that The pixel circuit further comprises: The third capacitor includes a first electrode receiving the second transmission signal and a second electrode electrically connected to the second electrode of the first capacitor.

6. The pixel circuit according to claim 5, in, The initialization gate signal, the bias gate signal, and the second emission signal have an activation period in a first period, the write gate signal has an active period in a second period after the first period, The first transmission signal has an activation period in a third period after the second period, and The first transmission signal and the second transmission signal have an activation period in a fourth period after the third period.

7. The pixel circuit according to claim 1, It is characterized in that The pixel circuit further comprises: A second emission transistor is configured to electrically connect the control electrode of the drive transistor to the first electrode of the first capacitor in response to the first emission signal.

8. The pixel circuit according to claim 7, It is characterized in that The pixel circuit further comprises: A third capacitor includes a first electrode receiving the first power supply voltage and a second electrode connected to the control electrode of the driving transistor.

9. The pixel circuit according to claim 8, It is characterized in that The pixel circuit further comprises: A compensation reference transistor is configured to provide the first power supply voltage to the first electrode of the first capacitor in response to the write gate signal.

10. The pixel circuit according to claim 9, in, The initialization gate signal and the bias gate signal have an active period in a first period, The bias gate signal and the write gate signal have an active period in a second period after the first period, and The first transmission signal has an activation period in a third period after the second period.

11. The pixel circuit according to any one of claims 1 to 10, in, The first initialization voltage is equal to the second initialization voltage.

12. A display device, include: A display panel including a pixel circuit; a gate driver configured to provide a write gate signal, an initialization gate signal, and a bias gate signal to the pixel circuit; an emission driver configured to provide a first emission signal to the pixel circuit; a data driver configured to provide a data voltage to the pixel circuit; as well as a timing controller configured to control the gate driver, the emission driver and the data driver, The pixel circuit comprises: a drive transistor configured to transmit a drive current; a write transistor configured to write the data voltage to the control electrode of the drive transistor in response to the write gate signal; a light emitting element, receiving the driving current to emit light, Characterized in that the pixel circuit further comprises: A first capacitor including a first electrode and a second electrode; a first emission transistor configured to provide a first power supply voltage to the second electrode of the first capacitor in response to the first emission signal; a first initialization transistor configured to provide a first initialization voltage to the control electrode of the driving transistor in response to the initialization gate signal; and The second initialization transistor is configured to provide a second initialization voltage to the second electrode of the driving transistor in response to the bias gate signal.

13. The display device according to claim 12, in, The pixel circuit further comprises: a second capacitor including a first electrode receiving the first power supply voltage and a second electrode electrically connected to the second electrode of the first capacitor, The first electrode of the first capacitor is electrically connected to the control electrode of the driving transistor.

14. The display device according to claim 12, in, The initialization gate signal and the bias gate signal have an active period in a first period, The write gate signal has an active period in a second period after the first period, and The first transmission signal has an activation period in a third period after the second period.

15. The display device according to claim 12, in, The emission driver is configured to further provide a second emission signal to the pixel circuit, The pixel circuit further includes a second emission transistor configured to electrically connect the first electrode of the drive transistor to the second electrode of the first capacitor in response to the second emission signal, and The first electrode of the first capacitor is electrically connected to the control electrode of the driving transistor.

Images