Low parasitic capacitance TFT array substrate capable of improving aperture opening ratio

Abstract

The utility model relates to the technical field of displays, and provides a low parasitic capacitance TFT array substrate capable of improving aperture opening ratio, which comprises a glass substrate; the first metal layer forms a grid electrode; the first gate insulating layer is fixedly arranged on the upper surfaces of the gate and the glass substrate; conductive layers and TP wires which are distributed at intervals are formed on the second metal layer; the second gate insulating layer is fixedly arranged on the upper surfaces of the TP wire, the conductive layer and the first gate insulating layer; an active layer; a source electrode and a drain electrode which are distributed at intervals are formed on the third metal layer; a passivation layer; the common electrode is fixedly arranged on the upper surface of the passivation layer; a dielectric insulating layer; and the pixel electrode is fixedly arranged on the upper surface of the dielectric insulating layer. The TFT array substrate has the advantages that the distance between the grid electrode and the drain electrode is increased and the stray capacitance between the grid electrode and the drain electrode is reduced on the premise of not influencing the control capability of the active layer, and the drain electrode is arranged above the TP routing, so that the aperture opening ratio of the TFT array substrate is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of displays, in particular to a low parasitic capacitance TFT array substrate with improved aperture ratio. Background Art

[0002] TFT-LCD displays have been developed so far, and the display technology has been continuously developed. There are many advantages, such as large viewing area, large amount of display information, large capacity and high-definition display, flat-panel structure, low power consumption and low voltage, matching with large-scale integrated circuits, no radiation, etc. However, with the demand for low power consumption and high brightness of products, and the continuous development of liquid crystal displays towards high quality and high image quality, the improvement of picture quality is one of the important directions for the development of liquid crystal displays. There are many factors that affect the picture quality of liquid crystal displays, such as aperture ratio, resolution, contrast, brightness, color temperature, color gamut, etc.

[0003] When light is emitted through the backlight panel, not all of it can pass through the panel. For example, the signal lines used for the source driver chip and gate driver chip of the LCD, the TFT itself, and the storage capacitors used to store voltage, etc., are not completely transparent. In addition, the light passing through these places is not controlled by the voltage and cannot display the correct grayscale. Therefore, they need to be shielded by the black matrix to avoid interfering with the correct brightness of other transparent areas. The ratio of the effective transparent area to the total area is called the aperture ratio.

[0004] For TFT-LCD displays, the side of the TFT connected to the pixel electrode is generally called the drain, and the capacitance formed between the drain and the gate metal is called parasitic capacitance. Figure 1 As shown in FIG. 1 , it is a schematic diagram of the structure of a conventional TFT array substrate; at the moment when the TFT is turned off, due to the existence of parasitic capacitance, the coupling effect between the capacitors will cause the voltage of the pixel electrode to be simultaneously pulled down by a jump amount in the positive polarity frame and the negative polarity frame. At this time, the common electrode Vcom point in the original ideal state will deviate from the center position, resulting in different voltages at both ends of the liquid crystal in the positive and negative polarity states, which will cause different light transmittances in the positive and negative polarities, causing the screen to flicker; Figure 1 The TP line is on the same layer as the source and drain, that is, on the upper surface of the gate insulating layer. The TP line is used to provide a voltage signal to the common electrode. One end of the liquid crystal is connected to the common electrode, and the other end of the liquid crystal is connected to the pixel electrode. The light-transmitting area of ​​the liquid crystal display is the pixel display area. Since the position of the TP line is not light-transmitting, Figure 1 The TP wiring in the display passes through the pixel display area, thereby reducing the aperture ratio of the display. Therefore, increasing the aperture ratio and reducing parasitic capacitance are the issues that should be solved at present. Utility Model Content

[0005] The technical problem to be solved by the utility model is to provide a low parasitic capacitance TFT array substrate with improved aperture ratio, increase the distance between the gate and the drain, reduce the parasitic capacitance between the gate and the drain, and arrange the drain above the TP routing to improve the aperture ratio.

[0006] The utility model is achieved in this way:

[0007] A low parasitic capacitance TFT array substrate with improved aperture ratio, comprising:

[0008] Glass substrate;

[0009] A first metal layer is fixedly disposed on the upper surface of the glass substrate to form a gate;

[0010] A first gate insulating layer, fixedly disposed on the upper surface of the gate electrode and the glass substrate, wherein the first gate insulating layer is provided with a first hole;

[0011] A second metal layer is fixedly disposed on the upper surface of the first gate insulating layer to form a conductive layer and TP wiring that are distributed at intervals, wherein the conductive layer is located directly above the gate and is connected to the gate through the first hole;

[0012] A second gate insulating layer is fixedly disposed on the upper surfaces of the TP wiring, the conductive layer and the first gate insulating layer;

[0013] An active layer, fixedly disposed on the upper surface of the second gate insulating layer and also located directly above the conductive layer;

[0014] A third metal layer is fixedly disposed on the upper surface of the second gate insulating layer to form a source electrode and a drain electrode that are spaced apart, wherein the source electrode is connected to the left end of the conductive layer, the drain electrode is connected to the right end of the conductive layer, and the drain electrode is also staggered and overlapped with the TP wiring;

[0015] A passivation layer is fixedly arranged on the upper surfaces of the source electrode, the drain electrode, the active layer and the second gate insulating layer, the passivation layer is provided with a second hole, and the second hole penetrates downwardly through the second gate insulating layer;

[0016] A common electrode, fixedly disposed on the upper surface of the passivation layer, and also passing through the second hole to be connected to the TP wiring;

[0017] A dielectric insulating layer is fixedly arranged on the upper surface of the common electrode and the passivation layer, and the dielectric insulating layer is further provided with a third hole, and the third hole penetrates downwardly through the passivation layer;

[0018] The pixel electrode is fixedly arranged on the upper surface of the dielectric insulating layer and is connected to the drain electrode through the third hole.

[0019] Furthermore, the first metal layer, the second metal layer and the third metal layer are all three-layer structures made of MO / AL / MO or Ti / AL / Ti.

[0020] Furthermore, the first gate insulating layer, the second gate insulating layer, the passivation layer, and the dielectric insulating layer are all made of a SiOx single-layer structure or a SiNx / SiOx double-layer structure.

[0021] Furthermore, the active layer is made of IGZO material, and the pixel electrode and the common electrode are both made of ITO material.

[0022] Furthermore, the first hole is located close to the source.

[0023] Furthermore, the first hole, the second hole and the third hole are all inverted cone shape.

[0024] Furthermore, it also includes a liquid crystal, one end of the liquid crystal is connected to the pixel electrode, the other end of the liquid crystal is connected to the common electrode, and the TP wiring is also located on the left side of the liquid crystal.

[0025] The utility model has the advantages that: a conductive layer is arranged between the gate and the active layer, the gate controls the active layer through the conductive layer, and under the premise of not affecting the control ability of the active layer, the distance between the gate and the drain is increased through the first gate insulating layer and the second gate insulating layer, and the parasitic capacitance between the gate and the drain is reduced, and the TP wiring and the conductive layer are arranged on the same layer, the drain is arranged above the TP wiring, the drain position and the TP wiring position are both opaque, and the increased space below the drain is effectively utilized, so that the TP wiring does not need to pass through the pixel display area, and the aperture ratio of the TFT array substrate is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The present invention will be further described below in conjunction with the embodiments with reference to the accompanying drawings.

[0027] Figure 1 It is a structural schematic diagram of a traditional TFT array substrate in the background technology.

[0028] Figure 2 The utility model is a structural schematic diagram of a low parasitic capacitance TFT array substrate with improved aperture ratio.

[0029] Figure 3 The utility model is a low parasitic capacitance TFT array substrate manufacturing process with improved aperture ratio Figure 1 .

[0030] Figure 4 The utility model is a low parasitic capacitance TFT array substrate manufacturing process with improved aperture ratio Figure 2 .

[0031] Figure 5 The utility model is a manufacturing process of a low parasitic capacitance TFT array substrate with improved aperture ratio. Figure 3 .

[0032] Figure 6 The utility model is a manufacturing process of a low parasitic capacitance TFT array substrate with improved aperture ratio. Figure 4 .

[0033] Figure 7 The utility model is a manufacturing process of a low parasitic capacitance TFT array substrate with improved aperture ratio. Figure 5 .

[0034] Figure 8 The utility model is a manufacturing process of a low parasitic capacitance TFT array substrate with improved aperture ratio. Figure 6 .

[0035] Fig. 9 The utility model is a manufacturing process of a low parasitic capacitance TFT array substrate with improved aperture ratio. Figure 7 .

[0036] Fig.10 The utility model is a manufacturing process of a low parasitic capacitance TFT array substrate with improved aperture ratio. Figure 8 .

[0037] Fig.11 The utility model is a manufacturing process of a low parasitic capacitance TFT array substrate with improved aperture ratio. Figure 9 .

[0038] Fig.12 The utility model is a manufacturing process of a low parasitic capacitance TFT array substrate with improved aperture ratio. Figure 10 .

[0039] Figure numerals: glass substrate 1; gate 2; gate insulating layer 3; first gate insulating layer 31; first hole 311; second gate insulating layer 32; conductive layer 4; TP trace 5; active layer 6; source 7; drain 8; passivation layer 9; second hole 91; common electrode 10; dielectric insulating layer 20; third hole 201; pixel electrode 30. DETAILED DESCRIPTION

[0040] The embodiment of the utility model solves the shortcomings of the TFT array substrate in the background technology that the parasitic capacitance causes the screen to flicker and the TP wiring passes through the pixel display area, thereby reducing the aperture ratio, by providing a low parasitic capacitance TFT array substrate with improved aperture ratio, thereby achieving the technical effects of improving the aperture ratio and reducing parasitic capacitance.

[0041] The technical solution in the embodiment of the utility model is to solve the above shortcomings, and the overall idea is as follows:

[0042] Compared with the traditional TFT array substrate in the background technology, the improvement of the utility model is that the distance between the gate and the drain is increased by the first gate insulating layer and the second gate insulating layer, thereby reducing the parasitic capacitance between the gate and the drain, and a conductive layer is arranged between the gate and the active layer, and the conductive layer is also between the first gate insulating layer and the second gate insulating layer. The gate controls the active layer through the conductive layer, and the purpose of reducing the parasitic capacitance between the gate and the drain is achieved without affecting the control ability of the active layer. The TP line and the conductive layer are arranged on the same layer, and the drain is arranged above the TP line. Since the drain position and the TP line position are both opaque, it is equivalent to covering the TP line with the drain, forming an interlaced superposition of the drain and the TP line, and advantageously utilizing the increased space under the drain, so that the TP line does not need to pass through the pixel display area, and the original position of the TP line can give way to the pixel display area, thereby improving the aperture ratio of the TFT array substrate.

[0043] In order to better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0044] See also Figures 1 to 12 , a preferred embodiment of the utility model.

[0045] A low parasitic capacitance TFT array substrate with improved aperture ratio, comprising:

[0046] Glass substrate 1;

[0047] A first metal layer is fixedly disposed on the upper surface of the glass substrate 1 to form a gate 2;

[0048] A first gate insulating layer 31 is fixedly disposed on the upper surface of the gate electrode 2 and the glass substrate 1, and a first hole 311 is opened in the first gate insulating layer 31;

[0049] A second metal layer is fixedly disposed on the upper surface of the first gate insulating layer 31 to form a conductive layer 4 and a TP trace 5 that are distributed at intervals. The conductive layer 4 is located directly above the gate 2 and is also connected to the gate 2 through the first hole 311.

[0050] A second gate insulating layer 32 is fixedly disposed on the upper surfaces of the TP wiring 5, the conductive layer 4 and the first gate insulating layer 31;

[0051] The active layer 6 is fixedly disposed on the upper surface of the second gate insulating layer 32 and is also located directly above the conductive layer 4;

[0052] A third metal layer is fixedly disposed on the upper surface of the second gate insulating layer 32 to form a source electrode 7 and a drain electrode 8 that are spaced apart. The source electrode 7 is connected to the left end of the conductive layer 4, and the drain electrode 8 is connected to the right end of the conductive layer 4. The drain electrode 8 is also staggered and overlapped with the TP trace 5.

[0053] A passivation layer 9 is fixedly arranged on the upper surfaces of the source electrode 7, the drain electrode 8, the active layer 6 and the second gate insulating layer 32, and the passivation layer 9 is provided with a second hole 91, and the second hole 91 penetrates downwardly through the second gate insulating layer 32;

[0054] The common electrode 10 is fixedly disposed on the upper surface of the passivation layer 9 and is also connected to the TP wiring 5 through the second hole 91;

[0055] The dielectric insulating layer 20 is fixedly arranged on the upper surface of the common electrode 10 and the passivation layer 9. The dielectric insulating layer 20 is also provided with a third hole 201, and the third hole 201 penetrates downwardly through the passivation layer 9.

[0056] The pixel electrode 30 is fixedly disposed on the upper surface of the dielectric insulating layer 20 , and is also connected to the drain electrode 8 through the third hole 201 .

[0057] The TFT array substrate of the present invention has two characteristics. The first characteristic is that a conductive layer 4 is added to the gate insulating layer between the gate electrode 2 and the active layer 6, and the conductive layer 4 is connected to the gate electrode 2 by digging a hole, so that the gate electrode 2 can control the active layer 6 through the conductive layer 4; the distance between the conductive layer 4 and the active layer 6 is equal to the distance between the gate electrode 2 and the active layer 6 of the traditional TFT array substrate in the background technology, so that the control ability of the active layer 6 is not affected, and due to the increased distance between the gate electrode 2 and the drain electrode 8, the parasitic capacitance between the gate electrode 2 and the drain electrode 8 is reduced. The second feature is that the TP trace 5 is made below the drain 8, effectively utilizing the increased distance space below the drain 8; compared with the background technology in which the TP trace 5 and the drain 8 are made on the same layer, the position of the TP trace 5 is not light-transmissive, and the aperture ratio is reduced when the TP trace 5 passes through the pixel display area. The utility model adjusts the position of the TP trace 5 to below the drain 8, and the TP trace 5 does not need to pass through the pixel display area. The TP trace 5 is staggered and overlapped with the drain 8, and the original position of the TP trace 5 can give way to the pixel display area, thereby improving the aperture ratio of the TFT array substrate.

[0058] The first metal layer, the second metal layer and the third metal layer are all three-layer structures made of MO / AL / MO or Ti / AL / Ti.

[0059] The first gate insulating layer 31 , the second gate insulating layer 32 , the passivation layer 9 , and the dielectric insulating layer 20 are all made of a SiOx single-layer structure or a SiNx / SiOx double-layer structure.

[0060] The active layer 6 is made of IGZO material, and the pixel electrode 30 and the common electrode 10 are both made of ITO material.

[0061] The first hole 311 is located close to the source electrode 7 . The conductive layer 4 is not directly below the drain electrode 8 .

[0062] The first hole 311, the second hole 91 and the third hole 201 are all inverted cones, which facilitates the deposition and fixing of materials in the holes.

[0063] It also includes a liquid crystal, one end of which is connected to the pixel electrode 30, and the other end of which is connected to the common electrode 10, and the TP line 5 is also located on the left side of the liquid crystal. The full name of the TP line 5 is Touch Panel Senser Line; the TP line 5 provides a voltage signal to the common electrode 10. Since the position of the TP line 5 is adjusted to the increased distance space below the drain 8, the original position of the TP line 5 becomes a light-transmitting area, and a larger size of liquid crystal can be used to cover the original position of the TP line 5, thereby increasing the light-transmitting area of ​​the liquid crystal display screen and improving the aperture ratio.

[0064] A method for manufacturing a low parasitic capacitance TFT array substrate with improved aperture ratio comprises the following steps:

[0065] S1. Combination Figure 3 , plating a first metal layer on the upper surface of the glass substrate 1 to form a gate 2;

[0066] The material of the first metal layer can be a three-layer structure of MO / AL / MO or a three-layer structure of Ti / AL / Ti, PVD film formation, acid wet etching. AL has a low resistance and is used for conductivity (it can be replaced by Cu), which can reduce impedance and power consumption; secondly, the expansion coefficient of the outer metal MO or Ti is small, which can suppress excessive deformation of AL during high-temperature processes and prevent AL oxidation.

[0067] S2. Combination Figure 4 , coating a first gate insulating layer 31 on the upper surface of the gate electrode 2 and the glass substrate 1 , wherein the first gate insulating layer 31 is provided with a first hole 311 , and the gate electrode 2 is exposed in the first hole 311 ;

[0068] The material of the first gate insulating layer 31 is SiOx single-layer structure, SiNx single-layer structure or SiNx / SiOx double-layer structure, and is formed by CVD. A first hole 311 is opened above the gate 2 by dry etching for connecting the conductive layer 4 to the gate 2.

[0069] S3. Combination Figure 5 , plating a second metal layer on the upper surface of the first gate insulating layer 31 to form a conductive layer 4 and a TP trace 5 that are distributed at intervals, wherein the conductive layer 4 is located directly above the gate 2 and is also connected to the gate 2 through the first hole 311;

[0070] The material of the second metal layer can be a three-layer structure of MO / AL / MO or a three-layer structure of Ti / AL / Ti, PVD film formation, acid wet etching. AL has a low resistance and is used for conductivity (it can be replaced by Cu), which can reduce impedance and power consumption; secondly, the expansion coefficient of the outer metal MO or Ti is small, which can suppress excessive deformation of AL during high-temperature processes and prevent AL oxidation.

[0071] S4. Combination Figure 6 , plating a second gate insulating layer 32 on the upper surfaces of the TP wiring 5 , the conductive layer 4 and the first gate insulating layer 31 ;

[0072] The material of the second gate insulating layer 32 is a SiOx single-layer structure or a SiNx / SiOx double-layer structure, formed by CVD.

[0073] S5. Combination Figure 7 , coating an active layer 6 on the upper surface of the second gate insulating layer 32 , wherein the active layer 6 is located directly above the conductive layer 4 ;

[0074] The material of the active layer 6 is a metal oxide semiconductor such as IGZO, formed by PVD, and etched by wet etching.

[0075] S6. Combination Figure 8 , plating a third metal layer on the upper surface of the second gate insulating layer 32 to form a source electrode 7 and a drain electrode 8 that are spaced apart, wherein the source electrode 7 is connected to the left end of the conductive layer 4, the drain electrode 8 is connected to the right part of the conductive layer 4, and the drain electrode 8 is also staggered and overlapped with the TP wiring 5;

[0076] The material of the third metal layer can be a three-layer structure of MO / AL / MO or a three-layer structure of Ti / AL / Ti, PVD film formation, acid wet etching. AL has a low resistance and is used for conductivity (it can be replaced by Cu), which can reduce impedance and power consumption; secondly, the expansion coefficient of the outer metal MO or Ti is small, which can suppress excessive deformation of AL during high-temperature processes and prevent AL oxidation.

[0077] S7, Combination Fig. 9, a passivation layer 9 is plated on the upper surfaces of the source electrode 7, the drain electrode 8, the active layer 6 and the second gate insulating layer 32, the passivation layer 9 is provided with a second hole 91, the second hole 91 penetrates downwardly through the second gate insulating layer 32, and the TP trace 5 is exposed in the second hole 91;

[0078] The material of the passivation layer 9 is a SiOx single-layer structure or a SiOx / SiNOx double-layer structure, formed by CVD, and the passivation layer 9 and the second gate insulating layer 32 are etched away above the TP wiring 5 by dry etching to open a second hole 91 for connecting the TP wiring 5 and the common electrode 10.

[0079] S8. Combination Fig.10 , plating a common electrode 10 on the upper surface of the passivation layer 9 , and the common electrode 10 also passes through the second hole 91 to connect with the TP trace 5 ;

[0080] The material of the common electrode 10 is ITO, mainly because ITO has good electrical conductivity and light transmittance, PVD film formation, and acid wet etching.

[0081] S9. Combination Fig.11 , a dielectric insulating layer 20 is plated on the upper surface of the common electrode 10 and the passivation layer 9, and the dielectric insulating layer 20 is also provided with a third hole 201, the third hole 201 penetrates downwardly through the passivation layer 9, and the drain electrode 8 is exposed in the third hole 201;

[0082] The dielectric insulating layer 20 serves as a capacitor medium between the pixel electrode 30 and the common electrode 10. The material is a SiOx single-layer structure or a SiOx / SiNOx double-layer structure, and the film is formed by CVD. The dielectric insulating layer 20 and the passivation layer 9 are etched away above the drain 8 by dry etching to open a third hole 201 for connecting the drain 8 and the pixel electrode 30.

[0083] S10, Combination Fig.12 , the pixel electrode 30 is plated on the upper surface of the dielectric insulating layer 20 , and the pixel electrode 30 is also connected to the drain electrode 8 through the third hole 201 .

[0084] The material of the pixel electrode 30 is ITO, mainly because ITO has good conductivity and light transmittance, PVD film formation, and acid wet etching.

[0085] Although the specific implementation methods of the present invention are described above, those skilled in the art should understand that the specific embodiments described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A low parasitic capacitance TFT array substrate with improved aperture ratio, characterized in that: include: Glass substrate; A first metal layer is fixedly disposed on the upper surface of the glass substrate to form a gate; A first gate insulating layer, fixedly disposed on the gate electrode and the upper surface of the glass substrate, wherein the first gate insulating layer is provided with a first hole; A second metal layer is fixedly disposed on the upper surface of the first gate insulating layer to form a conductive layer and TP wiring that are distributed at intervals, wherein the conductive layer is located directly above the gate and is connected to the gate through the first hole; A second gate insulating layer is fixedly disposed on the upper surface of the TP wiring, the conductive layer and the first gate insulating layer; An active layer, fixedly disposed on the upper surface of the second gate insulating layer and also located directly above the conductive layer; A third metal layer is fixedly disposed on the upper surface of the second gate insulating layer to form a source electrode and a drain electrode that are spaced apart, wherein the source electrode is connected to the left end of the conductive layer, the drain electrode is connected to the right end of the conductive layer, and the drain electrode is also staggered and overlapped with the TP wiring; A passivation layer is fixedly arranged on the upper surfaces of the source electrode, the drain electrode, the active layer and the second gate insulating layer, the passivation layer is provided with a second hole, and the second hole penetrates downwardly through the second gate insulating layer; A common electrode is fixedly disposed on the upper surface of the passivation layer and is also connected to the TP wiring through the second hole; A dielectric insulating layer is fixedly arranged on the upper surface of the common electrode and the passivation layer, and the dielectric insulating layer is further provided with a third hole, and the third hole penetrates downwardly through the passivation layer; The pixel electrode is fixedly arranged on the upper surface of the dielectric insulating layer and is connected to the drain electrode through the third hole.

2. The low parasitic capacitance TFT array substrate with improved aperture ratio according to claim 1, characterized in that: The first metal layer, the second metal layer and the third metal layer are all three-layer structures made of MO / AL / MO or Ti / AL / Ti.

3. The low parasitic capacitance TFT array substrate with improved aperture ratio according to claim 1, characterized in that: The first gate insulating layer, the second gate insulating layer, the passivation layer, and the dielectric insulating layer are all made of a SiOx single-layer structure or a SiNx / SiOx double-layer structure.

4. The low parasitic capacitance TFT array substrate with improved aperture ratio according to claim 1, characterized in that: The active layer is made of IGZO material, and the pixel electrode and the common electrode are both made of ITO material.

5. The low parasitic capacitance TFT array substrate with improved aperture ratio according to claim 1, characterized in that: The first hole is located close to the source.

6. The low parasitic capacitance TFT array substrate with improved aperture ratio according to claim 1, characterized in that: The first hole, the second hole and the third hole are all inverted cone shape.

7. The low parasitic capacitance TFT array substrate with improved aperture ratio according to claim 1, characterized in that: It also includes a liquid crystal, one end of the liquid crystal is connected to the pixel electrode, the other end of the liquid crystal is connected to the common electrode, and the TP wiring is also located on the left side of the liquid crystal.

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