Eye health photosensitive digital display circuit

Abstract

The utility model relates to an eye health photosensitive digital display circuit. The device comprises a photosensitive voltage-dividing driving module, a light intensity grading module, and an output signal processing and display module. A first output end, a second output end and a third output end of the photosensitive voltage division driving module are respectively connected with a first input end, a second input end and a third input end of the light intensity grading module; the light intensity grading module comprises a window comparator I, a window comparator II and a window comparator III. The first signal output end, the second signal output end and the third signal output end of the light intensity grading module are connected with the first input end, the second input end and the third input end of the output signal processing and displaying module respectively. The light intensity display device is simple in structure, sensitive in response, capable of visually displaying environment light intensity, beneficial to protecting vision health of users, and suitable for various occasions needing to pay attention to light intensity.

Description

Technical Field

[0001] The utility model discloses an eye health photosensitive digital display circuit, belonging to the technical field of electronics. Background Art

[0002] At present, with the popularization of electronic devices and the digitalization of work and learning modes, people are increasingly in an environment where they use their eyes for a long time. This long-term use of eyes, especially under unsuitable lighting conditions, significantly increases the risk of eye fatigue and vision problems. Scientific research shows that the light intensity range suitable for human eyes to read and write is about 300-500 Lux. Appropriate ambient lighting is essential for protecting eyesight and reducing eye fatigue, especially in a learning or working environment that requires long-term concentration. In the prior art, the monitoring and adjustment of ambient lighting are mostly concentrated on automated lighting systems or professional lighting measurement equipment. For example, the application number is 201711305358.5, and the patent name is a method for illuminance measurement and illuminance intelligent control based on convolutional neural networks. Using convolutional neural networks, real-time illuminance can be obtained by acquiring images, and the output results of the convolutional neural network are directly used as the input of feedback control, but these systems and devices are usually complex and expensive, and are not suitable for personal or small office environments. In addition, they often lack sufficient flexibility to adapt to changing ambient lighting conditions, or cannot provide users with instant and intuitive light intensity information. Therefore, there is a need to develop a simple, economical and effective device that can monitor and display the ambient light intensity in real time to help users protect their eyesight under changing light conditions. Such a device should be able to intuitively inform users of the current light level and provide obvious prompts when the light conditions are not suitable, thereby helping users take appropriate measures to protect their eye health. Summary of the invention

[0003] The technical problem solved by the utility model is as follows: the utility model proposes an eye health photosensitive digital display circuit, which aims to improve the complexity, high cost and inconvenience of existing environmental light monitoring equipment. The device has a simple structure, low cost, and is easy to use, and is suitable for various learning and working environments. The photosensitive voltage-dividing driving module of the utility model uses a photoresistor to convert ambient light into a voltage signal; the light intensity grading module divides the light intensity into three levels through a window comparator; the output signal processing and display module converts the signal into a digital and color display to intuitively indicate the current light level. The circuit can monitor light conditions in real time and notify the user through clear visual signals, thereby helping to protect eye health and reduce vision problems caused by inappropriate light.

[0004] The technical solution of the utility model is: an eye health photosensitive digital display circuit, comprising a photosensitive voltage-dividing driving module 1, a light intensity grading module 2, and an output signal processing and display module 3;

[0005] The first output end, the second output end and the third output end of the photosensitivity voltage-dividing driving module 1 are respectively connected to the first input end, the second input end and the third input end of the light intensity grading module 2; the light intensity grading module 2 includes a window comparator I, a window comparator II and a window comparator III, and the first signal output end, the second signal output end and the third signal output end of the light intensity grading module 2 are respectively connected to the first input end, the second input end and the third input end of the output signal processing and display module 3.

[0006] Furthermore, the photosensitivity voltage-dividing driving module 1 is used to detect the ambient light intensity and convert the detected light intensity into a corresponding voltage signal, the light intensity grading module 2 is used to receive the voltage signal generated by the photosensitivity voltage-dividing driving module 1, and grade the ambient light intensity based on the voltage signal, and the output signal processing and display module 3 is used to receive the level signal output by the light intensity grading module 2, and encode the signal into a digital signal, which is displayed through a digital tube and an LED.

[0007] Furthermore, the photosensitizer voltage-dividing driving module 1 includes a photoresistor PR1 and a resistor R1; the power supply VCC is connected to one end of the photoresistor PR1, the photoresistor PR1 and the resistor R1 are connected in series, the other end of the photoresistor PR1 is connected to one end of the resistor R1, the external wire between the photoresistor PR1 and the resistor R1 is connected to the light intensity grading module 2, and the other end of the resistor R1 is grounded.

[0008] Furthermore, the light intensity grading module 2 includes three groups of window comparators: window comparator I, window comparator II, and window comparator III. The window comparator I includes sliding rheostats R2, R4, resistors R3, R5, R6, R7, voltage comparators A1, A2, and diodes D1, D2. The in-phase end of the voltage comparator A1 in the window comparator I is connected to the reverse end of the voltage comparator A2, and the connecting end of the voltage comparator A1 and the voltage comparator A2 is connected to the first input signal from the photosensitive voltage divider driving module 1. The reverse input end of the voltage comparator A1 is connected to one end of R2 and one end of R3, the other end of R2 is connected to the power supply VCC, the other end of R3 is grounded, and the reverse input end of the voltage comparator A2 is connected to the reverse input end of the photosensitive voltage divider driving module 1. Connected to one end of R4 and one end of R5, the other end of R4 is connected to the power supply VCC, the other end of R5 is grounded, the output end of the voltage comparator A1 is connected to the anode of the diode D1, the output end of the voltage comparator A2 is connected to the anode of the diode D2, the connection end of the output end of the voltage comparator A1 and the anode of the diode D1 is connected to a resistor R6 as a pull-up resistor, the other end of the resistor R6 is connected to the power supply VCC2, the connection end of the output end of the voltage comparator A2 and the anode of the diode D2 is connected to a resistor R7 as a pull-up resistor, the other end of the resistor R7 is connected to the power supply VCC2, the cathodes of the two diodes D1 and D2 are connected to one end of a resistor R8, and the connection point is used as the output end through an external wire, and the other end of R8 is grounded.

[0009] Furthermore, the window comparator II includes sliding rheostats R9, R11, resistors R10, R12, R13, R14, voltage comparators A3, A4, diodes D3, D4, the in-phase end of the voltage comparator A3 in the window comparator II is connected to the reverse end of the voltage comparator A4, and the connecting end of the voltage comparator A3 and the voltage comparator A4 is connected to the second input signal from the photosensitive voltage divider driving module 1, the reverse input end of the voltage comparator A3 is connected to one end of R9 and one end of R10, the other end of R9 is connected to the power supply VCC, the other end of R10 is grounded, the reverse input end of the voltage comparator A4 is connected to one end of R11 and one end of R12, the other end of R11 is grounded One end is connected to the power supply VCC, and the other end of R12 is grounded. The output end of the voltage comparator A3 is connected to the anode of the diode D3, and the output end of the voltage comparator A4 is connected to the anode of the diode D4. The connection end between the output end of the voltage comparator A3 and the anode of the diode D3 is connected to a resistor R13 as a pull-up resistor. The other end of the resistor R13 is connected to the power supply VCC2. The connection end between the output end of the voltage comparator A4 and the anode of the diode D4 is connected to a resistor R14 as a pull-up resistor. The other end of the resistor R14 is connected to the power supply VCC2. The cathodes of the two diodes D3 and D4 are connected to one end of a resistor R15, and the connection point is used as the output end through an external wire. The other end of R15 is grounded.

[0010] Furthermore, the window comparator III includes sliding rheostats R16, R18, resistors R17, R19, R20, R21, voltage comparators A5, A6, diodes D5, D6, the in-phase end of the voltage comparator A5 in the window comparator III is connected to the reverse end of the voltage comparator A6, and the connecting end of the voltage comparator A5 and the voltage comparator A6 is connected to the third input signal from the photosensitive voltage divider driving module, the reverse input end of the voltage comparator A5 is connected to one end of R16 and one end of R17, the other end of R16 is connected to the power supply VCC, the other end of R17 is grounded, the reverse input end of the voltage comparator A6 is connected to one end of R18 and one end of R19, R18 The other end of R19 is connected to the power supply VCC, the other end of R19 is grounded, the output end of the voltage comparator A5 is connected to the anode of the diode D5, the output end of the voltage comparator A6 is connected to the anode of the diode D6, the connection end of the output end of the voltage comparator A5 and the anode of the diode D5 is connected to a resistor R20 as a pull-up resistor, the other end of the resistor R20 is connected to the power supply VCC2, the connection end of the output end of the voltage comparator A6 and the anode of the diode D6 is connected to a resistor R21 as a pull-up resistor, the other end of the resistor R21 is connected to the power supply VCC2, the cathodes of the two diodes D5 and D6 are connected to one end of a resistor R22, and the connection point is used as the output end through an external wire, and the other end of R22 is grounded.

[0011] Further, the output signal processing and display module 3 includes a 74148N encoder, a 7448N decoder, a common cathode seven-segment digital tube, NAND gates NAND1, NAND2, AND gates AND1, AND2, AND3, NOT gates N1, N2, N3 and light-emitting diodes LED1, LED2, LED3;

[0012] The input terminals D1, D2, and D3 of the 74148N encoder are respectively connected to the output terminals of the window comparator I, the output terminals of the window comparator II, and the output terminals of the window comparator III of the light intensity grading module 2, the output terminals of the window comparator I, the output terminals of the window comparator II, and the output terminals of the window comparator III of the light intensity grading module 2 are respectively connected to the three input terminals of the NAND gate NAND1, the output terminals of the NAND gate NAND1 are respectively connected to the input terminals D0, D4, D5, D6, and D7 of the 74148N encoder, and the output terminals A0, A1, and A2 of the 74148N encoder are respectively connected through one end of the NAND gates N1, N2, and N3;

[0013] The input terminals A, B, and C of the 7448N decoder are connected to the output terminals of the NOT gates N1, N2, and N3 respectively, the input terminal D thereof is grounded, and the ~LT, ~RBI, and ~BI / RBO thereof are connected to the power supply VCC2, the output terminals OA, OB, OC, OD, OE, OF, and OG of the 7448N decoder are connected to the A, B, C, D, E, F, and G terminals of the common cathode seven-segment digital tube respectively, and the CK terminal of the common cathode seven-segment digital tube is grounded;

[0014] The output ends of the NOT gates N1 and N2 are also connected to the two input ends of the NAND gate NAND2, the output of NAND2 serves as one input end of the AND gates AND1 and AND2 respectively, the output end of the NOT gate N1 is also connected to the other input end of the AND gate AND1, the output end of the AND gate AND1 is connected to the anode of the light emitting diode LED1, the output end of the NOT gate N2 is also connected to the other input end of the AND gate AND2, the output end of the AND gate AND2 is connected to the anode of the light emitting diode LED2, the input end of the AND gate AND3 is connected to the outputs of the NOT gates N1 and N2, and the cathodes of the light emitting diodes LED1, LED2, and LED3 are connected and then grounded.

[0015] The working principle of the utility model is:

[0016] A voltage dividing point is formed between the photoresistor PR1 and the resistor R1 in the photosensitive voltage dividing driving module 1, and the voltage dividing point generates a voltage input signal related to the light intensity of the environment. When the light intensity is below 300 Lux, a weak light input signal is generated, when the light intensity is within 300-500 Lux, a suitable light input signal is generated, and when the light intensity is above 500 Lux, a strong light input signal is generated;

[0017] The input signal enters three groups of window comparators, window comparator I, window comparator II, and window comparator III, and the corresponding voltage measurement ranges are adjusted by sliding resistors R2 and R4, sliding resistors R9 and R11, and sliding resistors R16 and R18 respectively. Window comparator I measures the weak light voltage range, window comparator II measures the suitable light voltage range, and window comparator III measures the strong light voltage range. When the input signal is within the measurement range of the window comparator, a low level will be output. When the input signal is outside the measurement range of the window comparator, a high level will be generated. Therefore, when a level of light enters the three groups of window comparators, one and only one group of window comparators will output a low level, and the rest are high levels.

[0018] When the weak light input signal enters the light intensity grading module, the window comparator I outputs a low level, and the window comparators II and III output a high level. The outputs of the window comparators I, II, and III enter the D1, D2, and D3 input terminals of the 74148N encoder respectively. The outputs of the window comparators I, II, and III also enter the input of the NAND gate NAND1 to generate a logic level 1. The output logic 1 of the NAND gate NAND1 enters the D0, D4, D5, D6, and D7 input terminals of the 74148N encoder, and then the output terminals A0, A1, and A2 of the 74148N encoder output logic levels 0, 1, and 1 respectively, and then enter the NOT gates N1, N2, and N3 respectively to generate logic levels 1, 0, and 0. The output logic levels of the NOT gates N1 and N2 enter the NAND gates NAND 2, the NAND gate NAND2 generates a logic level 1, and then enters one input end of the AND gates AND1 and AND2, the output logic level 1 of the NOT gate N1 also enters the other input end of the AND gate AND1, the output end of AND1 generates a logic level 1, and then enters the light-emitting diode LED1, at this time the light-emitting diode LED1 emits blue light; the output logic level 0 of the NOT gate N2 also enters the other input end of the AND gate AND2, the output end of AND2 generates a logic level 0, and then enters the light-emitting diode LED2, at this time the light-emitting diode LED2 is not bright; the output logic levels 1 and 0 of the NOT gates N1 and N2 also enter the input ends of the AND gate AND3 respectively, and the AND gate AND3 generates a logic level 0, and then enters the anode of the light-emitting diode LED3, at this time the light-emitting diode LED3 is not bright. The output logic levels 1, 0, 0 of NOT gates N1, N2, and N3 also enter the A, B, and C input terminals of the 7448N decoder respectively. The input terminal D of the 7448M decoder is grounded. Then the output terminals OA, OB, OC, OD, OE, OF, and OG of the 7448N decoder produce logic levels 0, 1, 1, 0, 0, 0, 0 respectively. The output logic levels enter the A, B, C, D, E, F, and G input terminals of the digital tube respectively, thereby displaying the number 1.

[0019] When the appropriate input signal enters the light intensity grading module, the window comparator II outputs a low level, and the window comparators I and III output a high level. The outputs of the window comparators I, II, and III enter the D1, D2, and D3 input terminals of the 74148N encoder respectively. The outputs of the window comparators I, II, and III also enter the input of the NAND gate NAND1 to generate a logic level 1. The output logic 1 of the NAND gate NAND1 enters the D0, D4, D5, D6, and D7 input terminals of the 74148N encoder, and then the output terminals A0, A1, and A2 of the 74148N encoder output logic levels 1, 0, and 1 respectively, and then enter the NOT gates N1, N2, and N3 respectively to generate logic levels 0, 1, and 0. The output logic levels of the NOT gates N1 and N2 enter the NAND gates NAND1 respectively. 2, the NAND gate NAND2 generates a logic level 1, and then enters one input end of the AND gates AND1 and AND2, the output logic level 0 of the NOT gate N1 also enters the other input end of the AND gate AND1, the output end of AND1 generates a logic level 0, and then enters the light-emitting diode LED1, at this time the light-emitting diode LED1 is not bright; the output logic level 1 of the NOT gate N2 also enters the other input end of the AND gate AND2, the output end of AND2 generates a logic level 1, and then enters the light-emitting diode LED2, at this time the light-emitting diode LED2 emits green light; the output logic levels 0 and 1 of the NOT gates N1 and N2 also enter the input ends of the AND gate AND3 respectively, and the AND gate AND3 generates a logic level 0, and then enters the anode of the light-emitting diode LED3, at this time the light-emitting diode LED3 is not bright. The output logic levels 0, 1, 0 of NOT gates N1, N2, and N3 also enter the A, B, and C input terminals of the 7448N decoder respectively. The input terminal D of the 7448M decoder is grounded. Then the output terminals OA, OB, OC, OD, OE, OF, and OG of the 7448N decoder produce logic levels 1, 1, 0, 1, 1, 0, 1 respectively. The output logic levels enter the A, B, C, D, E, F, and G input terminals of the digital tube respectively, thereby displaying the number 2.

[0020] When the strong light input signal enters the light intensity grading module, the window comparator III outputs a low level, and the window comparators I and II output a high level. The outputs of the window comparators I, II, and III enter the D1, D2, and D3 input terminals of the 74148N encoder respectively. The outputs of the window comparators I, II, and III also enter the input of the NAND gate NAND1 to generate a logic level 1. The output logic 1 of the NAND gate NAND1 enters the D0, D4, D5, D6, and D7 input terminals of the 74148N encoder, and then the output terminals A0, A1, and A2 of the 74148N encoder output logic levels 0, 0, and 1 respectively, and then enter the NOT gates N1, N2, and N3 respectively to generate logic levels 1, 1, and 0. The output logic levels of the NOT gates N1 and N2 enter the NAND gates NAND1 respectively. 2, the NAND gate NAND2 produces a logic level 0, and then enters one input end of the AND gates AND1 and AND2, the output logic level 1 of the NOT gate N1 also enters the other input end of the AND gate AND1, the output end of AND1 produces a logic level 0, and then enters the light-emitting diode LED1, at this time the light-emitting diode LED1 is not bright; the output logic level 1 of the NOT gate N2 also enters the other input end of the AND gate AND2, the output end of AND2 produces a logic level 0, and then enters the light-emitting diode LED2, at this time the light-emitting diode LED2 is not bright; the output logic levels 1 and 1 of the NOT gates N1 and N2 also enter the input end of the AND gate AND3 respectively, the AND gate AND3 produces a logic level 1, and then enters the anode of the light-emitting diode LED3, at this time the light-emitting diode LED3 emits red light. The output logic levels 1, 1, 0 of NOT gates N1, N2, and N3 also enter the A, B, and C input terminals of the 7448N decoder respectively. The input terminal D of the 7448M decoder is grounded. Then the output terminals OA, OB, OC, OD, OE, OF, and OG of the 7448N decoder produce logic levels 1, 1, 1, 1, 0, 0, 1 respectively. The output logic levels enter the A, B, C, D, E, F, and G input terminals of the digital tube respectively, thereby displaying the number 3.

[0021] The beneficial effects of the utility model are:

[0022] The utility model provides an eye health photosensitive digital display circuit, which realizes accurate monitoring and intuitive display of ambient light intensity through the coordinated work of a photosensitive voltage-dividing driving module, a light intensity grading module, and an output signal processing and display module. The device uses a window comparator to analyze the voltage signal received from a photoresistor, and divides the ambient light intensity into three levels of weak light, suitable light, and strong light according to these signals, and processes through an encoder and a decoder so that the digital tube and LED system can display the corresponding light level. Such a design not only simplifies the monitoring process of ambient light intensity, but also provides users with a visual indication that is easy to understand and respond to, helping them make timely adjustments in vision protection. In addition, due to its simple structure, low cost and easy implementation, this circuit is very suitable for a variety of environments such as schools, offices and homes, especially in situations where close attention needs to be paid to light quality to protect eyesight. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a block diagram of a photosensitive digital display circuit for eye health in the utility model;

[0024] Figure 2 The utility model discloses a principle diagram of a photosensitive digital display circuit for eye health.

[0025] Figure 2 The numbers in the figure are: 1-photosensitive voltage divider driving module, 2-light intensity grading module, 3-output signal processing and display module, I-window comparator I, II-window comparator II, III-window comparator III, PR1-photoresistor, R2, R4, R9, R11, R16, R18-sliding resistor, R1, R3, R5~R8, R10, R12~R15, R17, R19~R22-resistor, A1~A6-voltage comparator, D1~D6-diode, N1~N3-not gate, NAND1, NAND2-not and gate, AND1~AND3-AND gate, 74148N-74148N encoder, 7448N-7448N decoder, LED1~LED3-light emitting diode. DETAILED DESCRIPTION

[0026] The following is a further description of an eye health photosensitive digital display circuit proposed by the utility model in combination with the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are in a very simplified form and in an inaccurate proportion, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the utility model.

[0027] Example 1: Figure 1 , 2 As shown, a photosensitive digital display circuit for eye health includes a photosensitive voltage-dividing driving module 1, a light intensity grading module 2, and an output signal processing and display module 3;

[0028] The first output end, the second output end and the third output end of the photosensitivity voltage-dividing driving module 1 are respectively connected to the first input end, the second input end and the third input end of the light intensity grading module 2; the light intensity grading module 2 includes a window comparator I, a window comparator II and a window comparator III, and the first signal output end, the second signal output end and the third signal output end of the light intensity grading module 2 are respectively connected to the first input end, the second input end and the third input end of the output signal processing and display module 3.

[0029] Furthermore, the photosensitivity voltage-dividing driving module 1 is used to detect the ambient light intensity and convert the detected light intensity into a corresponding voltage signal, the light intensity grading module 2 is used to receive the voltage signal generated by the photosensitivity voltage-dividing driving module 1, and grade the ambient light intensity based on the voltage signal, and the output signal processing and display module 3 is used to receive the level signal output by the light intensity grading module 2, and encode the signal into a digital signal, which is displayed through a digital tube and an LED.

[0030] Furthermore, the photosensitizer voltage-dividing driving module 1 includes a photoresistor PR1 and a resistor R1; the power supply VCC is connected to one end of the photoresistor PR1, the photoresistor PR1 and the resistor R1 are connected in series, the other end of the photoresistor PR1 is connected to one end of the resistor R1, the external wire between the photoresistor PR1 and the resistor R1 is connected to the light intensity grading module 2, and the other end of the resistor R1 is grounded.

[0031] Furthermore, the light intensity grading module 2 includes three groups of window comparators: window comparator I, window comparator II, and window comparator III. The window comparator I includes sliding rheostats R2, R4, resistors R3, R5, R6, R7, voltage comparators A1, A2, and diodes D1, D2; the in-phase end of the voltage comparator A1 in the window comparator I is connected to the reverse end of the voltage comparator A2, and the connecting end of the voltage comparator A1 and the voltage comparator A2 is connected to the first input signal from the photosensitive voltage divider driving module 1, the reverse input end of the voltage comparator A1 is connected to one end of R2 and one end of R3, the other end of R2 is connected to the power supply VCC, the other end of R3 is grounded, and the reverse input end of the voltage comparator A1 is connected to the reference voltage provided by the power supply VCC through different resistors R2 and R3; the reverse input end of the voltage comparator A2 The voltage comparator A2 is connected to one end of R4 and one end of R5, the other end of R4 is connected to the power supply VCC, the other end of R5 is grounded, the reverse input end of the voltage comparator A2 is connected to the reference voltage provided by the power supply VCC through different resistors R4 and R5; the output end of the voltage comparator A1 is connected to the anode of the diode D1, the output end of the voltage comparator A2 is connected to the anode of the diode D2, the connection end between the output end of the voltage comparator A1 and the anode of the diode D1 is connected to the resistor R6 as a pull-up resistor, the other end of the resistor R6 is connected to the power supply VCC2, the connection end between the output end of the voltage comparator A2 and the anode of the diode D2 is connected to the resistor R7 as a pull-up resistor, the other end of the resistor R7 is connected to the power supply VCC2, the cathodes of the two diodes D1 and D2 are connected to one end of a resistor R8, and the connection point is used as the output end through an external wire, and the other end of R8 is grounded.

[0032] Furthermore, the window comparator II includes sliding resistors R9, R11, resistors R10, R12, R13, R14, voltage comparators A3, A4, diodes D3, D4, the in-phase end of the voltage comparator A3 in the window comparator II is connected to the reverse end of the voltage comparator A4, and the connecting end of the voltage comparator A3 and the voltage comparator A4 is connected to the second input signal from the photosensitive voltage divider driving module 1, the reverse input end of the voltage comparator A3 is connected to one end of R9 and one end of R10, the other end of R9 is connected to the power supply VCC, the other end of R10 is grounded, the reverse input end of the voltage comparator A3 is connected to the reference voltage provided by the power supply VCC through different resistors R9, R10; the reverse input end of the voltage comparator A4 is connected to one end of R11 and one end of R12, the other end of R11 is grounded. One end is connected to the power supply VCC, the other end of R12 is grounded, the reverse input end of the voltage comparator A4 is connected to the reference voltage provided by the power supply VCC through different resistors R11 and R12; the output end of the voltage comparator A3 is connected to the anode of the diode D3, the output end of the voltage comparator A4 is connected to the anode of the diode D4, the connection end between the output end of the voltage comparator A3 and the anode of the diode D3 is connected to the resistor R13 as a pull-up resistor, the other end of the resistor R13 is connected to the power supply VCC2, the output end of the voltage comparator A4 and the anode of the diode D4 are connected to the resistor R14 as a pull-up resistor, the other end of the resistor R14 is connected to the power supply VCC2, the cathodes of the two diodes D3 and D4 are connected to one end of a resistor R15, and the connection point is used as the output end through an external wire, and the other end of R15 is grounded.

[0033] Furthermore, the window comparator III includes sliding rheostats R16, R18, resistors R17, R19, R20, R21, voltage comparators A5, A6, diodes D5, D6. The in-phase end of the voltage comparator A5 in the window comparator III is connected to the reverse end of the voltage comparator A6, and the connecting end of the voltage comparator A5 and the voltage comparator A6 is connected to the third input signal from the photosensitive voltage divider driving module. The reverse input end of the voltage comparator A5 is connected to one end of R16 and one end of R17, the other end of R16 is connected to the power supply VCC, and the other end of R17 is grounded. The reverse input end of the voltage comparator A5 is connected to the reference voltage provided by the power supply VCC through different resistors R16, R17; the reverse input end of the voltage comparator A6 is connected to one end of R18 and one end of R19, and R18 The other end of R19 is connected to the power supply VCC, the other end of R19 is grounded, the reverse input end of the voltage comparator A6 is connected to the reference voltage provided by the power supply VCC through different resistors R18 and R19; the output end of the voltage comparator A5 is connected to the anode of the diode D5, the output end of the voltage comparator A6 is connected to the anode of the diode D6, the connection end of the output end of the voltage comparator A5 and the anode of the diode D5 is connected to a resistor R20 as a pull-up resistor, the other end of the resistor R20 is connected to the power supply VCC2, the output end of the voltage comparator A6 and the anode of the diode D6 are connected to a resistor R21 as a pull-up resistor, the other end of the resistor R21 is connected to the power supply VCC2, the cathodes of the two diodes D5 and D6 are connected to one end of a resistor R22, and the connection point is used as the output end through an external wire, and the other end of R22 is grounded.

[0034] Further, the output signal processing and display module 3 includes a 74148N encoder, a 7448N decoder, a common cathode seven-segment digital tube, NAND gates NAND1, NAND2, AND gates AND1, AND2, AND3, NOT gates N1, N2, N3 and light-emitting diodes LED1, LED2, LED3;

[0035] The input terminals D1, D2, and D3 of the 74148N encoder are respectively connected to the output terminals of the window comparator I, the output terminals of the window comparator II, and the output terminals of the window comparator III of the light intensity grading module 2, the output terminals of the window comparator I, the output terminals of the window comparator II, and the output terminals of the window comparator III of the light intensity grading module 2 are respectively connected to the three input terminals of the NAND gate NAND1, the output terminals of the NAND gate NAND1 are respectively connected to the input terminals D0, D4, D5, D6, and D7 of the 74148N encoder, and the output terminals A0, A1, and A2 of the 74148N encoder are respectively connected through one end of the NAND gates N1, N2, and N3;

[0036] The input terminals A, B, and C of the 7448N decoder are connected to the output terminals of the NOT gates N1, N2, and N3 respectively, the input terminal D thereof is grounded, and the ~LT, ~RBI, and ~BI / RBO thereof are connected to the power supply VCC2, the output terminals OA, OB, OC, OD, OE, OF, and OG of the 7448N decoder are connected to the A, B, C, D, E, F, and G terminals of the common cathode seven-segment digital tube respectively, and the CK terminal of the common cathode seven-segment digital tube is grounded;

[0037] The output ends of the NOT gates N1 and N2 are also connected to the two input ends of the NAND gate NAND2, the output of NAND2 serves as one input end of the AND gates AND1 and AND2 respectively, the output end of the NOT gate N1 is also connected to the other input end of the AND gate AND1, the output end of the AND gate AND1 is connected to the anode of the light emitting diode LED1, the output end of the NOT gate N2 is also connected to the other input end of the AND gate AND2, the output end of the AND gate AND2 is connected to the anode of the light emitting diode LED2, the input end of the AND gate AND3 is connected to the outputs of the NOT gates N1 and N2, and the cathodes of the light emitting diodes LED1, LED2, and LED3 are connected and then grounded.

[0038] A voltage dividing point is formed between the photoresistor PR1 and the resistor R1 in the photosensitive voltage dividing driving module 1, and the voltage dividing point generates a voltage input signal related to the light intensity of the environment. When the light intensity is below 300 Lux, a weak light input signal is generated, when the light intensity is within 300-500 Lux, a suitable light input signal is generated, and when the light intensity is above 500 Lux, a strong light input signal is generated;

[0039] The input signal enters three groups of window comparators, window comparator I, window comparator II, and window comparator III, and the corresponding voltage measurement ranges are adjusted by sliding resistors R2 and R4, sliding resistors R9 and R11, and sliding resistors R16 and R18 respectively. Window comparator I measures the weak light voltage range, window comparator II measures the suitable light voltage range, and window comparator III measures the strong light voltage range. When the input signal is within the measurement range of the window comparator, a low level will be output. When the input signal is outside the measurement range of the window comparator, a high level will be generated. Therefore, when a level of light enters the three groups of window comparators, one and only one group of window comparators will output a low level, and the rest are all low levels.

[0040] When the weak light input signal enters the light intensity grading module, the window comparator I outputs a low level, and the window comparators II and III output a high level. The outputs of the window comparators I, II, and III enter the D1, D2, and D3 input terminals of the 74148N encoder respectively. The outputs of the window comparators I, II, and III also enter the input of the NAND gate NAND1 to generate a logic level 1. The output logic 1 of the NAND gate NAND1 enters the D0, D4, D5, D6, and D7 input terminals of the 74148N encoder, and then the output terminals A0, A1, and A2 of the 74148N encoder output logic levels 0, 1, and 1 respectively, and then enter the NOT gates N1, N2, and N3 respectively to generate logic levels 1, 0, and 0. The output logic levels of the NOT gates N1 and N2 enter the NAND gates NAND 2, the NAND gate NAND2 generates a logic level 1, and then enters one input end of the AND gates AND1 and AND2, the output logic level 1 of the NOT gate N1 also enters the other input end of the AND gate AND1, the output end of AND1 generates a logic level 1, and then enters the light-emitting diode LED1, at this time the light-emitting diode LED1 emits blue light; the output logic level 0 of the NOT gate N2 also enters the other input end of the AND gate AND2, the output end of AND2 generates a logic level 0, and then enters the light-emitting diode LED2, at this time the light-emitting diode LED2 is not bright; the output logic levels 1 and 0 of the NOT gates N1 and N2 also enter the input ends of the AND gate AND3 respectively, and the AND gate AND3 generates a logic level 0, and then enters the anode of the light-emitting diode LED3, at this time the light-emitting diode LED3 is not bright. The output logic levels 1, 0, 0 of NOT gates N1, N2, and N3 also enter the A, B, and C input terminals of the 7448N decoder respectively. The input terminal D of the 7448M decoder is grounded. Then the output terminals OA, OB, OC, OD, OE, OF, and OG of the 7448N decoder produce logic levels 0, 1, 1, 0, 0, 0, 0 respectively. The output logic levels enter the A, B, C, D, E, F, and G input terminals of the digital tube respectively, thereby displaying the number 1.

[0041] Example 2: Figure 1 , 2As shown, a photosensitive digital display circuit for eye health is provided. This embodiment is the same as the embodiment 1, except that when the suitable input signal enters the light intensity grading module, the window comparator II outputs a low level, and the window comparators I and III output a high level. The outputs of the window comparators I, II, and III enter the D1, D2, and D3 input terminals of the 74148N encoder respectively. The outputs of the window comparators I, II, and III also enter the input of the NAND gate NAND1 to generate a logic level 1. The output logic 1 of the NAND gate NAND1 enters the D0, D4, D5, D6, and D7 input terminals of the 74148N encoder, and then the output terminals A0, A1, and A2 of the 74148N encoder output logic levels 1, 0, and 1 respectively, and then enter the NOT gates N1, N2, and N3 respectively to generate logic levels 0, 1, and 0. The NOT gates N1 and N2 The output logic level enters the two input ends of the NAND gate NAND2 respectively, and the NAND gate NAND2 generates a logic level 1, and then enters one input end of the AND gates AND1 and AND2. The output logic level 0 of the NOT gate N1 also enters the other input end of the AND gate AND1, and the output end of AND1 generates a logic level 0, and then enters the light-emitting diode LED1. At this time, the light-emitting diode LED1 is not lit; the output logic level 1 of the NOT gate N2 also enters the other input end of the AND gate AND2, and the output end of AND2 generates a logic level 1, and then enters the light-emitting diode LED2. At this time, the light-emitting diode LED2 emits green light; the output logic levels 0 and 1 of the NOT gates N1 and N2 also enter the input ends of the AND gate AND3 respectively, and the AND gate AND3 generates a logic level 0, and then enters the anode of the light-emitting diode LED3. At this time, the light-emitting diode LED3 is not lit. The output logic levels 0, 1, 0 of NOT gates N1, N2, and N3 also enter the A, B, and C input terminals of the 7448N decoder respectively. The input terminal D of the 7448M decoder is grounded. Then the output terminals OA, OB, OC, OD, OE, OF, and OG of the 7448N decoder produce logic levels 1, 1, 0, 1, 1, 0, 1 respectively. The output logic levels enter the A, B, C, D, E, F, and G input terminals of the digital tube respectively, thereby displaying the number 2.

[0042] Example 3: Figure 1 , 2As shown, a photosensitive digital display circuit for eye health is provided. This embodiment is the same as embodiment 1, except that when a strong light input signal enters the light intensity grading module, the window comparator III outputs a low level, and the window comparators I and II output a high level. The outputs of the window comparators I, II, and III enter the D1, D2, and D3 input terminals of the 74148N encoder respectively. The outputs of the window comparators I, II, and III also enter the input of the NAND gate NAND1 to generate a logic level 1. The output logic 1 of the NAND gate NAND1 enters the D0, D4, D5, D6, and D7 input terminals of the 74148N encoder, and then the output terminals A0, A1, and A2 of the 74148N encoder output logic levels 0, 0, and 1 respectively, and then enter the NOT gates N1, N2, and N3 to generate logic levels 1, 1, and 0. The NOT gates N1 and N2 The output logic level enters the two input ends of the NAND gate NAND2 respectively, and the NAND gate NAND2 produces a logic level 0, and then enters one input end of the AND gates AND1 and AND2. The output logic level 1 of the NOT gate N1 also enters the other input end of the AND gate AND1, and the output end of AND1 produces a logic level 0, and then enters the light-emitting diode LED1. At this time, the light-emitting diode LED1 is not lit; the output logic level 1 of the NOT gate N2 also enters the other input end of the AND gate AND2, and the output end of AND2 produces a logic level 0, and then enters the light-emitting diode LED2. At this time, the light-emitting diode LED2 is not lit; the output logic levels 1 and 1 of the NOT gates N1 and N2 also enter the input ends of the AND gate AND3 respectively, and the AND gate AND3 produces a logic level 1, and then enters the anode of the light-emitting diode LED3. At this time, the light-emitting diode LED3 emits red light. The output logic levels 1, 1, 0 of NOT gates N1, N2, and N3 also enter the A, B, and C input terminals of the 7448N decoder respectively. The input terminal D of the 7448M decoder is grounded. Then the output terminals OA, OB, OC, OD, OE, OF, and OG of the 7448N decoder produce logic levels 1, 1, 1, 1, 0, 0, 1 respectively. The output logic levels enter the A, B, C, D, E, F, and G input terminals of the digital tube respectively, thereby displaying the number 3.

[0043] The specific embodiments of the present invention are described in detail above in conjunction with the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in this field without departing from the purpose of the present invention.

Claims

1. A photosensitive digital display circuit for eye health, Features: It comprises a photosensitive voltage-dividing driving module (1), a light intensity grading module (2), and an output signal processing and display module (3); The first output end, the second output end and the third output end of the photosensitive voltage-dividing driving module (1) are respectively connected to the first input end, the second input end and the third input end of the light intensity grading module (2); the light intensity grading module (2) comprises a window comparator I, a window comparator II and a window comparator III; the first signal output end, the second signal output end and the third signal output end of the light intensity grading module (2) are respectively connected to the first input end, the second input end and the third input end of the output signal processing and display module (3).

2. The eye health photosensitive digital display circuit according to claim 1, Features: The light-sensitive voltage-dividing driving module (1) is used to detect the ambient light intensity and convert the detected light intensity into a corresponding voltage signal; the light intensity grading module (2) is used to receive the voltage signal generated by the light-sensitive voltage-dividing driving module (1) and grade the ambient light intensity based on the voltage signal; the output signal processing and display module (3) is used to receive the level signal output by the light intensity grading module (2), encode the level signal into a digital signal, and display it through a digital tube and an LED.

3. The eye health photosensitive digital display circuit according to claim 1, Features: The photosensitive voltage-dividing driving module (1) comprises a photoresistor PR1 and a resistor R1; a power source VCC is connected to one end of the photoresistor PR1, the photoresistor PR1 and the resistor R1 are connected in series, the other end of the photoresistor PR1 is connected to one end of the resistor R1, an external wire between the photoresistor PR1 and the resistor R1 is connected to a light intensity grading module (2), and the other end of the resistor R1 is grounded.

4. The eye health photosensitive digital display circuit according to claim 1, Features: The light intensity grading module (2) comprises three groups of window comparators: window comparator I, window comparator II and window comparator III. The window comparator I comprises sliding rheostats R2 and R4, resistors R3, R5, R6 and R7, voltage comparators A1 and A2, and diodes D1 and D2. The in-phase end of the voltage comparator A1 in the window comparator I is connected to the reverse end of the voltage comparator A2, and the connection end of the voltage comparator A1 and the voltage comparator A2 is connected to the first input signal from the light-sensitive voltage-dividing driving module (1). The reverse input end of the voltage comparator A1 is connected to one end of R2 and one end of R3, the other end of R2 is connected to a power supply VCC, the other end of R3 is grounded, and the reverse input end of the voltage comparator A2 is connected to one end of R2 and one end of R3. Connected to one end of R4 and one end of R5, the other end of R4 is connected to the power supply VCC, the other end of R5 is grounded, the output end of the voltage comparator A1 is connected to the anode of the diode D1, the output end of the voltage comparator A2 is connected to the anode of the diode D2, the connection end of the output end of the voltage comparator A1 and the anode of the diode D1 is connected to a resistor R6 as a pull-up resistor, the other end of the resistor R6 is connected to the power supply VCC2, the connection end of the output end of the voltage comparator A2 and the anode of the diode D2 is connected to a resistor R7 as a pull-up resistor, the other end of the resistor R7 is connected to the power supply VCC2, the cathodes of the two diodes D1 and D2 are connected to one end of a resistor R8, and the connection point is used as the output end through an external wire, and the other end of R8 is grounded.

5. The eye health photosensitive digital display circuit according to claim 1, Features: The window comparator II comprises sliding rheostats R9, R11, resistors R10, R12, R13, R14, voltage comparators A3, A4, diodes D3, D4, wherein the in-phase end of the voltage comparator A3 in the window comparator II is connected to the inverting end of the voltage comparator A4, and the connecting end of the voltage comparator A3 and the voltage comparator A4 is connected to the second input signal from the photosensitive voltage divider driving module (1), the inverting input end of the voltage comparator A3 is connected to one end of R9 and one end of R10, the other end of R9 is connected to the power supply VCC, the other end of R10 is grounded, the inverting input end of the voltage comparator A4 is connected to one end of R11 and one end of R12, the other end of R11 is grounded, The power supply VCC is terminated, and the other end of R12 is grounded. The output end of the voltage comparator A3 is connected to the anode of the diode D3, and the output end of the voltage comparator A4 is connected to the anode of the diode D4. The connection end between the output end of the voltage comparator A3 and the anode of the diode D3 is connected to a resistor R13 as a pull-up resistor. The other end of the resistor R13 is connected to the power supply VCC2. The connection end between the output end of the voltage comparator A4 and the anode of the diode D4 is connected to a resistor R14 as a pull-up resistor. The other end of the resistor R14 is connected to the power supply VCC2. The cathodes of the two diodes D3 and D4 are connected to one end of a resistor R15, and the connection point is used as the output end through an external wire. The other end of R15 is grounded.

6. The eye health photosensitive digital display circuit according to claim 1, Features: The window comparator III includes sliding rheostats R16, R18, resistors R17, R19, R20, R21, voltage comparators A5, A6, diodes D5, D6. The in-phase end of the voltage comparator A5 in the window comparator III is connected to the reverse end of the voltage comparator A6, and the connecting end of the voltage comparator A5 and the voltage comparator A6 is connected to the third input signal from the photosensitive voltage divider driving module. The reverse input end of the voltage comparator A5 is connected to one end of R16 and one end of R17, the other end of R16 is connected to the power supply VCC, the other end of R17 is grounded, the reverse input end of the voltage comparator A6 is connected to one end of R18 and one end of R19, the other end of R18 is grounded. One end is connected to the power supply VCC, and the other end of R19 is grounded. The output end of the voltage comparator A5 is connected to the anode of the diode D5, and the output end of the voltage comparator A6 is connected to the anode of the diode D6. The connection end between the output end of the voltage comparator A5 and the anode of the diode D5 is connected to a resistor R20 as a pull-up resistor. The other end of the resistor R20 is connected to the power supply VCC2. The connection end between the output end of the voltage comparator A6 and the anode of the diode D6 is connected to a resistor R21 as a pull-up resistor. The other end of the resistor R21 is connected to the power supply VCC2. The cathodes of the two diodes D5 and D6 are connected to one end of a resistor R22, and the connection point is used as the output end through an external wire. The other end of R22 is grounded.

7. The eye health photosensitive digital display circuit according to claim 1, Features: The output signal processing and display module (3) comprises a 74148N encoder, a 7448N decoder, a common cathode seven-segment digital tube, NAND gates NAND1, NAND2, AND gates AND1, AND2, AND3, NOT gates N1, N2, N3 and light emitting diodes LED1, LED2, LED3; The input terminals D1, D2 and D3 of the 74148N encoder are respectively connected to the output terminals of the window comparator I, the output terminals of the window comparator II and the output terminals of the window comparator III of the light intensity grading module (2); the output terminals of the window comparator I, the output terminals of the window comparator II and the output terminals of the window comparator III of the light intensity grading module (2) are respectively connected to the three input terminals of the NAND gate NAND1; the output terminals of the NAND gate NAND1 are respectively connected to the input terminals D0, D4, D5, D6 and D7 of the 74148N encoder; the output terminals A0, A1 and A2 of the 74148N encoder are respectively connected through one end of the NAND gates N1, N2 and N3; The input terminals A, B, and C of the 7448N decoder are connected to the output terminals of the NOT gates N1, N2, and N3 respectively, the input terminal D thereof is grounded, and the ~LT, ~RBI, and ~BI / RBO thereof are connected to the power supply VCC2, the output terminals OA, OB, OC, OD, OE, OF, and OG of the 7448N decoder are connected to the A, B, C, D, E, F, and G terminals of the common cathode seven-segment digital tube respectively, and the CK terminal of the common cathode seven-segment digital tube is grounded; The output ends of the NOT gates N1 and N2 are also connected to the two input ends of the NAND gate NAND2, the output of NAND2 serves as one input end of the AND gates AND1 and AND2 respectively, the output end of the NOT gate N1 is also connected to the other input end of the AND gate AND1, the output end of the AND gate AND1 is connected to the anode of the light emitting diode LED1, the output end of the NOT gate N2 is also connected to the other input end of the AND gate AND2, the output end of the AND gate AND2 is connected to the anode of the light emitting diode LED2, the input end of the AND gate AND3 is connected to the outputs of the NOT gates N1 and N2, and the cathodes of the light emitting diodes LED1, LED2, and LED3 are connected and then grounded.

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