Display panel, display device and tiled display device

Abstract

The embodiment of the utility model discloses a display panel, a display device and a splicing display device. The display panel comprises a driving backboard and light-emitting devices, the driving backboard comprises a plurality of binding electrode pairs, each binding electrode pair comprises a first binding electrode and a second binding electrode which are insulated from each other, and the light-emitting devices are bound to the driving backboard through the corresponding binding electrode pairs. The light-emitting device comprises a first electrode and a second electrode which are insulated from each other, the first electrode is electrically connected with the first binding electrode, and the second electrode is electrically connected with the second binding electrode; the light-emitting surface of the light-emitting device faces the driving back plate, the light-emitting device further comprises an epitaxial wafer, and the first electrode and the second electrode are both located on the side, away from the driving back plate, of the epitaxial wafer so that the light-emitting utilization rate of the bottom light-emitting display device can be improved. The problem that the emergent light utilization rate is low due to the fact that a bottom electrode of a flip chip in a bottom light-emitting display device shields emergent light of the chip is solved.

Description

Technical Field

[0001] The embodiments of the utility model relate to the technical field of display panels, and in particular to a display panel, a display device and a spliced ​​display device. Background Art

[0002] With the continuous development of Micro LED (micro light emitting diode) technology, Micro LED is increasingly being used in display devices. Micro LED displays have advantages in both image quality and performance. However, for bottom-emitting display devices, due to the use of traditional flip chip structure, the light from the back of the chip needs to be reflected by the front package reflective layer before emitting downward, and the utilization rate of the reflected light is reduced due to the obstruction of the bottom electrode of the flip chip. Utility Model Content

[0003] The embodiments of the utility model provide a display panel, a display device and a spliced ​​display device, which can improve the light output utilization rate of the bottom-emitting display device and improve the problem of low light output utilization rate caused by the bottom electrode of the flip chip in the bottom-emitting display device blocking the output light of the chip.

[0004] The present invention provides a display panel, which includes:

[0005] A driving backplane, the driving backplane comprising a plurality of binding electrode pairs, each of the binding electrode pairs comprising a first binding electrode and a second binding electrode insulated from each other; and

[0006] A light emitting device, wherein the light emitting device is bound to the driving backplane through the corresponding binding electrode pair, the light emitting device comprises a first electrode and a second electrode which are insulated from each other, the first electrode is electrically connected to the first binding electrode, and the second electrode is electrically connected to the second binding electrode;

[0007] The light emitting surface of the light emitting device faces the driving backplane, the light emitting device further comprises an epitaxial wafer, and the first electrode and the second electrode are both located on a side of the epitaxial wafer away from the driving backplane.

[0008] Furthermore, the display panel further includes a first connecting line and a second connecting line, the first connecting line is connected between the first electrode and the first binding electrode, and the second connecting line is connected between the second electrode and the second binding electrode.

[0009] Furthermore, the light emitting device also includes an insulating protective layer, which covers the epitaxial wafer and exposes the first electrode and the second electrode, and the first connecting wire and the second connecting wire are both arranged on a side of the insulating protective layer away from the epitaxial wafer.

[0010] Furthermore, the epitaxial wafer includes an N-type semiconductor layer and a P-type semiconductor layer and a quantum well layer arranged between the N-type semiconductor layer and the P-type semiconductor layer, the P-type semiconductor layer is located on the side of the N-type semiconductor layer away from the driving backplane, the first electrode is electrically connected to the N-type semiconductor layer, and the second electrode is electrically connected to the P-type semiconductor layer.

[0011] Furthermore, the N-type semiconductor layer includes a protrusion extending beyond a boundary of the quantum well layer, the first electrode is arranged on a side of the protrusion away from the driving backplane, and the second electrode is arranged on a side of the P-type semiconductor layer away from the quantum well layer.

[0012] Furthermore, the driving backplane further includes a substrate and a transistor disposed on the substrate, the first binding electrode and the second binding electrode are both located on a side of the transistor away from the substrate, wherein the first binding electrode is electrically connected to the transistor.

[0013] The present invention also provides a display device, which includes:

[0014] A display panel, wherein the display panel is the above-mentioned display panel;

[0015] A chip-on-film structure is arranged on a side of the light-emitting device away from the driving backplane and is bound to the driving backplane.

[0016] Furthermore, the chip-on-film structure comprises:

[0017] A substrate including a first surface and a second surface arranged opposite to each other;

[0018] A first circuit, covering the first surface, wherein the first circuit includes a driver chip binding area;

[0019] A display panel binding end, located on the second surface;

[0020] The first conductive part is connected to the first circuit and the binding end of the display panel respectively.

[0021] Furthermore, the first conductive portion passes through the substrate.

[0022] Further, the substrate further includes a third surface connected to the first surface and the second surface respectively;

[0023] The first conductive portion covers the third surface.

[0024] Furthermore, the display panel binding end and the first conductive portion are arranged to overlap in a target direction, and the target direction is a direction parallel to the second surface.

[0025] Furthermore, the chip-on-film structure further includes a second circuit;

[0026] The second circuit covers the second surface, the display panel binding end is located on a side of the second circuit away from the substrate, and the first conductive portion is connected to the display panel binding end through the second circuit.

[0027] Further, the display panel binding end and the first conductive portion are spaced apart in a target direction, and the target direction is a direction parallel to the second surface;

[0028] The second circuit is located between the display panel binding end and the first conductive portion.

[0029] Furthermore, the chip-on-film structure further includes a heat insulation layer;

[0030] The heat insulation layer is located on a side of the second circuit facing away from the substrate.

[0031] Furthermore, the chip-on-film structure further includes a first protective layer, and the first protective layer is located on a side of the first circuit away from the substrate;

[0032] Furthermore, the chip-on-film structure further includes a second protective layer, and the second protective layer is located between the second circuit and the thermal insulation layer.

[0033] Further, the first circuit also includes a circuit board binding area;

[0034] The circuit board binding area and the display panel binding end are respectively arranged close to two opposite ends of the substrate.

[0035] Furthermore, the chip-on-film structure also includes a driver chip;

[0036] The driving chip is located in the driving chip binding area and is connected to the first line.

[0037] An embodiment of the utility model further provides a spliced ​​display device, comprising a plurality of spliced ​​display devices, wherein the display device is the above-mentioned display device.

[0038] The beneficial effects of the embodiments of the utility model are as follows: by directing the light-emitting surface of the light-emitting device toward the driving backplane, and making the first electrode and the second electrode of the light-emitting device both located on the side of the epitaxial wafer away from the driving backplane, the first electrode and the second electrode will not block the emitted light of the light-emitting device, thereby improving the light emission utilization rate of the bottom-emitting display device and improving the problem of low light emission utilization rate caused by the bottom electrode of the flip-chip in the bottom-emitting display device blocking the emitted light of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0040] Figure 1 is a structural schematic diagram of a display device in the related art;

[0041] Figure 2 A schematic diagram of the structure of a display panel provided by an embodiment of the utility model;

[0042] Figure 3 for Figure 2 Detailed structural diagram of the light emitting device;

[0043] Figure 4 A schematic diagram of the structure of a display device provided by an embodiment of the utility model;

[0044] Figure 5 for Figure 4 Detailed structural diagram of the flip chip film structure;

[0045] Figure 6 Another schematic structural diagram of a chip-on-film structure provided by an embodiment of the utility model;

[0046] Figure 7 Another schematic structural diagram of a chip-on-film structure provided by an embodiment of the utility model;

[0047] Figure 8 Another schematic structural diagram of a chip-on-film structure provided by an embodiment of the utility model;

[0048] Fig. 9 Another schematic structural diagram of a chip-on-film structure provided by an embodiment of the utility model;

[0049] Fig.10 is another structural schematic diagram of a display device provided by an embodiment of the utility model;

[0050] Fig.11 is another structural schematic diagram of a display device provided by an embodiment of the utility model;

[0051] Fig.12 is another structural schematic diagram of a display device provided by an embodiment of the utility model;

[0052] Fig.13 is another structural schematic diagram of a display device provided by an embodiment of the utility model;

[0053] Fig.14 It is a structural schematic diagram of a splicing display device provided by an embodiment of the utility model. DETAILED DESCRIPTION

[0054] The specific structural and functional details disclosed herein are merely representative and are for the purpose of describing exemplary embodiments of the present invention. However, the present invention can be specifically implemented in many alternative forms and should not be interpreted as being limited to the embodiments described herein.

[0055] In the description of the present utility model, it should be understood that the terms "center", "lateral", "up", "down", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present utility model. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present utility model, unless otherwise specified, "multiple" means two or more. In addition, the term "including" and any variation thereof are intended to cover non-exclusive inclusions.

[0056] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0057] The terms used herein are only for describing specific embodiments and are not intended to limit exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms "one", "one" and "item" used herein are also intended to include plural numbers. It should also be understood that the terms "include" and / or "comprise" used herein specify the existence of stated features, integers, steps, operations, units and / or components, without excluding the existence or addition of one or more other features, integers, steps, operations, units, components and / or combinations thereof.

[0058] Reference Figure 1 , Figure 1 The present invention is a schematic diagram of a structure of a display device in the related art, wherein the display device includes a display panel 20' and a chip on flexible PCB (COF) structure 10' bound to the display panel 20'. The display panel 20' includes a driving backplane 27', a light emitting device 28' disposed on the driving backplane 27', and an encapsulation layer 23' covering the light emitting device 28'. The display device is a bottom-emitting display device, wherein the light emitting surface of the light emitting device 28' faces away from the driving backplane 27', and the light emitted by the light emitting device 28' is reflected by the encapsulation layer 23' and then emitted from the driving backplane 27'. However, since the light emitting device 28' of the display device adopts a traditional flip chip structure, the light emitted from the back of the light emitting device 28' needs to be reflected by the front encapsulation reflective layer before emitting downward, and the utilization rate of the reflected light is reduced due to the obstruction of the bottom electrode of the flip chip.

[0059] To this end, the present application provides a display panel, a display device, and a spliced ​​display device to solve the above problems.

[0060] Combined with reference Figure 2 and Figure 3 , Figure 2 A schematic diagram of the structure of a display panel provided by an embodiment of the utility model, Figure 3 for Figure 2 Detailed structural diagram of the light emitting device. Figure 2The display panel 20 includes a driving backplane 27 and a light-emitting device 28 disposed on one side of the driving backplane 27. The driving backplane 27 includes a plurality of binding electrode pairs, each of which includes a first binding electrode 271 and a second binding electrode 272 that are insulated from each other. The light-emitting device 28 is bound to the driving backplane 27 through the corresponding binding electrode pair, and the light-emitting device 28 includes a first electrode 221 and a second electrode 222 that are insulated from each other, the first electrode 221 is electrically connected to the first binding electrode 271, and the second electrode 222 is electrically connected to the second binding electrode 272. The light-emitting surface of the light-emitting device 28 faces the driving backplane 27, and the light-emitting device 28 also includes an epitaxial wafer 223, and the first electrode 221 and the second electrode 222 are both located on the side of the epitaxial wafer 223 that is away from the driving backplane 27.

[0061] The light-emitting surface of the light-emitting device 28 faces the driving backplane 27, so that the light emitted by the light-emitting device 28 can directly pass through the driving backplane 27, thereby realizing the bottom light emission of the display panel 20, and at the same time improving the utilization rate of the emitted light of the light-emitting device 28. By arranging the first electrode 221 and the second electrode 222 on the side of the epitaxial wafer 223 away from the driving backplane 27, that is, on the non-light-emitting side of the light-emitting device 28, the first electrode 221 and the second electrode 222 can be prevented from blocking the emitted light of the light-emitting device 28, thereby further improving the utilization rate of the emitted light of the light-emitting device 28.

[0062] In this embodiment, the light emitting surface of the light emitting device 28 is directed toward the driving backplane 27, and the first electrode 221 and the second electrode 222 of the light emitting device 28 are both located on the side of the epitaxial wafer 223 away from the driving backplane 27. In this way, the first electrode 221 and the second electrode 222 will not block the emitted light of the light emitting device 28, thereby improving the light emission utilization rate of the bottom-emitting display device and improving the problem of low light emission utilization rate caused by the bottom electrode of the flip chip in the bottom-emitting display device blocking the emitted light of the chip.

[0063] Specifically, continue to refer to Figure 2 The driving backplane 27 also includes a substrate 40 and a transistor 50 arranged on the substrate 40, the first binding electrode 271 and the second binding electrode 222 are both located on a side of the transistor 50 away from the substrate 40, wherein the first binding electrode 271 is electrically connected to the transistor 50.

[0064] Optionally, the substrate 40 can be a rigid substrate or a flexible substrate; when the substrate 40 is a rigid substrate, it can include a hard transparent substrate such as a glass substrate, a quartz substrate or a silicon wafer; when the substrate 40 is a flexible substrate, it can include a flexible transparent substrate such as a polyimide (PI) film, an ultra-thin glass film, etc.

[0065] The driving backplane 27 also includes a light shielding layer 60 disposed on the substrate 40 and corresponding to the transistor 50, and the light shielding layer 60 is used to shield the transistor 50. The transistor 50 includes an active layer 51, a gate 52, a source 54 and a drain 53, and the first binding electrode 271 is electrically connected to the drain 53. The material of the light shielding layer 60 includes a light shielding material such as metal. The material of the active layer 51 includes a semiconductor material such as polysilicon and metal oxide. The materials of the gate 52, the source 54 and the drain 53 include metals such as copper, aluminum, titanium, and molybdenum.

[0066] The driving backplane 27 further includes a plurality of insulating layers, such as a buffer layer 41, a gate insulating layer 42, an interlayer insulating layer 43, a passivation layer 44, and a planarization layer 45. The buffer layer 41 covers the light shielding layer 60 and the substrate 40, and the buffer layer 41 can prevent undesirable impurities or pollutants (such as moisture, oxygen, etc.) from diffusing from the substrate 40 to the device that may be damaged by these impurities or pollutants, and can also provide a flat top surface.

[0067] The active layer 51 is arranged on the buffer layer 41, the gate insulating layer 42 is arranged on the active layer 51, and the gate 52 is arranged on the gate insulating layer 42. The active layer 51 includes a channel and a source region and a drain region located on both sides of the channel, and the gate 52 and the gate insulating layer 42 are both arranged corresponding to the channel. The interlayer insulating layer 43 covers the gate 52 and the buffer layer 41. The source 54 and the drain 53 are arranged on the interlayer insulating layer 43, the source 54 is electrically connected to the source region of the active layer 51, and the drain 53 is electrically connected to the drain region of the active layer 51. The passivation layer 44 covers the source 54, the drain 53 and the interlayer insulating layer 43, and the planarization layer 45 covers the passivation layer 44. The first bonding electrode 271 and the second bonding electrode 272 are disposed on the planarization layer 45 , and the first bonding electrode 271 is electrically connected to the drain electrode 53 through a via hole penetrating the planarization layer 45 and the passivation layer 44 .

[0068] Optionally, the buffer layer 41, the gate insulating layer 42, the interlayer insulating layer 43 and the passivation layer 44 can be made of silicon nitride (SiNx), silicon oxide (SiOx) or a stack of inorganic materials such as silicon nitride and silicon oxide. The material of the planarization layer 45 includes organic materials such as photoresist.

[0069] The light emitting device 28 is arranged on a side of the planarization layer 45 away from the substrate 40. The light emitting device 28 includes a Micro LED chip, a Mini LED chip or an LED chip. The transistor 50 is used to control the turning on and off of the light emitting device 28. Specifically, the first electrode 221 on the light emitting device 28 is bound to the driving backplane 27 through the first binding electrode 271, and is electrically connected to the transistor 50 through the first binding electrode 271, and the second electrode 222 on the light emitting device 28 is bound to the driving backplane 27 through the second binding electrode 272. Optionally, the first electrode 221 is a cathode, and the second electrode 222 is an anode.

[0070] The display panel 20 further includes a first connection line 31 and a second connection line 32, wherein the first connection line 31 is connected between the first electrode 221 and the first binding electrode 271, and the second connection line 32 is connected between the second electrode 222 and the second binding electrode 272. The materials of the first connection line 31, the second connection line 32, the first binding electrode 271, the second binding electrode 272, the first electrode 221, and the second electrode 222 can all be transparent conductive materials such as indium tin oxide (ITO).

[0071] Furthermore, the light emitting device 28 further includes an insulating protective layer 224, the insulating protective layer 224 covers the epitaxial wafer 223 and exposes the first electrode 221 and the second electrode 222, and the first connecting wire 31 and the second connecting wire 32 are both arranged on the side of the insulating protective layer 224 away from the epitaxial wafer 223. That is, the insulating protective layer 224 covers all areas on the epitaxial wafer 223 except the first electrode 221 and the second electrode 222 to avoid short circuit between the first connecting wire 31 and the second connecting wire 32 and the epitaxial wafer 223. The insulating protective layer 224 can be a stack of inorganic materials such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon nitride and silicon oxide.

[0072] Reference Figure 3The epitaxial wafer 223 includes an N-type semiconductor layer 2231 and a P-type semiconductor layer 2232 and a quantum well layer 2233 disposed between the N-type semiconductor layer 2231 and the P-type semiconductor layer 2232. The P-type semiconductor layer 2232 is located on a side of the N-type semiconductor layer 2231 away from the driving backplane 27. The first electrode 221 is electrically connected to the N-type semiconductor layer 2231, and the second electrode 222 is electrically connected to the P-type semiconductor layer 2232. The N-type semiconductor layer 2231 includes a protrusion that exceeds the boundary of the quantum well layer 2233. The first electrode 221 is disposed on a side of the protrusion away from the driving backplane 27, and the second electrode 222 is disposed on a side of the P-type semiconductor layer 2232 away from the quantum well layer 2233. The orthographic projection of the first electrode 221 on the driving backplane 27 is separated from the orthographic projection of the second electrode 222 on the backplane.

[0073] In order to further improve the utilization rate of the emitted light of the light emitting device 28, the orthographic projection of the transistor 50 on the substrate 40 is separated from the orthographic projection of the epitaxial wafer 223 on the substrate 40. Separated in the present utility model means that the orthographic projections of two structures on the same surface do not have overlapping parts. For example, in this embodiment, the orthographic projection of the transistor 50 on the substrate 40 is separated from the orthographic projection of the epitaxial wafer 223 on the substrate 40, which means that the orthographic projection of the transistor 50 on the substrate 40 and the orthographic projection of the epitaxial wafer 223 on the substrate 40 do not have overlapping parts, so as to avoid the transistor 50 blocking the emitted light of the light emitting device 28.

[0074] Furthermore, the display panel 20 further includes an encapsulation layer 23, and the encapsulation layer 23 covers the light emitting device 28 and the driving backplane 27. The encapsulation layer 23 is used to protect the light emitting device 28 and prevent water and oxygen from invading the light emitting device 28. Optionally, the material of the encapsulation layer 23 is a material with reflective properties to further improve the utilization rate of the emitted light of the light emitting device 28.

[0075] In one embodiment, the present invention further provides a display device, see Figures 1 to 5 , Figure 4 A schematic diagram of a display device provided in an embodiment of the utility model is shown in FIG. Figure 5 for Figure 4 Detailed structural diagram of the flip chip film structure. Figure 4 The display device 100 includes a display panel 20 and a COF structure 10. The display panel 20 is the display panel 20 of one of the above embodiments. The COF structure 10 is disposed on a side of the light emitting device 28 away from the driving backplane 27 and is bound to the driving backplane 27.

[0076] Reference Figure 4 and Figure 5 The COF structure 10 includes a substrate 1, a first circuit 2, a display panel binding terminal 3, and a first conductive portion 4. The substrate 1 includes a first surface 11 and a second surface 12 that are arranged opposite to each other, and a third surface 13 and a fourth surface 14 that are connected between the first surface 11 and the second surface 12. The first surface 11 can be the lower surface of the substrate 1, the second surface 12 can be the upper surface of the substrate 1, the third surface 13 and the fourth surface 14 are arranged opposite to each other, and both the third surface 13 and the fourth surface 14 can be the side surfaces of the substrate 1. The substrate 1 can be a PI (polyimide) substrate.

[0077] The first circuit 2 covers the first surface 11 , and the first circuit 2 includes a driver chip binding area 21 . The flip chip structure 10 also includes a driver chip 8 . The driver chip 8 is located in the driver chip binding area 21 , and the driver chip 8 is connected to the first circuit 2 , so that the driver chip 8 is bound to the first circuit 2 .

[0078] The display panel binding end 3 is located on the second surface 12 and is used to bind with the display panel. The first conductive part 4 is connected to the first line 2 and the display panel binding end 3 respectively. In this way, the driver chip binding area 21 and the display panel binding end 3 are located on opposite sides of the substrate 1. After the driver chip 8 and the display panel 20 are bound, the driver chip 8 and the display panel 20 are located on opposite sides of the substrate 1 to improve the display unevenness problem of the display panel caused by the heating of the driver chip. Among them, the top of the display panel 20 has a first binding end 24, and the first binding end 24 is arranged in the same layer as the first binding electrode 271 and the second binding electrode 272. The display panel binding end 3 is arranged facing the display panel 20 and is connected to the first binding end 24.

[0079] It should be noted that, continue to refer to Figure 1 The display device also includes a driver chip 8', and the driver chip 8' and the display panel 20' are bound to the same side of the chip-on-film structure 10', and the driver chip 8' is located between the display panel 20' and the chip-on-film structure 10'. Since the height of the driver chip 8' is relatively high, the height of the metal welding layer for binding the display panel 20' and the chip-on-film structure 10' is relatively high, resulting in a high difficulty in binding, which is prone to reliability problems and affects the binding yield. In addition, the driver chip 8' generates heat when working, causing the temperature of the display panel area close to the driver chip 8' to rise, thereby causing the luminous efficiency of the light-emitting device 28' in the display panel to decrease, and the brightness to decrease, thereby causing the display unevenness of the display panel.

[0080] The driver chip binding area 21 in this embodiment is located on the first surface 11 of the substrate 1, and the display panel binding end 3 is located on the second surface 12 of the substrate 1, that is, the driver chip binding area 21 and the display panel binding end 3 are located on opposite sides of the substrate 1, so that after the driver chip 8 and the display panel 20 are bound, the driver chip 8 and the display panel 20 are located on opposite sides of the substrate 1, so that the height of the display panel binding end 3 does not need to be too high, such as it can be less than the height of the driver chip, thereby reducing the difficulty of binding the display panel and improving the binding yield and reliability. In addition, the driver chip 8 and the display panel 20 are located on opposite sides of the substrate 1, which is conducive to the heat dissipation of the driver chip, and the heating of the driver chip will not affect the display panel, thereby improving the display unevenness problem of the display panel caused by the heating of the driver chip.

[0081] Specifically, Figure 5 As shown, the first circuit 2 covers the first surface 11 of the substrate 1. The first circuit 2 may cover the first surface 11 of the substrate 1 in whole or in part. This embodiment is described by taking the first circuit 2 covering the first surface 11 of the substrate 1 in whole as an example. The driver chip binding area 21 on the first circuit 2 may be arranged near the central area of ​​the first surface 11. The flip-chip film structure 10 further includes a circuit board 9, and the first circuit 2 further includes a circuit board binding area 22, and the circuit board binding area 22 is used to bind the circuit board 9. The circuit board 9 is located in the circuit board binding area 22, and the circuit board 9 is connected to the first circuit 2, so that the circuit board 9 is bound to the first circuit 2. The material of the first circuit 2 is a conductive metal, such as tungsten, cobalt, copper, aluminum, etc.

[0082] The display panel binding end 3 is arranged near one end of the substrate 1, for example, the display panel binding end 3 is arranged near the third surface 13 of the substrate 1. The display panel binding end 3 and the circuit board binding area 22 are arranged near the opposite ends of the substrate 1, for example, the display panel binding end 3 is arranged near the third surface 13 of the substrate 1, and the circuit board binding area 22 is arranged near the fourth surface 14 of the substrate 1. The circuit board binding area 22 and the display panel binding end 3 are arranged near the opposite ends of the substrate 1, so as to avoid damage to the circuit board 9 caused by the binding heating of the display panel binding end 3 and the display panel 20 after the circuit board 9 is bound. Optionally, the display panel binding end 3 can be a welding metal, and the material of the welding metal is a conductive metal, such as tungsten, cobalt, copper, aluminum, etc.

[0083] The flip chip structure 10 also includes a second circuit 5, and the second surface 12 of the substrate 1 completely covers the second circuit 5, and the display panel binding terminal 3 is located on the side of the second circuit 5 away from the substrate 1. The first conductive part 4 can penetrate the substrate 1, so that one end of the first conductive part 4 is connected to the first circuit 2, and the other end of the first conductive part 4 is connected to the display panel binding terminal 3 through the second circuit 5, that is, the first conductive part 4 is connected to the first circuit 2 and the display panel binding terminal 3 respectively. In this way, after binding the driver chip 8 and the display panel 20, the driver chip 8 can be electrically connected to the display panel 20 through the first circuit 2, the first conductive part 4 and the display panel binding terminal 3. Among them, the first conductive part 4 and the display panel binding terminal 3 are spaced apart in the target direction A (i.e., the direction parallel to the second surface 12). The material of the first conductive part 4 is a conductive metal, such as tungsten, cobalt, copper, aluminum, etc.

[0084] In addition, when manufacturing the second circuit 5 in this embodiment, the second circuit 5 completely covers the second surface 12 of the substrate 1, and there is no need to etch the second circuit 5, so as to reduce the height of the display panel binding end 3, reduce the process difficulty of the display panel binding end 3, and simplify the manufacturing process of the second circuit 5.

[0085] Alternatively, if Figure 5 As shown, the flip chip structure 10 may further include a heat insulating layer 6, which is located on the side of the second circuit 5 away from the substrate 1. The heat insulating layer 6 may be provided in other areas of the second circuit 5 except the connection area with the display panel binding end 3 to isolate the heat generated by the second circuit 5, so as to prevent the heat generated by the second circuit 5 from affecting the display panel after the display panel is bound, thereby avoiding the problem of uneven display of the display panel caused by the heat dissipation of the second circuit 5.

[0086] Alternatively, if Figure 5 As shown, the flip chip structure 10 may further include a first protective layer 71, which is located on the side of the first circuit 2 away from the substrate 1. All areas of the first circuit 2 except the driver chip binding area 21 and the circuit board binding area 22 may be covered with the first protective layer 71, so that the first protective layer 71 can protect the first circuit 2.

[0087] Alternatively, if Figure 5 As shown, the COF structure 10 may further include a second protective layer 72, which is located between the second circuit 5 and the thermal insulation layer 6. All areas of the second circuit 5 except the connection area with the display panel binding end 3 may be covered with the second protective layer 72, so that the second protective layer 72 can protect the second circuit 5. The thermal insulation layer 6 may completely cover the second protective layer 72 to ensure that the heat generated by the second circuit 5 is effectively isolated.

[0088] In other embodiments, the chip-on-film structure 10 may also be the following structure. Figures 6 to 8 , Figures 6 to 8 It is a structural schematic diagram of a chip-on-film structure provided by an embodiment of the utility model.

[0089] In one embodiment, Figure 6 As shown, the first circuit 2 covers the first surface 11 of the substrate 1, and the first conductive part 4 covers the third surface 13 of the substrate 1, so that one end of the first conductive part 4 is connected to the first circuit 2. The display panel binding end 3 is located on the second surface 12 of the substrate 1, and the display panel binding end 3 and the first conductive part 4 are overlapped in the target direction A (i.e., the direction parallel to the second surface 12), that is, the display panel binding end 3 is arranged close to the third surface 13 of the substrate 1, so that the other end of the first conductive part 4 is directly connected to the display panel binding end 3, that is, the second surface 12 of the substrate 1 does not cover the second circuit 5. In this embodiment, the display panel binding end 3 is directly arranged on the second surface 12 of the substrate 1, while reducing the thickness of the flip chip film structure, the height of the display panel binding end 3 can be reduced as much as possible, reducing the difficulty of binding the display panel, and improving the binding yield and reliability.

[0090] In another embodiment, Figure 7 As shown, the first circuit 2 covers the first surface 11 of the substrate 1, and the first conductive part 4 penetrates the substrate 1, so that one end of the first conductive part 4 is connected to the first circuit 2. The display panel binding terminal 3 is located on the second surface 12 of the substrate 1, and the display panel binding terminal 3 and the first conductive part 4 are overlapped in the target direction A (i.e., the direction parallel to the second surface 12), so that the other end of the first conductive part 4 is directly connected to the display panel binding terminal 3. This embodiment can avoid the first conductive part 4 from being exposed while reducing the thickness of the chip-on-film structure and reducing the height of the display panel binding terminal 3 as much as possible, thereby avoiding the first conductive part 4 from being short-circuited with other conductive structures.

[0091] In another embodiment, Figure 8 As shown, the first circuit 2 covers the first surface 11 of the substrate 1, and the first conductive part 4 covers the third surface 13 of the substrate 1, so that one end of the first conductive part 4 is connected to the first circuit 2. The display panel binding end 3 and the first conductive part 4 are spaced apart in the target direction A (i.e., the direction parallel to the second surface 12), and the second surface 12 of the substrate 1 partially covers the second circuit 5, that is, the second circuit 5 is located between the display panel binding end 3 and the first conductive part 4, and the display panel binding end 3 is located on the side of the second circuit 5 away from the substrate 1, so that the other end of the first conductive part 4 is connected to the display panel binding end 3 through the second circuit 5. This embodiment can increase the area where the display panel binding end 3 can be set on the second surface 12 while reducing the height of the display panel binding end 3, thereby reducing the process difficulty of the display panel binding end 3.

[0092] like Figure 8 As shown, the flip chip structure may further include a heat insulating layer 6, which is located on the side of the second circuit 5 away from the substrate 1. The heat insulating layer 6 may be provided in other areas of the second circuit 5 except the connection area with the display panel binding end 3 to isolate the heat generated by the second circuit 5, so as to prevent the heat generated by the second circuit 5 from affecting the display panel after the display panel is bound, thereby avoiding the problem of uneven display of the display panel caused by the heat dissipation of the second circuit 5.

[0093] The chip-on-film structure may further include a second protective layer 72, which is located between the second circuit 5 and the thermal insulation layer 6. All areas of the second circuit 5 except the connection area with the display panel binding end 3 may be covered with the second protective layer 72, so that the second protective layer 72 can protect the second circuit 5. The thermal insulation layer 6 may completely cover the second protective layer 72 to ensure that the heat generated by the second circuit 5 is effectively isolated.

[0094] In another embodiment, Fig. 9 As shown, the first circuit 2 covers the first surface 11 of the substrate 1, and the first conductive part 4 penetrates the substrate 1, so that one end of the first conductive part 4 is connected to the first circuit 2. The display panel binding end 3 and the first conductive part 4 are spaced apart in the target direction A, and the second surface 12 of the substrate 1 partially covers the second circuit 5, that is, the second circuit 5 is located between the display panel binding end 3 and the first conductive part 4, and the display panel binding end 3 is located on the side of the second circuit 5 away from the substrate 1, so that the other end of the first conductive part 4 is connected to the display panel binding end 3 through the second circuit 5. This embodiment can reduce the height of the display panel binding end 3 and reduce the process difficulty of the display panel binding end 3, while avoiding the first conductive part 4 from being exposed, thereby avoiding the first conductive part 4 from being short-circuited with other conductive structures.

[0095] like Fig. 9 As shown, the flip chip structure may further include a heat insulating layer 6, which is located on the side of the second circuit 5 away from the substrate 1. The heat insulating layer 6 may be provided in other areas of the second circuit 5 except the connection area with the display panel binding end 3 to isolate the heat generated by the second circuit 5, so as to prevent the heat generated by the second circuit 5 from affecting the display panel after the display panel is bound, thereby avoiding the problem of uneven display of the display panel caused by the heat dissipation of the second circuit 5.

[0096] The chip-on-film structure may further include a second protective layer 72, which is located between the second circuit 5 and the thermal insulation layer 6. All areas of the second circuit 5 except the connection area with the display panel binding end 3 may be covered with the second protective layer 72, so that the second protective layer 72 can protect the second circuit 5. The thermal insulation layer 6 may completely cover the second protective layer 72 to ensure that the heat generated by the second circuit 5 is effectively isolated.

[0097] The flip chip film structure provided by the embodiment of the utility model covers a first circuit on the first surface of the substrate, and the first circuit includes a driver chip binding area, and a display panel binding end is arranged on the second surface of the substrate. The first surface and the second surface are arranged opposite to each other, and the first circuit is connected to the display panel binding end through the first conductive part to ensure that the driver chip and the display panel are bound to the opposite sides of the substrate, avoid the display panel binding end being too high, reduce the difficulty of binding the display panel, improve the binding yield and reliability, and facilitate the heat dissipation of the driver chip, thereby improving the display unevenness problem of the display panel caused by the heating of the driver chip.

[0098] Accordingly, in some embodiments, the display device of the present invention may also be of the following structure: Figures 10 to 13 , Figures 10 to 13 is a schematic diagram of the structure of a display device provided by an embodiment of the utility model, wherein Figures 10 to 13 The display device is composed of Figures 6 to 9 The chip-on-film structures 10 are respectively bonded with the display panels 20 to form.

[0099] Specifically, Figures 10 to 13 As shown, the top of the display panel 20 has a first binding end 24 , the COF structure 10 is located on the top of the display panel 20 , and the display panel binding end 3 in the COF structure 10 is arranged facing the display panel 20 to be connected to the first binding end 24 .

[0100] The display panel 20 includes a driving backplane 27, a light emitting device 28 located on the driving backplane 27, and an encapsulation layer 23 covering the light emitting device 28 and the driving backplane 27. The light emitting device 28 may be a micro light emitting diode MicroLED. The encapsulation layer 23 is used to encapsulate and protect the light emitting device 28. Of course, when the encapsulation layer 23 is made of a material with reflective properties, the encapsulation layer 23 can also be used to reflect the light emitted by the light emitting device 28 to the bottom of the display panel 20 (i.e., the side of the driving backplane 27 away from the encapsulation layer 23), so as to further improve the utilization rate of the light emitted by the light emitting device 28.

[0101] The first binding terminal 24 may be located on the driving backplane 27, and the encapsulation layer 23 does not cover the first binding terminal 24. The COF structure 10 may be located on the top of the display panel 20 (i.e., the side of the encapsulation layer 23 away from the driving backplane 27), and the display panel binding end 3 in the COF structure 10 is arranged facing the display panel 20 to be connected with the first binding end 24. The display panel 20 is connected to the COF structure 10 through the first binding terminal 24 and the display panel binding end 3, thereby realizing the binding of the display panel 20 to the COF structure 10.

[0102] The display device provided by the embodiment of the utility model can bind the driving chip and the display panel on the opposite sides of the substrate, thereby avoiding the height of the binding end of the display panel being too high, reducing the difficulty of binding the display panel, improving the binding yield and reliability, and being beneficial to the heat dissipation of the driving chip, thereby improving the display unevenness problem of the display panel caused by the heat generated by the driving chip.

[0103] In one embodiment, see Fig.14 The present utility model also provides a splicing display device. Fig.14 It is a structural schematic diagram of a splicing display device provided by an embodiment of the utility model.

[0104] like Fig.14 As shown, the spliced ​​display device provided by the embodiment of the present invention includes a plurality of spliced ​​display devices 100 , each of which can be the display device in the above embodiment, which will not be described in detail herein.

[0105] In summary, although the present invention has been disclosed as above in terms of preferred embodiments, the above preferred embodiments are not intended to limit the present invention. A person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined in the claims.

Claims

1. A display panel, characterized in that: include: A driving backplane, the driving backplane comprising a plurality of binding electrode pairs, each of the binding electrode pairs comprising a first binding electrode and a second binding electrode insulated from each other; as well as A light emitting device, wherein the light emitting device is bound to the driving backplane through the corresponding binding electrode pair, the light emitting device comprises a first electrode and a second electrode insulated from each other, the first electrode is electrically connected to the first binding electrode, and the second electrode is electrically connected to the second binding electrode; The light emitting surface of the light emitting device faces the driving backplane, the light emitting device further comprises an epitaxial wafer, and the first electrode and the second electrode are both located on a side of the epitaxial wafer away from the driving backplane.

2. The display panel according to claim 1, characterized in that: The display panel further includes a first connection line and a second connection line, wherein the first connection line is connected between the first electrode and the first binding electrode, and the second connection line is connected between the second electrode and the second binding electrode.

3. The display panel according to claim 2, characterized in that: The light emitting device further comprises an insulating protective layer, which covers the epitaxial wafer and exposes the first electrode and the second electrode. The first connecting wire and the second connecting wire are both arranged on a side of the insulating protective layer away from the epitaxial wafer.

4. The display panel according to any one of claims 1 to 3, characterized in that: The epitaxial wafer includes an N-type semiconductor layer and a P-type semiconductor layer and a quantum well layer arranged between the N-type semiconductor layer and the P-type semiconductor layer, the P-type semiconductor layer is located on the side of the N-type semiconductor layer away from the driving backplane, the first electrode is electrically connected to the N-type semiconductor layer, and the second electrode is electrically connected to the P-type semiconductor layer.

5. The display panel according to claim 4, characterized in that: The N-type semiconductor layer includes a protrusion that exceeds the boundary of the quantum well layer. The first electrode is arranged on a side of the protrusion away from the driving backplane. The second electrode is arranged on a side of the P-type semiconductor layer away from the quantum well layer.

6. The display panel according to claim 5, characterized in that: The driving backplane further includes a substrate and a transistor disposed on the substrate, the first binding electrode and the second binding electrode are both located on a side of the transistor away from the substrate, wherein the first binding electrode is electrically connected to the transistor.

7. A display device, characterized in that: include: A display panel, wherein the display panel is the display panel according to any one of claims 1 to 6; A chip-on-film structure is arranged on a side of the light-emitting device away from the driving backplane and is bound to the driving backplane.

8. The display device according to claim 7, characterized in that: The chip-on-film structure comprises: A substrate including a first surface and a second surface arranged opposite to each other; A first circuit, covering the first surface, wherein the first circuit includes a driver chip binding area; A display panel binding end, located on the second surface; A first conductive part, connected to the first circuit and the display panel binding end respectively; The top of the display panel has a first binding end, and the display panel binding end is arranged facing the display panel and connected to the first binding end.

9. The display device according to claim 8, characterized in that: The first conductive portion penetrates the substrate.

10. The display device according to claim 8, characterized in that: The substrate further includes a third surface connected to the first surface and the second surface respectively; The first conductive portion covers the third surface.

11. The display device according to any one of claims 8 to 10, characterized in that: The display panel binding end and the first conductive portion are overlapped in a target direction, and the target direction is a direction parallel to the second surface.

12. The display device according to any one of claims 8 to 10, characterized in that: The chip-on-film structure further includes a second circuit; The second circuit covers the second surface, the display panel binding end is located on a side of the second circuit away from the substrate, and the first conductive portion is connected to the display panel binding end through the second circuit.

13. The display device according to claim 12, characterized in that: The display panel binding end and the first conductive portion are spaced apart in a target direction, and the target direction is a direction parallel to the second surface; The second circuit is located between the display panel binding end and the first conductive portion.

14. The display device according to claim 12, characterized in that: The chip-on-film structure also includes a heat insulation layer; The heat insulation layer is located on a side of the second circuit facing away from the substrate.

15. The display device according to claim 8, characterized in that: The chip-on-film structure further includes a first protective layer; The first protection layer is located on a side of the first circuit facing away from the substrate.

16. The display device according to claim 14, characterized in that: The chip-on-film structure further includes a second protective layer; The second protective layer is located between the second circuit and the heat insulation layer.

17. The display device according to claim 8, characterized in that: The first circuit also includes a circuit board binding area; The circuit board binding area and the display panel binding end are respectively arranged close to two opposite ends of the substrate.

18. The display device according to claim 8, characterized in that The chip-on-film structure also includes a driver chip; The driving chip is located in the driving chip binding area and is connected to the first line.

19. A splicing display device, characterized in that: It comprises a plurality of display devices that are spliced ​​together, and the display device is the display device as described in any one of claims 7 to 18.

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