Display panel and display device

By introducing isolation columns into the display panel to separate the light emitting layer connections of adjacent sub-pixels, the crosstalk problem in the display panel is solved and the display effect is improved.

CN222235417UActive Publication Date: 2024-12-24BOE TECHNOLOGY GROUP CO LTD +1
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Patent Information

Application Number
CN202323269707.6
Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
Filing Date
2023-11-30
Publication Date
2024-12-24
Estimated Expiration
2033-11-30

AI Technical Summary

Technical Problem

In the display panel, the connection of light emitting layers of adjacent sub-pixels causes crosstalk, affecting the display effect.

Method used

A display panel is designed, including a substrate, a light emitting functional layer and a plurality of isolation columns. The isolation column is located between the openings of two adjacent sub-pixels, and the light emitting layer of two adjacent sub-pixels is separated and the cathode of two adjacent sub-pixels is connected. Prevent the light emitting layer from being connected.

Benefits of technology

It effectively prevents crosstalk, improves the display effect, and ensures the normal luminescence of the display panel.

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Abstract

The embodiment of the utility model provides a display panel and a display device, and the display panel comprises a substrate, a light-emitting function layer and a plurality of isolation columns. The light-emitting functional layer is arranged on one side of the substrate and comprises a first flat layer and a pixel limiting layer; the pixel limiting layer is provided with a plurality of pixel openings, the plurality of pixel openings are configured to accommodate a plurality of sub-pixels, and each sub-pixel comprises an anode, a light-emitting layer and a cathode which are sequentially arranged in the direction away from the substrate; the first flat layer and the pixel defining layer further comprise a plurality of isolation column openings, and each isolation column opening is located between every two adjacent pixel openings. And each isolation column in the plurality of isolation columns is located in the isolation column opening between the two adjacent pixel openings, and the isolation columns are configured to isolate the light emitting layers of the two adjacent sub-pixels and connect the cathodes of the two adjacent sub-pixels. According to the display panel provided by the embodiment of the invention, the isolation columns are arranged, so that crosstalk caused by connection of the light-emitting layers of the two adjacent sub-pixels is prevented.
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Description

Technical Field

[0001] The utility model relates to the field of display technology, in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, under-screen cameras have become a development trend. The display panel in the related art has a display area and a peripheral area surrounding the display area. The display area includes an under-screen camera area and a normal display area located on at least one side of the under-screen camera area. Both the under-screen camera area and the normal display area have multiple sub-pixels. The light-emitting layers of adjacent sub-pixels are connected, which will cause crosstalk and lead to poor display. Utility Model Content

[0003] The purpose of the embodiments of the utility model is to provide a display panel and a display device to prevent the occurrence of crosstalk caused by the connection of the light-emitting layers of two adjacent sub-pixels, thereby improving the display effect. The specific technical solution is as follows:

[0004] An embodiment of the first aspect of the present application proposes a display panel, which includes a display area and a peripheral area surrounding the display area, the display area including a first display area and a second display area, and the second display area is located on at least one side of the first display area; the display panel includes a substrate, a light-emitting functional layer and a plurality of isolation columns; the light-emitting functional layer is arranged on one side of the substrate, including a first flat layer and a pixel defining layer; the pixel defining layer has a plurality of pixel openings, and the plurality of pixel openings are configured to accommodate a plurality of sub-pixels, and the sub-pixels include an anode, a light-emitting layer and a cathode arranged in sequence in a direction away from the substrate; the first flat layer and the pixel defining layer also include a plurality of isolation column openings, each of the isolation column openings is located between two adjacent pixel openings; each of the plurality of isolation columns is located in the isolation column opening between two adjacent pixel openings, and the isolation column is configured to isolate the light-emitting layers of two adjacent sub-pixels and connect the cathodes of two adjacent sub-pixels.

[0005] In some embodiments of the present application, the isolation column opening includes: a first opening penetrating the first planar layer and a second opening penetrating the pixel defining layer, and the first opening is connected to the second opening;

[0006] The isolation column is located in the first opening.

[0007] In some embodiments of the present application, the isolation column includes: a first sub-isolation layer, a second sub-isolation layer, a third sub-isolation layer, and a fourth sub-isolation layer, which are sequentially arranged in a direction away from the substrate;

[0008] In a first direction, the second sub-isolating layer is retracted inwardly relative to the first sub-isolating layer; the third sub-isolating layer is retracted inwardly relative to the second sub-isolating layer and the fourth sub-isolating layer to form an undercut structure;

[0009] The second sub-isolating layer is a conductive structure, and cathodes of two adjacent sub-pixels are connected through the second sub-isolating layer.

[0010] In some embodiments of the present application, the orthographic projection of the fourth sub-isolation layer on the substrate covers the orthographic projection of the first sub-isolation layer on the substrate.

[0011] In some embodiments of the present application, the side surfaces of the first sub-isolating layer and the second sub-isolating layer are sloped surfaces;

[0012] In the first direction, cross sections of the first sub-isolating layer and the second sub-isolating layer are both upright trapezoidal structures.

[0013] In some embodiments of the present application, the isolation column includes: a fifth sub-isolation layer, a sixth sub-isolation layer, and a seventh sub-isolation layer, which are sequentially arranged in a direction away from the substrate;

[0014] In the first direction, the sixth sub-isolating layer is retracted inwardly relative to the fifth sub-isolating layer and the seventh sub-isolating layer to form an undercut structure;

[0015] The fifth sub-isolating layer is a conductive structure, and cathodes of two adjacent sub-pixels are connected through the fifth sub-isolating layer.

[0016] In some embodiments of the present application, the side surface of the fifth sub-isolation layer is a slope surface or a vertical surface;

[0017] The side surface of the sixth sub-isolating layer is a slope surface;

[0018] In the first direction, the cross section of the fifth sub-isolation layer is an upright trapezoidal structure or a rectangular structure; the cross section of the sixth sub-isolation layer is an upright trapezoidal structure.

[0019] In some embodiments of the present application, each of the isolation columns is disposed around one of the sub-pixels; and the isolation columns of two adjacent sub-pixels are connected to each other.

[0020] In some embodiments of the present application, the display panel further includes: a driving circuit layer;

[0021] The driving circuit layer is arranged between the substrate and the light-emitting functional layer; the driving circuit layer comprises a plurality of thin film transistors; the plurality of thin film transistors are electrically connected to the anodes of the plurality of sub-pixels one by one; the driving circuit layer further comprises a first gate insulating layer, a second gate insulating layer and an interlayer insulating layer, which are arranged in sequence in a direction away from the substrate;

[0022] The thin film transistor comprises: a first electrode, a second electrode, a gate electrode and an active layer;

[0023] The active layer is disposed between the substrate and the first gate insulating layer;

[0024] The gate is disposed between the first gate insulating layer and the second gate insulating layer;

[0025] The first electrode and the second electrode are arranged in the same layer and are located on a side of the interlayer insulating layer away from the substrate;

[0026] A plurality of first sets of holes are formed on the first gate insulating layer, the second gate insulating layer and the interlayer insulating layer, and the first electrode and the second electrode are respectively connected to the active layer through different first sets of holes.

[0027] In some embodiments of the present application, the driving circuit layer further includes: a passivation layer, a plurality of data lines and a conductive connection layer;

[0028] The passivation layer is arranged on a side of the first pole and the second pole away from the substrate;

[0029] The plurality of data lines are arranged in the same layer as the gate;

[0030] The conductive connection layer is arranged between the passivation layer and the light-emitting functional layer;

[0031] A plurality of second sets of holes are formed on the second gate insulating layer, the interlayer insulating layer and the passivation layer, and adjacent data lines are electrically connected to the conductive connection layer respectively through different second sets of holes.

[0032] In some embodiments of the present application, the driving circuit layer includes: a second planar layer;

[0033] The second planar layer is disposed between the first planar layer and the conductive connection layer;

[0034] The plurality of isolation columns are disposed on a side of the second planar layer away from the substrate and are disposed in contact with the second planar layer.

[0035] In some embodiments of the present application, the display panel further includes: a first inorganic layer and a buffer layer;

[0036] The first inorganic layer is formed on a side of the cathode away from the substrate and covers the cathode; the first inorganic layer extends to a side of the isolation column and is disconnected at the isolation column;

[0037] The buffer layer is disposed between the substrate and the active layer.

[0038] In some embodiments of the present application, the plurality of sub-pixels are respectively located in the first display area and the second display area, and a pixel density of the sub-pixels in the first display area is less than or equal to a pixel density of the sub-pixels in the second display area.

[0039] In some embodiments of the present application, the transmittance of the first display area is greater than the transmittance of the second display area.

[0040] An embodiment of the second aspect of the present application provides a display device, comprising a display panel implemented in any one of the first aspects, and a sensor located on a non-display surface side of the display panel, wherein the sensor's orthographic projection on the display panel at least partially overlaps with the first display area.

[0041] Beneficial effects of the embodiments of the present application:

[0042] The display panel of the embodiment of the present application has a display area and a peripheral area surrounding the display area, and the display area includes a first display area and a second display area; the display panel includes a substrate, a light-emitting functional layer and a plurality of isolation columns, and since the first display area and the second display area both have display functions, the first display area and the second display area both have a plurality of sub-pixels; each isolation column is located in an isolation column opening between two adjacent pixel openings, and the isolation column is configured to isolate the light-emitting layers of two adjacent sub-pixels and connect the cathodes of two adjacent sub-pixels; the cathodes of two adjacent sub-pixels are connected through the isolation column, thereby ensuring the normal light emission of the display panel; the light-emitting layers of two adjacent sub-pixels are isolated by the isolation column, thereby preventing the occurrence of crosstalk caused by the connection of the light-emitting layers of two adjacent sub-pixels, thereby improving the display effect.

[0043] The display device of the embodiment of the present application includes a display panel whose isolation column is configured to isolate the light-emitting layer of two adjacent sub-pixels and connect the cathodes of two adjacent sub-pixels; the cathodes of two adjacent sub-pixels are connected through the isolation column, thereby ensuring normal light emission of the display panel; the light-emitting layers of two adjacent sub-pixels are isolated by the isolation column, preventing the occurrence of crosstalk caused by the connection of the light-emitting layers of two adjacent sub-pixels, thereby improving the display effect.

[0044] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0046] Figure 1 A top view of a display panel according to an embodiment of the present application;

[0047] Figure 2a This is a schematic structural diagram of a display panel according to a first embodiment of the present application;

[0048] Figure 2b for Figure 2a A partial enlarged schematic diagram of

[0049] Figure 3 for Figure 2a A schematic diagram of the structure of the isolation column in the illustrated embodiment;

[0050] Figure 4a A diagram showing the position relationship between the isolation column and the sub-pixel in the first embodiment of the present application;

[0051] Figure 4b for Figure 1 A partial enlarged schematic diagram of the first display area;

[0052] Figure 4c for Figure 4b A diagram showing the relationship between the positions of the isolation columns and the sub-pixels in the display island area;

[0053] Figure 5 This is a schematic structural diagram of a display panel according to a second embodiment of the present application;

[0054] Figure 6 for Figure 5 A schematic diagram of the structure of the isolation column in the illustrated embodiment;

[0055] Figure 7 This is a schematic structural diagram of a display panel according to a third embodiment of the present application;

[0056] Figure 8 Schematic diagram of the structure of a display device according to an embodiment of the present application.

[0057] Description of reference numerals:

[0058] Display panel 10; sensor 20; display area AA; first display area A1; display island area A11; light-transmitting area A12; second display area A2; peripheral area BB; isolation column opening W; first set of holes H1; second set of holes H2; third set of holes H3; fourth set of holes H4; via H5; sub-pixel P; red sub-pixel P1; green sub-pixel P2; blue sub-pixel P3; substrate 100; light-emitting functional layer 200; pixel defining layer 210; pixel opening 211; second opening 212; cathode 220; light-emitting layer 230; red light-emitting layer 231; green light-emitting layer 232; anode 240; first flat layer 250; first opening 251; isolation column 300; conductive structure 301; first sub-pixel Isolation layer 311; second sub-isolation layer 312; third sub-isolation layer 313; fourth sub-isolation layer 314; fifth sub-isolation layer 315; sixth sub-isolation layer 316; seventh sub-isolation layer 317; drive circuit layer 400; pixel circuit 401; thin film transistor 410; first electrode 411; second electrode 412; gate 413; active layer 414; first electrode contact area 4141; semiconductor area 4142; second electrode contact area 4143; third electrode 415; first gate insulating layer 420; second gate insulating layer 430; interlayer insulating layer 440; passivation layer 450; data line 460; conductive connection layer 470; second planarization layer 480; first inorganic layer 500; buffer layer 600. DETAILED DESCRIPTION

[0059] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field based on this application belong to the scope of protection of the utility model.

[0060] The display panel in the related art has a display area and a peripheral area surrounding the display area, the display area includes an under-screen camera area and a normal display area located on at least one side of the under-screen camera area; the under-screen camera area and the normal display area both have multiple sub-pixels, and the light-emitting layers between adjacent sub-pixels are connected, which may cause crosstalk and result in poor display. The embodiment of the present application proposes a display panel and a display device to prevent the occurrence of crosstalk caused by the connection of the light-emitting layers of two adjacent sub-pixels, thereby improving the display effect.

[0061] like Figure 1 to Figure 2b As shown, Figure 1 is a top view of the display panel 10 according to an embodiment of the present application. Figure 2a Schematic diagram of the structure of the display panel 10 according to the first embodiment of the present application. Figure 2b for Figure 2aA partial enlarged schematic diagram; The embodiment of the first aspect of the present application provides a display panel 10, the display panel 10 includes a display area AA and a peripheral area BB surrounding the display area AA, the display area AA includes a first display area A1 and a second display area A2, the second display area A2 is located on at least one side of the first display area A1; Figure 2a and Figure 2b As shown, the display panel 10 includes a substrate 100, a light-emitting functional layer 200 and a plurality of isolation columns 300; the light-emitting functional layer 200 is disposed on one side of the substrate 100, and includes a first planar layer 250 and a pixel defining layer 210; the pixel defining layer 210 has a plurality of pixel openings 211, and the plurality of pixel openings 211 are configured to accommodate a plurality of sub-pixels P, and the sub-pixels P include an anode 240 (AND), a light-emitting layer 230 (EL) and a cathode 220 sequentially disposed in a direction away from the substrate 100; the first planar layer 250 and the pixel defining layer 210 also include a plurality of isolation column openings W (such as Figure 2b (as shown in the dashed box in the middle), each isolation column opening W is located between two adjacent pixel openings 211; each isolation column 300 among the multiple isolation columns 300 is located in the isolation column opening W between two adjacent pixel openings 211, and the isolation column 300 is configured to isolate the light-emitting layer 230 of two adjacent sub-pixels P and connect the cathode 220 of two adjacent sub-pixels P.

[0062] The display panel 10 of the embodiment of the present application has a display area AA and a peripheral area BB surrounding the display area AA, the display area AA includes a first display area A1 and a second display area A2; the display panel 10 includes a substrate 100, a light-emitting functional layer 200 and a plurality of isolation columns 300, and since the first display area A1 and the second display area A2 both have display functions, the first display area A1 and the second display area A2 both have a plurality of sub-pixels P; each isolation column 300 is located in an isolation column opening W between two adjacent pixel openings 211, and the isolation column 300 is configured to isolate the light-emitting layer 230 of two adjacent sub-pixels P and connect the cathode 220 of two adjacent sub-pixels P; the cathode 220 of two adjacent sub-pixels P is connected through the isolation column 300, thereby ensuring the normal light emission of the display panel 10; the light-emitting layer 230 of two adjacent sub-pixels P is isolated by the isolation column 300, thereby preventing the occurrence of crosstalk caused by the connection of the light-emitting layer 230 of two adjacent sub-pixels P, thereby improving the display effect.

[0063] like Figure 1 In the embodiment shown, the first display area A1 may be located at the top center of the display area AA; the second display area A2 may surround the first display area A1. In other embodiments of the present application, the first display area A1 may also be located at other positions such as the upper left corner, lower left corner, lower right corner or upper right corner of the display area AA; the second display area A2 may surround at least one side of the first display area A1.

[0064] Multiple sub-pixels P are respectively located in the first display area A1 and the second display area A2. When the first display area A1 is the Full Display With Camera (FDC) area and the second display area A2 is the normal display area, the pixel density of the sub-pixels P in the first display area A1 may be less than or equal to the pixel density of the sub-pixels P in the second display area A2. When the pixel density of the sub-pixels P in the first display area A1 is less than the pixel density of the sub-pixels P in the second display area A2, it is beneficial to improve the transmittance of the first display area A1, thereby facilitating the operation of the camera corresponding to the first display area A1. When the pixel densities of the first display area A1 and the second display area A2 are equal, the display difference between the two can be reduced, thereby improving the display effect.

[0065] In the first embodiment of the present application, the light transmittance of the first display area A1 may be greater than the light transmittance of the second display area A2, thereby facilitating the stable operation of the camera arranged corresponding to the first display area A1.

[0066] It can be understood that since the cathode 220 is a translucent material, the cathodes 220 of two adjacent sub-pixels P are connected through the isolation column 300, which is equivalent to replacing part of the cathode 220 with the isolation column 300. For the top-emitting display panel, the light needs to be emitted through the cathode 220. In this way, when the transmittance of the isolation column 300 is greater than the transmittance of the cathode 220, for example, the isolation column 300 is made of a transparent material, the transmittance of the display panel 10 can be increased, which is beneficial to the stable operation of the camera set corresponding to the first display area A1.

[0067] In the first embodiment of the present application, Figure 2b As shown, the isolation column opening W includes a first opening 251 penetrating the first flat layer 250 and a second opening 212 penetrating the pixel defining layer 210, and the first opening 251 and the second opening 212 are connected; the isolation column 300 is located in the first opening 251. In some other embodiments of the present application, the first opening 251 of the first flat layer 250 may also be a groove, and does not penetrate the first flat layer 250, and can be set according to actual needs, and the present application does not limit this.

[0068] In the first embodiment of the present application, Figure 3 and Figure 4a As shown, Figure 3 for Figure 2a The schematic diagram of the structure of the isolation column 300 in the embodiment shown, Figure 4a: is a positional relationship diagram of the isolation column 300 and the sub-pixel P in the first embodiment of the present application. The isolation column 300 includes a first sub-isolation layer 311, a second sub-isolation layer 312, a third sub-isolation layer 313 and a fourth sub-isolation layer 314, which are sequentially arranged in a direction away from the substrate 100 (PI, polyimide); Figure 4a The first direction may be the width direction of the isolation column 300; the second sub-isolation layer 312 is retracted inwardly relative to the first sub-isolation layer 311; the third sub-isolation layer 313 is retracted inwardly relative to the second sub-isolation layer 312 and the fourth sub-isolation layer 314, forming an undercut structure (as shown in FIG. Figure 3 As shown in the dotted box), the undercut structure is a groove formed by the third sub-isolation layer 313 being indented inwardly relative to the fourth sub-isolation layer 314; the light-emitting layer 230 of two adjacent sub-pixels P can be effectively disconnected; Figure 2a As shown, each light-emitting layer 230 is formed in the corresponding pixel opening 211, and extends outward from the pixel opening 211 to the side of the isolation column 300. The light-emitting layers 230 of adjacent sub-pixels P are disconnected at the isolation column 300, and the light-emitting layer 230 is not provided on the top surface of the isolation column 300, thereby avoiding the light-emitting layers 230 of adjacent sub-pixels P from being connected to each other to cause poor display. Specifically, the light-emitting layers 230 of the plurality of sub-pixels P may include a red light-emitting layer 231, a green light-emitting layer 232, and a blue light-emitting layer (not shown in the figure).

[0069] like Figure 2a As shown, each cathode 220 is formed in the corresponding pixel opening 211 and extends outward from the pixel opening 211 to the side of the second sub-isolation layer 312; the second sub-isolation layer 312 is a conductive structure 301, and the cathodes 220 of two adjacent sub-pixels P are connected through the second sub-isolation layer 312; thereby ensuring the normal display of the display panel 10.

[0070] It can be understood that in some other embodiments of the present application, the conductive structure 301 can also be other film layers of the isolation column 300. The cathode 220 is arranged in contact with any film layer in the first sub-isolation layer 311, the second sub-isolation layer 312, the third sub-isolation layer 313 and the fourth sub-isolation layer 314 of the isolation column 300. In this case, the film layer should serve as the conductive structure 301 and have conductive ability. It can be set according to actual conditions, and the present application does not limit this.

[0071] Optionally, the materials of the first sub-isolating layer 311, the second sub-isolating layer 312, the third sub-isolating layer 313 and the fourth sub-isolating layer 314 may be Mo (molybdenum), Al (aluminum), Mo (molybdenum), ITO (indium tin oxide) in sequence. In this way, all film layers of the isolation column 300 have conductive capabilities, and the cathode 220 can be in contact with any film layer.

[0072] In the first embodiment of the present application, Figure 3 As shown, the orthographic projection of the fourth sub-isolation layer 314 on the substrate 100 is located within the range of the orthographic projection of the first sub-isolation layer 311 on the substrate 100. In this way, the light-emitting layers 230 of adjacent sub-pixels P can be effectively disconnected.

[0073] In some other embodiments of the present application, the orthographic projection of the fourth sub-isolating layer 314 on the substrate 100 covers the orthographic projection of the first sub-isolating layer 311 on the substrate 100. Such a configuration can achieve a better disconnection effect.

[0074] In the first embodiment of the present application, Figure 3 As shown, the side surfaces of the first sub-isolating layer 311 and the second sub-isolating layer 312 are sloped surfaces; in the first direction, the cross-sections of the first sub-isolating layer 311 and the second sub-isolating layer 312 are both upright trapezoidal structures. The first sub-isolating layer 311 forms a first trapezoidal sharp corner, the second sub-isolating layer 312 forms a second trapezoidal sharp corner, the third sub-isolating layer 313 shrinks after etching, and the fourth sub-isolating layer 314 cooperates with the third sub-isolating layer 313 to form an undercut structure after etching, so as to effectively disconnect the light-emitting layer 230.

[0075] Alternatively, if Figure 3 As shown, the distance a of the third sub-isolating layer 313 inwardly retracted relative to the fourth sub-isolating layer 314 satisfies: a=0.5μm-1μm; the distance b of the third sub-isolating layer 313 inwardly retracted relative to the top surface of the second sub-isolating layer 312 satisfies: b=0.2μm-0.5μm; the range of the slope angle α of the side surface of the second sub-isolating layer 312 satisfies: α>65°

[0076] In the first embodiment of the present application, Figure 4a As shown, the multiple sub-pixels P may include a red sub-pixel P1, a green sub-pixel P2 and a blue sub-pixel P3; each isolation column 300 is arranged around a sub-pixel P; the isolation columns 300 of two adjacent sub-pixels P are connected to each other; thereby, the multiple sub-pixels P can be effectively separated to avoid poor display caused by the connection of the light-emitting layers 230 of the multiple sub-pixels P.

[0077] In some other embodiments of the present application, the plurality of isolation columns 300 may also be independent of each other and spaced apart from each other, which is not limited in the present application.

[0078] Understandably, Figure 4a In the illustrated embodiment, since the isolation columns 300 of two adjacent sub-pixels P are connected to each other, the space between the adjacent sub-pixels P can be saved, which is beneficial to improving the pixel density.

[0079] In the first embodiment of the present application, Figure 2aAs shown, the display panel 10 further includes a driving circuit layer 400; the driving circuit layer 400 is disposed between the substrate 100 and the light-emitting functional layer 200; the driving circuit layer 400 includes a plurality of thin film transistors 410; the plurality of thin film transistors 410 are electrically connected to the anodes 240 of the plurality of sub-pixels P in a one-to-one correspondence. The plurality of thin film transistors 410 may correspond to a plurality of pixel circuits, and the pixel circuits may be configured to provide a driving current to drive the corresponding sub-pixels P to emit light.

[0080] In the first embodiment of the present application, Figure 1 and Figure 4b As shown, Figure 4b for Figure 1 The first display area A1 is a partially enlarged schematic diagram. The first display area A1 may include a plurality of display island areas A11 and a plurality of light-transmitting areas A12 arranged in an array. The light-transmitting area A12 is used to improve the light transmittance of the first display area A1. Specifically, only the substrate 100 may be provided in the light-transmitting area A12 without other film layers. In the second direction, the display island areas A11 and the light-transmitting areas A12 may be alternately provided. In the third direction, the plurality of display island areas A11 may be arranged continuously. The shapes and sizes of the plurality of light-transmitting areas A12 may be substantially the same. The shapes and sizes of the plurality of display island areas A11 may be substantially the same. The second direction may be the width direction of the display panel 10, and correspondingly, the third direction is the length direction of the display panel 10. The second direction may also be the length direction of the display panel 10, and correspondingly, the third direction is the width direction of the display panel 10.

[0081] Furthermore, if Figure 4b As shown, each sub-pixel P may correspond to a pixel circuit 401; each display island area A11 may include four sub-pixels P and four pixel circuits 401, and the four sub-pixels P are arranged in a one-to-one correspondence with the four pixel circuits 401. The four pixel circuits 401 in each display island area A11 may be arranged sequentially along the second direction; the four sub-pixels P may include a red sub-pixel P1, two green sub-pixels P2, and one blue sub-pixel P3.

[0082] like Figure 4c As shown, Figure 4c for Figure 4b FIG. 1 is a positional relationship diagram of the isolation column 300 and the sub-pixel P in the display island area A11. The isolation column 300 is located between adjacent sub-pixels P. The isolation column 300 is only formed in the display island area A11, and no isolation column 300 is provided in the light-transmitting area A12. Figure 4a The embodiments shown and Figure 4c The embodiment shown embodies different pixel arrangements on the pixel island A11. Figure 4a In the illustrated embodiment, the pixel opening 211 is hexagonal, and the isolation column 300 is disposed around each sub-pixel P; Figure 4cIn the illustrated embodiment, the pixel opening 211 is circular, and the isolation column 300 is located between adjacent sub-pixels P, but does not surround each sub-pixel P. The shapes of the pixel opening 211 and the isolation column 300 , as well as the positional relationship therebetween, can be set according to actual needs, and this application does not limit this.

[0083] In the first embodiment of the present application, Figure 2a As shown, the driving circuit layer 400 also includes a first gate insulating layer 420 (GI1), a second gate insulating layer 430 (GI2) and an interlayer insulating layer 440 (ILD) which are sequentially arranged in a direction away from the substrate 100; the thin film transistor 410 includes a first electrode 411, a second electrode 412, a gate 413 and an active layer 414; the active layer 414 is arranged between the substrate 100 and the first gate insulating layer 420, and is covered by the first gate insulating layer 420; the gate 413 is arranged between the first gate insulating layer 420 and the second gate insulating layer 430, and is covered by the second gate insulating layer 430; the first electrode 411 and the second electrode 412 are arranged in the same layer and are located on a side of the interlayer insulating layer 440 away from the substrate 100; a plurality of first sets of holes H1 are formed on the first gate insulating layer 420, the second gate insulating layer 430 and the interlayer insulating layer 440, and the first electrode 411 and the second electrode 412 are respectively connected to the active layer 414 through different first sets of holes H1.

[0084] The plurality of thin film transistors 410 are electrically connected to the anodes 240 of the plurality of sub-pixels P in a one-to-one correspondence, thereby driving the sub-pixels P to emit light in a one-to-one correspondence. Specifically, the first electrode 411 may be a source electrode, the second electrode 412 may be a drain electrode, or the first electrode 411 may be a drain electrode, and the second electrode 412 may be a source electrode; the active layer 414 may include a first electrode contact region 4141, a second electrode contact region 4143, and a semiconductor region 4142, the first electrode contact region 4141 is disposed in contact with the first electrode 411, the second electrode contact region 4143 is disposed in contact with the second electrode 412, and the semiconductor region 4142 is disposed between the first electrode 411 and the second electrode 412.

[0085] In the first embodiment of the present application, Figure 2a As shown, the driving circuit layer 400 also includes a passivation layer 450, a plurality of data lines 460 and a conductive connection layer 470; the passivation layer 450 is arranged on the side of the first pole 411 and the second pole 412 away from the substrate 100, and covers the first pole 411, the second pole 412 and the interlayer insulating layer 440; the plurality of data lines 460 are arranged on the same layer as the gate 413; the conductive connection layer 470 is arranged between the passivation layer 450 and the light-emitting functional layer 200; a plurality of second sets of holes H2 are formed on the second gate insulating layer 430, the interlayer insulating layer 440 and the passivation layer 450, and adjacent data lines 460 are electrically connected to the conductive connection layer 470 respectively through different second sets of holes H2.

[0086] Optionally, the material of the data line 460 can be the same as that of the gate 413, so that the data line 460 and the gate 413 can be formed by one preparation, which is beneficial to improving production efficiency; the material of the conductive connection layer 470 can be ITO, which is a transparent material, which is beneficial to improving the transmittance of the display panel 10.

[0087] In the first embodiment of the present application, Figure 2a As shown, the driving circuit layer 400 also includes a second planar layer 480; the second planar layer 480 is arranged between the first planar layer 250 and the conductive connection layer 470, and covers the passivation layer 450 and the conductive connection layer 470; a plurality of isolation columns 300 are arranged on a side of the second planar layer 480 away from the substrate 100, and are arranged in contact with the second planar layer 480.

[0088] A plurality of third sets of holes H3 are formed on the first planar layer 250 , the second planar layer 480 and the passivation layer 450 , and the anodes 240 of the plurality of sub-pixels P are electrically connected to the second electrode 412 of the thin film transistor 410 through different third sets of holes H3 .

[0089] Alternatively, if Figure 2b As shown, the pixel defining layer 210 and the first planar layer 250 are both disconnected at the isolation column 300 to form a nested opening (eg, Figure 2b The orthographic projection of the isolation column opening W on the substrate 100 covers the orthographic projection of the isolation column 300 on the substrate 100, so that the bottom surface of the isolation column 300 is in contact with the top surface of the second planar layer 480.

[0090] In the first embodiment of the present application, Figure 2a As shown, the display panel 10 further includes a first inorganic layer 500 (CVD) and a buffer layer 600 (Buffer); the first inorganic layer 500 is formed on the side of the cathode 220 away from the substrate 100 and covers the cathode 220; the first inorganic layer 500 extends to the side of the isolation column 300 and is disconnected at the isolation column 300; the buffer layer 600 is disposed between the substrate 100 and the active layer 414. The first inorganic layer 500 can be used as an encapsulation layer to block water and oxygen and protect the display panel 10. Since the first inorganic layer 500 is disconnected at the isolation column 300, when the isolation column 300 is as shown in FIG. Figure 4a When arranged in the manner shown, the first inorganic layer 500 can achieve separate encapsulation of multiple sub-pixels P.

[0091] The display panel 10 of the second embodiment of the present application is different from the display panel 10 of the first embodiment of the present application in that the structure of the isolation column 300 is different. The isolation column 300 in the display panel 10 of the first embodiment of the present application is a four-layer structure, and the isolation column 300 in the display panel 10 of the second embodiment of the present application is a three-layer structure.

[0092] In the second embodiment of the present application, Figure 5 and Figure 6 As shown, Figure 5 is a schematic structural diagram of a display panel 10 according to a second embodiment of the present application, Figure 6 for Figure 5 The schematic diagram of the structure of the isolation column 300 in the illustrated embodiment, the isolation column 300 comprises a fifth sub-isolation layer 315, a sixth sub-isolation layer 316 and a seventh sub-isolation layer 317, which are sequentially arranged in a direction away from the substrate 100; in the first direction, the sixth sub-isolation layer 316 is indented inward relative to the fifth sub-isolation layer 315 and the seventh sub-isolation layer 317, forming an undercut structure; each cathode 220 is formed in the corresponding pixel opening 211, and extends outward from the pixel opening 211 to the side of the isolation column 300, and is arranged in contact with the edge of the fifth sub-isolation layer 315; the fifth sub-isolation layer 315 is a conductive structure 301. The undercut structure can effectively disconnect the light-emitting layer 230, and the fifth sub-isolation layer 315 connects the cathode 220 of the adjacent sub-pixel P, thereby ensuring the normal display of the display panel 10.

[0093] Optionally, the material of the fifth sub-isolation layer 315 and the seventh sub-isolation layer 317 can be ITO; the material of the sixth sub-isolation layer 316 and the material of the first flat layer 250 can be the same, both of which are organic matter; in this way, the sixth sub-isolation layer 316 and the first flat layer 250 can be formed by one preparation; the isolation column 300 can be prepared with a transparent material, thereby improving the transmittance of the display panel 10; ensuring the transmittance of the first display area A1 at a high PPI (pixel density), which is beneficial to the normal operation of the camera set in the first display area A1.

[0094] In the second embodiment of the present application, Figure 6 As shown, the side surfaces of the fifth sub-isolating layer 315 and the sixth sub-isolating layer 316 are sloped surfaces; in the first direction, the cross-sections of the fifth sub-isolating layer 315 and the sixth sub-isolating layer 316 are upright trapezoidal structures.

[0095] In some other embodiments of the present application, the side surface of the fifth sub-isolation layer 315 may also be a vertical surface; in the first direction, the cross-section of the fifth sub-isolation layer 315 is a rectangular structure.

[0096] Alternatively, if Figure 6As shown, the distance c that the top surface of the sixth sub-isolation layer 316 is retracted inward relative to the seventh sub-isolation layer 317 satisfies: c=0.5μm-1μm; the distance d that the bottom surface of the sixth sub-isolation layer 316 is retracted inward relative to the top surface of the fifth sub-isolation layer 315 satisfies: d>1μm; the range of the slope angle β of the side of the sixth sub-isolation layer 316 satisfies: β>65°.

[0097] The display panel 10 of the third embodiment of the present application is different from the display panel 10 of the first embodiment of the present application in that: Figure 7 As shown, Figure 7 This is a structural diagram of the display panel 10 of the third embodiment of the present application. The driving circuit layer 400 in the display panel 10 of the third embodiment of the present application also includes a third electrode 415 connected to the second electrode 412. The third electrode 415 is not provided in the display panel 10 of the first embodiment of the present application.

[0098] In the third embodiment of the present application, Figure 7 As shown, the driving circuit layer 400 further includes a second flat layer 480 (PLN2); the second flat layer 480 is arranged between the light-emitting functional layer 200 and the conductive connection layer 470, and covers the passivation layer 450 (PVX) and the conductive connection layer 470; a plurality of isolation columns 300 are arranged on the side of the second flat layer 480 away from the substrate 100, and are arranged in contact with the second flat layer 480; the light-emitting functional layer 200 further includes a first flat layer 250 (PLN1); the first flat layer 250 is arranged between the anode 240 and the second flat layer 480; the first flat layer 250 is disconnected at the isolation column 300; the thin film transistor 410 further includes a third electrode 415; the third electrode 415 is formed between the second flat layer 480 and the first flat layer 250; the third electrode 415 is respectively connected to the second electrode 412 and the anode 240 arranged corresponding thereto. Optionally, the first flat layer 250 and the second flat layer 480 may be organic insulating layers, and the passivation layer 450 may be an inorganic insulating layer.

[0099] Optionally, the materials of the first sub-isolation layer 311, the second sub-isolation layer 312, the third sub-isolation layer 313 and the fourth sub-isolation layer 314 may be Mo (molybdenum), Al (aluminum), Mo (molybdenum), ITO (indium tin oxide) in sequence. When the third level is divided into three layers, and the materials of the three layers are Mo, Al and Mo in sequence in the direction away from the substrate 100, after depositing the three layers of Mo, Al and Mo in sequence, the first sub-isolation layer 311, the second sub-isolation layer 312, the third sub-isolation layer 313 and the third pole 415 can be formed by one etching, saving process steps without adding additional film layers; at this time, the top surface height of the third pole 415 can be the same as the height of the first sub-isolation layer 311, the second sub-isolation layer 312 and the third sub-isolation layer 313 superimposed; when the material of the anode 240 is also ITO, the fourth sub-isolation layer 314 and the anode 240 can be formed by one etching after depositing the ITO layer, saving process steps without adding additional film layers.

[0100] like Figure 7 As shown, a fourth set of holes H4 are formed on the second planar layer 480 and the passivation layer 450; the third electrode 415 is electrically connected to the second electrode 412 through the fourth set of holes H4; a plurality of via holes H5 are formed on the first planar layer 250, and the anodes 240 of the plurality of sub-pixels P are electrically connected to the third electrode 415 of the thin film transistor 410 through different via holes H5.

[0101] Multiple first electrodes 411 and multiple second electrodes 412 constitute a first source-drain metal layer (SD1), and multiple third electrodes 415 constitute a second source-drain metal layer (SD2). By setting a double-layer source-drain metal layer, more wiring can be arranged compared to setting only one first source-drain metal layer, thereby facilitating the display panel 10 to realize more functions.

[0102] like Figure 8 As shown, Figure 8 This is a structural schematic diagram of a display device according to an embodiment of the present application. The implementation of the second aspect of the present application proposes a display device, including a display panel 10 according to any embodiment of the first aspect, and a sensor 20 located on the non-display surface side of the display panel 10, wherein the orthographic projection of the sensor 20 on the display panel 10 at least partially overlaps with the first display area A1.

[0103] The display device of the embodiment of the present application includes an isolation column 300 of a display vertical panel which is configured to isolate the light-emitting layer 230 of two adjacent sub-pixels P and connect the cathodes 220 of two adjacent sub-pixels P; the cathodes 220 of two adjacent sub-pixels P are connected through the isolation column 300, thereby ensuring normal light emission of the display panel 10; the light-emitting layer 230 of two adjacent sub-pixels P is isolated by the isolation column 300, thereby preventing the occurrence of crosstalk caused by the connection of the light-emitting layers 230 of two adjacent sub-pixels P, thereby improving the display effect.

[0104] It is understandable that if Figure 8 As shown in the viewing angle, the display surface side of the display panel 10 is the upper side, which is the light emitting side of the display panel 10, and the non-display surface side is the lower side. The sensor 20 can be hardware such as a camera. Preferably, as Figure 8 As shown, the orthographic projection of the sensor 20 on the display panel 10 can be located within the first display area A1 of the display panel 10. This arrangement is conducive to the normal operation of the sensor 20. Figure 1 and Figure 8 As shown, the first display area A1 may be circular, and the size of the orthographic projection of the sensor 20 on the display panel 10 may be smaller than the size of the first display area A1. In some other embodiments of the present application, the size of the orthographic projection of the sensor 20 on the display panel 10 may also be equal to the size of the first display area A1, which is not limited in the present application.

[0105] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A display panel, characterized in that: The display panel comprises a display area and a peripheral area surrounding the display area, the display area comprises a first display area and a second display area, and the second display area is located at least on one side of the first display area; the display panel comprises: substrate; a light-emitting functional layer, the light-emitting functional layer being arranged on one side of the substrate, comprising a first flat layer and a pixel defining layer; the pixel defining layer having a plurality of pixel openings, the plurality of pixel openings being configured to accommodate a plurality of sub-pixels, the sub-pixels comprising an anode, a light-emitting layer and a cathode sequentially arranged in a direction away from the substrate; the first flat layer and the pixel defining layer further comprising a plurality of isolation column openings, each of the isolation column openings being located between two adjacent pixel openings; A plurality of isolation columns, each of the plurality of isolation columns is located in the isolation column opening between two adjacent pixel openings, and the isolation column is configured to isolate the light-emitting layers of two adjacent sub-pixels and connect the cathodes of two adjacent sub-pixels.

2. The display panel according to claim 1, characterized in that: The isolation column opening includes: a first opening penetrating the first planar layer and a second opening penetrating the pixel defining layer, and the first opening is connected to the second opening; The isolation column is located in the first opening.

3. The display panel according to claim 1, characterized in that: The isolation column comprises: a first sub-isolation layer, a second sub-isolation layer, a third sub-isolation layer and a fourth sub-isolation layer which are sequentially arranged in a direction away from the substrate; In a first direction, the second sub-isolating layer is retracted inwardly relative to the first sub-isolating layer; the third sub-isolating layer is retracted inwardly relative to the second sub-isolating layer and the fourth sub-isolating layer to form an undercut structure; The second sub-isolating layer is a conductive structure, and cathodes of two adjacent sub-pixels are connected through the second sub-isolating layer.

4. The display panel according to claim 3, characterized in that: The orthographic projection of the fourth sub-isolation layer on the substrate covers the orthographic projection of the first sub-isolation layer on the substrate.

5. The display panel according to claim 3, characterized in that: The side surfaces of the first sub-isolating layer and the second sub-isolating layer are sloped surfaces; In the first direction, cross sections of the first sub-isolating layer and the second sub-isolating layer are both upright trapezoidal structures.

6. The display panel according to claim 1, characterized in that: The isolation column comprises: a fifth sub-isolation layer, a sixth sub-isolation layer and a seventh sub-isolation layer which are sequentially arranged in a direction away from the substrate; In the first direction, the sixth sub-isolating layer is retracted inwardly relative to the fifth sub-isolating layer and the seventh sub-isolating layer to form an undercut structure; The fifth sub-isolating layer is a conductive structure, and cathodes of two adjacent sub-pixels are connected through the fifth sub-isolating layer.

7. The display panel according to claim 6, characterized in that: The side surface of the fifth sub-isolating layer is a slope surface or a vertical surface; The side surface of the sixth sub-isolating layer is a slope surface; In the first direction, the cross section of the fifth sub-isolation layer is an upright trapezoidal structure or a rectangular structure; the cross section of the sixth sub-isolation layer is an upright trapezoidal structure.

8. The display panel according to any one of claims 1 to 7, characterized in that: Each of the isolation columns is arranged around one of the sub-pixels; and the isolation columns of two adjacent sub-pixels are connected to each other.

9. The display panel according to claim 8, characterized in that: The display panel further includes: a driving circuit layer; The driving circuit layer is arranged between the substrate and the light-emitting functional layer; the driving circuit layer comprises a plurality of thin film transistors; the plurality of thin film transistors are electrically connected to the anodes of the plurality of sub-pixels one by one; the driving circuit layer further comprises a first gate insulating layer, a second gate insulating layer and an interlayer insulating layer, which are arranged in sequence in a direction away from the substrate; The thin film transistor comprises: a first electrode, a second electrode, a gate electrode and an active layer; The active layer is disposed between the substrate and the first gate insulating layer; The gate is disposed between the first gate insulating layer and the second gate insulating layer; The first electrode and the second electrode are arranged in the same layer and are located on a side of the interlayer insulating layer away from the substrate; A plurality of first sets of holes are formed on the first gate insulating layer, the second gate insulating layer and the interlayer insulating layer, and the first electrode and the second electrode are respectively connected to the active layer through different first sets of holes.

10. The display panel according to claim 9, characterized in that: The driving circuit layer further includes: a passivation layer, a plurality of data lines and a conductive connection layer; The passivation layer is arranged on a side of the first pole and the second pole away from the substrate; The plurality of data lines are arranged in the same layer as the gate; The conductive connection layer is arranged between the passivation layer and the light-emitting functional layer; A plurality of second sets of holes are formed on the second gate insulating layer, the interlayer insulating layer and the passivation layer, and adjacent data lines are electrically connected to the conductive connection layer respectively through different second sets of holes.

11. The display panel according to claim 10, characterized in that: The driving circuit layer includes: a second planar layer; The second planar layer is disposed between the first planar layer and the conductive connection layer; The plurality of isolation columns are disposed on a side of the second planar layer away from the substrate and are disposed in contact with the second planar layer.

12. The display panel according to claim 9, characterized in that: The display panel further includes: a first inorganic layer and a buffer layer; The first inorganic layer is formed on a side of the cathode away from the substrate and covers the cathode; the first inorganic layer extends to a side of the isolation column and is disconnected at the isolation column; The buffer layer is disposed between the substrate and the active layer.

13. The display panel according to claim 1, characterized in that: The plurality of sub-pixels are respectively located in the first display area and the second display area, and a pixel density of the sub-pixels in the first display area is less than or equal to a pixel density of the sub-pixels in the second display area.

14. The display panel according to claim 1, characterized in that: The light transmittance of the first display area is greater than the light transmittance of the second display area.

15. A display device, characterized in that: The invention comprises the display panel according to any one of claims 1 to 14, and a sensor located on a non-display surface side of the display panel, wherein the orthographic projection of the sensor on the display panel at least partially overlaps with the first display area.