Semiconductor package

Abstract

The embodiment of the utility model relates to a semiconductor packaging piece. The semiconductor packaging piece comprises a first transistor, a first via hole, a second via hole, a third via hole, a first interconnection structure, a second interconnection structure and an external connecting piece. A first via and a second via extend from a front side to a back side of the first substrate. A third via extends from the first transistor to a backside of the first substrate. A first interconnect structure is over the first transistor and a front side of the first substrate. A second interconnect structure is over the backside of the first substrate, and a third via electrically connects the second interconnect structure to the first transistor.

Description

Technical Field

[0001] The embodiment of the utility model relates to a semiconductor package. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the increasing integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, the increase in integration density comes from iterative reductions in minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices continues to grow, there has been a trend towards smaller and more innovative semiconductor die packaging technologies.

[0003] As semiconductor technology has further developed, stacking and bonding semiconductor devices has become an effective alternative to further reduce the physical size of semiconductor devices. In stacked semiconductor devices, active circuits such as logic, memory, processor circuits, etc. are at least partially fabricated on separate substrates and then physically and electrically bonded together to form a functional device. This bonding process utilizes complex technology and needs to be improved. Utility Model Content

[0004] In one embodiment, a semiconductor package includes: a first transistor on a front side of a first substrate; a first via extending from the front side to the back side of the first substrate, the first via having a first width measured at the front side of the first substrate and a second width measured at the back side of the first substrate, the first width being greater than the second width; a second via extending from the front side to the back side of the first substrate, the second via having a third width measured at the front side of the first substrate and a fourth width measured at the back side of the first substrate, the third width being greater than the fourth width, and the third width being greater than the first width of the first via; a third via extending from the first transistor to the back side of the first substrate, the third via having a third width measured at the front side of the first substrate and a fourth width measured at the back side of the first substrate, the third width being greater than the fourth width, and the third width being greater than the first width of the first via; and a third via extending from the first transistor to the back side of the first substrate, the third via having a third width measured at the front side of the first substrate and a fourth width measured at the back side of the first substrate. The via has a fifth width measured at the first transistor and a sixth width measured at the back side of the first substrate, the fifth width being smaller than the sixth width; a first internal wiring structure, above the first transistor and the front side of the first substrate; a first bonding pad, above the first internal wiring structure, the first bonding pad bonding to the second bonding pad of the first tube core; a second internal wiring structure, above the back side of the first substrate, the third via electrically connecting the second internal wiring structure to the first transistor; a third bonding pad, above the second internal wiring structure, the third bonding pad bonding to the fourth bonding pad of the second tube core; and an external connector, along the back side of the second tube core, the back side of the second tube core relative to the fourth bonding pad.

[0005] In one embodiment, a semiconductor package includes: a first active device on a front side of a first substrate; a first via extending from the front side to the back side of the first substrate, wherein a width of the first via measured at the front side of the first substrate is greater than a width of the first via measured at the back side of the first substrate; an interlayer dielectric located on the front side of the first substrate and surrounding the first active device; a second via extending through the interlayer dielectric and the first substrate and extending from the front side to the back side of the first substrate, wherein a width of the second via measured at the front side of the first substrate is greater than a width of the second via measured at the back side of the first substrate; and a third via extending from the front side of the first substrate to the back side of the first substrate. A through hole extending from the first active device to the back side of the first substrate, the third through hole having a width measured at the first active device less than the width of the third through hole measured at the back side of the first substrate; a first interconnect structure on the first active device and the front side of the first substrate; a first bonding pad on the first interconnect structure, the first bonding pad bonding to the second bonding pad of the first die; a second interconnect structure on the back side of the first substrate, the third through hole electrically connecting the second interconnect structure to the first active device; and a third bonding pad on the second interconnect structure, the third bonding pad bonding to the fourth bonding pad of the second die. In other embodiments, the semiconductor package further includes: a buried contact embedded in the front side of the first substrate, and the interlayer dielectric covers the buried contact; and a fourth through hole extending from the buried contact to the back side of the first substrate, the fourth through hole having a width measured at the buried contact less than the width of the fourth through hole measured at the back side of the first substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1A to 1C Cross-sectional views are shown of intermediate steps during a process of forming an integrated circuit die in accordance with some embodiments.

[0008] Figures 2A to 2E Cross-sectional views are shown of intermediate steps during a process of forming an integrated circuit die in accordance with some embodiments.

[0009] Figures 3A to 3B Cross-sectional views are shown of intermediate steps during a process of forming an integrated circuit die in accordance with some embodiments.

[0010] Figures 4 to 8 Cross-sectional views are shown of intermediate steps during a process of forming a semiconductor package in accordance with some embodiments.

[0011] Figures 9 to 12 Layouts of various semiconductor packages are shown in accordance with some embodiments. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for implementing the different features of the provided themes. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature may not be in direct contact with the second feature. In addition, the present disclosure may repeat figure numerals and / or letters in various examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0014] Various embodiments provide an improved method for forming a multilayer semiconductor package with enhanced electrical connections between component integrated circuit dies. According to some embodiments, integrated circuit dies are formed at the wafer level and assembled into semiconductor packages having three or more layers. For example, a first integrated circuit can be formed in a wafer, a second integrated circuit formed in a die (e.g., a middle die) can be bonded to the wafer, and a third integrated circuit formed in another die (e.g., a top die) can be bonded to the middle die. In particular, the middle die may be formed with front and back inner wiring structures and various vias to facilitate high-density electrical connections therebetween. Since there are high-density electrical connections in the middle die, the middle die can also have high-density electrical connections with the wafer and the top die. According to different embodiments, the semiconductor package can have greater layout diversity, wherein each semiconductor package can be assembled with higher efficiency and increased yield (e.g., thereby reducing costs). In addition, the component integrated circuit dies can achieve high performance with a smaller footprint and improved performance by having a higher density of direct electrical connections between each other.

[0015] Various embodiments are described below in specific contexts. Specifically, a multi-layer, chips on wafer on substrate-type, system on integrated chip (SOIC) package is described. However, various embodiments may also be applied to other types of packaging technologies, such as chips on wafer on substrate (CoWoS) packages, die-die-substrate stacking packages, integrated fan-out (InFO) packages, and / or other types of semiconductor packages.

[0016] Figures 1A to 1C A cross-sectional view is shown of the formation of an exemplary wafer (eg, bottom wafer 100 ) that is subsequently included in a lower level of a multi-layer semiconductor package according to various embodiments. Figures 2A to 2E A cross-sectional view is shown of the formation of an exemplary integrated circuit die (eg, middle die 200 ) that is subsequently included in one or more middle levels of a multi-layer semiconductor package according to various embodiments. Figures 3A to 3B A cross-sectional view is shown of the formation of an exemplary integrated circuit die (eg, upper die 300 ) that is subsequently included in an upper level of a multi-layer semiconductor package according to various embodiments. Figures 4 to 8 A cross-sectional view showing the formation of an embodiment layout of a multi-layer semiconductor package including a bottom wafer 100 , one or more middle dies 200 , and one or more upper dies 300 according to various embodiments is shown. Figures 9 to 12 Various additional example layouts of multi-layer semiconductor packages are shown, which may be formed using the same or similar process steps. As discussed further below, the semiconductor package may be arranged in a variety of layouts not specifically described and are fully intended to be within the scope of the present disclosure.

[0017] Figures 1A to 1CA cross-sectional view of forming a bottom wafer 100 according to some embodiments is shown. The bottom wafer 100 may include a plurality of integrated circuit dies, which may be packaged and singulated in subsequent processing to form various embodiments of semiconductor packages (also referred to as packaged semiconductor devices). The integrated circuit die may be a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system on a chip (SoC), an application processor (AP), a microcontroller, or the like); a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, or the like); a power management die (e.g., a power management integrated circuit (PMIC) die); a radio frequency (RF) die; a sensor die; a microelectromechanical system (MEMS) die; a signal processing die (e.g., a digital signal processing (DSP) die); a front-end die (e.g., an analog front-end (AFE) die); or a combination thereof.

[0018] exist Figure 1A In the present invention, various devices 104 can be formed along the front side of the substrate 102. For example, the substrate 102 can include a semiconductor substrate, such as doped or undoped silicon, or an active layer of a semiconductor on insulator (SOI) substrate. The semiconductor substrate can include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, can be used. The substrate 102 has an active surface, which can be referred to as a front side (e.g., at Figure 1A The surface facing upward, on which the device 104 is formed, and the inactive surface, which may be referred to as the back surface (e.g., Figure 1A surface facing downwards).

[0019] Device 104 (represented by a transistor) may be formed at the front side of substrate 102. Device 104 may be an active device (e.g., a transistor, a diode, or the like), a capacitor, a resistor, etc. Interlayer dielectric 110 is on the front side of substrate 102. Interlayer dielectric 110 surrounds and may cover device 104. Interlayer dielectric 110 may include one or more dielectric layers formed of materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.

[0020] Conductive plug 112 may be formed to extend through interlayer dielectric 110. Conductive plug 112 may be electrically and physically coupled to device 104. In embodiments where device 104 is a transistor, conductive plug 112 may be coupled to a gate and / or source / drain region of the transistor (source / drain region may be referred to individually or collectively as source or drain, depending on the context). Conductive plug 112 may be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, etc., or combinations thereof.

[0021] exist Figure 1B In the embodiment of the present invention, an interconnect structure 120 is formed over the substrate 102 and the device 104, and a via 130 can be formed to extend through the interlayer dielectric 110 and into the substrate 102. In some embodiments, the via 130 can be connected to an upper portion of the interconnect structure 120 and extend through a lower portion of the interconnect structure 120. In some embodiments (not specifically shown), the via 130 can be connected to a lower portion of the interconnect structure 120. The via 130 can then be exposed through the back side of the substrate 102 and can be used to provide an electrical connection through the substrate 102 (e.g., between the front side and the back side of the substrate 102) (see, for example, Figures 7 to 8 Therefore, the via 130 may also be referred to as a through substrate via (TSV).

[0022] In some embodiments, the via 130 may be formed through the interlayer dielectric 110 and a portion of the substrate 102. The recess may be formed by etching, milling, laser technology, combinations thereof, and the like. A liner (not specifically shown) may be formed in the recess, for example, by thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and the like. The liner may be a dielectric material and include an oxide, such as silicon oxide, silicon oxynitride, and the like. A barrier layer and / or an adhesion layer (not specifically shown) may then be conformally deposited in the recess (e.g., along the liner), for example, by CVD, ALD, physical vapor deposition (PVD), combinations thereof, and the like. The barrier layer and / or the adhesion layer may be formed of titanium, titanium nitride, tantalum, tantalum nitride, and the like. A conductive fill material is deposited on the barrier layer and / or the adhesion layer and fills the recess. The conductive fill material may be deposited by an electrochemical plating process, CVD, ALD, PVD, combinations thereof, and the like. Examples of the conductive filling material include copper, copper alloys, silver, gold, tungsten, ruthenium, cobalt, aluminum, nickel, combinations thereof, etc. Excess portions of the conductive filling material, adhesion layer, barrier layer, and / or liner, such as portions extending along the top surface of the interlayer dielectric 110 and / or the substrate 102, are removed from the surface of the interlayer dielectric 110 and / or the substrate 102 by a planarization process (e.g., chemical mechanical polishing (CMP), a grinding process, an etch-back process, etc.). The remaining portions of the barrier layer, adhesion layer, and / or conductive filling material form the via 130.

[0023] The interconnect structure 120 is formed on the interlayer dielectric 110 and connected to the conductive plug 112. The interconnect structure 120 interconnects the devices 104 to form an integrated circuit. In some embodiments, the interconnect structure 120 can be formed by a metallization pattern in a dielectric layer on the interlayer dielectric 110. The metallization pattern includes metal lines and vias formed in one or more low-k dielectric layers. The metallization pattern of the interconnect structure 120 is electrically coupled to the device 104 through the conductive plug 112 and is electrically connected to the via 130.

[0024] exist Figure 1C In the embodiment of the present invention, a metal pad 140 (e.g., an aluminum pad), a bonding pad via 144, and a bonding pad 146 are formed on the inner wiring structure 120, and an external connection is formed thereon. The metal pad 140 is on the front side of the substrate 102, for example, in the inner wiring structure 120 and / or on the inner wiring structure 120. As shown in the figure, the metal pad 140 is arranged on the metallization layer of the inner wiring structure 120 and electrically connects the metallization layer of the inner wiring structure 120. The metal pad 140 can be in one or more dielectric layers 141 and include a metal, such as aluminum, copper, etc. For example, the dielectric layer 141 may include silicon oxide and / or silicon nitride, such as silicon oxynitride (SiON), silicon carbide (SiC) or any suitable material. The metal pad 140 can be considered as a part of the inner wiring structure 120.

[0025] According to some embodiments, a bonding pad via 144 and a bonding pad 146 are formed on the metal pad 140 and the interconnect structure 120. The bonding pad via 144 and the bonding pad 146 can be formed using a single damascene process or a dual damascene process. For example, a dielectric bonding layer 142 can be formed on the metal pad 140, and the dielectric bonding layer 142 and the dielectric layer 141 can be etched to form a recess. The recess can then be filled to form the bonding pad via 144 and the bonding pad 146, similar to the above-described via 130.

[0026] For example, a dielectric bonding layer 142 may be formed over the interconnect structure 120 and the metal pad 140. The dielectric bonding layer 142 may be one or more dielectric layers including an oxide such as silicon oxide, a nitride such as silicon nitride, or a combination thereof, and may be formed using CVD, ALD, or the like, or a suitable method. According to some embodiments, the dielectric bonding layer 142 comprises a silicon oxide layer. The dielectric bonding layer 142 and / or the plurality of underlying dielectric layers 141 are etched to form a recess exposing the metal pad 140. In an embodiment using a dual damascene process, the recess may be formed using multiple etching processes, and similar to the above-described via 130, the bonding pad via 144 and the bonding pad 146 may be formed simultaneously. For example, a conductive liner and a conductive material may be deposited in the recess and over the dielectric bonding layer 142, and a planarization process may be performed to remove excess portions of the conductive material and the conductive liner from the top surface of the dielectric bonding layer 142. In some embodiments (not specifically shown), bond pad vias 144 may be formed through dielectric layer 141 , and bond pads 146 may subsequently be formed through dielectric bonding layer 142 .

[0027] In some embodiments (not specifically shown), the bonding pad 146 can be formed after the bonding pad through hole 144, and the bonding pad 146 can be a microbump, a ball grid array (BGA) connection terminal, a solder ball, a metal column, a controlled collapse chip connection (controlled collapse chip connection, C4) bump, a bump formed by chemical nickel plating-chemical palladium immersion gold technology (ENEPIG), etc. The bonding pad 146 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc. or a combination thereof. In some embodiments, the bonding pad 146 is formed by a layer of solder, which is first formed by evaporation, electroplating, printing, solder transfer, ball planting, etc. Once the layer of solder is formed on the structure, reflow can be performed to shape the material into the desired bump shape. In addition, the dielectric bonding layer 142 may be a polymer such as PBO, polyimide, BCB or the like; a nitride such as silicon nitride or the like; an oxide such as silicon oxide, PSG, BSG, BPSG or the like; the like or a combination thereof. The dielectric bonding layer 142 may be formed by spin coating, lamination, CVD, or the like. Initially, the dielectric bonding layer 142 may bury the bonding pad 146 so that the topmost surface of the dielectric bonding layer 142 is above the topmost surface of the bonding pad 146. In some embodiments, a solder region may be formed on the bonding pad 146, and the dielectric bonding layer 142 may bury the solder region. In some embodiments, the bonding pad 146 is exposed or protrudes above the dielectric bonding layer 142 through the dielectric bonding layer 142 during the formation of the bottom wafer 100. In some embodiments, the bonding pad 146 remains buried and is exposed in a subsequent process to encapsulate the bottom wafer 100. Exposing bond pads 146 may include removing any solder regions that may be present on bond pads 146 .

[0028] Figures 2A to 2E is a cross-sectional view of forming the middle die 200 according to some embodiments. The middle die 200 includes an integrated circuit die formed in a wafer, and the wafer may include different device areas, which are divided in subsequent steps to form multiple separate integrated circuit dies. The wafer including the middle die 200 can be processed according to an applicable production process to form separate middle dies 200. Unless otherwise specified, the formation of the middle die 200 can be similar to similar features of the bottom wafer 100 described above. The middle die 200 can be a logic die (e.g., a CPU, a GPU, a SoC, an AP, a microcontroller, or the like); a memory die (e.g., a DRAM die, an SRAM die, or the like); a power management die (e.g., a PMIC die); an RF die; a sensor die; a micro-electromechanical system die; a signal processing die (e.g., a DSP die); a front-end die (e.g., an AFE die); or a combination thereof.

[0029] As discussed in more detail below, the middle die 200 can include one or more of four general types of vias (e.g., through-holes such as TSVs) extending from the front side to the back side of the substrate 202 of the middle die 200. As discussed in more detail below, the first via 231 can be formed using a via-first process, in which the conductive material of the first via 231 is formed in the front side of the substrate 202 of the middle die 200 before forming the device 204 and the overlying interconnect structure 220. In addition, the second via 232 can be formed using a via-middle process, in which the conductive material of the second via 232 is also formed in the front side of the substrate 202 of the middle die 200 after forming the device 204 and before or during forming the overlying interconnect structure 220. Furthermore, the third via 233 and the fourth via 234 may be formed using a via-last process, wherein the conductive material of the third via 233 and the fourth via 234 is formed in the back side of the substrate 202 of the middle die 200 .

[0030] exist Figure 2A In the embodiment, the device 204 is formed in the front side of the substrate 202, and the first through hole 231 and the second through hole 232 can be formed in the front side of the substrate 202. In addition, the buried contact 230, which is subsequently formed as the third through hole 233, can be connected to the front side of the substrate 202 and can also be formed in the front side of the substrate 202. For example, the substrate 202 may include a semiconductor substrate, such as doped or undoped silicon, or an active layer of a semiconductor on insulator (SOI) substrate. The semiconductor substrate may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof. Other substrates may be used, such as multilayer or gradient substrates. The substrate 202 has an active surface, which may be referred to as a front side (e.g., at Figure 2A The surface facing upward, on which the device 204 is formed, and the inactive surface, which may be referred to as the back surface (e.g., Figure 2A A device 204 (represented by a transistor) may be formed at the front side of the substrate 202. The device 204 may be an active device (eg, a transistor, a diode, or the like), a capacitor, a resistor, or the like.

[0031] The first via 231 is a first type of via and is formed to extend into the substrate 202. The first via 231 may then be exposed through the back side of the substrate 202 and may be used to provide an electrical connection through the substrate 202 (e.g., between the front side and the back side of the substrate 202) (see Figures 2C to 2E). Therefore, the first through-hole 231 may also be referred to as a TSV. In some embodiments, the first through-hole 231 is formed before forming the device 204.

[0032] The second via 232 is a second type of via and is formed to extend through the interlayer dielectric 210 and into the substrate 202, similar to the via 130 described above. In some embodiments, the second via 232 may be connected to a lower portion of the subsequently formed interconnect structure 220 (see Figure 2B ). In some embodiments (not specifically shown), the second via 232 can be connected to the upper portion of the interconnect structure 220, similar to the via 130 of the bottom wafer 100 described above. The second via 232 can then be exposed through the back side of the substrate 202 and can be used to provide an electrical connection through the substrate 202 (e.g., between the front side and the back side of the substrate 202) (see Figures 2C to 2E ). Therefore, the second through hole 232 may also be referred to as a TSV.

[0033] Unless otherwise stated, the first through hole 231 and the second through hole 232 can be formed similarly to each other and to the via 130. As described above, it should be noted that the first through hole 231 is formed before the interlayer dielectric 210 is deposited, while the second through hole 232 is formed after the interlayer dielectric 210 is deposited. For example, the first through hole 231 is formed by forming a recess in the substrate 202, and the second through hole 232 is formed by forming a recess in the interlayer dielectric 210 and the substrate 202. The respective recesses can be formed by etching, milling, laser technology, a combination thereof, etc. A liner (not specifically shown) can be formed in the recess, for example, by thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), etc. The liner can be a dielectric material and include an oxide, such as silicon oxide, silicon oxynitride, etc. A barrier layer and / or adhesion layer (not specifically shown) may then be conformally deposited in the recess (e.g., along the liner), such as by CVD, ALD, physical vapor deposition (PVD), combinations thereof, and the like. The barrier layer and / or adhesion layer may be formed of titanium, titanium nitride, tantalum, tantalum nitride, and the like. A conductive fill material is deposited on the barrier layer and / or adhesion layer and fills the recess. The conductive fill material may be deposited by an electrochemical plating process, CVD, ALD, PVD, combinations thereof, and the like. Examples of conductive fill materials include copper, copper alloys, silver, gold, tungsten, ruthenium, cobalt, aluminum, nickel, combinations thereof, and the like. Excessive portions of the conductive filling material, adhesive layer, barrier layer and / or liner, such as portions extending along the top surface of the substrate 202 (e.g., during the formation of the first through hole 231) and / or the interlayer dielectric 210 (e.g., during the formation of the second through hole 232), are removed by a planarization process (e.g., chemical mechanical polishing (CMP), grinding process, etch-back process, etc.). The remaining portions of the corresponding barrier layer, the corresponding adhesive layer and / or the corresponding conductive filling material form the first through hole 231 and the second through hole 232.

[0034] The middle die 200 may include one or both of the first through-hole 231 and the second through-hole 232. In some embodiments (not specifically shown), instead of forming the first through-hole 231 and the second through-hole 232, the third through-hole 233 and / or the fourth through-hole 234 may be formed. Any combination of some or all of the four types of through-holes may be formed in the middle die 200.

[0035] As described above, the third through hole 233 is a type of via that can be subsequently formed through the back side of the substrate 202 and connected to a feature called a buried contact 230. In such an embodiment, the buried contact 230 can be formed along the substrate 202 before depositing the interlayer dielectric 210. In addition, the buried contact 230 can be formed before forming the device 204 or during forming the device 204. For example, a recess can be etched into the substrate 202 and filled with a conductive material. In some embodiments, the conductive material includes one or more layers, such as a barrier layer and a conductive fill material. The barrier layer can be titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride, ruthenium, rhodium, platinum, other precious metals, other refractory metals, their nitrides, combinations thereof, etc. In addition, the conductive fill material can be tungsten, cobalt, ruthenium, rhodium, alloys thereof, or combinations thereof.

[0036] Continue to refer Figure 2A , an interlayer dielectric 210 is formed on the front side of the substrate 202. The interlayer dielectric 210 surrounds and may cover the device 204 as well as the buried contact 230 and the first via 231 (if present). The interlayer dielectric 210 may include one or more dielectric layers formed of materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.

[0037] The conductive plug 212 may be formed to extend through the interlayer dielectric 210. The conductive plug 212 may be electrically and physically coupled to the device 204 and the first via 231 and the buried contact 230 (if present). In an embodiment where the device 204 is a transistor, the conductive plug 212 may be coupled to the gate and / or source / drain region of the transistor. The conductive plug 212 may be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, etc., or a combination thereof.

[0038] exist Figure 2B In the embodiment, the interconnect structure 220 is formed over the substrate 202, the interlayer dielectric 210 and the device 204. In some embodiments (not specifically shown), the second via 232 can be formed during the formation of the interconnect structure 220 and connected to the lower portion or the upper portion of the interconnect structure 220.

[0039] The interconnect structure 220 can be formed similar to the interconnect structure 120 described above. For example, the interconnect structure 220 is formed on the interlayer dielectric 210 and connected to the conductive plug 212 and the second via (if present). The interconnect structure 220 interconnects the devices 204 to form an integrated circuit. In some embodiments, the interconnect structure 220 can be formed by a metallization pattern in a dielectric layer on the interlayer dielectric 210. The metallization pattern includes metal lines and vias formed in one or more low-k dielectric layers. The metallization pattern of the interconnect structure 220 is electrically coupled to the device 204, electrically coupled to the buried contact 230, and electrically coupled to the first via 231 through the conductive plug 212, and electrically connected to the second via 232.

[0040] exist Figure 2C In some embodiments, the third via 233 and / or the fourth via 234 may be formed through the back side of the substrate 202. As described above, the third via 233 is connected to the buried contact 230, while the fourth via 234 is connected to the device 204 (e.g., the gate and / or source / drain region of the transistor).

[0041] Before forming the third through hole 233 and the fourth through hole 234, the carrier substrate 250 is bonded to the interconnect structure 220, and a thinning process is performed on the back side of the substrate 202. In some embodiments, the carrier substrate 250 can be bonded with, for example, an adhesive layer 252 or other type of dielectric layer, which facilitates the bonding of the carrier substrate 250 to the interconnect structure 220. As shown, the topmost dielectric layer (not separately labeled) of the interconnect structure 220 can be disposed above the topmost metallization layer of the interconnect structure 220, which improves the adhesion of the carrier substrate 250 through dielectric to dielectric bonding between the adhesive layer 252 and the dielectric layer.

[0042] After attaching the carrier substrate 250, a thinning process is performed on the back side of the substrate 202, which may expose the first through hole 231 and the second through hole 232. The substrate 202 may be thinned using CMP, a grinding process, an etch-back process, a lapping process, or a polishing process.

[0043] After thinning the back side of the substrate 202, a third through hole 233 and a fourth through hole 234 can be formed through the back side of the substrate 202 and are similar to the first through hole 231 and / or the second through hole 232 described above. Unless otherwise specified, the third through hole 233 and the fourth through hole 234 can be formed similarly and simultaneously. As described above, it should be noted that the third through hole 233 is formed to connect to the buried contact and the fourth through hole 234 is formed to connect to the device 204 (e.g., the gate and / or the source / drain region).

[0044] For example, the third through hole 233 and the fourth through hole 234 are formed by forming a recess in the thinned back side of the substrate 202. The corresponding recess can be formed by etching, milling, laser technology, a combination thereof, etc. A liner (not specifically shown) can be formed in the recess, for example, by thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), etc. The liner can be a dielectric material and include an oxide, such as silicon oxide, silicon oxynitride, etc. Then a barrier layer and / or an adhesion layer (not specifically shown) can be conformally deposited in the recess (e.g., along the liner), for example, by CVD, ALD, physical vapor deposition (PVD), a combination thereof, etc. The barrier layer and / or the adhesion layer can be formed of titanium, titanium nitride, tantalum, tantalum nitride, etc. A conductive filling material is deposited on the barrier layer and / or the adhesion layer and fills the recess. The conductive filling material can be deposited by an electrochemical plating process, CVD, ALD, PVD, a combination thereof, etc. Examples of the conductive filling material include copper, copper alloys, silver, gold, tungsten, ruthenium, cobalt, aluminum, nickel, combinations thereof, and the like. Excess portions of the conductive filling material, the adhesion layer, the barrier layer, and / or the liner, such as portions extending along the top surface of the substrate 202 (e.g., during the formation of the first via 231) and / or the interlayer dielectric 210 (e.g., during the formation of the second via 232), are removed by a planarization process (e.g., chemical mechanical polishing (CMP), a grinding process, an etch-back process, and the like). In embodiments where the first via 231 and the second via 232 are still covered by the back side of the substrate 202, these planarization processes may expose the first via 231 and the second via 232 after the above-mentioned thinning process. The remaining portions of the respective barrier layer, the respective adhesion layer, and / or the respective conductive filling material form the third via 233 and the fourth via 234.

[0045] Figure 2D Shown in Figure 2C 201. The vias are shown as conductive fill material and liner layers, which may be corresponding barrier layers and / or adhesive layers as discussed above when forming them. For example, first via 231 is shown as liner layer 231A and conductive fill material 231B. Second via 232 is shown as liner layer 232A and conductive fill material 232B. Third via 233 is shown as liner layer 233A and conductive fill material 233B. Fourth via 234 is shown as liner layer 234A and conductive fill material 234B.

[0046] In some embodiments, the first via 231 may have an uppermost width (e.g., at the front side surface of the substrate 202) that is equal to or less than an uppermost width (e.g., at the top surface of the interlayer dielectric 210) of the second via 232. Similarly, the first via 231 may have a lowermost width that is equal to or less than a lowermost width of the second via 232. In addition, the uppermost and lowermost widths of the second via 232 may be equal to or less than similar widths of the via 130 of the bottom wafer 100. In addition, the third via 233 and the fourth via 234 may have an uppermost width (e.g., at the buried contact 230 and the corresponding device 204, respectively) that is less than the lowermost width of the first via 231 and the second via 232. In addition, the third via 233 and the fourth via 234 may have a lower width (e.g., at the back side surface of the substrate 202) that is less than the uppermost width of the first via 231 and the second via 232.

[0047] exist Figure 2E In the embodiment of the present invention, an interconnect structure 270 is formed on the back side of the middle die 200, and a metal pad 280 (e.g., an aluminum pad), a bonding pad via 284, and a bonding pad 286 are formed on the interconnect structure 270 to make external connections. The interconnect structure 270, the metal pad 280, and other backside features can be collectively referred to as a back-side power delivery network (BSPDN). The BSPDN allows power and signals for the integrated circuit of the middle die 200 to be routed to one or both of the front side and the back side of the middle die 200, thereby achieving several advantages. For example, the footprint of the middle die 200 (or a subsequently formed semiconductor package including the middle die 200) may be reduced by up to 28% to 30%, the surface density of the bonding pads 286 and the interconnect structures may be increased by up to 1500%, the signal path to the directly connected die may be reduced by 10.8%, the total voltage drop may be reduced by up to 60% on average with decreasing distance (e.g., from an external power source to the device 204), and the maximum voltage drop may be reduced by up to 20%. As a result, the performance of the middle die 200 may be improved by up to 15%. The formation of the interconnect structure 270 may be similar to the interconnect structures 120, 220 described above. The formation of the metal pad 280, the bonding pad via 284, and the bonding pad 286 may be similar to the metal pad 140, the bonding pad via 144, and the bonding pad 146 described above, respectively.

[0048] The interconnect structure 270 is formed on the back side of the substrate 202 and is connected to the vias or TSVs (e.g., the first via 231, the second via 232, the third via 233, and / or the fourth via 234). The interconnect structure 270 interconnects the devices 204 to become part of the integrated circuit. In some embodiments, the interconnect structure 270 can be formed by a metallization pattern embedded in a dielectric layer. The metallization pattern includes metal lines and vias formed in one or more low-k dielectric layers. The metallization pattern of the interconnect structure 270 is electrically coupled to the device 204 through the vias or TSVs and is electrically connected to the interconnect structure 220.

[0049] According to some embodiments, metal pads 280 (e.g., aluminum pads), bonding pad vias 284, and bonding pads 286 are formed on the inner connection structure 270 on the back side of the middle tube core 200 to make external connections. As shown, the metal pads 280 are arranged on the metallization layer of the inner connection structure 270 and are electrically connected to the metallization layer of the inner connection structure 270. The metal pads 280 can be in one or more dielectric layers 281 and include metals, such as aluminum, copper, etc. For example, the dielectric layer 281 can include silicon oxide and / or silicon nitride, such as silicon oxynitride (SiON), silicon carbide (SiC), or any suitable material. The metal pads 280 can be considered as part of the inner connection structure 270. In some embodiments (not specifically shown), solder areas (e.g., solder balls or solder bumps) can be provided on the metal pads 280. The solder areas can be used to perform chip probe testing on the integrated circuits of the middle tube core 200. A chip probe test can be performed on the middle die 200 to determine whether the middle die 200 is a known good die (KGD). Therefore, only the middle die 200 that is a KGD undergoes subsequent processing and is packaged. Dies that fail the chip probe test are not packaged. After testing, the solder area can be removed in a subsequent processing step.

[0050] According to some embodiments, bonding pad vias 284 and bonding pads 286 are formed over metal pads 280 and interconnect structures 270. Bonding pad vias 284 and bonding pads 286 may be formed using a single damascene process or a dual damascene process, similar to the bonding pad vias 144 and bonding pads 146 of the bottom wafer described above. For example, a dielectric bonding layer 282 may be formed over metal pads 280, and dielectric bonding layer 282 and dielectric layer 281 may be etched to form recesses. The recesses may then be filled to form bonding pad vias 284 and bonding pads 286.

[0051] For example, a dielectric bonding layer 282 may be formed over the interconnect structure 270 and the metal pad 280. The dielectric bonding layer 282 may be one or more dielectric layers including an oxide such as silicon oxide, a nitride such as silicon nitride, or a combination thereof, and may be formed using CVD, ALD, or the like, or a suitable method. According to some embodiments, the dielectric bonding layer 282 includes a silicon oxide layer. The dielectric bonding layer 282 and the underlying dielectric layer 281 are etched to form a recess exposing the metal pad 280. In an embodiment using a dual damascene process, the recess may be formed using multiple etching processes, and the bonding pad via 284 and the bonding pad 286 may be formed simultaneously. For example, after the recess is formed, a conductive liner and a conductive material may be deposited in the recess and over the dielectric bonding layer 282, and a planarization process may be performed to remove excess portions of the conductive material and the conductive liner from the top surface of the dielectric bonding layer 282. In some embodiments (not specifically shown), bond pad vias 284 may be formed through dielectric layer 281 , and bond pads 286 may subsequently be formed through dielectric bonding layer 282 .

[0052] In some embodiments (not specifically shown), the bonding pad 286 can be formed after the bonding pad through hole 284, and the bonding pad 286 can be a microbump, a ball grid array (BGA) connection terminal, a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a bump formed by electroless nickel plating-electroless palladium immersion gold technology (ENEPIG), etc. The bonding pad 286 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc. or a combination thereof. In some embodiments, the bonding pad 286 is formed by a layer of solder, which is first formed by evaporation, electroplating, printing, solder transfer, ball planting, etc. Once the layer of solder is formed on the structure, reflow can be performed to shape the material into a desired bump shape. In addition, the dielectric bonding layer 282 can be a polymer such as PBO, polyimide, BCB or the like; a nitride such as silicon nitride or the like; an oxide such as silicon oxide, PSG, BSG, BPSG or the like; the like or a combination thereof. Dielectric bonding layer 282 may be formed by spin coating, lamination, CVD, etc. Initially, dielectric bonding layer 282 may bury bonding pad 286 so that the topmost surface of dielectric bonding layer 282 is above the topmost surface of bonding pad 286. In some embodiments, solder regions may be formed on bonding pad 286 and dielectric bonding layer 282 may bury the solder regions. In some embodiments, bonding pad 286 is exposed through dielectric bonding layer 282 or protrudes above dielectric bonding layer 282 during the formation of middle die 200. In some embodiments, bonding pad 286 remains buried and is exposed in a subsequent process to package middle die 200. Exposing bonding pad 286 may include removing any solder regions that may be present on bonding pad 286.

[0053] Figures 3A to 3B A cross-sectional view of forming an upper die 300 according to some embodiments is shown. The upper die 300 includes an integrated circuit die formed in a wafer, and the wafer may include different device areas that are divided in subsequent steps to form a plurality of separate integrated circuit dies. The wafer including the upper die 300 may be processed according to an applicable production process to form separate upper dies 300. Unless otherwise specified, the upper die 300 may be formed to be similar to the similar features of the bottom wafer 100 or the middle die 200 described above. The upper die 300 may be a logic die (e.g., a CPU, a GPU, a SoC, an AP, a microcontroller, or the like); a memory die (e.g., a DRAM die, an SRAM die, or the like); a power management die (e.g., a PMIC die); an RF die; a sensor die; a micro-electromechanical system die; a signal processing die (e.g., a DSP die); a front-end die (e.g., an AFE die); or a combination thereof.

[0054] exist Figure 3A , device 304 is formed in the front side of substrate 302. For example, substrate 302 may include a semiconductor substrate, such as doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates may be used, such as multilayer or gradient substrates. Substrate 302 has an active surface, which may be referred to as a front side (e.g., at Figure 3A The surface facing upward, on which the device 304 is formed, and the inactive surface, which may be referred to as the back surface (e.g., Figure 3A 3. The front side of the substrate 302 is shown in FIG. 3. A device 304 (represented by a transistor) may be formed at the front side of the substrate 302. The device 304 may be an active device (e.g., a transistor, a diode, or the like), a capacitor, a resistor, etc. An interlayer dielectric 310 is also formed on the front side of the substrate 302.

[0055] According to some embodiments, interlayer dielectric 310 is on the front side of substrate 302. Interlayer dielectric 310 surrounds and may cover device 304. Interlayer dielectric 310 may include one or more dielectric layers formed of materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), and the like.

[0056] Conductive plug 312 may be formed to extend through interlayer dielectric 310. Conductive plug 312 may be electrically and physically coupled to device 304. In embodiments where device 304 is a transistor, conductive plug 312 may be coupled to a gate and / or source / drain region of the transistor. Conductive plug 312 may be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, etc., or combinations thereof.

[0057] exist Figure 3B In the embodiment, an interconnect structure 320 is formed above the interlayer dielectric 310 of the upper die 300, and a metal pad 340 (e.g., an aluminum pad), a bonding pad via 344, and a bonding pad 346 are formed above the interconnect structure 320, on which external connections are made. The formation of the interconnect structure 320 can be similar to the above-mentioned interconnect structures 120, 220, 270. The formation of the metal pad 340, the bonding pad via 344, and the bonding pad 346 can be similar to the above-mentioned metal pads 140, 280, the bonding pad via 144, 284, and the bonding pad 146, 286, respectively.

[0058] The interconnect structure 320 is formed on the front side of the substrate 302 and connected to the conductive plug 312. The interconnect structure 320 interconnects the devices 304 to become part of the integrated circuit. In some embodiments, the interconnect structure 320 can be formed by a metallization pattern embedded in a dielectric layer. The metallization pattern includes metal lines and vias formed in one or more low-k dielectric layers. The metallization pattern of the interconnect structure 320 is electrically coupled to the device 304 through the conductive plug 312.

[0059] According to some embodiments, a metal pad 340 (e.g., an aluminum pad), a bonding pad via 344, and a bonding pad 346 are formed on the interconnect structure 320, on which external connections are made. As shown, the metal pad 340 is arranged on the metallization layer of the interconnect structure 320 and electrically connects the metallization layer of the interconnect structure 320. The metal pad 340 can be in one or more dielectric layers 341 and include a metal, such as aluminum, copper, etc. For example, the dielectric layer 341 may include silicon oxide and / or silicon nitride, such as silicon oxynitride (SiON), silicon carbide (SiC), or any suitable material. The metal pad 340 can be considered as a part of the interconnect structure 320. In some embodiments (not specifically shown), a solder area (e.g., a solder ball or solder bump) can be provided on the metal pad 340. The solder area can be used to perform chip probe testing on the integrated circuit of the upper tube core 300. A chip probe test can be performed on the upper die 300 to determine whether the upper die 300 is a known good die (KGD). Therefore, only the upper die 300 that is a KGD undergoes subsequent processing and is packaged. Dies that fail the chip probe test are not packaged. After testing, the solder area can be removed in a subsequent processing step.

[0060] According to some embodiments, bonding pad vias 344 and bonding pads 346 are formed over metal pads 340 and interconnect structures 320. Bonding pad vias 344 and bonding pads 346 may be formed using a single damascene process or a dual damascene process, similar to the above-described bonding pad vias 144, 284 and bonding pads 146, 286 of bottom wafer 100 and middle die 200, respectively. For example, dielectric bonding layer 342 may be formed over metal pads 340, and dielectric bonding layer 342 and dielectric layer 341 may be etched to form recesses. The recesses may then be filled to form bonding pad vias 344 and bonding pads 346.

[0061] For example, a dielectric bonding layer 342 may be formed over the interconnect structure 320 and the metal pad 340. The dielectric bonding layer 342 may be one or more dielectric layers including an oxide such as silicon oxide, a nitride such as silicon nitride, or a combination thereof, and may be formed using CVD, ALD, etc. or a suitable method. According to some embodiments, the dielectric bonding layer 342 includes a silicon oxide layer. The dielectric bonding layer 342 and one or more underlying dielectric layers 341 are etched to form a recess exposing the metal pad 340. In an embodiment using a dual damascene process, the recess may be formed using multiple etching processes, and the bonding pad via 344 and the bonding pad 346 may be formed simultaneously. For example, after the recess is formed, a conductive liner and a conductive material may be deposited in the recess and over the dielectric bonding layer 342, and a planarization process may be performed to remove excess portions of the conductive material and the conductive liner from the top surface of the dielectric bonding layer 342. In some embodiments (not specifically shown), bond pad vias 344 may be formed through dielectric layer 341 , and bond pads 346 may subsequently be formed through dielectric bonding layer 342 .

[0062] In some embodiments (not specifically shown), the bonding pad 346 can be formed after the bonding pad through hole 344, and the bonding pad 346 can be a microbump, a ball grid array (BGA) connection terminal, a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a bump formed by electroless nickel plating-electroless palladium immersion gold technology (ENEPIG), etc. The bonding pad 346 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc. or a combination thereof. In some embodiments, the bonding pad 346 is formed by a layer of solder, which is first formed by evaporation, electroplating, printing, solder transfer, ball planting, etc. Once the layer of solder is formed on the structure, reflow can be performed to shape the material into a desired bump shape. In addition, the dielectric bonding layer 342 can be a polymer such as PBO, polyimide, BCB, or the like; a nitride such as silicon nitride or the like; an oxide such as silicon oxide, PSG, BSG, BPSG, or the like; or the like or a combination thereof. Dielectric bonding layer 342 may be formed by spin coating, lamination, CVD, etc. Initially, dielectric bonding layer 342 may bury bonding pad 346 so that the topmost surface of dielectric bonding layer 342 is above the topmost surface of bonding pad 346. In some embodiments, solder regions may be formed on bonding pad 346 and dielectric bonding layer 342 may bury the solder regions. In some embodiments, bonding pad 346 is exposed through dielectric bonding layer 342 or protrudes above dielectric bonding layer 342 during the formation of upper die 300. In some embodiments, bonding pad 346 remains buried and is exposed in a subsequent process to package upper die 300. Exposing bonding pad 346 may include removing any solder regions that may be present on bonding pad 346.

[0063] In some embodiments (not specifically shown), vias may be formed extending from the front side to the back side of the substrate 302 of the upper die 300. For example, the vias may be formed similar to the vias 130 of the bottom wafer 100 and some or all of the first vias 231, second vias 232, third vias 233 (e.g., including buried contacts 230), and fourth vias 234 of the middle die 200. In such embodiments, additional conductive features may be formed on the back side of the upper die 300, such as interconnect structures, pads, bond pad vias, and bond pads, similar to the upper die 300, the middle die 200, and / or the bottom wafer 100 described above.

[0064] Figures 4 to 8A cross-sectional view of a semiconductor package formed using the above elements according to some embodiments is shown. In the illustrated embodiment, one or more middle dies 200 are bonded to the bottom wafer 100. The middle die 200 is subsequently processed. One or more upper dies 300 are bonded to the middle die 200, and the structure is further processed to form a multi-layer semiconductor package. Note that the semiconductor package is illustrated as showing one integrated circuit die in the bottom wafer 100, one middle die 200, and one upper die 300, although any suitable number of middle dies 200 and upper dies 300 may be included in the semiconductor package.

[0065] exist Figure 4 , an exemplary middle die 200 (see Figure 2E ) is attached to an exemplary bottom wafer 100 (see Figure 1C ). In addition, the carrier substrate 250 is removed and an encapsulation 402 is formed around the middle die 200. As shown, the back side of the middle die 200 can face the front side of the bottom wafer 100 in a face to back connection. Forming the BSPDN (e.g., the interconnect structure 270 and other features) on the middle die 200 allows this connection to be similar to a face to face connection.

[0066] According to some embodiments, the middle die 200 is attached to the package area of ​​the bottom wafer 100 with the back side of the middle die 200 facing the front side of the bottom wafer 100. It should be noted that other middle dies 200 may be attached to other package areas of the bottom wafer 100 (e.g., at the wafer level), which may not be specifically shown. For example, fusion bonding, dielectric bonding, metal bonding, etc. or combinations thereof, such as dielectric to dielectric and metal to metal bonding, may be used to directly bond the dielectric bonding layer 282 and the bonding pad 286 of the middle die 200 to the dielectric bonding layer 142 and the bonding pad 146, respectively, without adhesive or solder.

[0067] As described above, the bonding of the middle die 200 to the bottom wafer 100 may be formed by metal-to-metal direct bonding (between the bonding pads 286 of the middle die 200 and the bonding pads 146 of the bottom wafer 100) and dielectric-to-dielectric bonding (e.g., Si-O-Si and / or Si-N-Si between the dielectric bonding layer 282 and the dielectric bonding layer 142).

[0068] For example, the dielectric bonding layer 282 of the middle die 200 is bonded to the dielectric bonding layer 142 of the bottom wafer 100 by dielectric-to-dielectric bonding without any adhesive material (e.g., a die attach film). Similarly, the bonding pad 286 is bonded to the bonding pad 146 by metal-to-metal bonding without any eutectic material (e.g., solder). The bonding may include pre-bonding and annealing. During the pre-bonding, a small pressure may be applied to press the middle die 200 toward the bottom wafer 100. The pre-bonding is performed at a low temperature, such as room temperature (e.g., ranging from 15° C. to 30° C.), and after the pre-bonding, the dielectric bonding layer 282 and the dielectric bonding layer 142 are bonded to each other. The bonding strength is then increased in a subsequent annealing step, in which the structure is annealed at a high temperature, such as a temperature of 100° C. to 450° C. After annealing, a bond (e.g., a fusion bond and / or a chemical bond) is formed between the dielectric bonding layer 282 and the dielectric bonding layer 142. For example, the bond between the material of dielectric bonding layer 282 and the material of dielectric bonding layer 142 may be a covalent bond.

[0069] As shown in the figure, the bonding pad 286 of the middle tube core 200 and the bonding pad 146 of the bottom wafer 100 are aligned with each other and electrically connected to each other. The bonding pad 286 and the bonding pad 146 can be physically contacted during the pre-bonding period, or can be expanded to physically contact during the annealing period. In addition, during the annealing period, the material (such as copper) of the bonding pad 286 and the material (such as copper) of the bonding pad 146 blend, thereby also forming a metal to metal bond. Therefore, the key generated between the middle tube core 200 and the bottom wafer 100 includes a combination of dielectric to dielectric bond and metal to metal bond.

[0070] Continue to refer Figure 4 , the carrier substrate 250 is removed from the middle die 200. Some or all of the adhesive layer 252 (if present) may remain on the interconnect structure 220. In some embodiments, the peeling process can be performed by projecting light such as laser light or ultraviolet (UV) light onto the adhesive layer 252, causing the adhesive layer 252 to decompose under the heat of the light, thereby allowing the removal of the carrier substrate 250. In some embodiments, the carrier substrate 250 and the adhesive layer 252 (if present) are removed by a lapping process. It should be noted that any suitable method can be used to remove the carrier substrate 250.

[0071] According to some embodiments, encapsulant 402 is formed on and around various components, and a thinning process may be performed to remove excess encapsulant 402 disposed on the interconnect structure 220. After formation, encapsulant 402 encapsulates the upper surface and sidewalls of the middle tube core 200. Encapsulant 402 is also formed in the gap area between adjacent middle tube cores 200. Encapsulant 402 may be a molding material, epoxy resin, resin, etc. Encapsulant 402 may be applied by compression molding, transfer molding, or a similar method thereof, and may be formed on the structure so that the middle tube core 200 is buried or covered. As another example, encapsulant 402 may include nitride (e.g., silicon nitride) and / or oxide (e.g., silicon oxide) and may be deposited using spin coating, FCVD, PECVD, LPCVD, ALD, or any suitable process. Encapsulant 402 may be applied in liquid or semi-liquid form and then subsequently cured. The encapsulant 402 is optionally thinned to expose the middle die 200. The thinning process may be a grinding process, CMP, etch back, a combination thereof, or the like, and may remove a portion of the middle die 200 (e.g., a portion or all of the adhesive layer 252, if present). After the thinning process, the top surface of the encapsulant 402 and the top surface of the middle die 200 are coplanar (within process variation). Thinning is performed until the desired amount of the encapsulant 402 and the middle die 200 are removed. According to some embodiments, thinning may be stopped without exposing the interconnect structure 220 of the middle die 200.

[0072] In some embodiments (not specifically shown), a liner layer may be formed on and between the middle die 200 before forming the encapsulation 402. The liner layer may be a conformal layer extending along the upper surface and sidewalls of the middle die 200 and along the upper surface of the dielectric bonding layer 142, and may be used as a moisture barrier. The liner layer is formed of a dielectric material having good adhesion to the sidewalls of the middle die 200. For example, the liner layer may be formed of an extra low-k (ELK) material, including a nitride (e.g., silicon nitride) and / or an oxide (e.g., silicon oxide). The deposition of the liner layer may include a conformal deposition process, such as ALD, CVD, or any suitable process. The encapsulation 402 may then be formed on the liner layer as described above. The thinning process may then remove portions of the liner layer and the encapsulation 402 from the top surface (e.g., backside) of the middle die 200.

[0073] exist Figure 5In the embodiment of the present invention, a bonding pad via 244 and a bonding pad 246 are formed on the interconnect structure 220 of the middle die 200 and electrically connect the interconnect structure 220 of the middle die 200. The bonding pad via 244 and the bonding pad 246 can be formed similar to other features of the same name described above. For example, a dielectric bonding layer 242 can be deposited on the middle die 200 and the encapsulation body 402. Recesses can be formed in the dielectric bonding layer 242 and any other dielectric layer below the dielectric bonding layer 242 on the interconnect structure 220 to expose the interconnect structure 220. The bonding pad via 244 and the bonding pad 246 can be formed sequentially in a single damascene process or simultaneously in a dual damascene process.

[0074] exist Figure 6 , an exemplary upper die 300 (see Figure 3B ) is bonded to the middle die 200 and forms an encapsulation body 404 around the upper die 300. According to some embodiments, the upper die 300 can be bonded to the middle die 200 in a manner such that the front side of the upper die 300 faces the front side of the middle die 200. It should be noted that other upper dies 300 may be bonded to the same or different middle dies 200, which are not specifically shown. For example, fusion bonding, dielectric bonding, metal bonding, etc. or a combination thereof, such as dielectric-to-dielectric and metal-to-metal bonding, can be used to directly bond the dielectric bonding layer 342 and the bonding pad 346 of the upper die 300 to the dielectric bonding layer 242 and the bonding pad 246, respectively, without adhesive or solder.

[0075] In some embodiments, the upper die 300 is bonded to the middle die 200, similar to the bonding of the middle die 200 to the bottom wafer 100 described above. For example, the bonding of the upper die 300 to the middle die 200 can be through metal-to-metal direct bonding (between bonding pads 346 of the upper die 300 and bonding pads 246 of the middle die 200) and dielectric-to-dielectric bonding (such as Si-O-Si and / or Si-N-Si bonding formed between dielectric bonding layer 342 and dielectric bonding layer 242).

[0076] After attaching the upper tube core 300, the encapsulant 404 is formed on and around the various elements, and a thinning process can be performed to remove the excess encapsulant 404 disposed on the substrate 302 of the upper tube core 300. After formation, the encapsulant 404 encapsulates the upper surface and sidewalls of the upper tube core 300. The encapsulant 404 is also formed in the gap area between the adjacent upper tube cores 300. The encapsulant 404 can be a molding material, an epoxy resin, a resin, etc. The encapsulant 404 can be applied by compression molding, transfer molding, or the like, and can be formed on the structure so that the upper tube core 300 is buried or covered. As another example, the encapsulant 404 may include a nitride (e.g., silicon nitride) and / or an oxide (e.g., silicon oxide), and can be deposited using spin coating, FCVD, PECVD, LPCVD, ALD, or any suitable process. The encapsulant 404 can be applied in a liquid or semi-liquid form and then subsequently cured. The encapsulant 404 is optionally thinned to expose the upper die 300. The thinning process may be a grinding process, CMP, etch back, a combination thereof, or the like, and may remove a portion of the upper die 300 (e.g., a portion or all of the adhesive layer 252, if present). After the thinning process, the top surface of the encapsulant 404 and the top surface of the upper die 300 (e.g., substrate 302) are coplanar (within process variation). Thinning is performed until a desired amount of the encapsulant 404 and the upper die 300 are removed, for example, to reduce the semiconductor package to a desired thickness.

[0077] In some embodiments (not specifically shown), a liner layer may be formed on and between the upper die 300 before forming the encapsulation 404. The liner layer may be a conformal layer extending along the upper surface and sidewalls of the upper die 300 and along the upper surface of the dielectric bonding layer 242, and may serve as a moisture barrier. The liner layer is formed of a dielectric material having good adhesion to the sidewalls of the upper die 300. For example, the liner layer may be formed of an ultra-low-k (ELK) material, including a nitride (e.g., silicon nitride) and / or an oxide (e.g., silicon oxide). The deposition of the liner layer may include a conformal deposition process, such as ALD, CVD, or any suitable process. The encapsulation 404 may then be formed on the liner layer as described above. The thinning process may then remove portions of the liner layer and the encapsulation 404 from the top surface (e.g., backside) of the upper die 300.

[0078] exist Figure 7In the embodiment, the carrier substrate 410 is attached to the upper die 300, and a thinning process is performed on the substrate 102 of the bottom wafer 100 to expose the vias 130. In some embodiments, for example, an adhesive layer 412 or other type of dielectric layer may be used to attach the carrier substrate 410, which facilitates the bonding of the carrier substrate 410 to the upper die 300. After attaching the carrier substrate 250, a thinning process is performed on the substrate 102 of the bottom wafer 100, which may expose the vias 130. The substrate 102 may be thinned using CMP, a grinding process, an etch-back process, a lapping process, or a polishing process.

[0079] exist Figure 8 In some embodiments, the backside of the bottom wafer 100 can be processed to facilitate subsequent external electrical connections and / or attachment of the semiconductor package to an electronic device (not specifically shown). According to some embodiments, the backside processing can include forming an internal connection structure 170 and a metal pad 180 (e.g., a backside power delivery network similar to the middle die 200 and achieving similar advantages as the middle die 200) on the bottom wafer 100. For example, the internal connection structure 170 is formed on the backside of the substrate 102, and a metal pad 180 (e.g., an aluminum pad) is formed on the internal connection structure 170, on which the external connection is made. The internal connection structure 170 can be formed similar to the above-mentioned internal connection structures 120, 220, 270, 320. The metal pad 180 can be formed similar to the above-mentioned metal pads 140, 240, 280, 340.

[0080] The interconnect structure 170 is formed on the back side of the substrate 102 and connected to the via 130 (e.g., TSV). The interconnect structure 170 interconnects the devices 104 to become part of the integrated circuit in the bottom wafer 100. In some embodiments, the interconnect structure 170 can be formed by a metallization pattern embedded in a dielectric layer. The metallization pattern includes metal lines and vias formed in one or more low-k dielectric layers. The metallization pattern of the interconnect structure 170 is electrically coupled to the device 104 through the via 130 and is electrically connected to the interconnect structure 120 on the front side of the substrate 102.

[0081] As shown, metal pad 180 is arranged on the metallization layer of interconnect structure 170 and electrically connected to the metallization layer of interconnect structure 170. Metal pad 180 can be in one or more dielectric layers 181 and include metal, such as aluminum, copper, etc. For example, dielectric layer 181 may include silicon oxide and / or silicon nitride, such as silicon oxynitride (SiON), silicon carbide (SiC) or any suitable material. Metal pad 180 can be considered as a part of interconnect structure 170. In some embodiments (not specifically shown), metal pad 180 can be formed on the back side of substrate 102 and connected to via 130 without forming interconnect structure 170.

[0082] In some embodiments (not specifically shown), some of the metal pads 180 may be exposed to perform, for example, electrical and thermal tests of the semiconductor package. For example, probes may be used to directly contact these metal pads 180, or solder areas (e.g., solder balls or solder bumps) may be provided on the metal pads 180 for direct contact with the probes.

[0083] Although not specifically shown, subsequent processing of the semiconductor package may be performed, such as forming external connectors on and electrically connecting the metal pads 180, and performing segmentation to separate the structure into separate semiconductor packages. Electrical and thermal testing of the semiconductor package described above may be performed after forming the external connectors. In addition, some embodiments (not specifically shown) may include a BSPDN on the upper die 300. In such embodiments, the external connectors may also or alternatively be formed on the upper die 300.

[0084] Figures 9 to 12 Shows that it can be used Figures 1A to 3B Various arrangements of additional semiconductor packages formed from the elements described in the drawings. These semiconductor packages may be used Figures 4 to 8 As further shown, the external connector 420 has been formed on the inner wiring structure 170 of the bottom wafer 100, using the process described above for the back side processing of the bottom wafer 100. For semiconductor packages having multiple middle tube cores 200 and / or multiple upper tube cores 300, it is noted that each middle tube core 200 and / or upper tube core 300 can be the same integrated circuit tube core (e.g., formed simultaneously in the same wafer), the same kind of integrated circuit tube core, the same kind but different integrated circuit tube core, or different kinds of integrated circuit tube core. All relevant combinations are fully intended to be included in the scope of the present disclosure.

[0085] Fig. 9 A semiconductor package is shown in which two or more middle dies 200 and two or more upper dies 300 are attached to a single device area of ​​a bottom wafer 100. Thus, after singulation, each semiconductor package will include two or more middle dies 200 and two or more upper dies 300. Although two middle dies 200 and two upper dies 300 are shown, any suitable number may be included in each semiconductor package. In addition, the number of middle dies 200 may be different from the number of upper dies 300. Note that each upper die 300 will only be directly electrically connected to the corresponding lower middle die 200, and the upper dies 300 are indirectly electrically connected to each other.

[0086] Fig.10The semiconductor package of one middle die 200 and two or more upper dies 300 attached to or attached to a device area of ​​the bottom wafer 100 is shown. Thus, after singulation, each semiconductor package will include one middle die 200 and two or more upper dies 300. Although two upper dies 300 are shown, any suitable number of upper dies 300 may be included in each semiconductor package. Note that each upper die 300 is directly electrically connected to the middle die 200.

[0087] Fig.11 A semiconductor package is shown in which two or more middle dies 200 and one upper die 300 are attached to a device area of ​​a bottom wafer 100. Thus, after singulation, each semiconductor package will include two or more middle dies 200 and one upper die 300. Although two middle dies 200 are shown, any suitable number of middle dies 200 may be included in each semiconductor package. Note that each middle die 200 is directly electrically connected to the bottom wafer 100 and directly electrically connected to the upper die 300 (e.g., electrically interposed between the bottom wafer 100 and the upper die 300). Thus, the middle dies 200 are indirectly electrically connected to each other.

[0088] Fig.12 A semiconductor package is shown in which two or more levels or layers (e.g., an N-layer stack) of middle dies 200 are attached to one device area of ​​a bottom wafer 100. Although illustrated as each of the upper dies 300 being directly electrically connected to a corresponding middle die 200 in the Nth layer of the N-layer stack, the layout of the Nth layer middle die 200 and the upper die 300 may follow the layout described above with respect to Figures 8 to 11 In addition, the layout of the N-layer stack of the middle die 200 can be similar to the above-mentioned Figures 8 to 11 Any of the layouts described in .

[0089] Embodiments can achieve various advantages. As described above, the formation of various integrated circuit dies allows for many different layouts for assembling semiconductor packages. In particular, the semiconductor package can have three or more levels of integrated circuit dies, including integrated circuits within the bottom wafer 100, one or more middle dies 200, and one or more upper dies 300. According to different embodiments, semiconductor packages can be assembled to have more stacking flexibility, a smaller footprint, faster and more reliable electrical connections between integrated circuit dies, higher interconnect density, and improved performance.

[0090] In one embodiment, a method includes: bonding the front side of a first die to the front side of a wafer, the first bonding pad being along the back side of the first die, the wafer including a substrate and a transistor along the substrate, the transistor facing the front side of the wafer, the first die including: a first bonding pad along the back side of the first die; a first back side interconnect structure adjacent to and electrically connected to the first bonding pad; a first front side interconnect structure adjacent to and electrically connected to the first back side interconnect structure; a first semiconductor substrate sandwiched between the first back side interconnect structure and the first front side interconnect structure; and a first transistor along the first semiconductor substrate, the first transistor facing the front side of the first die; forming a second bonding pad on the first front side interconnect structure; and bonding the second front side of the second die to the second bonding pad of the first die, the second die including a second semiconductor substrate and a second transistor, the second transistor facing the front side of the second die. In other embodiments, the first die includes a first type of via extending through the first semiconductor substrate and a second type of via, wherein the width of the first type of via decreases in a direction from the front side of the first die to the back side of the first die, and wherein the width of the second type of via decreases in a direction from the back side of the first die to the front side of the first die. In other embodiments, the first type of via includes a first via and a second via, wherein the first via extends from the front side of the first semiconductor substrate to the back side of the first semiconductor substrate, and wherein the second via extends from the first front-side interconnect structure to the back side of the first semiconductor substrate. In other embodiments, the second type of via includes a third via and a fourth via, and wherein the third via extends from the back side of the first semiconductor substrate and is electrically coupled to a buried contact embedded in the front side of the first semiconductor substrate. In other embodiments, the fourth via extends from the back side of the first semiconductor substrate and is electrically coupled to the first transistor. In other embodiments, the first type of via is wider than the second type of via. In other embodiments, the second bonding pad is formed after the back side of the first die is bonded to the front side of the wafer. In other embodiments, the method further includes: bonding a carrier to the back side of the second die; thinning the substrate along the back side of the wafer; and forming a backside interconnect structure on the back side of the wafer.

[0091] In one embodiment, a method includes: forming a first die, the forming of the first die including: forming a first via in the front side of a substrate; forming a transistor including a gate and a source / drain region on the front side of the substrate; forming a first interconnect structure on the front side of the substrate, the first interconnect structure being electrically connected to the gate; forming a second via in the back side of the substrate, the second via connecting the source / drain region; and forming a second interconnect structure on the back side of the substrate; bonding the first die to a wafer, the wafer and the first die being electrically connected; and bonding the second die to the first die, the first die being electrically inserted between the wafer and the second die. In other embodiments, the active side of the second die faces the front side of the substrate of the first die. In other embodiments, the method further includes: forming a third interconnect structure on the back side of the wafer after bonding the second die to the first die; and forming external connectors on the third interconnect structure and on the back side of the wafer. In other embodiments, forming the first die includes forming a plurality of first dies at a wafer level, wherein attaching the first die to the wafer includes attaching the plurality of first dies to the wafer, wherein after attaching the second die to the first die, the second die is electrically connected to each of the plurality of first dies. In other embodiments, attaching the second die to the first die includes attaching the plurality of second dies to the first die, and wherein each of the plurality of second dies is electrically connected to the first die. In other embodiments, forming the first die includes forming a plurality of first dies at a wafer level, and further includes attaching an additional first die to the first die, wherein the first die is electrically inserted between the wafer and the additional first die, and wherein attaching the second die to the first die includes attaching the second die to the additional first die.

[0092] In one embodiment, a semiconductor package includes: a first transistor on a front side of a first substrate; a first via extending from the front side to the back side of the first substrate, the first via having a first width measured at the front side of the first substrate and a second width measured at the back side of the first substrate, the first width being greater than the second width; a second via extending from the front side to the back side of the first substrate, the second via having a third width measured at the front side of the first substrate and a fourth width measured at the back side of the first substrate, the third width being greater than the fourth width, and the third width being greater than the first width of the first via; a third via extending from the first transistor to the back side of the first substrate, the third via having a third width measured at the front side of the first substrate and a fourth width measured at the back side of the first substrate, the third width being greater than the fourth width, and the third width being greater than the first width of the first via; and a third via extending from the first transistor to the back side of the first substrate, the third via having a third width measured at the front side of the first substrate and a fourth width measured at the back side of the first substrate. The via has a fifth width measured at the first transistor and a sixth width measured at the back side of the first substrate, the fifth width being less than the sixth width; a first interconnect structure, over the first transistor and the front side of the first substrate; a first bonding pad, over the first interconnect structure, the first bonding pad bonding to the second bonding pad of the first die; a second interconnect structure, over the back side of the first substrate, the third via electrically connecting the second interconnect structure to the first transistor; a third bonding pad, over the second interconnect structure, the third bonding pad bonding to the fourth bonding pad of the second die; and an external connector, along the back side of the second die, the back side of the second die relative to the fourth bonding pad. In other embodiments, the first die includes a second transistor over the active side of the second substrate, the active side of the second substrate facing the front side of the first substrate. In other embodiments, the second die includes a third transistor over the active side of the third substrate, the active side of the third substrate facing the back side of the first substrate. In other embodiments, the first width of the first via is greater than the sixth width of the third via. In other embodiments, the semiconductor package further comprises: a buried contact embedded in the front side of the first substrate; and a fourth via extending from the buried contact to the back side of the first substrate, the fourth via having a seventh width measured at the buried contact and an eighth width measured at the back side of the first substrate, the seventh width being less than the eighth width. In other embodiments, the sixth width of the third via is the same as the eighth width of the fourth via.

[0093] In one embodiment, a semiconductor package includes: a first active device on a front side of a first substrate; a first via extending from the front side to the back side of the first substrate, wherein a width of the first via measured at the front side of the first substrate is greater than a width of the first via measured at the back side of the first substrate; an interlayer dielectric located on the front side of the first substrate and surrounding the first active device; a second via extending through the interlayer dielectric and the first substrate and extending from the front side to the back side of the first substrate, wherein a width of the second via measured at the front side of the first substrate is greater than a width of the second via measured at the back side of the first substrate; and a third via extending from the front side to the back side of the first substrate. A via extending from the first active device to the back side of the first substrate, the third via having a width measured at the first active device less than the width of the third via measured at the back side of the first substrate; a first interconnect structure on the first active device and the front side of the first substrate; a first bonding pad on the first interconnect structure, the first bonding pad bonding to the second bonding pad of the first die; a second interconnect structure on the back side of the first substrate, the third via electrically connecting the second interconnect structure to the first active device; and a third bonding pad on the second interconnect structure, the third bonding pad bonding to the fourth bonding pad of the second die. In other embodiments, the semiconductor package further includes: a buried contact embedded in the front side of the first substrate, and the interlayer dielectric covers the buried contact; and a fourth via extending from the buried contact to the back side of the first substrate, the fourth via having a width measured at the buried contact less than the width of the fourth via measured at the back side of the first substrate. In other embodiments, the width of the second via measured at the top surface of the interlayer dielectric is greater than the width of the second via measured at the back side of the first substrate. In other embodiments, the width of the first via measured at the front side of the first substrate is equal to or less than the width of the second via measured at the top surface of the interlayer dielectric.

[0094] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and those skilled in the art may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor package, characterized in that: include: a first transistor over the front side of the first substrate; a first via extending from the front side to the back side of the first substrate, the first via having a first width measured at the front side of the first substrate and a second width measured at the back side of the first substrate, the first width being greater than the second width; a second via extending from the front side to the back side of the first substrate, the second via having a third width measured at the front side of the first substrate and a fourth width measured at the back side of the first substrate, the third width being greater than the fourth width, and the third width being greater than the first width of the first via; a third via extending from the first transistor to the back side of the first substrate, the third via having a fifth width measured at the first transistor and a sixth width measured at the back side of the first substrate, the fifth width being smaller than the sixth width; a first interconnect structure over the first transistor and the front side of the first substrate; a first bonding pad, on the first inner connection structure, the first bonding pad being bonded to the second bonding pad of the first die; a second internal connection structure on the back side of the first substrate, the third via electrically connecting the second internal connection structure to the first transistor; a third bonding pad, on the second inner connection structure, the third bonding pad being bonded to the fourth bonding pad of the second die; as well as An external connector is provided along a back side of the second die, the back side of the second die being opposite to the fourth bonding pad. 2 . The semiconductor package of claim 1 , wherein the first die comprises a second transistor on an active side of a second substrate, the active side of the second substrate facing the front side of the first substrate. 3 . The semiconductor package of claim 2 , wherein the second die comprises a third transistor on an active side of a third substrate, the active side of the third substrate facing the back side of the first substrate. 4 . The semiconductor package according to claim 1 , wherein the first width of the first via is greater than the sixth width of the third via.

5. The semiconductor package according to claim 1, further comprising: a buried contact embedded in the front side of the first substrate; as well as A fourth conductive via extends from the buried contact to the back side of the first substrate, the fourth conductive via having a seventh width measured at the buried contact and an eighth width measured at the back side of the first substrate, the seventh width being smaller than the eighth width. 6 . The semiconductor package according to claim 5 , wherein the sixth width of the third via hole is the same as the eighth width of the fourth via hole.

7. A semiconductor package, characterized in that: include: a first active device on the front side of the first substrate; a first conductive via extending from the front side to the back side of the first substrate, the width of the first conductive via measured at the front side of the first substrate being greater than the width of the first conductive via measured at the back side of the first substrate; an interlayer dielectric on the front side of the first substrate and surrounding the first active device; a second via extending through the interlayer dielectric and the first substrate and extending from the front side to the back side of the first substrate, wherein a width of the second via measured at the front side of the first substrate is greater than a width of the second via measured at the back side of the first substrate; a third conductive via extending from the first active device to the back side of the first substrate, wherein a width of the third conductive via measured at the first active device is smaller than a width of the third conductive via measured at the back side of the first substrate; a first interconnect structure over the first active device and the front side of the first substrate; a first bonding pad, on the first inner connection structure, the first bonding pad being bonded to the second bonding pad of the first die; a second interconnect structure on the back side of the first substrate, the third via electrically connecting the second interconnect structure to the first active device; as well as The third bonding pad is on the second inner connection structure, and the third bonding pad is bonded to the fourth bonding pad of the second tube core.

8. The semiconductor package according to claim 7, further comprising: a buried contact embedded in the front side of the first substrate, and the interlayer dielectric covers the buried contact; as well as A fourth conductive via extends from the buried contact to the back side of the first substrate, the fourth conductive via having a width measured at the buried contact that is smaller than a width of the fourth conductive via measured at the back side of the first substrate. 9 . The semiconductor package of claim 7 , wherein a width of the second via measured at a top surface of the interlayer dielectric is greater than a width of the second via measured at the back side of the first substrate. 10 . The semiconductor package of claim 7 , wherein a width of the first via measured at the front side of the first substrate is equal to or smaller than a width of the second via measured at a top surface of the interlayer dielectric.

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