Pixel and display device including same

Abstract

The utility model relates to a pixel and a display device. A pixel according to an embodiment of the present disclosure includes: a light emitting element; a pulse width control circuit electrically connected to a data line to which a data voltage is applied, generating an emission control signal having a pulse width according to the data voltage, and outputting the emission control signal; and a pixel driving circuit receiving the emission control signal and providing a driving current to the light emitting element in a period according to a pulse width of the emission control signal. According to an embodiment of the present disclosure, a pixel that displays images of various gray levels by controlling a period of light emission of a light emitting element, a method for driving the pixel, and a display device including the pixel may be provided.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0008605 filed on January 20, 2023 in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present disclosure relate to a pixel, a method of driving a pixel, and a display device including the pixel. Background Art

[0004] As information technology develops, the importance of display devices as a connection medium between users and information has been emphasized. In response to this, the use of non-luminescent display devices such as liquid crystal display devices and luminescent display devices such as organic light emitting display devices has increased.

[0005] The light-emitting display device may include a plurality of pixels including one or more light-emitting elements, and may display images of various grayscale levels by changing the magnitude of a driving current flowing through the light-emitting element.

[0006] However, when the display device is used for a long time, the grayscale of the image displayed by the pixel may change due to the change of the characteristics of the transistor that provides the driving current to the light emitting element. This may manifest as a phenomenon that the color coordinates preset in the display device are distorted.

[0007] Therefore, there is a demand for a pixel and a display device that can display images of various grayscale levels without changing the magnitude of a driving current supplied to a light emitting element. Utility Model Content

[0008] The present disclosure provides a pixel for displaying an image of various grayscales by controlling the length of a period in which a light emitting element emits light, a method of driving the pixel, and a display device including the pixel.

[0009] A pixel according to an embodiment of the present disclosure may include: a light emitting element; a pulse width control circuit electrically connected to a data line to which a data voltage is applied, generating an emission control signal having a pulse width according to the data voltage, and outputting the emission control signal; and a pixel driving circuit receiving the emission control signal and providing a driving current to the light emitting element within a period according to the pulse width of the emission control signal.

[0010] The pulse width control circuit may include a first capacitor including a first electrode to which the data voltage is applied and a second electrode to which the triangular wave is applied.

[0011] The pulse width control circuit may further include a first switching element which switches an electrical connection between the first electrode of the first capacitor and the data line.

[0012] The pulse width control circuit may further include a second switching element, the second switching element including a gate electrode, a source electrode and a drain electrode, the gate electrode being electrically connected to the first electrode of the first capacitor. The gate electrode of the second switching element may be electrically connected to the first electrode of the first capacitor and the first switching element at the first node. One of the source electrode and the drain electrode of the second switching element may be electrically connected to the first power line to which the first power supply voltage is applied. The other of the source electrode and the drain electrode of the second switching element may be electrically connected to the second power line to which the second power supply voltage is applied.

[0013] The pulse width control circuit may further include a third switching element that switches an electrical connection between the first power line and the second switching element.

[0014] The second switching element and the third switching element may be electrically connected at the second node. The emission control signal may be output through the second node.

[0015] The pulse width control circuit may further include a second capacitor including an electrode electrically connected to the second node.

[0016] The emission control signal may have a high level voltage or a low level voltage. One of the high level voltage and the low level voltage may be a voltage of the first power line. The other of the high level voltage and the low level voltage may be a voltage of the second power line.

[0017] The light emitting element may be electrically connected to a third power line. The pixel driving circuit may include: a first emission control switching element including a gate electrode to which an emission control signal is input and switches the electrical connection between the first power line and the fourth node; a fourth switching element including a gate electrode, a source electrode, and a drain electrode electrically connected to the third node; and a fifth switching element switching the electrical connection between the fourth node and the fourth power line. One of the source electrode and the drain electrode of the fourth switching element may be electrically connected to the fourth node, and the other of the source electrode and the drain electrode of the fourth switching element may be electrically connected to the fifth node.

[0018] The pixel driving circuit may further include a second emission control switching element which switches an electrical connection between the fifth node and the light emitting element.

[0019] The pixel driving circuit may further include a storage capacitor including one electrode electrically connected to the third node and another electrode electrically connected to the first power line.

[0020] The pixel driving circuit may further include a first initialization switching element that switches electrical connection between the third node and a second power line to which a second power voltage is applied. A gate electrode of the first emission control switching element may be electrically connected to the second power line through a pulse width control circuit.

[0021] The driving current flowing through the light emitting element may flow from the first power line to which the first power voltage is applied via the pixel driving circuit. The high level voltage of the emission control signal may be a voltage applied from the first power line to the pixel driving circuit via the pulse width control circuit.

[0022] A display device according to an embodiment of the present disclosure may include: a display panel on which a plurality of pixels including light-emitting elements and a plurality of data lines electrically connected to the plurality of pixels are arranged; and a data driving circuit that provides a data voltage to the plurality of data lines. Each of the plurality of pixels may emit light in a period according to the data voltage.

[0023] The display device may further include: a timing controller that outputs input image data to the data driving circuit. The input image data may include grayscale information for each of the plurality of pixels, and the data driving circuit may output a data voltage having a voltage level corresponding to the grayscale information. Each of the plurality of pixels may emit light in a period according to the grayscale information included in the input image data.

[0024] A plurality of first scan lines may be provided on the display panel, and each of the plurality of first scan lines may be electrically connected to pixels in the same pixel row among the plurality of pixels. According to the data voltage, the pixels in the same pixel row among the plurality of pixels may have different start emission times or different end emission times.

[0025] The display device may further include a triangular wave output circuit, which outputs a first voltage or a triangular wave linearly increased from the first voltage. At least one sweep line to which a triangular wave is applied may be provided on the display panel, and at least one sweep line may be electrically connected to a plurality of pixels. A period in which a data voltage is input to a plurality of pixels electrically connected to at least one sweep line may overlap with a period in which the triangular wave output circuit outputs the first voltage. A period in which a plurality of pixels electrically connected to at least one sweep line emit light may overlap with a period in which the triangular wave output circuit outputs a triangular wave.

[0026] According to an embodiment of the present disclosure, a method for driving a pixel including a light-emitting element may include: inputting a data voltage into the pixel; generating an emission control signal having a pulse width corresponding to the data voltage in the pixel; and emitting light from the light-emitting element within a period corresponding to the pulse width of the emission control signal.

[0027] The method for driving a pixel may further include inputting a triangular wave to the pixel through a scanning line electrically connected to the pixel. The light emitting element may emit light during the period of inputting the triangular wave to the pixel.

[0028] The method for driving a pixel may further include inputting a first voltage to the scan line. Inputting a data voltage may be performed during a period in which the first voltage is input. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

[0030] Figure 1 is a schematic system block diagram of a display device according to an embodiment of the present disclosure.

[0031] Figure 2A is a schematic diagram showing a driving circuit of pixels in a display device that displays images in a sequential emission method.

[0032] Figure 2B is a schematic diagram showing a driving circuit of pixels in a display device that displays images in a non-sequential emission method.

[0033] Figure 3 is a schematic system block diagram of a pixel according to an embodiment of the present disclosure.

[0034] Figure 4 is an equivalent schematic diagram showing a pulse width control circuit according to an embodiment of the present disclosure.

[0035] Figure 5 is a schematic diagram showing a second emission control signal generated by a pulse width control circuit according to an embodiment of the present disclosure.

[0036] Figure 6 is a diagram illustrating an embodiment of adjusting the length of a non-emission period according to a level of a data voltage.

[0037] Figure 7 is a schematic diagram showing the relationship between the pulse width of the second emission control signal and the length of the emission period according to an embodiment of the present disclosure.

[0038] Figure 8 is an equivalent schematic diagram showing a pixel driving circuit according to an embodiment of the present disclosure.

[0039] Fig. 9 is a schematic diagram showing a signal input to a pixel driving circuit and a voltage of a scanning line according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of various embodiments or implementations of the present disclosure. As used herein, "embodiment" and "implementation" are interchangeable words, which are non-limiting examples of the devices or methods disclosed herein. However, it is apparent that various embodiments can be practiced without these specific details or with one or more equivalent arrangements. Here, various embodiments do not have to be exclusive or limit the present disclosure. For example, the specific shape, configuration, and characteristics of an embodiment can be used or implemented in another embodiment.

[0041] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that a person skilled in the art can easily implement the present disclosure. The present disclosure can be implemented in various different forms and is not limited to the embodiments described herein.

[0042] In order to clearly describe the present disclosure, parts not related to the description are omitted, and the same or similar components are represented by the same reference numerals throughout the specification. Therefore, the above reference numerals can also be used in other drawings.

[0043] Unless otherwise specified, the described embodiments should be understood to provide exemplary features of the present disclosure. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter, individually or collectively referred to as "elements") of various embodiments may be combined, separated, interchanged and / or rearranged in other ways without departing from the present disclosure.

[0044] Various embodiments are described herein with reference to cross-sectional views and / or exploded views as schematic diagrams of embodiments and / or intermediate structures. Therefore, variations in the shapes in the figures, such as due to manufacturing techniques and / or tolerances, should be expected. Therefore, the embodiments disclosed herein should not necessarily be interpreted as being limited to the specific illustrated regional shapes, but should include deviations in shapes such as those caused by manufacturing. In this way, the regions shown in the drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and are not necessarily intended to be limiting.

[0045] In addition, for convenience of description, the size and thickness of each component shown in the drawings are arbitrarily shown, and therefore the present disclosure is not necessarily limited to those shown in the drawings. In the drawings, the thickness may be exaggerated to clearly represent layers and regions.

[0046] Furthermore, in the specification, the expression "is the same" may mean "substantially the same". That is, it may be sufficiently identical to convince a person of ordinary skill in the art that it is the same. In other expressions, "substantially" may be omitted.

[0047] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0048] For descriptive purposes, spatially relative terms such as "below," "above," "on," "above," "higher," "side" (e.g., as in "sidewall"), etc. may be used herein, and thereby describe the relationship of one element to another element (or elements) as shown in the accompanying drawings. In addition to the orientation depicted in the accompanying drawings, spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture. For example, if the device in the accompanying drawings is flipped, an element described as being "below" or "below" other elements or features will then be oriented "above" the other elements or features. Thus, the exemplary term "below" may encompass both above and below orientations. Additionally, the device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and therefore, the spatially relative descriptors used herein should be interpreted accordingly.

[0049] The terms used herein are for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. In addition, when used in this specification, the terms "comprises", "comprising", "includes" and / or "including" specify the existence of the features, wholes, steps, operations, elements, components and / or groups thereof described, but do not exclude the existence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. It is also noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms rather than as degree terms, and are therefore used to allow for the inherent deviations in the measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0050] When an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it may be directly on, directly connected to, or directly coupled to the other element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection, and / or a fluid connection with or without intervening elements.

[0051] In addition, the first direction DR1, the second direction DR2 and the third direction DR3 are not limited to the three axes of the rectangular coordinate system, such as the x-axis, the y-axis and the z-axis, and can be interpreted in a broader sense. For example, the first direction DR1, the second direction DR2 and the third direction DR3 can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of X, Y and Z" and "at least one selected from the group consisting of X, Y and Z" can be interpreted as any combination of only X, only Y, only Z or two or more of X, Y and Z, such as, for example, XYZ, XYY, YZ and ZZ. In the specification and claims, for the purpose of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B or A and B". The terms "and" and "or" can be used in a combined or separate sense and can be understood to be equivalent to "and / or".

[0052] The display surface may be parallel to the surface defined by the first direction DR1 and the second direction DR2. The normal direction of the display surface (i.e., the thickness direction of the display device) may represent a third direction DR3. In the present specification, the expression "when viewed from a plane or on a plane" or "in a plan view" may represent the situation when viewed in the third direction DR3. In the following, the front surface (or top surface) and the rear surface (or bottom surface) of each of the layers or units may be distinguished by the third direction DR3. However, the directions represented by the first direction DR1, the second direction DR2, and the third direction DR3 may be relative concepts and converted relative to each other, for example, converted to opposite directions.

[0053] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless explicitly defined in this specification.

[0054] Figure 1 is a schematic system block diagram of a display device 100 according to an embodiment of the present disclosure.

[0055] The display device 100 according to an embodiment of the present disclosure may include a display panel 110 , a data driving circuit 120 , a gate driving circuit 130 , a triangle wave output circuit 140 , a timing controller 150 , a power management circuit 160 , and the like.

[0056] A plurality of pixels PXL may be provided on the display panel 110. Each of the pixels PXL may include one or more light emitting elements. In the case where each of the pixels PXL includes one or more light emitting elements, the display device 100 may be implemented as a light emitting type display device.

[0057] In the case where the display device 100 is implemented as a light-emitting display device, the display device 100 may be implemented as an inorganic light-emitting display device. The display device 100 may be a curved display device, a flexible display device, a foldable display device, a rollable display device, a stretchable display device, a transparent display device, a mirror display device, etc. The display device 100 may be implemented as a display device including, for example, an inorganic light-emitting element having a nanometer size to a micrometer size. The display device 100 may be implemented as an organic light-emitting display device including an organic light-emitting element. The display device 100 according to an embodiment of the present disclosure is not limited thereto.

[0058] A plurality of data lines DL1 to DLm (where m may be a natural number greater than or equal to 2), gate lines GL1 to GLn (where n may be a natural number greater than or equal to 2), and sweep lines SWL1 to SWLn (where n may be a natural number greater than or equal to 2) electrically connected to the pixel PXL may be provided on the display panel 110. A plurality of power lines may be provided on the display panel 110 to transfer a power voltage to be applied to the pixel PXL. One of the first power voltage ELVDD, the second power voltage VINIT, the third power voltage ELVSS, the fourth power voltage DATA_PAM, and the fifth power voltage VAINIT may be applied to one of the power lines provided on the display panel 110.

[0059] The data lines DL1 to DLm may be disposed on the display panel 110 to extend in a first direction DR1. For example, the first direction DR1 may be a direction connecting the upper side and the lower side of the display panel 110. The first direction DR1 may be, for example, a column direction.

[0060] The gate lines GL1 to GLn may be arranged on the display panel 110 to extend in a second direction DR2. The second direction DR2 and the first direction DR1 may be different. For example, the second direction DR2 may intersect with the first direction DR1. The second direction DR2 may be, for example, a direction connecting the left and right sides of the display panel 110. The second direction DR2 may be, for example, a row direction. However, the directions indicated by the first direction DR1 and the second direction DR2 are not limited to the above description.

[0061] refer to Figure 1 , the scanning lines SWL1 to SWLn may be arranged on the display panel 110 to extend in the second direction DR2. Figure 2B As described, in the case where the display device 100 according to the embodiment of the present disclosure is operated in the non-sequential driving method, the scanning lines SWL1 to SWLn may extend in a direction (eg, the first direction DR1 ) different from the second direction DR2 .

[0062] The power lines may be disposed on the display panel 110 to extend in the first direction DR1 .

[0063] The data driving circuit 120 may output data voltages to the data lines DL1 to DLm. The data driving circuit 120 may generate data voltages for displaying an image and output the generated data voltages to the data lines DL1 to DLm. The data driving circuit 120 may receive input image data DATA and a data driving circuit control signal DCS from the timing controller 150 to generate data voltages, and output the generated data voltages to the data lines DL1 to DLm according to the timing.

[0064] The data driving circuit control signal DCS may include a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, and the like.

[0065] The gate drive circuit 130 may output a gate drive signal to the gate lines GL1 to GLn. The gate drive circuit 130 may output a gate voltage of an on level or an off level to the gate lines GL1 to GLn. The gate drive signal may include an on level gate voltage and an off level gate voltage. The operation timing of the switching element in the pixel PXL may be controlled by the gate drive signal. The gate drive circuit 130 may receive a gate drive circuit control signal GCS from the timing controller 150, and output the gate drive signal (or the on level gate voltage or the on level gate voltage) to the gate lines GL1 to GLn according to the timing. The gate drive circuit 130 may sequentially output the gate drive signal to the gate lines GL1 to GLn, but the present disclosure is not limited thereto.

[0066] The triangular wave output circuit 140 can drive the sweep lines SWL1 to SWLn. The triangular wave output circuit 140 can output a triangular wave to the sweep lines SWL1 to SWLn. The triangular wave may include a signal whose voltage level changes linearly over time. In the present disclosure, the triangular wave may also be referred to as a sweep signal. The triangular wave output circuit 140 can generate a triangular wave, and the triangular wave output circuit 140 can output the generated triangular wave to the sweep lines SWL1 to SWLn. The triangular wave output circuit 140 can sequentially output the generated triangular wave to the sweep lines SWL1 to SWLn, but the present disclosure is not limited thereto. The triangular wave output circuit 140 can receive a triangular wave output circuit control signal SCS from the timing controller 150 to generate a triangular wave, and output the generated triangular wave to the sweep lines SWL1 to SWLn.

[0067] The timing controller 150 may control the data driving circuit 120, the gate driving circuit 130, and the triangular wave output circuit 140. The timing controller 150 may receive image data from the outside (e.g., a host system, etc.), and convert the image data according to an interface (or a preset interface). The timing controller 150 may transmit the input image data DATA converted according to the interface to the data driving circuit 120. The interface may include, for example, a low voltage differential signaling interface (LVDS), a serial peripheral interface (SPI), an inter-integrated circuit (I2C), or an embedded display port (eDP).

[0068] The timing controller 150 may generate the input image data DATA in consideration of the arrangement of the pixels PXL provided on the display panel 110. For example, the timing controller 150 may receive RGB type image data, convert the RGB type image data into RGBG type input image data DATA, and transmit the converted input image data DATA (e.g., the converted RGBG type input image data DATA) to the data driving circuit 120.

[0069] The power management circuit 160 may generate a plurality of power supply voltages to be provided to the display panel 110 and output the generated power supply voltages. The power supply voltages may be voltages commonly input to the pixels PXL.

[0070] The data driving circuit 120, the gate driving circuit 130, the triangular wave output circuit 140, and the timing controller 150 may be classified according to the function performed by each component within the display device 100, and two or more of the components may be formed as a single integrated circuit. For example, the data driving circuit 120 and the timing controller 150 may be integrally formed as a single integrated circuit and provided in the display device 100. The gate driving circuit 130 and the triangular wave output circuit 140 may be integrally formed as a single integrated circuit and provided in the display device 100.

[0071] The timing controller 150 may be formed as an integrated circuit and provided in the display device 100. The timing controller 150 may be implemented as a processor, a logic circuit, etc. and provided in the display device 100. The timing controller 150 may include one or more registers.

[0072] Figure 2A is a schematic diagram showing a driving circuit of a pixel PXLij in a display device 100 that displays an image in a sequential emission method. Figure 2B is a schematic diagram showing a driving circuit of a pixel PXLij in a display device 100 that displays an image in a non-sequential emission method.

[0073] refer to Figure 2A and Figure 2B , the pixel PXLij (hereinafter referred to as pixel PXLij) can be located in the i-th row (1≤i≤n, where n can be a natural number greater than or equal to 2) and the j-th column (1≤j≤m, where m can be a natural number greater than or equal to 2) in the display panel 110.

[0074] refer to Figure 2A , shows a pixel PXLij of a display device 100 that displays an image in a sequential driving method (or a sequential emission method). For example, the gate driving circuit 130 can drive the pixel PXLij from the first gate line GL1 (eg, see Figure 1 ) to the nth gate line GLn (eg, see Figure 1 ) sequentially outputs the gate drive signal. For example, the triangular wave output circuit 140 can output the gate drive signal from the first sweep line SWL1 (for example, see Figure 1 ) to the nth sweep line SWLn (for example, see Figure 1 ) outputs triangular waves sequentially.

[0075] The i-th gate line GLi (for example, see Figure 1 ) may be electrically connected to the pixel PXLij. The i-th gate line GLi may include an i-th first scan line SCL1i, an i-th second scan line SCL2i, an i-th third scan line GWLi, an i-th fourth scan line GILi, an i-th fifth scan line GBLi, and an i-th first emission control line EMLi.

[0076] The ith first scan line SCL1i may be a line to which a gate signal (or a gate voltage of an on level) is applied so that a data voltage applied to the data line DLj is input to the pixel PXLij.

[0077] The i th second scan line SCL2i, the i th third scan line GWLi, the i th fourth scan line GILi, the i th fifth scan line GBLi, and the i th first emission control line EMLi will be described below.

[0078] The i-th scanning line SWLi may be electrically connected to the pixel PXLij.

[0079] The gate driving signal (eg, an on-level gate voltage or an on-level gate voltage) and the triangular wave may be input to the pixels PXL (eg, see FIG. 1 ) located in the same pixel row (eg, the i-th pixel row) at substantially the same timing. Figure 1 ). The gate drive signal and the triangular wave may be input to the pixels PXL located in different pixel rows at different timings (for example, see Figure 1 ).

[0080] refer to Figure 2B , shows a pixel PXLij of the display device 100 displaying an image in a non-sequential driving method. The non-sequential driving method may include a simultaneous emission method.

[0081] In the present disclosure, the simultaneous emission method may refer to "wherein pixels PXL located in different pixel rows (see, e.g. Figure 1 ) simultaneously start to emit light" or "wherein pixels PXL located in different pixel rows (see, for example, Figure 1 ) while terminating the luminescence method.

[0082] refer to Figure 2B , the i-th gate line GLi (for example, see Figure 1 ) may be electrically connected to the pixel PXLij. The i-th gate line GLi may include an i-th first scan line SCL1i, an i-th second scan line SCL2, an i-th third scan line GWL, an i-th fourth scan line GIL, an i-th fifth scan line GBL, an i-th first emission control line EML, and the like.

[0083] At least one of the i-th second scan line SCL2, the i-th third scan line GWL, the i-th fourth scan line GIL, the i-th fifth scan line GBL, and the i-th first emission control line EML may be a common line commonly connected to two or more pixel rows. The i-th second scan line SCL2 may be a common second scan line SCL2. The i-th third scan line GWL may be a common third scan line GWL. The i-th fourth scan line GIL may be a common fourth scan line GIL. The i-th fifth scan line GBL may be a common fifth scan line GBL. The i-th first emission control line EML may be a common first emission control line EML.

[0084] The i-th scanning line SWL may be electrically connected to the pixel PXLij. The i-th scanning line SWL may be commonly connected to two or more pixel rows. The i-th scanning line SWL may be a common scanning line SWL.

[0085] refer to Figure 2AAccording to the embodiment of the present disclosure, the display device 100 can display an image in a sequential driving method. According to the sequential driving method, the period of displaying an image of each pixel row can be controlled. According to the sequential driving method, the period of emitting light of the pixel PXLij within one frame period can be increased.

[0086] refer to Figure 2B According to the embodiment of the present disclosure, the display device 100 can display an image in a non-sequential driving method. According to the non-sequential driving method, pixels PXL located in different pixel rows (for example, see Figure 1 ) can start emitting light at the same time, or can end emitting light at the same time. According to the non-sequential driving method, the gate driving circuit 130 can be simple.

[0087] Hereinafter, the i-th first scan line SCL1i may be referred to as the first scan line SCL1, the i-th second scan line SCL2i or SCL2 may be referred to as the second scan line SCL2, the i-th third scan line GWLi or GWL may be referred to as the third scan line GWL, the i-th fourth scan line GILi or GIL may be referred to as the fourth scan line GIL, the i-th fifth scan line GBLi or GBL may be referred to as the fifth scan line GBL, the i-th first emission control line EMLi or EML may be referred to as the first emission control line EML, the i-th scan line SWLi or SWL may be referred to as the scan line SWL, and the j-th data line DLj may be referred to as the data line DL.

[0088] According to an embodiment of the present disclosure, the display device 100 may display an image in at least one of a sequential driving method and a non-sequential driving method.

[0089] Figure 3 is a schematic system block diagram of a pixel PXL according to an embodiment of the present disclosure.

[0090] refer to Figure 3 , the pixel PXL according to the embodiment of the present disclosure may include a pulse width control circuit PWMC, a pixel driving circuit PDC, and a light emitting element LE.

[0091] The pulse width control circuit PWMC may generate and output the second emission control signal EM2. The pulse width control circuit PWMC may be electrically connected to the data line DL and control the pulse width (or duty ratio) of the second emission control signal EM2 based on the input data voltage.

[0092] The pulse width control circuit PWMC may be electrically connected to the sweep line SWL, the data line DL, the first scan line SCL1, and the second scan line SCL2. The pulse width of the second emission control signal EM2 may be controlled in the pulse width control circuit PWMC by a signal provided to the lines (e.g., the sweep line SWL, the data line DL, the first scan line SCL1, the second scan line SCL2, etc.).

[0093] The pulse width control circuit PWMC may be electrically connected to a power line to which a high level voltage is applied and a power line to which a low level voltage is applied. For example, the pulse width control circuit PWMC may be electrically connected to a first power line PL1 to which a first power voltage ELVDD is applied. The high level voltage of the second emission control signal EM2 may be equal to or substantially equal to the first power voltage ELVDD. For example, the pulse width control circuit PWMC may be electrically connected to a second power line PL2 to which a second power voltage VINIT is applied. The low level voltage of the second emission control signal EM2 may be equal to or substantially equal to the second power voltage VINIT.

[0094] The pixel driving circuit PDC may be electrically connected to the first power line PL1. The pixel driving circuit PDC may receive the first power voltage ELVDD and provide a driving current to the light emitting element LE. The pixel driving circuit PDC may receive the second emission control signal EM2 and control a period during which the driving current is provided to the light emitting element LE according to a pulse width of the input second emission control signal EM2.

[0095] The light emitting element LE may include an electrode electrically connected to the pixel driving circuit PDC and another electrode electrically connected to the third power line PL3. The third power supply voltage ELVSS may be applied to the third power line PL3. The third power supply voltage ELVSS may be, for example, a ground voltage. The light emitting element LE may emit light when the driving current flows, and may not emit light when the driving current does not flow.

[0096] In the pixel PXL according to the embodiment of the present disclosure, the gray level of the corresponding pixel PXL may be adjusted according to the period during which the light emitting element LE emits light within one frame period.

[0097] For example, if the period of light emission of the light emitting element LE in one frame period is long, the corresponding pixel PXL can display a high grayscale image. For example, if the period of light emission of the light emitting element LE in one frame period is short, the corresponding pixel PXL can display a low grayscale image.

[0098] In the pixel PXL according to the embodiment of the present disclosure, the magnitude of the driving current flowing through the light emitting element LE may be constant regardless of the grayscale displayed by the corresponding pixel PXL.

[0099] Figure 4 is an equivalent schematic diagram showing a pulse width control circuit PWMC according to an embodiment of the present disclosure.

[0100] The pulse width control circuit PWMC may include one or more switching elements and one or more capacitors.

[0101] The switching element may include a transistor. The transistor may be implemented as a p-type thin film transistor including a p-type semiconductor or an n-type thin film transistor including an n-type semiconductor. In a p-type thin film transistor, the on-level voltage may be a low-level voltage, and the off-level voltage may be a high-level voltage. In an n-type thin film transistor, the on-level voltage may be a high-level voltage, and the off-level voltage may be a low-level voltage. The transistor may include a polycrystalline silicon semiconductor. In another embodiment, the transistor may include a single crystal silicon semiconductor, an oxide semiconductor, an amorphous silicon semiconductor, etc.

[0102] Hereinafter, an embodiment will be described in which one or more switching elements included in the pulse width control circuit PWMC are implemented as a p-type thin film transistor or an n-type thin film transistor. However, the present disclosure is not limited thereto.

[0103] refer to Figure 4 , the pulse width control circuit PWMC according to an embodiment of the present disclosure may include a first transistor TR1 , a second transistor TR2 , a third transistor TR3 , a first capacitor Csw and a second capacitor Chold.

[0104] The first transistor TR1 may switch the electrical connection between the data line DL and the first node N1. The gate electrode of the first transistor TR1 may be electrically connected to the first scan line SCL1. The operation timing of the first transistor TR1 may be controlled by the first scan signal SCAN1. Figure 4 1 is illustrated as a p-type thin film transistor, but the present disclosure is not limited thereto, and the first transistor TR1 may be implemented as an n-type thin film transistor.

[0105] The second transistor TR2 may switch the electrical connection between the second power line PL2 and the second node N2. The gate electrode of the second transistor TR2 may be electrically connected to the first node N1. The operation timing of the second transistor TR2 may be controlled according to the voltage of the first node N1. When the second transistor TR2 is turned on, the second power supply voltage VINIT may be applied to the second node N2. Although the second transistor TR2 is Figure 4 2 is illustrated as an n-type thin film transistor, but the present disclosure is not limited thereto, and the second transistor TR2 may be implemented as a p-type thin film transistor.

[0106] The third transistor TR3 may switch the electrical connection between the first power line PL1 and the second node N2. The gate electrode of the third transistor TR3 may be electrically connected to the second scan line SCL2. The operation timing of the third transistor TR3 may be controlled by the second scan signal SCAN2. When the third transistor TR3 is turned on, the first power supply voltage ELVDD may be applied to the second node N2. Although the third transistor TR3 is Figure 4 3 is illustrated as a p-type thin film transistor, but the present disclosure is not limited thereto, and the third transistor TR3 may be implemented as an n-type thin film transistor.

[0107] The first capacitor Csw may include a first electrode E1 and a second electrode E2. The first electrode E1 of the first capacitor Csw may be electrically connected to the first node N1. The data voltage DATA_PWM may be input to the first electrode E1 of the first capacitor Csw. The second electrode E2 of the first capacitor Csw may be electrically connected to the sweep line SWL. The triangle wave SWEEP may be input to the second electrode E2 of the first capacitor Csw.

[0108] In the case where the triangular wave SWEEP is input to the second electrode E2, the first capacitor Csw can change the voltage of the first electrode E1. In the case where the triangular wave SWEEP is applied to the second electrode E2 in a state (or floating state) where a constant voltage is not applied to the first electrode E1 of the first capacitor Csw, the voltage level of the first electrode E1 can be changed. The phenomenon that the voltage level of the first electrode E1 changes may be due to the coupling effect of the capacitor. The first capacitor Csw may also be referred to as a sweep capacitor.

[0109] The second capacitor Chold may include one electrode electrically connected to the second node N2 and another electrode to which the first power voltage ELVDD is applied. The other electrode may be electrically connected to, for example, the first power line PL1. The second capacitor Chold may remove noise generated in the second node N2.

[0110] The pulse width control circuit PWMC may output the second emission control signal EM2 through the second node N2. The high level voltage of the second emission control signal EM2 may be the first power supply voltage ELVDD. The low level voltage of the second emission control signal EM2 may be the second power supply voltage VINIT.

[0111] Figure 5 is a schematic diagram showing a second emission control signal EM2 generated by a pulse width control circuit PWMC according to an embodiment of the present disclosure.

[0112] refer to Figure 5 , the frame may include a first period PR1, a second period PR2 and a third period PR3.

[0113] The first period PR1 may be a second scan signal SCAN2 of a turn-on level input to the pixel PXL (eg, see Figure 1 In the first period PR1, a first scan signal SCAN1 of an off level may be input to the pixel PXL. The first power supply voltage ELVDD may be applied to the second node N2.

[0114] The second period PR2 may be a period in which the first scan signal SCAN1 at the on level is input to the pixel PXL (eg, see Figure 1 ) period. In the second period PR2, the second scan signal SCAN2 of the off level may be input to the pixel PXL. The data voltage Vdata[k] (corresponding to Figure 4 DATA_PWM) may be input to the first node N1. For example, in the second period PR2, the data voltage Vdata[k-1] written in the previous frame period (eg, the (k-1)th frame) may be erased, and the data voltage Vdata[k] of the corresponding frame may be written.

[0115] The third period PR3 may be a period of the input triangle wave SWEEP. In an embodiment of the present disclosure, during the third period PR3, the voltage of the sweep line SWL may change (e.g., increase) from the first voltage V1 (e.g., a predetermined or selectable voltage V1) by a voltage ΔV (e.g., a predetermined or selectable voltage ΔV).

[0116] refer to Figure 5 , only a section where the voltage of the sweep line SWL increases linearly in the third period PR3 is shown once, but the present disclosure is not limited thereto. In another embodiment, the third period PR3 may include a section where the voltage of the sweep line SWL decreases linearly.

[0117] In the case where the voltage of the sweep line SWL increases or decreases linearly, the voltage of the first node N1 may change identically (or similarly) to the voltage of the sweep line SWL. The voltage change at the first node N1 may be due to the coupling effect described above.

[0118] refer to Figure 5 , the third period PR3 may include a section in which the voltage level of the second node N2 is at a high level and a section in which the voltage level of the second node N2 is at a low level. One of the section in which the voltage level of the second node N2 is at a high level and the section in which the voltage level of the second node N2 is at a low level may be the emission period LP, and the other may be the non-emission period NLP.

[0119] In the pixel driving circuit PDC (see, for example, Figure 3) in the case where the transistor receiving the second emission control signal EM2 is a p-type transistor, a section in which the voltage level of the second node N2 is at a high level may be a non-emission period NLP, and a section in which the voltage level of the second node N2 is at a low level may be an emission period LP.

[0120] In the pixel driving circuit PDC (see, for example, Figure 3 ) in the case where the transistor receiving the second emission control signal EM2 is an n-type transistor, a section in which the voltage level of the second node N2 is at a high level may be an emission period LP, and a section in which the voltage level of the second node N2 is at a low level may be a non-emission period NLP.

[0121] Hereinafter, explanation will be made based on that a section in which the voltage level of the second node N2 is at a high level is the non-emission period NLP and a section in which the voltage level of the second node N2 is at a low level is the emission period LP. However, the present disclosure is not limited thereto.

[0122] The timing at which the voltage level of the first node N1 in the third period PR3 becomes higher than the threshold voltage Vth of the second transistor TR2 may vary according to the level of the data voltage Vdata[k]. Therefore, the timing at which the second power supply voltage VINIT is applied to the second node N2 may vary.

[0123] As described above, the pulse width control circuit PWMC (see, for example, Figure 4 ) can generate a second emission control signal EM2. The pulse width control circuit PWMC can adjust the pulse width of the second emission control signal EM2.

[0124] Figure 6 is a diagram showing an embodiment of adjusting the length of the non-emission period NLP1 or NLP2 according to the level of the data voltage Vdata1 or Vdata2. Two levels of data voltages Vdata1 and Vdata2 will be described.

[0125] In case 1, in the second period PR2, the high-level data voltage Vdata1 may be input to the first node N1. The voltage of the first node N1 may increase in the third period PR3, and at a point in time, the voltage of the first node N1 may become greater than the threshold voltage Vth of the second transistor TR2. The period from the start of the third period PR3 to the point where the voltage of the first node N1 reaches the threshold voltage Vth of the second transistor TR2 may be referred to as a first non-emission period NLP1.

[0126] In case 2, in the second period PR2, the low level data voltage Vdata2 may be input to the first node N1. The voltage of the first node N1 may increase in the third period PR3, and at a point in time, the voltage of the first node N1 may become greater than the threshold voltage Vth of the second transistor TR2. The period from the start of the third period PR3 to the point where the voltage of the first node N1 reaches the threshold voltage Vth of the second transistor TR2 may be referred to as a second non-emission period NLP2.

[0127] refer to Figure 6 , the first non-emission period NLP1 may be shorter than the second non-emission period NLP2. For example, in case 1, because the emission period is longer, an image with a higher grayscale level may be displayed. In case 2, because the emission period is shorter, an image with a lower grayscale level may be displayed.

[0128] According to an embodiment of the present disclosure, images of different gray levels may be displayed according to the levels of data voltages.

[0129] Figure 7 is a schematic diagram showing the relationship between the pulse width of the second emission control signal EM2 and the length of the emission period LP1 or LP2 according to an embodiment of the present disclosure.

[0130] In case 1, the length of the non-emission period NLP1 may be relatively short, and the length of the emission period LP1 may be relatively long. Therefore, in case 1, an image of a higher grayscale level may be displayed.

[0131] In case 2, the length of the non-emission period NLP2 may be relatively long, and the length of the emission period LP2 may be relatively short. Therefore, in case 2, an image of a lower grayscale level may be displayed.

[0132] refer to Figure 7 , the first period PR1 and the second period PR2 may be periods in which the first emission control signal EM1 has an off-level voltage (e.g., a high-level gate voltage VGH), and the third period PR3 may be a period in which the first emission control signal EM1 has an on-level voltage (e.g., a low-level gate voltage VGL). The first emission control signal EM1 may be input to the pixel driving circuit PDC (e.g., see Figure 3 ) signal, which will refer to Figure 8 and Fig. 9 Detailed description.

[0133] The time point at which the third period PR3 starts and the time point TM1 at which the first emission control signal EM1 of the on-level is input may be the same. However, a margin period (e.g., a predetermined or selectable margin period) may be provided between the two time points (e.g., the time point at which the third period PR3 starts and the time point TM1). The time point at which the third period PR3 ends and the time point TM2 at which the first emission control signal EM1 of the off-level is input may be the same. However, a margin period (e.g., a predetermined or selectable margin period) may be provided between the two time points (e.g., the time point at which the third period PR3 ends and the time point TM2).

[0134] Figure 8 is an equivalent schematic diagram showing a pixel driving circuit PDC according to an embodiment of the present disclosure.

[0135] The pixel driving circuit PDC according to an embodiment of the present disclosure may be electrically connected to the light emitting element LE. The pixel driving circuit PDC may include a transistor electrically connected to the second node N2. The pixel driving circuit PDC may include one or more capacitors.

[0136] Figure 8 It is shown that the pixel driving circuit PDC includes fourth to tenth transistors TR4 to TR10 and a storage capacitor Cstg. However, the present disclosure is not limited thereto.

[0137] The light emitting element LE may include a first electrode electrically connected to the sixth node N6 and a second electrode electrically connected to the third power line PL3 to which the third power voltage ELVSS is applied. The first electrode of the light emitting element LE may be one of an anode electrode and a cathode electrode, and the second electrode may be the other of the anode electrode and the cathode electrode.

[0138] In the embodiment of the present disclosure, the length of the period during which the driving current flows through the light emitting element LE can be adjusted. The magnitude of the driving current flowing through the light emitting element LE can be constant, and the ... Figure 1 ) is independent of the grayscale of the image displayed.

[0139] The light emitting element LE may be an organic light emitting element including an organic light emitting layer. In another embodiment, the light emitting element LE may be an inorganic light emitting element including an inorganic material. In another embodiment, the light emitting element LE may be a light emitting element composed of a combination of an inorganic material and an organic material. In another embodiment, the light emitting element LE may have a form in which a plurality of inorganic light emitting elements are connected in parallel and / or in series between the third power line PL3 and the sixth node N6.

[0140] The fourth transistor TR4 may switch the electrical connection between the fourth node N4 and the fifth node N5. The gate electrode of the fourth transistor TR4 may be electrically connected to the third node N3. One of the source electrode and the drain electrode of the fourth transistor TR4 may be electrically connected to the fourth node N4. The other of the source electrode and the drain electrode of the fourth transistor TR4 may be electrically connected to the fifth node N5. The fourth transistor TR4 may be used as a driving transistor for providing a driving current to the light emitting element LE.

[0141] The fifth transistor TR5 may switch electrical connection between the fourth power line PL4 and the fourth node N4. A gate electrode of the fifth transistor TR5 may be electrically connected to the third scan line GWL. An operation timing of the fifth transistor TR5 may be controlled by the third scan signal GW.

[0142] The fourth power voltage DATA_PAM may be applied to the fourth power line PL4. The fourth power voltage DATA_PAM and the data voltage DATA_PWM or Vdata (eg, see Figure 4 ) may be different in that the fourth power voltage DATA_PAM may be commonly input to the plurality of pixels PXL.

[0143] The sixth transistor TR6 may switch the electrical connection between the third node N3 and the fifth node N5. The gate electrode of the sixth transistor TR6 may be electrically connected to the third scan line GWL. The operation timing of the sixth transistor TR6 may be controlled by the third scan signal GW. During the period in which the sixth transistor TR6 is turned on, the fourth transistor TR4 may be connected in a diode form.

[0144] The seventh transistor TR7 can switch the electrical connection between the second power line PL2 and the third node N3. The gate electrode of the seventh transistor TR7 can be electrically connected to the fourth scan line GIL. The operation timing of the seventh transistor TR7 can be controlled by the fourth scan signal GI. During the period when the seventh transistor TR7 is turned on, the voltage of the third node N3 can be initialized with the second power voltage VINIT.

[0145] The eighth transistor TR8 may switch the electrical connection between the first power line PL1 and the fourth node N4. A gate electrode of the eighth transistor TR8 may be electrically connected to the second node N2. In the present disclosure, the eighth transistor TR8 may be referred to as a first emission control transistor.

[0146] refer to Figure 8 , although the eighth transistor TR8 is illustrated as a p-type transistor, the present disclosure is not limited thereto, and the eighth transistor TR8 may be implemented as an n-type transistor.

[0147] The ninth transistor TR9 may switch the electrical connection between the fifth node N5 and the sixth node N6. The gate electrode of the ninth transistor TR9 may be electrically connected to the first emission control line EML. The operation timing of the ninth transistor TR9 may be controlled by the first emission control signal EM1. During at least a portion of the period in which the ninth transistor TR9 is turned on, the fourth transistor TR4 may be electrically connected to the light emitting element LE.

[0148] The tenth transistor TR10 may switch the electrical connection between the sixth node N6 and the fifth power line PL5. The gate electrode of the tenth transistor TR10 may be electrically connected to the fifth scan line GBL. The operation timing of the tenth transistor TR10 may be controlled by the fifth scan signal GB. During the period in which the tenth transistor TR10 is turned on, the voltage of the sixth node N6 may be initialized with the fifth power supply voltage VAINIT.

[0149] The storage capacitor Cstg may include one electrode electrically connected to the third node N3 and another electrode electrically connected to the first power line PL1. The storage capacitor Cstg may apply a voltage corresponding to the fourth power voltage DATA_PAM to the third node N3 in one frame.

[0150] Figure 8 It is shown that only the fourth transistor TR4 is an n-type transistor and the fifth transistor TR5 to the tenth transistor TR10 are p-type transistors. However, the present disclosure is not limited thereto. In another embodiment, the fourth transistor TR4 may be implemented as a p-type transistor, and one or more of the fifth transistor TR5 to the tenth transistor TR10 may be implemented as an n-type transistor.

[0151] refer to Figure 8 The emission control signal EM may include a first emission control signal EM1 and a second emission control signal EM2. In an embodiment of the present disclosure, a driving current may be provided to the light emitting element LE during at least a portion of a period in which both the first emission control signal EM1 and the second emission control signal EM2 are at an on level.

[0152] Figure 8 It is shown that the second emission control signal EM2 is input to the gate electrode of the eighth transistor TR8 , and the first emission control signal EM1 is input to the gate electrode of the ninth transistor TR9 .

[0153] However, the present disclosure is not limited thereto, and the second emission control signal EM2 may be input to the gate electrode of the ninth transistor TR9 , and the first emission control signal EM1 may be input to the gate electrode of the eighth transistor TR8 .

[0154] Therefore, when the pulse width of the second emission control signal EM2 is controlled, the period of supplying the driving current to the light emitting element LE can be controlled.

[0155] Fig. 9 FIG. 1 is a diagram showing an input to a pixel driving circuit PDC (eg, see FIG. 1 ) according to an embodiment of the present disclosure. Figure 8 ) signal and the voltage of the sweep line SWL.

[0156] refer to Fig. 9 , the frame period may further include a fourth period PR4, a fifth period PR5, and a sixth period PR6 between the first period PR1 and the third period PR3.

[0157] In the first period PR1, the second emission control signal EM2 of a high level voltage may be input. The high level voltage of the second emission control signal EM2 may be a cut-off level voltage.

[0158] In the fourth period PR4, the fourth scan signal GI of the turn-on level may be input. The second power supply voltage VINIT may be applied to the third node N3.

[0159] In the fifth period PR5, the third scanning signal GW of the on level may be input. Figure 8 As described, the fifth transistor TR5 and the sixth transistor TR6 may be turned on. Corresponding to the fourth power supply voltage DATA_PAM (eg, see Figure 8 ) may be input to the third node N3. The second voltage V2 may be an on-level voltage.

[0160] In the sixth period PR6, the fifth scanning signal GB of the on level may be input. Figure 8 As described, the tenth transistor TR10 may be turned on and the voltage of the sixth node N6 may be initialized with the fifth power supply voltage VAINIT.

[0161] The second period PR2 (see, for example, Figure 5 , Figure 6 and Figure 7 ) may overlap with one of the fourth period PR4, the fifth period PR5, and the sixth period PR6. However, the present disclosure is not limited thereto, and the second period PR2 may not overlap with the fourth period PR4, the fifth period PR5, and the sixth period PR6. The second period PR2 may exist between the first period PR1 and the fourth period PR4, between the fourth period PR4 and the fifth period PR5, between the fifth period PR5 and the sixth period PR6, or between the sixth period PR6 and the third period PR3.

[0162] In the third period PR3, the first emission control signal EM1 of the on level may be input. Figure 8 As described, the ninth transistor TR9 may be turned on.

[0163] refer to Fig. 9 , the time point at which the voltage of the sweep line SWL starts to increase linearly and the time point at which the first emission control signal EM1 of the conduction level is input may be the same, but a margin period (e.g., a predetermined or selectable margin period) may be provided between the two time points (e.g., the time point at which the voltage of the sweep line SWL starts to increase linearly and the time point at which the first emission control signal EM1 of the conduction level is input). Fig. 9 , the time point when the voltage of the sweep line SWL drops and the time point when the first emission control signal EM1 of the cut-off level is input may be the same, but a margin period (e.g., a predetermined or selectable margin period) may be provided between the two time points (e.g., the time point when the voltage of the sweep line SWL drops and the time point when the first emission control signal EM1 of the cut-off level is input).

[0164] During the third period PR3, the second emission control signal EM2 of the on level may be input. Figure 8 As described above, when the second emission control signal EM2 of the on level is input, the eighth transistor TR8 may be turned on. When the second emission control signal EM2 of the on level is input, the driving current may be provided to the light emitting element LE (eg, see Figure 8 ).

[0165] To sum up, the content is as follows.

[0166] According to an embodiment of the present disclosure, the period of light emission of the light emitting element LE can be controlled by controlling the pulse width of the second emission control signal EM2. Therefore, the corresponding pixel PXL can display images of various gray levels from low gray level to high gray level.

[0167] According to an embodiment of the present disclosure, images of various grayscale levels can be displayed without controlling the size of the driving current. Therefore, it may be unnecessary to control the size of the driving current within a fine range. According to an embodiment of the present disclosure, a pixel PXL, a method for driving the pixel PXL, and a display device 100 including the pixel PXL can be provided, which can alleviate the phenomenon that the color coordinates are distorted due to changes in the characteristics (e.g., threshold voltage, mobility, etc.) of transistors located on the path where the driving current flows (e.g., driving transistors of the pixel driving circuit PDC, etc.).

[0168] According to an embodiment of the present disclosure, a pixel PXL that displays images of various gray levels by controlling a period in which a light emitting element LE emits light, a method of driving the pixel PXL, and a display device 100 including the pixel PXL may be provided.

[0169] The above description is an example of the technical features of the present disclosure, and those skilled in the art to which the present disclosure belongs will be able to make various modifications and changes.Therefore, the embodiments of the present disclosure described above can be implemented individually or in combination with each other.

[0170] Therefore, the embodiments disclosed in the present disclosure are not intended to limit the technical spirit of the present disclosure, but to describe the technical spirit of the present disclosure, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. The protection scope of the present disclosure should be interpreted by the attached claims, and it should be understood that all technical spirits within the equivalent scope are included in the scope of the present disclosure.

Claims

1. Pixel, characterized in that The pixels include: Light emitting element; a pulse width control circuit electrically connected to the data line to which the data voltage is applied, generating an emission control signal having a pulse width according to the data voltage, and outputting the emission control signal; and a pixel driving circuit that receives the emission control signal and provides a driving current to the light emitting element within a period according to the pulse width of the emission control signal, wherein the driving current flowing through the light emitting element flows from a first power line to which a first power supply voltage is applied to the light emitting element via the pixel driving circuit, and The high-level voltage of the emission control signal is a voltage applied from the first power line to the pixel driving circuit via the pulse width control circuit.

2. The pixel according to claim 1, characterized in that The pulse width control circuit comprises: a first capacitor including a first electrode to which the data voltage is applied and a second electrode to which a triangular wave is applied; and The first switching element switches the electrical connection between the first electrode of the first capacitor and the data line.

3. The pixel according to claim 2, characterized in that The pulse width control circuit further includes: a second switching element including a gate electrode, a source electrode, and a drain electrode, the gate electrode being electrically connected to the first electrode of the first capacitor; and a third switching element for switching electrical connection between the first power supply line to which the first power supply voltage is applied and the second switching element, the gate electrode of the second switching element is electrically connected to the first electrode of the first capacitor and the first switching element at a first node, One of the source electrode and the drain electrode of the second switching element is electrically connected to the first power line, and The other of the source electrode and the drain electrode of the second switching element is electrically connected to a second power supply line to which a second power supply voltage is applied.

4. The pixel according to claim 3, characterized in that The second switching element and the third switching element are electrically connected at a second node, and The emission control signal is output through the second node, and The pulse width control circuit further includes a second capacitor, and the second capacitor includes an electrode electrically connected to the second node.

5. The pixel according to claim 1, characterized in that The light emitting element is electrically connected to a third power line, The pixel driving circuit comprises: a first emission control switching element including a gate electrode to which the emission control signal is input and switches an electrical connection between a first power line to which the first power voltage is applied and a fourth node; a fourth switching element including a gate electrode, a source electrode, and a drain electrode electrically connected to the third node; a fifth switching element for switching the electrical connection between the fourth node and a fourth power line, a second emission control switch element, switching the electrical connection between the fifth node and the light emitting element; a storage capacitor including one electrode electrically connected to the third node and another electrode electrically connected to the first power line; and a first initialization switching element that switches electrical connection between the third node and a second power line to which a second power voltage is applied, One of the source electrode and the drain electrode of the fourth switching element is electrically connected to the fourth node, The other of the source electrode and the drain electrode of the fourth switching element is electrically connected to the fifth node, and The gate electrode of the first emission control switching element is electrically connected to the second power supply line through the pulse width control circuit.

6. A display device, characterized in that The display device comprises: A display panel having a plurality of pixels including light emitting elements and a plurality of data lines electrically connected to the plurality of pixels disposed thereon; and a data driving circuit for providing data voltages to the plurality of data lines; wherein each of the plurality of pixels emits light in a period according to the data voltage, Wherein, at least one of the plurality of pixels further comprises: a pulse width control circuit electrically connected to one of the plurality of data lines to which the data voltage is applied, generating an emission control signal having a pulse width according to the data voltage, and outputting the emission control signal; and a pixel driving circuit that receives the emission control signal and provides a driving current to the light emitting element within a period according to the pulse width of the emission control signal, wherein the driving current flowing through the light emitting element flows from a first power line to which a first power supply voltage is applied to the light emitting element via the pixel driving circuit, and The high-level voltage of the emission control signal is a voltage applied from the first power line to the pixel driving circuit via the pulse width control circuit.

7. The display device according to claim 6, characterized in that The display device further includes: A timing controller outputs input image data to the data driving circuit, wherein: the input image data comprises grayscale information for each of the plurality of pixels, The data driving circuit outputs the data voltage having a voltage level corresponding to the grayscale information, and Each of the plurality of pixels emits light in a period according to the grayscale information included in the input image data.

8. The display device according to claim 6, characterized in that A plurality of first scan lines are arranged on the display panel, Each of the plurality of first scan lines is electrically connected to pixels located in the same pixel row among the plurality of pixels, and According to the data voltage, the pixels in the same pixel row among the plurality of pixels have different light-emitting start times or different light-emitting end times.

9. The display device according to claim 6, characterized in that The display device further includes: A triangular wave output circuit outputs a first voltage or a triangular wave linearly increasing from the first voltage, wherein: At least one sweep line to which the triangular wave is applied is arranged on the display panel, The at least one scanning line is electrically connected to the plurality of pixels, A period during which the data voltage is input to the plurality of pixels electrically connected to the at least one scanning line overlaps a period during which the triangular wave output circuit outputs the first voltage, and A period during which the plurality of pixels electrically connected to the at least one scanning line emit light overlaps a period during which the triangular wave output circuit outputs the triangular wave.

Images