Display device

Abstract

An embodiment of the utility model discloses a display device. The display device comprises a substrate, a first substrate, a second substrate and a bending substrate, wherein the substrate comprises a first area with a display area, a second area and a bending area between the first area and the second area; the display element is configured in the display area; a first wiring extending so as to surround at least a part of the display area; a first inspection pad, a second inspection pad, and a third inspection pad disposed in the second region; a first inspection wiring electrically connected to the first wiring in the second region and electrically connected to the first inspection pad; a second inspection wiring extending to pass through the bending region, and electrically connected with the first wiring in the first region, and electrically connected with the second inspection pad; and a third inspection wiring spaced apart from the first inspection wiring, electrically connected with the first wiring in the second region, and electrically connected with the third inspection pad.

Description

Technical Field

[0001] An embodiment of the utility model relates to a display device. Background Art

[0002] A display device is a device that visually displays data and is used for displays of small products such as mobile phones, and also for displays of large products such as televisions.

[0003] Such a display device includes a substrate divided into a display area and a non-display area, and the gate lines and data lines in the display area are insulated from each other. A plurality of sub-pixel regions are defined in the display area, and the sub-pixels respectively arranged in the plurality of sub-pixel regions receive electrical signals from the gate lines and data lines that intersect each other to emit light in order to display images to the outside. A thin film transistor and a sub-pixel electrode electrically connected to the thin film transistor are provided in each sub-pixel region (each sub-pixel region or each of sub-pixel regions), and a counter electrode is commonly provided in the sub-pixel region. The non-display area may be provided with various wirings for transmitting electrical signals to the sub-pixels in the display area, a gate driving unit, and pads capable of connecting the data driving unit and the control unit, etc.

[0004] Recently, the uses of display devices are becoming more diverse. In addition, as the thickness of display devices becomes thinner and the weight becomes lighter, the scope of their use tends to become wider. In particular, when the display device is moved or handled, cracks may be easily generated due to external forces. Moisture or oxygen flowing in from the outside through the cracks may reach the organic light-emitting diodes in the display device. In such a case, the organic light-emitting diodes may be easily oxidized, which may result in reduced reliability. Therefore, the importance of research on predicting and detecting whether cracks in display devices are generated is increasing, and related research is being actively carried out. Utility Model Content

[0005] The embodiments of the present invention provide a display device capable of detecting cracks in a non-driven state as a means of solving various problems. However, such a subject is exemplary and the scope of the present invention is not limited thereto.

[0006] In one aspect of the present invention, a display device is disclosed, comprising: a substrate comprising a first area having a display area, a second area, and a curved area between the first area and the second area; a display element arranged in the display area; a first wiring extending in a manner surrounding at least a portion of the display area; a first inspection pad, a second inspection pad, and a third inspection pad arranged in the second area; a first inspection wiring electrically connected to the first wiring in the second area and to the first inspection pad; a second inspection wiring extending in a manner passing through the curved area and electrically connected to the first wiring in the first area and to the second inspection pad; and a third inspection wiring separated from the first inspection wiring, electrically connected to the first wiring in the second area, and electrically connected to the third inspection pad.

[0007] In one embodiment, the substrate may be bent in the bent region so that a back surface of the second region faces at least a portion of a back surface of the first region.

[0008] In one embodiment, the display device may further include: a fourth inspection pad, arranged in the second area; and a fourth inspection wiring, extending through the bending area and electrically connected to the first wiring in the first area and to the fourth inspection pad.

[0009] In one embodiment, the first inspection wiring and the second inspection wiring may be arranged on one side of the substrate, and the third inspection wiring and the fourth inspection wiring may be arranged on the other side of the substrate opposite to the one side of the substrate.

[0010] In one embodiment, the first wiring may be integrated with the first inspection wiring, the second inspection wiring, and the third inspection wiring.

[0011] In one embodiment, the substrate may include a through hole defined in the first area, and the display device may further include: a through hole detection wiring electrically connected to the first wiring and arranged adjacent to the through hole; and a second wiring electrically connected to the through hole detection wiring and extending in a manner surrounding at least a portion of the display area.

[0012] In one embodiment, the through-hole detection wiring may have a shape doubly surrounding the through-hole.

[0013] In one embodiment, the first wiring may be arranged outside the second wiring.

[0014] In one embodiment, the first wiring may include: a 1-1 wiring extending along one side edge of the substrate; and a 1-2 wiring extending along the other side edge of the substrate, and the second wiring may include: a 2-1 wiring extending along one side edge of the substrate; and a 2-2 wiring extending along the other side edge of the substrate.

[0015] In one embodiment, the display device may further include: a first pad disposed in the second region; a first voltage line electrically connected to the first pad; and a second voltage line electrically connected to the 2-1 wiring.

[0016] In one embodiment, the 1-1th wiring may be electrically connected to the first pad.

[0017] In one embodiment, the display device may further include: a first data line and a second data line, which are arranged in the display area and extend along the first direction respectively; a first transistor, which is connected between the first voltage line and the first data line; and a second transistor, which is connected between the second voltage line and the second data line.

[0018] In one embodiment, the first transistor and the second transistor may be controlled simultaneously.

[0019] In one embodiment, the display device may further include: a second pad disposed in the second region; a third voltage line electrically connected to the second pad; and a fourth voltage line electrically connected to the 2-2 wiring.

[0020] In one embodiment, the 2-1st wiring may be electrically connected to the second pad.

[0021] In one embodiment, the display device may further include: a third data line and a fourth data line, which are arranged in the display area and extend respectively along the first direction; a third transistor, which is connected between the third voltage line and the third data line; and a fourth transistor, which is connected between the fourth voltage line and the fourth data line.

[0022] In one embodiment, the third transistor and the fourth transistor may be controlled simultaneously.

[0023] In one embodiment, the display device may further include: a fourth inspection pad, arranged in the second area; and a fourth inspection wiring, extending through the bending area and electrically connected to the first wiring in the first area and to the fourth inspection pad.

[0024] In one embodiment, the first inspection wiring and the second inspection wiring may be electrically connected to the 1-1 wiring, and the third inspection wiring and the fourth inspection wiring may be electrically connected to the 1-2 wiring.

[0025] In one embodiment, the first inspection wiring and the second inspection wiring may be arranged on one side of the substrate, and the third inspection wiring and the fourth inspection wiring may be arranged on the other side of the substrate opposite to the one side of the substrate.

[0026] As described above, according to an embodiment of the present invention, a display device capable of detecting cracks in a non-driven state and detecting cracks in a process unit during the manufacturing process can be realized. Of course, the scope of the present invention is not limited by such effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 FIG. 1 is a plan view schematically showing a display device according to an embodiment of the present invention.

[0028] Figure 2 FIG. 1 is a side view schematically showing a display device according to an embodiment of the present invention.

[0029] Figure 3 FIG. 1 is a schematic diagram showing an equivalent circuit of a sub-pixel according to an embodiment of the present invention.

[0030] Figure 4 is a cross-sectional view schematically showing a portion of a display device according to an embodiment of the present invention.

[0031] Figure 5 FIG. 1 is a plan view schematically showing a display device according to another embodiment of the present invention.

[0032] Figure 6 FIG. 4 is a side view schematically showing a display device according to another embodiment of the present invention.

[0033] Figure 7 It is a schematic diagram Figure 5 An enlarged plan view of portion D of the display device.

[0034] Figure 8 It is enlarged to show Figure 5 A plan view of a detection circuit of a display device.

[0035] (Explanation of Reference Numerals)

[0036] 1: Display device

[0037] 10: Display Panel

[0038] DA: Display Area

[0039] PA: Surrounding area

[0040] MR: Main Region

[0041] BR: Bending Region

[0042] SR: Sub-region

[0043] 100: Substrate

[0044] 1100: Through hole

[0045] 500: First wiring

[0046] 600: Detection wiring

[0047] 610: First peripheral detection wiring

[0048] 620: Second peripheral detection wiring

[0049] 630: Through hole detection wiring

[0050] P1, P1': first pad

[0051] P2, P2': Second pad

[0052] TP1, TP2, TP3, TP4: First to fourth inspection pads

[0053] TL1, TL2, TL3, TL4: First to fourth inspection wiring DETAILED DESCRIPTION

[0054] The present invention can be modified in various ways and can have various embodiments, and specific embodiments are illustrated in the drawings and described in detail herein. Figure 1 The effects and features of the present invention and methods for achieving them will become clear from the embodiments described in detail below. However, the present invention is not limited to the embodiments disclosed below, and can be implemented in various forms.

[0055] In the following embodiments, the terms such as first and second are used for the purpose of distinguishing one constituent element from other constituent elements, and are not used in a limiting sense.

[0056] In the following embodiments, a singular expression includes a plural expression unless it is clearly indicated to be different in the context.

[0057] In the following embodiments, terms such as including or having refer to the existence of features or constituent elements recorded in the specification, and do not preclude the possibility of the addition of one or more other features or constituent elements.

[0058] In the following embodiments, when a film, region, constituent element, etc. is expressed as being on or above another part, it includes not only the case where it is directly on the other part, but also the case where other films, regions, constituent elements, etc. are interposed therebetween.

[0059] In this specification, "A and / or B" means A, or B, or A and B. In addition, in this specification, "at least one of A and B" means A, or B, or A and B.

[0060] In the following embodiments, the wiring "extending in the first direction or the second direction" means not only extending in a straight line shape but also extending in a zigzag shape or a curved line along the first direction or the second direction.

[0061] In the following embodiments, when it is expressed as "on a plane", it means the situation when the object part is viewed from above, and when it is expressed as "on a cross section", it means the situation when a cross section of the object part is vertically cut from the side. In the following embodiments, when it is expressed as "overlapping", it includes overlapping "on a plane" and "on a cross section".

[0062] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, the same or corresponding components are marked with the same reference numerals.

[0063] Figure 1 is a plan view schematically showing a display device according to an embodiment of the present invention, Figure 2 FIG. 1 is a side view schematically showing a display device according to an embodiment of the present invention. A portion of the display device according to this embodiment is bent, but Figure 1 For convenience, it is shown without bending.

[0064] Reference Figure 1 The display device 1 includes a display panel 10. Any display device 1 may be used as long as it includes the display panel 10. For example, the display device 1 may be a smart phone, a tablet, a notebook computer, a television, or a billboard.

[0065] The display panel 10 includes a display area DA and a peripheral area PA outside the display area DA. Figure 1 As shown, the peripheral area PA may be configured to surround the display area DA. Of course, since the display panel 10 includes the substrate 100, it can also be said that the substrate 100 has such a display area DA and the peripheral area PA.

[0066] In addition, the display panel 10 may include a main region MR, a curved region BR outside the main region MR, and a sub-region SR located on the opposite side of the main region MR with the curved region BR as the center. The main region MR may include a display area DA. The sub-region SR may correspond to one side of the peripheral area PA. In one embodiment, the main region MR may be a first region and the sub-region SR may be a second region.

[0067] The edge of the display area DA may have a shape similar to a rectangle or a square as a whole. The display area DA may include a first edge E1 and a second edge E2 facing each other and a third edge E3 and a fourth edge E4 located between the first edge E1 and the second edge E2 facing each other. The bending area BR and the sub-area SR may be adjacent to the second edge E2 of the display area DA.

[0068] like Figure 2 As shown, in the curved region BR, the substrate 100 and the display panel 10 may be curved. When the curved display panel 10 is observed in the z direction, at least a portion of the sub-region SR may overlap with the main region MR. The bending allows the back side of the sub-region SR to face at least a portion of the back side of the main region MR. However, the present invention is not limited to a curved display device 1, but may also be applicable to a non-curved display device 1. The sub-region SR may be a non-display region. The display panel 10 is curved in the curved region BR, so that when the display device 1 is observed from the front (in the -z direction), the non-display region is not recognized, or even if it is recognized, its recognized area may be minimized.

[0069] A driving chip 20 may be disposed in the sub-region SR of the display panel 10. The driving chip 20 may include an integrated circuit for driving the display panel 10. Such an integrated circuit may be a data driving integrated circuit for generating a data signal, but the present invention is not limited thereto.

[0070] The driving chip 20 may be mounted on the sub-region SR of the display panel 10. The driving chip 20 is mounted on the same surface as the display surface of the display area DA, and as described above, as the display panel 10 is bent in the bending region BR, the driving chip 20 may be located on the back of the main region MR.

[0071] A printed circuit substrate 30 or the like may be attached to the end of the sub-region SR of the display panel 10 . Such a printed circuit substrate 30 or the like may be electrically connected to the driving chip 20 or the like through the pads on the substrate 100 . Figure 1 Although the driving chip 20 is shown to be disposed on the sub-region SR, as another example, the driving chip 20 may be disposed on the printed circuit board 30 .

[0072] The display panel 10 may include a plurality of sub-pixels PX disposed in the display area DA, and the plurality of sub-pixels PX may include display elements respectively. The utility model uses an organic light emitting diode as an example of a display element. The organic light emitting diode of each sub-pixel PX may emit, for example, red, green, cyan, or white light.

[0073] The sub-pixel circuits driving the plurality of sub-pixels PX may be connected to signal lines or voltage lines for controlling display elements. Figure 1 The gate lines GL extending in a first direction (eg, ±x direction) and the data lines DL extending in a second direction (eg, ±y direction) are shown as signal lines, and the driving voltage lines PL are shown as voltage lines.

[0074] Each sub-pixel PX may be electrically connected to a peripheral circuit disposed in the peripheral area PA. For example, a driving voltage supply wiring 160, a common voltage supply wiring 170, a gate driving circuit GDC, and a pad portion PAD may be disposed in the peripheral area PA.

[0075] The driving voltage supply wiring 160 may include a first sub-wiring 161 and a second sub-wiring 162 extending in parallel along a first direction (e.g., ±x direction) across the display area DA, and a third sub-wiring 163 extending from the second sub-wiring 162 along a second direction (e.g., -y direction), and supply a driving voltage (e.g., ELVDD). The driving voltage may be provided to the sub-pixel circuit of each sub-pixel PX through a driving voltage line PL connected to the driving voltage supply wiring 160. A common voltage supply wiring 170 partially surrounding the display area DA may be configured on the peripheral area PA. For example, the common voltage supply wiring 170 may have a loop shape open to the pad portion PAD side. A common voltage (e.g., ELVSS) may be transmitted in the common voltage supply wiring 170, and the common voltage may be provided to the counter electrode of each sub-pixel PX connected to the common voltage supply wiring 170.

[0076] The gate drive circuit GDC may be connected to a gate line GL extending in a first direction (e.g., ±x direction). The gate lines GL are respectively connected to sub-pixels PX located in the same row, and transmit electrical signals in sequence. The gate drive circuit GDC may include a scan drive circuit and a light emitting control drive circuit. The scan drive circuit included in the gate drive circuit GDC may provide a scan signal to each sub-pixel PX through a scan signal line. In addition, the light emitting control drive circuit included in the gate drive circuit GDC may provide a light emitting control signal to each sub-pixel PX through a light emitting control line.

[0077] Figure 1The gate driving circuit GDC is shown to be arranged on the left side of the display panel 10. As another example, the gate driving circuit GDC may be arranged on the right side of the display panel 10. As yet another example, there may be multiple gate driving circuits GDC. Multiple gate driving circuits GDC may be arranged on the left and right sides of the display panel 10 across the display area DA.

[0078] The pad portion PAD may be disposed on one side (eg, the lower side or the lower end) of the peripheral area PA. Figure 1 As shown, the pad portion PAD may be disposed at an end portion of the sub-region SR of the display panel 10 .

[0079] The pad portion PAD may be electrically attached to various electronic components or a printed circuit substrate 30, etc. The pad portion PAD may be uncovered and exposed by the insulating layer, thereby being electrically connected to the printed circuit substrate 30. The terminal portion 30P of the printed circuit substrate 30 may be electrically connected to the pad portion PAD of the display panel 10. The printed circuit substrate 30 may be directly combined with the display panel 10, or connected to the display panel 10 through another circuit substrate.

[0080] The pad portion PAD may include a data pad DP, a voltage supply pad PP, a first pad P1, a second pad P2, a first inspection pad TP1, a second inspection pad TP2, a third inspection pad TP3, and a fourth inspection pad TP4. The data pad DP, the voltage supply pad PP, the first pad P1, the second pad P2, and the first to fourth inspection pads TP1, TP2, TP3, TP4 may be spaced apart from each other and arranged along a first direction (e.g., ±x direction).

[0081] The data pad DP may be connected to a data line DL extending in a second direction (e.g., ±y direction). The data line DL may be connected to the sub-pixels PX located in the same column and transmit electrical signals in sequence. The data line DL may be connected to the driver chip 20. In one embodiment, the data line DL may be electrically connected to the data pad DP via the driver chip 20. As described above, the driver chip 20 may include a data driver integrated circuit that generates a data signal, and the driver chip 20 may provide the data signal to each sub-pixel PX via the data line DL.

[0082] The voltage supply pad PP may be electrically connected to the driving voltage supply wiring 160 and / or the common voltage supply wiring 170. The voltage supply pad PP may supply a driving voltage received from the outside to the driving voltage supply wiring 160. The voltage supply pad PP may supply a common voltage received from the outside to the common voltage supply wiring 170. The number and arrangement of the data pads DP and the voltage supply pad PP are not limited to Figure 1 shown.

[0083] On the other hand, in the peripheral area PA, the first wiring 500 , the first inspection wiring TL1 , the second inspection wiring TL2 , the third inspection wiring TL3 , and the fourth inspection wiring TL4 may be arranged.

[0084] The first wiring 500 is disposed in the peripheral area PA and extends to surround at least a portion of the display area DA. For example, the first wiring 500 may extend along the first edge E1, the third edge E3, and the fourth edge E4 of the display area DA. Both ends of the first wiring 500 surrounding at least a portion of the display area DA may extend to pass through the bending area BR in a direction toward the pad portion PAD.

[0085] In one embodiment, if Figure 1 As shown, the first wiring 500 can be electrically connected to the pad portion PAD. The first pad P1 and the second pad P2 can be electrically connected to the first wiring 500. It can be that the first pad P1 is configured on one side (for example, the left side) of the pad portion PAD, and the second pad P2 is configured on the other side (for example, the right side) of the pad portion PAD. However, the utility model is not limited to this. In another embodiment, both ends of the first wiring 500 can be electrically connected to a drive circuit or a drive chip 20, etc.

[0086] In one embodiment, the first wiring 500 may be a wiring that functions in the driving state of the display device 1. For example, the first wiring 500 may be a guard ring wiring provided in the touch sensor layer 400 described later. The guard ring wiring may prevent the touch sensor layer 400 from malfunctioning or the internal circuit from being damaged by an electrostatic force applied from the outside. At this time, the first pad P1 and the second pad P2 electrically connected to the first wiring 500 may be connected to a ground power supply. Alternatively, the first wiring 500 may be a wiring for detecting cracks of the display panel 10 in the driving state of the display device 1. At this time, the first wiring 500 may be electrically connected to a crack detection circuit that operates in the driving state of the display device 1.

[0087] The first to fourth inspection pads TP1, TP2, TP3, TP4 can be electrically connected to the first inspection wiring TL1, the second inspection wiring TL2, the third inspection wiring TL3, and the fourth inspection wiring TL4, respectively. It can be that the first inspection pad TP1 and the second inspection pad TP2 are arranged on one side (for example, the left side) of the pad portion PAD, and the third inspection pad TP3 and the fourth inspection pad TP4 are arranged on the other side (for example, the right side) of the pad portion PAD. The first to fourth inspection pads TP1, TP2, TP3, TP4 can be electrically connected to the printed circuit substrate 30, and the signal transmitted from the printed circuit substrate 30 is transmitted to the first to fourth inspection wirings TL1, TL2, TL3, TL4. As another embodiment, the first to fourth inspection pads TP1, TP2, TP3, TP4 can be electrically connected to a separate inspection circuit board before attaching the printed circuit substrate 30. The first to fourth inspection pads TP1, TP2, TP3, TP4 can transmit the signal transmitted from the inspection circuit board to the first to fourth inspection wirings TL1, TL2, TL3, TL4. The first to fourth inspection pads TP1, TP2, TP3, and TP4 may be pads for transmitting an inspection signal or measuring loop resistance.

[0088] The first to fourth inspection wirings TL1, TL2, TL3, and TL4 may be electrically connected to the first wiring 500. The first inspection wiring TL1 and the second inspection wiring TL2 may be arranged on one side (e.g., the left side) of the substrate 100, and the third inspection wiring TL3 and the fourth inspection wiring TL4 may be arranged on the other side (e.g., the right side) of the substrate 100 opposite to the one side (e.g., the left side) of the substrate 100.

[0089] The first inspection wiring TL1 may be electrically connected to a portion of one side (e.g., left side) of the first wiring 500 in the sub-region SR (e.g., between the bending region BR and the pad portion PAD). The first inspection wiring TL1 may be electrically connected to the first inspection pad TP1. The first inspection wiring TL1 may electrically connect the first wiring 500 and the first inspection pad TP1.

[0090] The second inspection wiring TL2 may extend toward the display area DA in the pad portion PAD in a manner passing through the bending region BR. The second inspection wiring TL2 may be electrically connected to a portion of one side (e.g., left side) of the first wiring 500 in the main region MR (e.g., between the bending region BR and the display area DA). The second inspection wiring TL2 may be electrically connected to the second inspection pad TP2. The second inspection wiring TL2 may electrically connect the first wiring 500 and the second inspection pad TP2.

[0091] The third inspection wiring TL3 may be electrically connected to the other side (e.g., right side) portion of the first wiring 500 in the sub-region SR (e.g., between the bending region BR and the pad portion PAD). The third inspection wiring TL3 may be electrically connected to the third inspection pad TP3. The third inspection wiring TL3 may electrically connect the first wiring 500 and the third inspection pad TP3.

[0092] The fourth inspection wiring TL4 may extend in the pad portion PAD toward the display area DA in a manner passing through the bending region BR. The fourth inspection wiring TL4 may be electrically connected to the other side (e.g., right side) portion of the first wiring 500 in the main region MR (e.g., between the bending region BR and the display area DA). The fourth inspection wiring TL4 may be electrically connected to the fourth inspection pad TP4. The fourth inspection wiring TL4 may electrically connect the first wiring 500 and the fourth inspection pad TP4.

[0093] In one embodiment, the first inspection wiring TL1, the second inspection wiring TL2, the third inspection wiring TL3, and the fourth inspection wiring TL4 may be configured in the same layer as the first wiring 500 and include the same substance. The first inspection wiring TL1, the second inspection wiring TL2, the third inspection wiring TL3, and the fourth inspection wiring TL4 may be provided as one body with the first wiring 500. However, the present invention is not limited thereto. In another embodiment, at least a portion of the first inspection wiring TL1, the second inspection wiring TL2, the third inspection wiring TL3, and the fourth inspection wiring TL4 may be configured in a different layer from the first wiring 500 and include a different substance.

[0094] In this way, whether cracks occur in the display device 1 can be checked through the first to fourth inspection wirings TL1 , TL2 , TL3 , and TL4 and the first to fourth inspection pads TP1 , TP2 , TP3 , and TP4 connected to the first wiring 500 .

[0095] For example, the first inspection wiring TL1, a portion of the first wiring 500, and the third inspection wiring TL3 are connected to each other to form a first pattern in the form of a loop that surrounds the display area DA and is open on one side. The loop resistance value of the first pattern can be measured by the first inspection pad TP1 and the third inspection pad TP3. When cracks are generated in a portion of the first wiring 500, the first inspection wiring TL1, and the third inspection wiring TL3 that form the first pattern, the resistance value of the first pattern can be measured to be greater than the set resistance value. Whether cracks have occurred in the display device 1 can be confirmed by the change in the resistance value of the first pattern.

[0096] The first inspection wiring TL1, a portion of the first wiring 500, and the second inspection wiring TL2 can be connected to each other to form a second pattern in the form of a loop that passes through the left bending area BR and is open on one side. The loop resistance value of the second pattern can be measured by the first inspection pad TP1 and the second inspection pad TP2. When cracks occur in a portion of the first wiring 500, the first inspection wiring TL1, and the second inspection wiring TL2 that form the second pattern, the resistance value of the second pattern can be measured to be greater than the set resistance value. The bending area BR of the display device 1 can be confirmed by such a change in the resistance value of the second pattern, specifically, to confirm whether a crack occurs in the left bending area BR.

[0097] The third inspection wiring TL3, a portion of the first wiring 500, and the fourth inspection wiring TL4 can be connected to each other to form a third pattern in the form of a loop that passes through the right bending area BR and has one side open. The loop resistance value of the third pattern can be measured by the third inspection pad TP3 and the fourth inspection pad TP4. When cracks occur in a portion of the first wiring 500, the third inspection wiring TL3, and the fourth inspection wiring TL4 that form the third pattern, the resistance value of the third pattern can be measured to be greater than the set resistance value. The bending area BR of the display device 1 can be confirmed by such a change in the resistance value of the third pattern, specifically, to confirm whether cracks occur in the right bending area BR.

[0098] The display device 1 according to an embodiment of the present invention may include a first wiring 500 surrounding the display area DA, first to fourth inspection wirings TL1, TL2, TL3, TL4 connected thereto, and first to fourth inspection pads TP1, TP2, TP3, TP4, so as to confirm whether cracks of the display device 1 are generated in a non-driving state. In particular, whether cracks of the left or right bending area BR of the display device 1 are generated can be confirmed in a non-driving state. In addition, during the manufacturing process of the display device 1, the loop resistance passing through the first to fourth inspection pads TP1, TP2, TP3, TP4 can be measured, so as to confirm whether cracks of the display device 1 are generated using a process unit.

[0099] Figure 3 FIG. 1 is a schematic diagram showing an equivalent circuit of a sub-pixel according to an embodiment of the present invention.

[0100] Reference Figure 3 , the sub-pixel PX may include a sub-pixel circuit PC and a light-emitting element LED electrically connected to the sub-pixel circuit PC. The sub-pixel circuit PC may include a driving transistor T1, a switching transistor T2, and a storage capacitor Cst. The sub-pixel PX may emit, for example, red, green, or cyan light through the light-emitting element LED, or emit red, green, cyan, or white light.

[0101] The switching transistor T2 may be connected to the scan line SL and the data line DL, and transfer a data voltage or a data signal Dm input from the data line DL to the driving transistor T1 according to a scan voltage or a scan signal Sn input from the scan line SL.

[0102] The storage capacitor Cst may be connected to the switching transistor T2 and the driving voltage line PL and store a voltage corresponding to a difference between a voltage received from the switching transistor T2 and a driving voltage ELVDD supplied to the driving voltage line PL.

[0103] The driving transistor T1 may be connected to the driving voltage line PL and the storage capacitor Cst, and may control the driving current flowing from the driving voltage line PL through the light emitting element LED in accordance with the voltage value stored in the storage capacitor Cst. The light emitting element LED may emit light having a predetermined brightness by the driving current. The counter electrode (e.g., cathode) of the light emitting element LED may receive the common voltage ELVSS.

[0104] Figure 3 The sub-pixel circuit PC is shown to include 2 transistors and 1 storage capacitor. In another embodiment, the sub-pixel circuit PC may include 3 or more transistors.

[0105] Figure 4 is a cross-sectional view schematically showing a portion of a display device according to an embodiment of the present invention. Figure 4 It is along Figure 1 A cross-sectional view taken along line I-I'.

[0106] Reference Figure 4 The display panel 10 may include a substrate 100, a sub-pixel circuit layer, a light-emitting diode layer DEL, a packaging layer TFE, and a touch sensor layer 400. An optical function layer (not shown) and a cover window (not shown) may also be configured on the touch sensor layer 400.

[0107] The substrate 100 may include various materials having flexible or bendable properties. For example, the substrate 100 may include a polymer resin such as polyethersulphone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), or cellulose acetate propionate (CAP).

[0108] A sub-pixel circuit layer may be disposed on the substrate 100. The sub-pixel circuit layer may include a sub-pixel circuit PC, an inorganic insulating layer, and an organic insulating layer. In one embodiment, the inorganic insulating layer may include a buffer layer 111, a gate insulating layer 113, a first interlayer insulating layer 115, and a second interlayer insulating layer 117. In one embodiment, the organic insulating layer may include a first organic insulating layer 118 and a second organic insulating layer 119.

[0109] The sub-pixel circuit layer may include a thin film transistor and a capacitor. Figure 4 TFT and storage capacitor Cst are shown. The thin film transistor TFT may be equivalent to the one set in reference Figure 3 Any of the thin film transistors of the sub-pixel circuit PC described below is provided in the driving transistor T1, for example. The thin film transistor TFT may include a semiconductor layer Act, a source electrode SE, a gate electrode GE, and a drain electrode DE.

[0110] The buffer layer 111 is located on the substrate 100, and can reduce or block foreign matter, moisture, or external air from penetrating from the bottom of the substrate 100, and provide a flat surface on the substrate 100. The buffer layer 111 may include inorganic substances such as oxides or nitrides, or organic substances, or organic-inorganic composites, and is formed of a single layer or multilayer structure of inorganic and organic substances.

[0111] The semiconductor layer Act may include a channel region CH overlapping the gate electrode GE, a source region S and a drain region D disposed on both sides of the channel region CH and including a dopant having a higher concentration than that of the channel region CH. Here, the dopant may include an N-type dopant or a P-type dopant. The source region S and the drain region D may be electrically connected to the source electrode SE and the drain electrode DE of the thin film transistor TFT.

[0112] The semiconductor layer Act may include an oxide semiconductor and / or a silicon semiconductor. When the semiconductor layer Act is formed of an oxide semiconductor, for example, it may include an oxide of one or more substances selected from a group including indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti) and zinc (Zn). For example, the semiconductor layer Act may be indium tin zinc oxide (InSnZnO; ITZO), indium gallium zinc oxide (InGaZnO; IGZO), etc. When the semiconductor layer Act is formed of a silicon semiconductor, for example, it may include amorphous silicon or low temperature polysilicon (Low Temperature Poly-Silicon; LTPS) that crystallizes amorphous silicon.

[0113] The gate electrode GE may include a conductive substance including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed of a multilayer or single layer including the respective materials. The gate electrode GE may be connected to a gate line applying an electrical signal to the gate electrode GE.

[0114] A gate insulating layer 113 may be disposed between the semiconductor layer Act and the gate electrode GE, thereby insulating the semiconductor layer Act and the gate electrode GE. The gate insulating layer 113 may include one or more inorganic insulators selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, or zinc oxide. The gate insulating layer 113 may be a single layer or multilayer structure including the aforementioned inorganic insulators.

[0115] The storage capacitor Cst may include a first capacitor electrode CE1 and a second capacitor electrode CE2 disposed on the first capacitor electrode CE1. The first capacitor electrode CE1 and the second capacitor electrode CE2 of the storage capacitor Cst may be disposed overlapping each other. In one embodiment, the gate electrode GE of the thin film transistor TFT may include the first capacitor electrode CE1 of the storage capacitor Cst.

[0116] A first interlayer insulating layer 115 may be disposed between the first capacitor electrode CE1 and the second capacitor electrode CE2. The first interlayer insulating layer 115 may include inorganic insulators such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, and / or zinc oxide, and may be a single layer or multilayer structure including such inorganic insulators.

[0117] exist Figure 4 The figure shows that the storage capacitor Cst can overlap with the thin film transistor TFT and the first capacitor electrode CE1 is integrated with the gate electrode GE of the thin film transistor TFT. However, as another embodiment, the storage capacitor Cst may not overlap with the thin film transistor TFT and the first capacitor electrode CE1 may be an independent component different from the gate electrode GE of the thin film transistor TFT.

[0118] The second interlayer insulating layer 117 may be disposed on the second capacitor electrode CE2 of the storage capacitor Cst. The second interlayer insulating layer 117 may include one or more inorganic insulators selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, or zinc oxide. The second interlayer insulating layer 117 may be a single layer or multilayer structure including the aforementioned substances.

[0119] A source electrode SE and a drain electrode DE may be disposed on the second interlayer insulating layer 117. The source electrode SE and the drain electrode DE may include, for example, materials such as molybdenum (Mo), aluminum (Al), copper (Cu) and / or titanium (Ti), and may be a multilayer or single-layer structure including the foregoing materials. The source electrode SE and the drain electrode DE may be formed of a multilayer structure of Ti / Al / Ti. As an embodiment, the source electrode SE and the drain electrode DE may include the same material as the driving voltage supply wiring 160 and the common voltage supply wiring 170.

[0120] A light emitting diode layer DEL may be disposed on the second interlayer insulating layer 117. The light emitting diode layer DEL may include an organic light emitting diode OLED. The organic light emitting diode OLED may be electrically connected to the sub-pixel circuit PC. The organic light emitting diode OLED may be electrically connected to the sub-pixel circuit PC to implement a sub-pixel PX. The organic light emitting diode OLED may include a sub-pixel electrode 210, a light emitting layer 220, and an opposite electrode 230.

[0121] The sub-pixel electrode 210 may be electrically connected to the sub-pixel circuit PC. Figure 4As shown, the sub-pixel circuit PC can be electrically connected to the sub-pixel electrode 210 through the connecting electrode CM. As another embodiment, an additional connecting electrode can be further configured between the sub-pixel circuit PC and the sub-pixel electrode 210. In this case, the sub-pixel circuit PC and the sub-pixel electrode 210 can be electrically connected through the connecting electrode CM and the additional connecting electrode. Alternatively, the sub-pixel circuit PC and the sub-pixel electrode 210 can be directly electrically connected without the connecting electrode CM.

[0122] The connection electrode CM may be disposed on the first organic insulating layer 118 and connected to the sub-pixel circuit PC through a contact hole formed in the first organic insulating layer 118. The connection electrode CM may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. Alternatively, the connection electrode CM may include a transparent conductive material, such as a transparent conductive oxide (TCO). The connection electrode CM may be formed by a single layer or a multilayer structure including the aforementioned materials.

[0123] The first organic insulating layer 118 may include an organic substance. For example, the first organic insulating layer 118 may include a general-purpose polymer such as polymethylmethacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenol group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a p-xylene polymer, a vinyl alcohol polymer, and an organic insulating material such as a mixture thereof.

[0124] The second organic insulating layer 119 may be disposed on the connection electrode CM. The second organic insulating layer 119 may include an organic substance. For example, the second organic insulating layer 119 may include an organic insulating substance such as acrylic acid, benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO).

[0125] The sub-pixel electrode 210 may include a reflective film of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. Alternatively, the sub-pixel electrode 210 may further include a conductive conductive oxide layer on and / or below the aforementioned reflective film. The conductive oxide layer may include indium tin oxide (ITO; indium tin oxide), indium zinc oxide (IZO; indium zinc oxide), zinc oxide (ZnO; zinc oxide), indium oxide (In 2 O 3 In one embodiment, the sub-pixel electrode 210 may have a three-layer structure of ITO / Ag / ITO.

[0126] A dam layer 180 may be disposed on the sub-pixel electrode 210. The dam layer 180 may have an opening so that the central portion of the sub-pixel electrode 210 is exposed. The opening of the dam layer 180 may define a light-emitting region of the organic light-emitting diode OLED, and the light-emitting region of the organic light-emitting diode OLED may correspond to the sub-pixel PX. In addition, the dam layer 180 may increase the distance between the edge of the sub-pixel electrode 210 and the counter electrode 230 above the sub-pixel electrode 210, thereby preventing arcing, etc., from being generated in the edge of the sub-pixel electrode 210.

[0127] The dam layer 180 may include an organic insulator. In another embodiment, the dam layer 180 may include an inorganic insulator such as silicon nitride, silicon oxynitride, or silicon oxide. In another embodiment, the dam layer 180 may include an organic insulator and an inorganic insulator. In some embodiments, the dam layer 180 may include a light-shielding material and be set to black. The light-shielding material may include a resin or conductive paste containing carbon black, carbon nanotubes, black dye, metal particles (e.g., nickel, aluminum, molybdenum) and alloys thereof, metal oxide particles (e.g., chromium oxide), or metal nitride particles (e.g., chromium nitride), etc.

[0128] A spacer (not shown) may be disposed on the bank layer 180. The spacer may prevent the organic light emitting diode OLED from being damaged due to sagging of the mask during a manufacturing process using the mask.

[0129] The light emitting layer 220 may be disposed on the sub-pixel electrode 210. The light emitting layer 220 may overlap with the opening of the sub-pixel electrode 210. The light emitting layer 220 may include a low-molecular or high-molecular substance and emit red, green, cyan, or white light.

[0130] Functional layers may be selectively disposed below and above the light-emitting layer 220. For example, a hole injection layer (HIL) and / or a hole transport layer (HTL) may be disposed between the light-emitting layer 220 and the sub-pixel electrode 210. In addition, an electron transport layer (ETL) and / or an electron injection layer (EIL) may be disposed between the light-emitting layer 220 and the counter electrode 230.

[0131] In one embodiment, the light emitting layer 220 may be patterned so as to correspond to each of the plurality of sub-pixel electrodes 210. In some embodiments, the light emitting layer 220 may be formed as a whole by the plurality of sub-pixel electrodes 210. In one embodiment, the functional layers disposed below and above the light emitting layer 220 may be formed as a whole by the plurality of sub-pixel electrodes 210.

[0132] The counter electrode 230 may be disposed on the light emitting layer 220. In one embodiment, the counter electrode 230 may be configured to entirely cover the display area DA. That is, the counter electrode 230 may be formed as a whole in a manner of covering a plurality of sub-pixels PX.

[0133] The counter electrode 230 may be formed of a conductive material with a low work function. For example, the counter electrode 230 may include a (semi) transparent layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or alloys thereof. Alternatively, the counter electrode 230 may further include ITO, IZO, ZnO or In on the (semi) transparent layer including the aforementioned materials. 2 O 3 Such layers.

[0134] An encapsulation component may be disposed on the organic light emitting diode OLED. The encapsulation component may include an encapsulation layer TFE, or an encapsulation substrate in the shape of a substrate such as a chip. The encapsulation component may protect the organic light emitting diode OLED from external moisture and oxygen.

[0135] The encapsulation layer TFE may include one or more organic encapsulation layers and one or more inorganic encapsulation layers. The encapsulation layer TFE may be configured to cover the entire display area DA and extend to the peripheral area PA side to cover a portion of the peripheral area PA.

[0136] The encapsulation layer TFE may include a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 330 disposed on the first inorganic encapsulation layer 310, and an organic encapsulation layer 320 between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may each include one or more inorganic insulators. The inorganic insulator may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, or / and silicon oxynitride.

[0137] The organic encapsulation layer 320 may include a polymer series material. The polymer series element may include acrylic resin, epoxy resin, polyimide, polyethylene, etc. The organic encapsulation layer 320 may include acrylic resin, such as polymethyl methacrylate, polyacrylic acid, etc. The organic encapsulation layer 320 may be formed by curing a monomer or coating a polymer.

[0138] The touch sensor layer 400 may acquire coordinate information according to external input (eg, touch activity). The touch sensor layer 400 may include touch electrodes and touch wiring connected to the touch electrodes. The touch sensor layer 400 may sense external input in a self-capacitance manner or a mutual-capacitance manner.

[0139] The touch sensor layer 400 may be formed on the encapsulation layer TFE. Alternatively, the touch sensor layer 400 may be formed separately on the touch substrate and then bonded to the encapsulation layer TFE through an adhesive layer such as an optically clear adhesive (OCA). As an embodiment, the touch sensor layer 400 may be formed directly above the encapsulation layer TFE, in which case the adhesive layer may not be interposed between the touch sensor layer 400 and the encapsulation layer TFE.

[0140] The optical function layer may include an anti-reflection layer. The anti-reflection layer may reduce the reflectivity of light (external light) incident from the outside toward the display panel 10. In one embodiment, the optical function layer may be a polarizing film. Alternatively, the optical function layer may be formed by a black matrix and a filter plate including a color filter.

[0141] The cover window may be disposed on the display panel 10. The cover window may protect the display panel 10. The cover window may include at least one of glass, sapphire, and plastic. The cover window may be, for example, ultra-thin reinforced glass (UTG) or colorless polyimide (CPI).

[0142] Figure 5 is a plan view schematically showing a display device according to another embodiment of the utility model, Figure 6FIG. 4 is a side view schematically showing a display device according to another embodiment of the present invention. Figure 7 It is a schematic diagram Figure 5 An enlarged plan view of portion D of the display device. Figure 5 As Figure 1 The following is a modified embodiment of the present invention, which is described mainly based on the differences, and the contents repeated in the aforementioned embodiment are omitted.

[0143] Reference Figure 5 as well as Figure 6 , a detection circuit 40 may be configured in the sub-region SR of the display panel 10. Figure 5 The detection circuit 40 is shown to be disposed more adjacent to the display area DA than the driving chip 20. As another embodiment, the driving chip 20 may be disposed more adjacent to the display area DA than the detection circuit 40. As yet another embodiment, the driving chip 20 and the detection circuit 40 may be disposed overlapping each other.

[0144] The detection circuit 40 may include a plurality of voltage lines and a plurality of transistors. The detection circuit 40 may be electrically connected to a detection wiring 600 described later, and detect cracks by using an electrical signal (eg, a voltage value) transmitted from the detection wiring 600 when the display device 1 is driven.

[0145] In one embodiment, the detection circuit 40 may be formed as one body with the display panel 10. For example, the detection circuit 40 may be formed by using a conductive layer and an insulating layer in the display panel 10. As another embodiment, the detection circuit 40 is separately provided and mounted in the sub-region SR of the display panel like the driving chip 20 or the printed circuit substrate 30.

[0146] The sensing circuit 40 is located in the sub-region SR of the display panel 10 , and thus, as the display panel 10 is bent in the bending region BR, the sensing circuit 40 may be located on the rear surface of the main region MR.

[0147] Reference Figure 5 as well as Figure 7 , the substrate 100 may include a through hole 1100. The through hole 1100 may be defined in the display area DA. However, the area where the through hole 1100 is located and its surroundings do not form sub-pixels, so the through hole 1100 cannot display an image.

[0148] The detection wiring 600 may be configured in the peripheral area PA. The detection wiring 600 may include a first peripheral detection wiring 610, a second peripheral detection wiring 620, and a through-hole detection wiring 630. The first peripheral detection wiring 610 and the second peripheral detection wiring 620 are configured on the outside of the display area DA in a manner surrounding at least a portion of the display area DA. For example, the first peripheral detection wiring 610 and the second peripheral detection wiring 620 may extend along the first edge E1, the third edge E3, and the fourth edge E4 of the display area DA, respectively. The first peripheral detection wiring 610 may be configured on the outside of the second peripheral detection wiring 620. The second peripheral detection wiring 620 may be configured between the first peripheral detection wiring 610 and the display area DA. The end of each of the first peripheral detection wiring 610 and the second peripheral detection wiring 620 may extend in a manner passing through the bending area BR in a direction toward the pad portion PAD. In one embodiment, the first peripheral detection wiring 610 may be a first wiring.

[0149] At least a portion of the through-hole detection wiring 630 is disposed adjacent to the through-hole 1100. The first peripheral detection wiring 610 and the through-hole detection wiring 630 may be electrically connected, and the through-hole detection wiring 630 and the second peripheral detection wiring 620 may be electrically connected.

[0150] The through hole detection wiring 630 may be a wiring for detecting whether a crack is generated around the through hole 1100. One end of the through hole detection wiring 630 disposed adjacent to the through hole 1100 may be electrically connected to the first peripheral detection wiring 610. The other end of the through hole detection wiring 630 may be electrically connected to the second peripheral detection wiring 620.

[0151] The first peripheral detection wiring 610 may include a 1-1 peripheral detection wiring 611 and a 1-2 peripheral detection wiring 612, and the second peripheral detection wiring 620 may include a 2-1 peripheral detection wiring 621 and a 2-2 peripheral detection wiring 622. The 1-1 peripheral detection wiring 611 and the 2-1 peripheral detection wiring 621 may extend along one side (e.g., left side) edge of the substrate 100. The 1-2 peripheral detection wiring 612 and the 2-2 peripheral detection wiring 622 may extend along the other side (e.g., right side) edge of the substrate 100.

[0152] The through hole detection wiring 630 may have a shape that double surrounds the periphery of the through hole 1100. The through hole detection wiring 630 may include a first portion 631, a second portion 632, and a third portion 633. The first portion 631 may surround a portion of one side (e.g., the left side) of the through hole 1100. The second portion 632 may be bent from the first portion 631 and surround the through hole 1100 as a whole. The third portion 633 may be bent from the second portion 632 and surround a portion of the other side (e.g., the right side) of the through hole 1100. The through hole detection wiring 630 may include a first bending portion 630C1 between the first portion 631 and the second portion 632 and a second bending portion 630C2 between the second portion 632 and the third portion 633. The first bending portion 630C1 and the second bending portion 630C2 may face each other and be spaced apart.

[0153] One end 630e1 of the through hole detection wiring 630 may be electrically connected to the second peripheral detection wiring 620 via the first connection wiring L1. The other end 630e2 of the through hole detection wiring 630 may be electrically connected to the first peripheral detection wiring 610 via the second connection wiring L2.

[0154] The detection wiring 600 may be electrically connected to the pad portion PAD. The pad portion PAD may include a data pad DP, first to fourth inspection pads TP1, TP2, TP3, TP4, a first pad P1', and a second pad P2'. The first pad P1' may be electrically connected to the 1-1 peripheral detection wiring 611 and the first voltage line VL1 described later. The second pad P2' may be electrically connected to the 1-2 peripheral detection wiring 612 and the third voltage line VL3.

[0155] The detection wiring 600 may be electrically connected to the detection circuit 40. Figure 5 As shown, the detection circuit 40 may include a first voltage line VL1, a second voltage line VL2, a third voltage line VL3, and a fourth voltage line VL4. The first voltage line VL1 may be electrically connected to the first pad P1' and the 1-1 peripheral detection wiring 611. The second voltage line VL2 may be electrically connected to the 2-1 peripheral detection wiring 621. The signal transmitted from the first pad P1' may be transmitted to the 1-1 peripheral detection wiring 611 and the first voltage line VL1. In other words, the signal transmitted from the first pad P1' may be transmitted to the detection circuit 40 through the second voltage line VL2 after passing through the 1-1 peripheral detection wiring 611, the through-hole detection wiring 630, and the 2-1 peripheral detection wiring 621, or may be directly transmitted to the detection circuit 40 through the first voltage line VL1. Whether a crack of the display device 1 is generated or not may be confirmed based on the signal transmitted through the first voltage line VL1 and the electrical signal transmitted through the second voltage line VL2. At this time, the electrical signal may be a current and / or a voltage.

[0156] The third voltage line VL3 may be electrically connected to the second pad P2' and the 1-2 peripheral detection wiring 612. The fourth voltage line VL4 may be electrically connected to the 2-2 peripheral detection wiring 622. The signal transmitted from the second pad P2' may be transmitted to the 1-2 peripheral detection wiring 612 and the third voltage line VL3. In other words, the signal transmitted from the second pad P2' may be transmitted to the detection circuit 40 through the fourth voltage line VL4 after passing through the 1-2 peripheral detection wiring 612, the through-hole detection wiring 630, and the 2-2 peripheral detection wiring 622, or may be directly transmitted to the detection circuit 40 through the third voltage line VL3. Whether a crack of the display device 1 is generated or not may be confirmed based on the signal transmitted through the third voltage line VL3 and the electrical signal transmitted through the fourth voltage line VL4. In one embodiment, the same electrical signal may be applied to the first pad P1' and the second pad P2' at the same time.

[0157] Figure 8 It is enlarged to show Figure 5 FIG. 4 is a plan view of a detection circuit 40 of a display device. Figure 8 , a portion of the sub-pixels PX and a portion of the data lines DL arranged in the display panel 10 are shown.

[0158] Reference Figure 8 , the sub-pixels PX may include a red sub-pixel R that emits red light, a cyan sub-pixel B that emits cyan light, and a green sub-pixel G that emits green light. The red sub-pixels R and the cyan sub-pixels B may be arranged alternately in the same column, and the green sub-pixels G may be arranged in a column adjacent to the column in which the red sub-pixels R and the cyan sub-pixels B are arranged. In one embodiment, each of the red sub-pixels R and the cyan sub-pixels B may be alternately arranged to avoid being repeatedly arranged in the same column in two adjacent rows. Figure 8 2 , the sub-pixel PX is shown to be composed of a red sub-pixel R, a cyan sub-pixel B, and a green sub-pixel G. However, the sub-pixel PX may also include colors other than red, green, and cyan.

[0159] A data line DL may be configured in each column. The data lines DL may be connected to the data pads DP of the pad portion PAD, respectively. On the other hand, the data line DL connected to the first voltage line VL1 of the detection circuit 40 may be referred to as the first data line DL1, the data line DL connected to the second voltage line VL2 of the detection circuit 40 may be referred to as the second data line DL2, the data line DL connected to the third voltage line VL3 of the detection circuit 40 may be referred to as the third data line DL3, and the data line DL connected to the fourth voltage line VL4 of the detection circuit 40 may be referred to as the fourth data line DL4.

[0160] exist Figure 8 In the figure, it is shown that there is one first data line DL1 connected to the first voltage line VL1. As another embodiment, there may be multiple first data lines DL1 connected to the first voltage line VL1. The first data line DL1 is used as a reference for the description, but the third data line DL3 is also applicable. That is, there may be multiple third data lines DL3 connected to the third voltage line VL3. In addition, Figure 8 The sub-pixel PX connected to the first data line DL1 is shown to be composed of a green sub-pixel G. As another embodiment, the sub-pixel PX connected to the first data line DL1 may be composed of a red sub-pixel R and / or a cyan sub-pixel B. The first data line DL1 is used as a reference for the description, but the third data line DL3 is also applicable.

[0161] The detection circuit 40 may include the aforementioned first voltage line VL1 , second voltage line VL2 , third voltage line VL3 , fourth voltage line VL4 , and first transistor TT1 , second transistor TT2 , third transistor TT3 , and fourth transistor TT4 .

[0162] The first transistor TT1 may include a first terminal connected to the first voltage line VL1, a second terminal connected to the first data line DL1, and a gate. The first transistor TT1 may be turned on by a control signal applied to the gate and may connect the first voltage line VL1 and the first data line DL1.

[0163] The second transistor TT2 may include a first terminal connected to the second voltage line VL2, a second terminal connected to the second data line DL2, and a gate. The second transistor TT2 may be turned on by a control signal applied to the gate and turns on the second voltage line VL2 and the second data line DL2.

[0164] The third transistor TT3 may include a first terminal connected to the third voltage line VL3, a second terminal connected to the third data line DL3, and a gate. The third transistor TT3 may be turned on by a control signal applied to the gate and turn on the third voltage line VL3 and the third data line DL3.

[0165] The fourth transistor TT4 may include a first terminal connected to the fourth voltage line VL4, a second terminal connected to the fourth data line DL4, and a gate. The fourth transistor TT4 may be turned on by a control signal applied to the gate and connect the fourth voltage line VL4 and the fourth data line DL4.

[0166] In one embodiment, the gate of each of the first to fourth transistors TT1, TT2, TT3, and TT4 may be a part of the first gate line GWL that is set as one. The first gate line GWL may be electrically connected to the driving chip 20. The first to fourth transistors TT1, TT2, TT3, and TT4 may be controlled simultaneously. In other words, the first to fourth transistors TT1, TT2, TT3, and TT4 may be turned on or off simultaneously by the same control signal. For example, when the pad portion PAD is attached to the printed circuit substrate 30, during the period when the data pad DP applies the data signal, the first to fourth transistors TT1, TT2, TT3, and TT4 may operate by the same control signal.

[0167] The detection circuit 40 may include matching resistors Rm and Rm'. The matching resistor Rm may be connected to the first voltage line VL1. The matching resistor Rm may be set by considering the loop resistance reaching the second voltage line VL2 through the 1-1 peripheral detection wiring 611, the through-hole detection wiring 630, and the 2-1 peripheral detection wiring 621. Similarly, the matching resistor Rm' may be connected to the third voltage line VL3. The matching resistor Rm' may be set by considering the loop resistance reaching the fourth voltage line VL4 through the 1-2 peripheral detection wiring 612, the through-hole detection wiring 630, and the 2-2 peripheral detection wiring 622.

[0168] The detection circuit 40 can predict whether cracks occur in the display device 1 and / or the display panel 10 as follows.

[0169] For example, a black data voltage may be applied to the first pad P1' and the second pad P2'. When no crack is generated, the electric signal transmitted through the 1-1 peripheral detection wiring 611, the through hole detection wiring 630, and the 2-1 peripheral detection wiring 621 and the second voltage line VL2 and the electric signal transmitted through the first voltage line VL1 may be equal to the black data voltage. In addition, the electric signal transmitted through the 1-2 peripheral detection wiring 612, the through hole detection wiring 630, and the 2-2 peripheral detection wiring 622 and the fourth voltage line VL4 and the electric signal transmitted through the third voltage line VL3 may be equal to the black data voltage.

[0170] Therefore, the first data line DL1 connected to the first voltage line VL1 through the first transistor TT1 receives the black data voltage, and the sub-pixel PX connected to the first data line DL1 receives the black data voltage without emitting light. Similarly, the second data line DL2 connected to the second voltage line VL2 through the second transistor TT2 receives the black data voltage, and the sub-pixel PX connected to the second data line DL2 receives the black data voltage without emitting light. The third data line DL3 connected to the third voltage line VL3 through the third transistor TT3 receives the black data voltage, and the sub-pixel PX connected to the third data line DL3 receives the black data voltage without emitting light. In addition, the fourth data line DL4 connected to the fourth voltage line VL4 through the fourth transistor TT4 receives the black data voltage, and the sub-pixel PX connected to the fourth data line DL4 receives the black data voltage without emitting light.

[0171] When a crack is generated and the 2-1st peripheral detection wiring 621 is disconnected, the electrical signal transmitted through the second voltage line VL2 may be higher or lower than the black data voltage. Therefore, the second data line DL2 connected to the second voltage line VL2 through the second transistor TT2 receives a voltage different from the black data voltage, and the sub-pixel PX connected to the second data line DL2 emits light. The sub-pixel PX connected to each of the first data line DL1, the third data line DL3, and the fourth data line DL4 does not emit light.

[0172] When a crack is generated and the 2-2 peripheral detection wiring 622 is disconnected, the electric signal transmitted through the fourth voltage line VL4 may be higher or lower than the black data voltage. Therefore, the fourth data line DL4 connected to the fourth voltage line VL4 through the fourth transistor TT4 receives a voltage different from the black data voltage, and the sub-pixel PX connected to the fourth data line DL4 does not emit light. The sub-pixel PX connected to each of the first data line DL1, the second data line DL2, and the third data line DL3 does not emit light.

[0173] When a crack is generated and the through hole detection wiring 630 is disconnected, or the 2-1 peripheral detection wiring 621 and the 2-2 peripheral detection wiring 622 are all disconnected, the electric signal transmitted through the second voltage line VL2 and the electric signal transmitted through the fourth voltage line VL4 can be higher or lower than the black data voltage. Therefore, the second data line DL2 connected to the second voltage line VL2 through the second transistor TT2 and the fourth data line DL4 connected to the fourth voltage line VL4 through the fourth transistor TT4 receive a voltage different from the black data voltage, and the sub-pixel PX connected to the second data line DL2 and the fourth data line DL4 emits light. The sub-pixel PX connected to each of the first data line DL1 and the third data line DL3 does not emit light.

[0174] However, when a crack is generated and causes the 1-1 peripheral detection wiring 611 to be disconnected, the electric signal transmitted from the second pad P2' through the 1-2 peripheral detection wiring 612 is transmitted through the second voltage line VL2 via the 2-1 peripheral detection wiring 621. The first voltage line VL1 may be directly connected to the first pad P1'. Therefore, the electric signal transmitted through the second voltage line VL2 and the electric signal transmitted through the first voltage line VL1 may be equal to the black data voltage. Similarly, when a crack is generated and causes the 1-2 peripheral detection wiring 612 to be disconnected, the electric signal transmitted from the first pad P1' through the 1-1 peripheral detection wiring 611 may be transmitted through the fourth voltage line VL4 via the 2-2 peripheral detection wiring 622. The third voltage line VL3 may be directly connected to the second pad P2'. The electric signal transmitted through the fourth voltage line VL4 and the electric signal transmitted through the third voltage line VL3 may be equal to the black data voltage. Therefore, all of the sub-pixels PX connected to each of the first data line DL1 , the second data line DL2 , the third data line DL3 , and the fourth data line DL4 may not emit light.

[0175] According to the aforementioned detection circuit 40, not only whether a crack occurs in the display device 1, but also the position where the crack occurs can be predicted according to whether the sub-pixel PX connected to each of the first data line DL1 to the fourth data line DL4 emits light. However, it may be that the detection circuit 40 cannot detect cracks in the display device 1 in a non-driving state, and cannot detect cracks generated in the 1-1 peripheral detection wiring 611 or the 1-2 peripheral detection wiring 612 in the detection wiring 600.

[0176] Reference Figure 5 , the display device 1 may include first to fourth inspection pads TP1 , TP2 , TP3 , TP4 and first to fourth inspection wirings TL1 , TL2 , TL3 , TL4 .

[0177] The first to fourth inspection pads TP1, TP2, TP3, TP4 may be electrically connected to the first inspection wiring TL1, the second inspection wiring TL2, the third inspection wiring TL3, and the fourth inspection wiring TL4, respectively. The first to fourth inspection pads TP1, TP2, TP3, TP4 may be pads for transmitting inspection signals or measuring loop resistance.

[0178] The first peripheral detection wiring 610 may be electrically connected to the first to fourth inspection wirings TL1, TL2, TL3, and TL4. The first inspection wiring TL1 may be electrically connected to the 1-1 peripheral detection wiring 611 in the sub-region SR (e.g., between the bending region BR and the pad portion PAD). The first inspection wiring TL1 may electrically connect the 1-1 peripheral detection wiring 611 and the first inspection pad TP1.

[0179] The second inspection wiring TL2 may extend toward the display area DA in the pad portion PAD in a manner passing through the bending region BR. The second inspection wiring TL2 may be electrically connected to the 1-1 peripheral inspection wiring 611 in the main region MR (e.g., between the bending region BR and the display area DA). The second inspection wiring TL2 may electrically connect the 1-1 peripheral inspection wiring 611 and the second inspection pad TP2.

[0180] The third inspection wiring TL3 may be electrically connected to the 1-2 peripheral inspection wiring 612 in the sub-region SR (eg, between the bending region BR and the pad portion PAD). The third inspection wiring TL3 may electrically connect the 1-2 peripheral inspection wiring 612 and the third inspection pad TP3.

[0181] The fourth inspection wiring TL4 may extend in the pad portion PAD toward the display area DA in a manner passing through the bending region BR. The fourth inspection wiring TL4 may be electrically connected to the 1-2 peripheral inspection wiring 612 in the main region MR (e.g., between the bending region BR and the display area DA). The fourth inspection wiring TL4 may electrically connect the 1-2 peripheral inspection wiring 612 and the fourth inspection pad TP4.

[0182] According to an embodiment of the present invention, whether cracks occur in the display device 1 can be confirmed in a non-driving state through the first to fourth inspection wirings TL1, TL2, TL3, TL4 and the first to fourth inspection pads TP1, TP2, TP3, TP4 connected to the first peripheral detection wiring 610.

[0183] For example, the first inspection wiring TL1, a portion of the first peripheral detection wiring 610, and the third inspection wiring TL3 may be connected to each other to form a first pattern in the form of a loop that surrounds the display area DA and is open on one side. The loop resistance value of the first pattern may be measured by the first inspection pad TP1 and the third inspection pad TP3. When a crack is generated in the first pattern, the resistance value of the first pattern may be measured to be greater than the set resistance value. Whether a crack is generated in the display device 1 may be confirmed by such a change in the resistance value of the first pattern.

[0184] The first inspection wiring TL1, a portion of the first peripheral detection wiring 610, and the second inspection wiring TL2 can be connected to each other to form a second pattern in the form of a loop that passes through the left bending area BR and is open on one side. The loop resistance value of the second pattern can be measured by the first inspection pad TP1 and the second inspection pad TP2. When a crack occurs in the second pattern, the resistance value of the second pattern can be measured to be greater than the set resistance value. The bending area BR of the display device 1 is confirmed by such a change in the resistance value of the second pattern, specifically, whether a crack occurs in the left bending area BR.

[0185] The third inspection wiring TL3, a portion of the first peripheral detection wiring 610, and the fourth inspection wiring TL4 can be connected to each other to form a third pattern in the form of a loop that passes through the right bending area BR and is open on one side. The loop resistance value of the third pattern can be measured by the third inspection pad TP3 and the fourth inspection pad TP4. When a crack occurs in the third pattern, the resistance value of the third pattern can be measured to be greater than the set resistance value. The bending area BR of the display device 1 can be confirmed by such a change in the resistance value of the third pattern, specifically, to confirm whether a crack occurs in the right bending area BR.

[0186] The display device 1 according to an embodiment of the present invention includes first to fourth inspection wirings TL1, TL2, TL3, TL4 and first to fourth inspection pads TP1, TP2, TP3, TP4 connected to the first peripheral inspection wiring 610 extending to surround the display area DA, so that whether cracks of the display device 1 are generated can be confirmed in a non-driven state. In particular, whether cracks of the left or right bending area BR of the display device 1 are generated can be confirmed. In addition, whether cracks of the first peripheral inspection wiring 610 that cannot be detected by the detection circuit 40 are generated can also be confirmed in the driven state of the display device 1.

[0187] The present invention is described by referring to an embodiment shown in the accompanying drawings, but those with ordinary knowledge in the technical field can understand that it is only exemplary and various modifications and variations of the embodiments can be made therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical concept of the attached claims.

Claims

1. A display device, characterized in that: include: A substrate, comprising a first area having a display area, a second area, and a curved area between the first area and the second area; Display elements are arranged in the display area; A first wiring extending in a manner surrounding at least a portion of the display area; A first inspection pad, a second inspection pad and a third inspection pad are arranged in the second area; a first inspection wiring electrically connected to the first wiring in the second region and electrically connected to the first inspection pad; a second inspection wiring extending in a manner passing through the bending region and electrically connected to the first wiring in the first region and electrically connected to the second inspection pad; as well as A third inspection wiring is spaced apart from the first inspection wiring and is electrically connected to the first wiring in the second region, and is electrically connected to the third inspection pad.

2. The display device according to claim 1, characterized in that The substrate is bent in the bending region so that a rear surface of the second region faces at least a portion of a rear surface of the first region.

3. The display device according to claim 1, characterized in that The display device further includes: a fourth inspection pad, disposed in the second area; and A fourth inspection wiring extends so as to pass through the bending region, is electrically connected to the first wiring in the first region, and is electrically connected to the fourth inspection pad.

4. The display device according to claim 3, characterized in that The first inspection wiring and the second inspection wiring are arranged on one side of the substrate, The third inspection wiring and the fourth inspection wiring are arranged on the other side of the substrate opposite to the one side of the substrate.

5. The display device according to claim 1, characterized in that The first wiring is provided integrally with the first inspection wiring, the second inspection wiring, and the third inspection wiring.

6. The display device according to claim 1, characterized in that: The substrate includes a through hole defined in the first area, The display device further includes: a through hole detection wiring electrically connected to the first wiring and arranged adjacent to the through hole; and The second wiring is electrically connected to the through hole detection wiring and extends to surround at least a portion of the display area.

7. The display device according to claim 6, characterized in that: The through hole detection wiring has a shape doubly surrounding the through hole.

8. The display device according to claim 6, characterized in that: The first wiring is arranged outside the second wiring.

9. The display device according to claim 6, characterized in that: The first wiring includes: a 1-1 wiring extending along one side edge of the substrate; and a 1-2 wiring extending along the other side edge of the substrate. The second wiring includes: a 2-1 wiring extending along one side edge of the substrate; and a 2-2 wiring extending along the other side edge of the substrate.

10. The display device according to claim 9, characterized in that: The display device further includes: A first pad, disposed in the second area; A first voltage line electrically connected to the first pad; and The second voltage line is electrically connected to the 2-1 wiring.

Images