Display panel

Abstract

A display panel is provided. The display panel includes first to Nth display areas disposed in a row direction. The P-th display area includes a first pixel circuit including a first pixel driving transistor, a first pixel initialization transistor receiving an initialization voltage, and a first pixel compensation transistor connected in series to the first pixel initialization transistor, wherein the first pixel compensation transistor connects the first pixel driving transistor and the first pixel initialization transistor to each other based on a compensation gate signal; and a Pth display area control circuit including a first control transistor outputting a high gate voltage of the compensation gate signal and a second control transistor outputting a low gate voltage of the compensation gate signal, in which the first control transistor and the second control transistor are controlled based on the Pth display area control signal.

Description

Technical Field

[0001] Embodiments of the present application relate to a display panel, and more particularly, to a display panel for performing multi-frequency driving (MFD). Background Art

[0002] Typically, a display device includes a display panel and a display panel driver. The display panel may include gate lines, data lines, emission lines, and pixels. The display panel driver may include a gate driver for providing a gate signal to the gate line, a data driver for providing a data voltage to the data line, an emission driver for providing an emission signal to the emission line, and a drive controller for controlling the gate driver, the data driver, and the emission driver.

[0003] The display device can display images at a constant driving frequency such as 60 Hz, 120 Hz, or 240 Hz. However, in order to reduce the power consumption of the display device, the display device can operate based on a variable frequency by changing the time length of the frame per frame. The display device can change the time length of the frame by changing the time length of the blank period. The display device can change the time length of the blank period by controlling the gate signal. In addition, when the static image is not displayed on the entire area of ​​the display panel, that is, when the static image is displayed only on a portion of the display panel, the display device can perform a multi-frequency drive (MFD) that displays an image at a different driving frequency in each of the multiple display areas. Utility Model Content

[0004] Conventional display devices generally operate based on variable frequencies by controlling a gate signal applied to each of a plurality of pixel rows, and conventional display devices can control the driving frequency of pixels in the same pixel row. Therefore, conventional display devices can support different driving frequencies for display areas that are arranged to be adjacent to each other in the column direction. However, such conventional display devices may not be operable based on different driving frequencies for display areas that are arranged to be adjacent to each other in the row direction. In addition, in order to perform multi-frequency driving, it is desirable that the conventional display device adjusts the compensation gate signal for controlling the compensation transistor included in the pixel and the data initialization gate signal for controlling the initialization transistor included in the pixel.

[0005] Embodiments of the present application provide a display panel for driving display areas disposed adjacent to each other in a row direction at different driving frequencies.

[0006] Embodiments of the present application provide a display device including a display panel.

[0007] In an embodiment of a display panel according to the present application, a display panel includes a first display area to an Nth display area arranged in a row direction, wherein N is an integer of 2 or greater, wherein the display panel also includes a Pth display area, wherein P is an integer between 1 and N, and the Pth display area includes: a first pixel circuit, the first pixel circuit includes a first pixel driving transistor, a first pixel initialization transistor receiving an initialization voltage, and a first pixel compensation transistor connected in series to the first pixel initialization transistor, wherein the first pixel compensation transistor connects the first pixel driving transistor and the first pixel initialization transistor to each other based on a compensation gate signal; and a Pth display area control circuit, the Pth display area control circuit includes a first control transistor with a high gate voltage that outputs a compensation gate signal and a second control transistor with a low gate voltage that outputs the compensation gate signal, wherein the first control transistor and the second control transistor are controlled based on the Pth display area control signal.

[0008] In an embodiment, the first control transistor may include a gate electrode receiving a P display area control signal, a first electrode receiving a high gate voltage, and a second electrode connected to the gate electrode of the first pixel compensation transistor, and the second control transistor includes a gate electrode receiving a P display area control signal, a first electrode receiving a low gate voltage, and a second electrode connected to the gate electrode of the first pixel compensation transistor.

[0009] In an embodiment, the P display area may further include a second pixel circuit, wherein the second pixel circuit may be arranged to be adjacent to the first pixel circuit in the same pixel row, and include a second pixel driving transistor, a second pixel initialization transistor receiving an initialization voltage, and a second pixel compensation transistor connected in series to the second pixel initialization transistor, wherein the second pixel compensation transistor connects the second pixel driving transistor and the second pixel initialization transistor to each other based on a compensation gate signal.

[0010] In an embodiment, the first control transistor may include a gate electrode receiving a P display area control signal, a first electrode receiving a high gate voltage, and a second electrode connected to the gate electrode of the first pixel compensation transistor and the gate electrode of the second pixel compensation transistor, and the second control transistor may include a gate electrode receiving a P display area control signal, a first electrode receiving a low gate voltage, and a second electrode connected to the gate electrode of the first pixel compensation transistor and the gate electrode of the second pixel compensation transistor.

[0011] In an embodiment, when the driving frequency of the display panel is the maximum driving frequency, a data write operation can be performed once and a self-scan operation can be performed once during a frame period, and when the driving frequency of the display panel is not the maximum driving frequency, a data write operation can be performed once and a self-scan operation can be performed at least twice during a frame period.

[0012] In an embodiment, the first pixel circuit may further include: a first pixel light-emitting element, the first pixel light-emitting element receives a first pixel driving current of a first pixel driving transistor; a first pixel write transistor, the first pixel write transistor applies a first pixel data voltage to a first electrode of the first pixel driving transistor; a first pixel first light-emitting transistor, the first pixel first light-emitting transistor transmits a first power supply voltage to the first electrode of the first pixel driving transistor; a first pixel second light-emitting transistor, the first pixel second light-emitting transistor connects the second electrode of the first pixel driving transistor to the anode electrode of the first pixel light-emitting element; a first pixel anode initialization transistor, the first pixel anode initialization transistor applies an anode initialization voltage to the anode electrode of the first pixel light-emitting element; a first pixel storage capacitor, the first pixel storage capacitor stores a voltage of a gate electrode of the first pixel driving transistor; and a first pixel holding capacitor, the first pixel holding capacitor stores a voltage of a first electrode of the first pixel driving transistor.

[0013] In an embodiment, the first pixel light emitting element may include an anode electrode connected to the fourth node of the first pixel and a cathode electrode receiving a second power supply voltage, the first pixel driving transistor may include a gate electrode connected to the first node of the first pixel, a first electrode connected to the second node of the first pixel, and a second electrode connected to the third node of the first pixel, the first pixel write transistor may include a gate electrode receiving a data write gate signal, a first electrode receiving a first pixel data voltage, and a second electrode connected to the second node of the first pixel, the first pixel compensation transistor may include a gate electrode receiving a compensation gate signal based on a P display area control signal, a first electrode connected to the third node of the first pixel, and a second electrode connected to the first node of the first pixel, the first pixel initialization transistor may include a gate electrode receiving a data initialization gate signal, a first electrode receiving an initialization voltage, and connected to the second electrode of the third node of the first pixel, the first light-emitting transistor of the first pixel may include a gate electrode receiving an emission signal, a first electrode receiving a first power supply voltage, and a second electrode connected to the second node of the first pixel, the second light-emitting transistor of the first pixel may include a gate electrode receiving an emission signal, a first electrode connected to the third node of the first pixel, and a second electrode connected to the fourth node of the first pixel, the first pixel anode initialization transistor may include a gate electrode receiving an anode initialization gate signal, a first electrode receiving an anode initialization voltage, and a second electrode connected to the fourth node of the first pixel, the first pixel storage capacitor may include a first electrode receiving the first power supply voltage and a second electrode connected to the first node of the first pixel, and the first pixel holding capacitor may include a first electrode receiving the first power supply voltage and a second electrode connected to the second node of the first pixel.

[0014] In an embodiment, the data write gate signal may include an Mth data initialization gate signal, and the anode initialization gate signal may be an M+Kth data initialization gate signal, where each of M and K is an integer of 1 or greater.

[0015] In an embodiment, when a data write operation is performed, each of the data initialization gate signal, the compensation gate signal, the data write gate signal, the anode initialization gate signal, and the emission signal may include at least one turn-on voltage period.

[0016] In an embodiment, when a data write operation is performed, a portion of a turn-on voltage period of the data initialization gate signal may overlap a portion of a turn-on voltage period of the compensation gate signal.

[0017] In an embodiment, when a portion of a turn-on voltage period of the data initialization gate signal overlaps a portion of a turn-on voltage period of the compensation gate signal, a voltage of the gate electrode of the first pixel driving transistor may be initialized.

[0018] In an embodiment, when the self-scan operation is performed, each of the data write gate signal, the anode initialization gate signal, and the emission signal may include at least one on-voltage period, and each of the data initialization gate signal and the compensation gate signal may not include an on-voltage period.

[0019] According to an embodiment of the display panel, the display panel may include a first display area to an Nth display area arranged in a row direction. In such an embodiment, the Pth display area may include a first pixel circuit, the first pixel circuit including a first pixel driving transistor, a first pixel initialization transistor receiving an initialization voltage, and a first pixel compensation transistor connected in series to the first pixel initialization transistor, wherein the first pixel compensation transistor connects the first pixel driving transistor and the first pixel initialization transistor to each other based on a compensation gate signal. In such an embodiment, the Pth display area may include a first control transistor outputting a high gate voltage of the compensation gate signal and a second control transistor outputting a low gate voltage of the compensation gate signal. In such an embodiment, the first control transistor and the second control transistor may be controlled based on the Pth display area control signal. Therefore, the display device can drive the display areas arranged to be adjacent to each other in the row direction at different driving frequencies, respectively.

[0020] In such an embodiment, the first pixel compensation transistor can be connected in series to the first pixel initialization transistor. Therefore, the display device can adjust the compensation gate signal based on the Pth display area control signal to drive the display areas arranged to be adjacent to each other in the row direction at different driving frequencies. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and other features of the embodiments of the present application will become more apparent by describing the embodiments of the present application in detail with reference to the accompanying drawings, in which:

[0022] Figure 1 is a block diagram illustrating a display device according to an embodiment;

[0023] Figure 2 is a block diagram illustrating an example of a display panel including first to N-th display areas;

[0024] Figure 3 It is a graphic Figure 2 A conceptual diagram of the driving frequency of the display panel 100;

[0025] Figure 4 It is a graphic Figure 2 A circuit diagram of a first pixel circuit in a Pth display area and a Pth display area control circuit;

[0026] Figure 5 It is a graphic Figure 2 A circuit diagram of a first pixel circuit, a second pixel circuit and a P-th display area control circuit in a P-th display area;

[0027] Figure 6 The figure shows that when the driving frequency of the display panel 100 is 240 Hz Figure 4 and Figure 5 A timing diagram of a driving signal of a pixel;

[0028] Figure 7 is a timing diagram illustrating an example of a gate signal in a data writing period;

[0029] Figure 8 is a timing diagram illustrating an example of a gate signal in a self-scan period;

[0030] Fig. 9 is a block diagram illustrating an electronic device according to an embodiment; and

[0031] Fig.10 It is a diagram showing Fig. 9 FIG. 1 is a diagram of an embodiment in which the electronic device is implemented as a smart phone. DETAILED DESCRIPTION

[0032] The present application will now be described more fully below with reference to the accompanying drawings in which various embodiments are shown. However, the present application may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be exhaustive and comprehensive, and will fully convey the scope of the present application to those skilled in the art. The same reference numerals always refer to the same elements.

[0033] It will be understood that when an element is referred to as being “on” another element, the element can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

[0034] It will be understood that although the terms "first", "second", "third", etc. can be used to describe various elements, components, regions, layers and / or parts in this article, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings herein, the "first element", "first component", "first region", "first layer" or "first part" discussed below can be referred to as the second element, second component, second region, second layer or second part.

[0035] The terms used herein are only for the purpose of describing specific embodiments, and are not intended to be limited. As used herein, "a", "an", "the" and "at least one" do not represent the limitation of quantity, and are intended to include both the singular and the plural, unless the context clearly indicates otherwise. For example, unless the context clearly indicates otherwise, "element" has the same meaning as "at least one element". "At least one" is not interpreted as limiting "a" or "an". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the items listed in the association. It will be further understood that the term "comprises" and / or "comprising", or "includes" and / or "including" specifies the existence of stated features, regions, wholes, steps, operations, elements and / or components when used in this specification, but does not exclude the existence or addition of one or more other features, regions, wholes, steps, operations, elements, components and / or their groups.

[0036] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the figures. It will be understood that relative terms are intended to include different orientations of the device other than the orientation depicted in the figures. For example, if the device in one of the figures is flipped, the element described as being on the "lower" side of the other elements will be oriented to be on the "upper" side of the other elements. Therefore, the term "lower" can include both the orientations of "lower" and "upper", depending on the specific orientation of the figure. Similarly, if the device in one of the figures is flipped, the element described as being "below" or "below" the other elements will be oriented to be "above" the other elements. Therefore, the terms "below" and "below" can include both the orientations of the upper and lower parts.

[0037] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined as such herein.

[0038] The embodiments described herein should not be construed as being limited to the specific shapes of the regions illustrated herein, but rather include deviations in shape caused by, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. In addition, illustrated sharp corners may be rounded. Therefore, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions and are not intended to limit the scope of the claims.

[0039] Hereinafter, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0040] Figure 1 is a block diagram illustrating a display device 10 according to an embodiment. Figure 2 1 is a block diagram illustrating an example of a display panel 100 including first to N-th display regions DR[1] to DR[N].

[0041] refer to Figure 1 and Figure 2 , an embodiment of the display device 10 may include a display panel 100 and a display panel driver 700. The display panel driver 700 may include a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and an emission driver 600.

[0042] For example, in an embodiment, the driving controller 200 and the data driver 500 may be formed integrally with each other. For example, in an alternative embodiment, the driving controller 200, the gamma reference voltage generator 400, and the data driver 500 may be formed integrally with each other (e.g., integrally formed as a single module or circuit). For example, in an alternative embodiment, the driving controller 200, the gate driver 300, the gamma reference voltage generator 400, and the data driver 500 may be formed integrally with each other. For example, in an alternative embodiment, the driving controller 200, the gate driver 300, the gamma reference voltage generator 400, the data driver 500, and the emission driver 600 may be formed integrally with each other. A driving module in which at least the driving controller 200 and the data driver 500 are integrally formed may be referred to as a timing controller embedded data driver (TED).

[0043] The display panel 100 may include a display portion configured to display an image and a peripheral portion disposed adjacent to the display portion.

[0044] For example, in an embodiment, the display panel 100 may be an organic light emitting diode display panel including an organic light emitting diode. For example, in an alternative embodiment, the display panel 100 may be a quantum dot organic light emitting diode display panel including an organic light emitting diode and a quantum dot color filter. For example, in an alternative embodiment, the display panel 100 may be a quantum dot nano light emitting diode display panel including a nano light emitting diode and a quantum dot color filter. For example, in an alternative embodiment, the display panel 100 may be a liquid crystal display panel including a liquid crystal layer.

[0045] The display panel 100 may include gate lines GIL, GCL, and GWL, data lines DL, emission lines EL, and pixels PXL electrically connected to the gate lines GIL, GCL, and GWL, the data lines DL, and the emission lines EL. The gate lines GIL, GCL, and GWL may extend in a first direction D1, and the data lines DL may extend in a second direction D2 crossing the first direction D1.

[0046] In an embodiment, if Figure 2As shown in , the display panel 100 may include a first display area DR[1] to an Nth display area DR[N] (where N is an integer of 2 or greater). The first display area DR[1] to the Nth display area DR[N] may be arranged based on a first direction D1 (i.e., a row direction). In an embodiment, each of the first display area DR[1] to the Nth display area DR[N] may extend in a second direction D2, and the first display area DR[1] to the Nth display area DR[N] may be arranged sequentially in the first direction D1. The display panel 100 may perform a multi-frequency drive (MFD) in which the display areas are driven at different driving frequencies, respectively. For example, the display panel 100 may be driven at a first driving frequency in the first display area DR[1]. For example, the display panel 100 may be driven at a second driving frequency in the second display area DR[2]. For example, the display panel 100 may be driven at an Nth driving frequency in the Nth display area DR[N].

[0047] Return to reference Figure 1 , the driving controller 200 may receive input image data IMG and an input control signal CONT from an external device. For example, in an embodiment, the input image data IMG may include red image data, green image data, and blue image data. According to an embodiment, the input image data IMG may also include white image data. For example, in an alternative embodiment, the input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a main clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0048] The driving controller 200 may generate a first control signal CONT1 , a second control signal CONT2 , a third control signal CONT3 , a fourth control signal CONT4 , and a data signal DATA based on input image data IMG and an input control signal CONT.

[0049] The driving controller 200 may generate a first control signal CONT1 configured to control the operation of the gate driver 300 based on the input control signal CONT and output the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0050] The driving controller 200 may generate a second control signal CONT2 configured to control the operation of the data driver 500 based on the input control signal CONT, and output the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0051] The driving controller 200 may generate a data signal DATA based on the input image data IMG. The driving controller 200 may output the data signal DATA to the data driver 500.

[0052] The driving controller 200 may generate a third control signal CONT3 configured to control the operation of the gamma reference voltage generator 400 based on the input control signal CONT, and output the third control signal CONT3 to the gamma reference voltage generator 400 .

[0053] The driving controller 200 may generate a fourth control signal CONT4 configured to control the operation of the emission driver 600 based on the input control signal CONT, and output the fourth control signal CONT4 to the emission driver 600 .

[0054] The driving controller 200 may generate first to N-th display area control signals DRC[1] to DRC[N] (where N is an integer of 2 or more) configured to control the first to N-th frequencies, respectively, based on the input control signal CONT, and output the generated display area control signals to the first to N-th display areas DR[1] to DR[N], as shown in FIG. Figure 2 as shown in .

[0055] The gate driver 300 may generate a gate signal configured to drive the gate lines GIL, GCL, and GWL in response to the first control signal CONT1 received from the driving controller 200. The gate driver 300 may output the gate signal to the gate lines GIL, GCL, and GWL.

[0056] In an implementation, the gate driver 300 may be integrated on a peripheral portion of the display panel.

[0057] The gamma reference voltage generator 400 may generate a gamma reference voltage VGREF in response to the third control signal CONT3 received from the driving controller 200. The gamma reference voltage generator 400 may provide the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF may have a value corresponding to each data signal DATA.

[0058] In an implementation, the gamma reference voltage generator 400 may be provided in the driving controller 200 or in the data driver 500 .

[0059] The data driver 500 may receive the second control signal CONT2 and the data signal DATA from the driving controller 200, and receive the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 may convert the data signal DATA into an analog data voltage by using the gamma reference voltage VGREF. The data driver 500 may output the data voltage to the data line DL.

[0060] The emission driver 600 may generate an emission signal configured to drive the emission line EL in response to the fourth control signal CONT4 received from the driving controller 200. The emission driver 600 may output the emission signal to the emission line EL.

[0061] Figure 3 It is a graphic Figure 2 A conceptual diagram of the driving frequency of the display panel 100.

[0062] refer to Figures 1 to 3 , an embodiment of the display panel 100 may be driven at a variable frequency. A first frame FR1 having a first driving frequency may include a first active period AC1 and a first blank period BL1. A second frame FR2 having a second driving frequency different from the first driving frequency may include a second active period AC2 and a second blank period BL2. A third frame FR3 having a third driving frequency different from the first driving frequency and the second driving frequency may include a third active period AC3 and a third blank period BL3.

[0063] The first active period AC1 may have the same length as that of the second active period AC2 , and the first blank period BL1 may have a different length from that of the second blank period BL2 .

[0064] The second active period AC2 may have the same length as that of the third active period AC3 , and the second blank period BL2 may have a different length from that of the third blank period BL3 .

[0065] The display device supporting variable frequency may include a data writing period in which a data voltage is written to a pixel and a self-scanning period in which a data voltage is not written to a pixel and only light is emitted. The data writing period may be set in the first activation period AC1, the second activation period AC2, and the third activation period AC3. The self-scanning period may be set in the first blank period BL1, the second blank period BL2, and the third blank period BL3.

[0066] Figure 4 It is a graphic Figure 2A circuit diagram of a first pixel circuit PX in a Pth display region DR[P] and a Pth display region control circuit (including a first control transistor TC1[P] and a second control transistor TC2[P]). Figure 5 It is a graphic Figure 2 Circuit diagram of a first pixel circuit, a second pixel circuit and a P display area control circuit in the P display area.

[0067] refer to Figures 1 to 5 , in the Pth display region DR[P] (where P is an integer between 1 and N), as Figure 4 As shown in, a first pixel circuit PX and a P display area control circuit (including a first control transistor TC1[P] and a second control transistor TC2[P]) that applies a compensation gate signal GC to a gate electrode of a first pixel compensation transistor T3A of the first pixel circuit PX based on a P display area control signal DRC[P] (where P is an integer between 1 and N) may be included. In an embodiment, in the P display area DR[P], as shown in FIG. Figure 5 As shown in, a second pixel circuit PX+1 may also be included, and the Pth display area control circuit (including the first control transistor TC1[P] and the second control transistor TC2[P]) may apply the compensation gate signal GC to the gate electrode of the first pixel compensation transistor T3A of the first pixel circuit PX and the gate electrode of the second pixel compensation transistor T3B of the second pixel circuit PX+1 based on the Pth display area control signal DRC[P]. Figure 4 The display panel and Figure 5 The display panels are basically the same, except Figure 4 The display panel is connected to one pixel circuit of each display area control circuit in the same pixel row of the P-th display area DR[P], and Figure 5 The display panel is connected to multiple pixel circuits of each display area control circuit in the same pixel row of the P display area DR[P]. For example, in an alternative embodiment, in the same pixel row of the P display area DR[P], each display area control circuit may be connected to three pixel circuits. For example, in an alternative embodiment, in the same pixel row of the P display area DR[P], each display area control circuit may be connected to four pixel circuits. For example, in an alternative embodiment, in the same pixel row of the P display area DR[P], one display area control circuit may be connected to all pixel circuits in the same pixel row of the P display area DR[P]. In the following, for ease of description, the detailed description will be given. Figure 5 Embodiment of the display panel.

[0068] The Pth display area control circuit (including the first control transistor TC1[P] and the second control transistor TC2[P]) may apply the compensation gate signal GC to the gate electrode of the first pixel compensation transistor T3A and / or the gate electrode of the second pixel compensation transistor T3B.

[0069] In an embodiment, the first pixel circuit PX and the second pixel circuit PX+1 may be disposed adjacent to each other in the Pth display region DR[P] and in the same pixel row, ie, receive the same gate signal as each other.

[0070] The first pixel circuit PX may include a first pixel driving transistor T1A, a first pixel initialization transistor T4A configured to receive (or receive) an initialization voltage VINT, and a first pixel compensation transistor T3A connected in series to the first pixel initialization transistor T4A and connecting the first pixel driving transistor T1A and the first pixel initialization transistor T4A to each other based on a compensation gate signal GC.

[0071] The first pixel driving transistor T1A may include a gate electrode connected to the first pixel first node N1A, a first electrode connected to the first pixel second node N2A, and a second electrode connected to the first pixel third node N3A.

[0072] The first pixel compensation transistor T3A may include a gate electrode configured to receive a compensation gate signal GC based on the Pth display region control signal DRC[P], a first electrode connected to the first pixel third node N3A, and a second electrode connected to the first pixel first node N1A.

[0073] The first pixel initialization transistor T4A may include a gate electrode configured to receive the data initialization gate signal GI, a first electrode configured to receive the initialization voltage VINT, and a second electrode connected to the first pixel third node N3A.

[0074] The first pixel circuit PX may further include a first pixel light emitting element EEA configured to receive a first pixel driving current of the first pixel driving transistor T1A, a first pixel writing transistor T2A configured to apply a first pixel data voltage VDATA1 transmitted via a first pixel data line DL1 to a first electrode of the first pixel driving transistor T1A, a first pixel first light emitting transistor T5A configured to transmit a first power supply voltage ELVDD to the first electrode of the first pixel driving transistor T1A, a first pixel second light emitting transistor T6A configured to connect the second electrode of the first pixel driving transistor T1A to the anode electrode of the first pixel light emitting element EEA, a first pixel anode initialization transistor T7A configured to apply an anode initialization voltage VAINT to the anode electrode of the first pixel light emitting element EEA, a first pixel storage capacitor CSTA configured to store a voltage of a gate electrode of the first pixel driving transistor T1A, and a first pixel holding capacitor CHOLDA configured to store a first voltage of the first electrode of the first pixel driving transistor T1A.

[0075] The first pixel light emitting element EEA may include an anode electrode connected to the first pixel fourth node N4A and a cathode electrode configured to receive the second power supply voltage ELVSS.

[0076] The first pixel write transistor T2A may include a gate electrode configured to receive the data write gate signal GW, a first electrode configured to receive the first pixel data voltage VDATA1 , and a second electrode connected to the first pixel second node N2A.

[0077] The first pixel first light emitting transistor T5A may include a gate electrode configured to receive the emission signal EM, a first electrode configured to receive the first power voltage ELVDD, and a second electrode connected to the first pixel second node N2A.

[0078] The first pixel second light emitting transistor T6A may include a gate electrode configured to receive the emission signal EM, a first electrode connected to the first pixel third node N3A, and a second electrode connected to the first pixel fourth node N4A.

[0079] The first pixel anode initialization transistor T7A may include a gate electrode configured to receive the anode initialization gate signal GB, a first electrode configured to receive the anode initialization voltage VAINT, and a second electrode connected to the first pixel fourth node N4A.

[0080] In an embodiment, the first pixel driving transistor T1A, the first pixel writing transistor T2A, the first pixel first light emitting transistor T5A, the first pixel second light emitting transistor T6A and the first pixel anode initialization transistor T7A may be P-type transistors. In such an embodiment, the first pixel compensation transistor T3A and the first pixel initialization transistor T4A may be N-type transistors.

[0081] The first pixel storage capacitor CSTA may include a first electrode configured to receive the first power supply voltage ELVDD and a second electrode connected to the first pixel first node N1A.

[0082] The first pixel holding capacitor CHOLDA may include a first electrode configured to receive the first power supply voltage ELVDD and a second electrode connected to the first pixel second node N2A.

[0083] In an embodiment, the data write gate signal GW[M] may be an Mth data initialization gate signal, and the anode initialization gate signal GB[M] may be an M+Kth data initialization gate signal (wherein each of M and K is an integer of 1 or greater). In an embodiment, for example, K may be 1.

[0084] The second pixel circuit PX+1 may include a second pixel driving transistor T1B, a second pixel initialization transistor T4B configured to receive an initialization voltage VINT, and a second pixel compensation transistor T3B connected in series to the second pixel initialization transistor T4B and connecting the second pixel driving transistor T1B and the second pixel initialization transistor T4B to each other based on a compensation gate signal GC.

[0085] The second pixel driving transistor T1B may include a gate electrode connected to the second pixel first node N1B, a first electrode connected to the second pixel second node N2B, and a second electrode connected to the second pixel third node N3B.

[0086] The second pixel compensation transistor T3B may include a gate electrode configured to receive a compensation gate signal GC based on the Pth display region control signal DRC[P], a first electrode connected to the second pixel third node N3B, and a second electrode connected to the second pixel first node N1B.

[0087] The second pixel initialization transistor T4B may include a gate electrode configured to receive the data initialization gate signal GI, a first electrode configured to receive the initialization voltage VINT, and a second electrode connected to the second pixel third node N3B.

[0088] The second pixel circuit PX+1 may further include a second pixel light emitting element EEB configured to receive a second pixel driving current of the second pixel driving transistor T1B, a second pixel write transistor T2B configured to apply a second pixel data voltage VDATA2 transmitted via the second pixel data line DL2 to the first electrode of the second pixel driving transistor T1B, a second pixel first light emitting transistor T5B configured to transmit the first power supply voltage ELVDD to the first electrode of the second pixel driving transistor T1B, a second pixel second light emitting transistor T6B configured to connect the second electrode of the second pixel driving transistor T1B to the anode electrode of the second pixel light emitting element EEB, a second pixel anode initialization transistor T7B configured to apply an anode initialization voltage VAINT to the anode electrode of the second pixel light emitting element EEB, a second pixel storage capacitor CSTB configured to store a voltage of the gate electrode of the second pixel driving transistor T1B, and a second pixel holding capacitor CHOLDB configured to store a voltage of the first electrode of the second pixel driving transistor T1B.

[0089] The second pixel light emitting element EEB may include an anode electrode connected to the second pixel fourth node N4B and a cathode electrode configured to receive the second power supply voltage ELVSS.

[0090] The second pixel write transistor T2B may include a gate electrode configured to receive the data write gate signal GW, a first electrode configured to receive the second pixel data voltage VDATA2 , and a second electrode connected to the second pixel second node N2B.

[0091] The second pixel first light emitting transistor T5B may include a gate electrode configured to receive the emission signal EM, a first electrode configured to receive the first power voltage ELVDD, and a second electrode connected to the second pixel second node N2B.

[0092] The second pixel second light emitting transistor T6B may include a gate electrode configured to receive the emission signal EM, a first electrode connected to the second pixel third node N3B, and a second electrode connected to the second pixel fourth node N4B.

[0093] The second pixel anode initialization transistor T7B may include a gate electrode configured to receive the anode initialization gate signal GB, a first electrode configured to receive the anode initialization voltage VAINT, and a second electrode connected to the second pixel fourth node N4B.

[0094] In an embodiment, the second pixel driving transistor T1B, the second pixel writing transistor T2B, the second pixel first light emitting transistor T5B, the second pixel second light emitting transistor T6B and the second pixel anode initialization transistor T7B may be P-type transistors. In such an embodiment, the second pixel compensation transistor T3B and the second pixel initialization transistor T4B may be N-type transistors.

[0095] The second pixel storage capacitor CSTB may include a first electrode configured to receive the first power supply voltage ELVDD and a second electrode connected to the second pixel first node N1B.

[0096] The second pixel holding capacitor CHOLDB may include a first electrode configured to receive the first power voltage ELVDD and a second electrode connected to the second pixel second node N2B.

[0097] The Pth display area control circuit may include a first control transistor TC1[P] and a second control transistor TC2[P], the first control transistor TC1[P] including a gate electrode configured to receive a Pth display area control signal DRC[P], a first electrode configured to receive a high gate voltage VGH, and a second electrode connected to the gate electrode of the first pixel compensation transistor T3A and the gate electrode of the second pixel compensation transistor T3B, the second control transistor TC2[P] including a gate electrode configured to receive the Pth display area control signal DRC[P], a first electrode configured to receive a low gate voltage VGL, and a second electrode connected to the gate electrode of the first pixel compensation transistor T3A and the gate electrode of the second pixel compensation transistor T3B.

[0098] In an embodiment, the first control transistor TC1[P] may be a P-type transistor, and the second control transistor TC2[P] may be an N-type transistor. Alternatively, the first control transistor TC1[P] may be an N-type transistor, and the second control transistor TC2[P] may be a P-type transistor.

[0099] In an embodiment, as described above, the Pth display area control circuit (including the first control transistor TC1[P] and the second control transistor TC2[P]) can output the compensation gate signal GC to the gate electrode of the first pixel compensation transistor T3A and the gate electrode of the second pixel compensation transistor T3B based on the Pth display area control signal DRC[P].

[0100] Figure 6 The figure shows that when the driving frequency of the display panel 100 is 240 Hz Figure 4 and Figure 5 1 is a timing diagram of the driving signal of the pixel PXL.

[0101] The timing diagram of the gate signal of the first pixel circuit PX and the timing diagram of the gate signal of the second pixel circuit PX+1 are substantially the same as each other. Therefore, for the convenience of illustration and description, the timing diagram of the gate signal of the first pixel circuit PX will be described as an example, and the timing diagram of the gate signal of the second pixel circuit PX+1 will be omitted.

[0102] In an embodiment, when the driving frequency of the display panel 100 is the maximum driving frequency, one data write operation and one self-scanning operation may be performed during a frame period, and when the driving frequency of the display panel 100 is not the maximum driving frequency, one data write operation and at least two self-scanning operations may be performed during a frame period.

[0103] like Figure 6 As shown in , the display panel 100 can be driven at a variable frequency, for example, at a maximum of 240 Hz. When the display panel 100 is driven at 240 Hz, the light emitting operation of the first pixel light emitting element EEA can be performed at 480 Hz, the threshold voltage compensation operation of the first pixel driving transistor T1A can be performed at 240 Hz, the initialization operation of the anode electrode of the first pixel light emitting element EEA can be performed at 240 Hz, and the initialization operation of the gate electrode of the first pixel driving transistor T1A can be performed at 240 Hz.

[0104] When the display panel 100 is driven at 240Hz, the data write gate signal GW and the anode initialization gate signal GB may have an activation pulse in each of the first period P1 to the eighth period P8. Here, each of the first period P1 to the eighth period P8 may be a period of light emitting operation of the pixel, which is half of the frame period of the display panel when driven at the maximum driving frequency. Therefore, in such an embodiment, when the display panel 100 is driven at 240Hz, the data initialization gate signal GI and the compensation gate signal GC may have an activation pulse only in the first period P1, the third period P3, the fifth period P5, and the seventh period P7. Therefore, the data write operation may be performed only in the first period P1, the third period P3, the fifth period P5, and the seventh period P7.

[0105] In the embodiment, as described above, when the display panel 100 is driven at 240 Hz and the light emitting operation is driven at 480 Hz, it can be said that the display panel 100 operates at 2 cycles.

[0106] When the display panel 100 is driven at 120 Hz, the light emitting operation of the first pixel light emitting element EEA may be performed at 480 Hz, the threshold voltage compensation operation of the first pixel driving transistor T1A may be performed at 120 Hz, the initialization operation of the anode electrode of the first pixel light emitting element EEA may be performed at 120 Hz, and the initialization operation of the gate electrode of the first pixel driving transistor T1A may be performed at 120 Hz.

[0107] When the display panel 100 is driven at 120 Hz, the data write gate signal GW and the anode initialization gate signal GB may have an activation pulse in each of the first period P1 to the eighth period P8. However, the data initialization gate signal GI and the compensation gate signal GC may have an activation pulse only in the first period P1 and the fifth period P5. Therefore, the data write operation may be performed only in the first period P1 and the fifth period P5.

[0108] In such an embodiment, as described above, when the display panel 100 is driven at 120 Hz and the light emitting operation is driven at 480 Hz, it can be said that the display panel 100 operates in 4 cycles.

[0109] Figure 7 is a timing chart illustrating an example of a gate signal in a data writing period. Figure 8 is a timing chart illustrating an example of a gate signal in a self-scan period.

[0110] refer to Figures 1 to 8 , the display device 10 supporting a variable frequency (or operable in a variable frequency) may include a data writing period in which a data voltage is written to a pixel and a self-scanning period in which a data voltage is not written to the pixel and only light is emitted.

[0111] In an embodiment, if Figure 7 As shown in , when a data write operation is performed, each of the data initialization gate signal GI, the compensation gate signal GC, the data write gate signal GW, the anode initialization gate signal GB, and the emission signal EM may include at least one turn-on voltage period.

[0112] Since the first pixel first light emitting transistor T5A and the first pixel second light emitting transistor T6A are turned off in the period in which the emission signal EM has the disable level, the first pixel light emitting element EEA may not emit light. When the emission signal EM is changed to the activation level, the first pixel first light emitting transistor T5A and the first pixel second light emitting transistor T6A are turned on, so that the first pixel light emitting element EEA can emit light.

[0113] The data initialization gate signal GI may be applied to the gate electrode of the first pixel initialization transistor T4A. Since the first pixel initialization transistor T4A is turned on when the data initialization gate signal GI is at an active level, the initialization voltage VINT may be applied to the second electrode of the first pixel driving transistor T1A through the first pixel initialization transistor T4A.

[0114] The compensation gate signal GC may be applied to the gate electrode of the first pixel compensation transistor T3A. Since the first pixel compensation transistor T3A is turned on when the compensation gate signal GC is at an active level, the threshold voltage of the first pixel driving transistor T1A may be compensated by the first pixel compensation transistor T3A.

[0115] A portion of the on-voltage period of the data initialization gate signal GI and a portion of the on-voltage period of the compensation gate signal GC may overlap with each other. When a portion of the on-voltage period of the data initialization gate signal GI and a portion of the on-voltage period of the compensation gate signal GC overlap with each other (i.e., when the data initialization gate signal GI and the compensation gate signal GC are simultaneously at an activation level), an initialization operation of the gate electrode of the first pixel driving transistor T1A may be performed. When the data initialization gate signal GI and the compensation gate signal GC are simultaneously at an activation level, the first pixel compensation transistor T3A and the first pixel initialization transistor T4A may be turned on, and the initialization voltage VINT may be applied to the gate electrode of the first pixel driving transistor T1A through the first pixel compensation transistor T3A and the first pixel initialization transistor T4A.

[0116] The data write gate signal GW may be applied to the gate electrode of the first pixel write transistor T2A. When the data write gate signal GW is at an active level, the first pixel write transistor T2A may be turned on and the first pixel data voltage VDATA1 may be applied to the first pixel second node N2A through the first pixel write transistor T2A.

[0117] The anode initialization gate signal GB may be applied to the gate electrode of the first anode initialization transistor T7A. When the anode initialization gate signal GB is at an activation level, the first anode initialization transistor T7A may be turned on, and the anode initialization voltage VAINT may be applied to the anode electrode of the first pixel light emitting element EEA through the first anode initialization transistor T7A.

[0118] In an embodiment, if Figure 8 As shown in , when performing a self-scan operation, each of the data write gate signal GW, the anode initialization gate signal GB, and the emission signal EM may include at least one on-voltage period, and each of the data initialization gate signal GI and the compensation gate signal GC may not include an on-voltage period.

[0119] Since the data writing gate signal GW and the anode initialization gate signal GB have two activation pulses, the data writing operation and the initialization operation of the anode electrode of the first pixel light emitting element EEA can be performed twice. Figure 8 , the data write gate signal GW and the anode initialization gate signal GB are illustrated as having two activation pulses, but the present disclosure is not limited thereto. Alternatively, the data write gate signal GW and the anode initialization gate signal GB may have one activation pulse or three or more activation pulses.

[0120] because Figure 8 The self-scan period is shown, so the data initialization gate signal GI, the compensation gate signal GC and the data writing gate signal GW may have Figure 8 For example, the disable level of the data initialization gate signal GI and the compensation gate signal GC may be a low level, and the disable level of the data write gate signal GW may be a high level.

[0121] The anode initialization gate signal GB may have an activation level. When the anode initialization gate signal GB is at the activation level, the first anode initialization transistor T7A may be turned on, and the anode initialization voltage VAINT may be applied to the anode electrode of the first pixel light emitting element EEA through the first anode initialization transistor T7A.

[0122] In an embodiment, as described above, the display panel 100 may include a first display region DR[1] to an Nth display region DR[N] arranged in a row direction. The Pth display region DR[P] may include a first pixel circuit PX, the first pixel circuit PX including a first pixel driving transistor T1A, a first pixel initialization transistor T4A configured to receive an initialization voltage VINT, and a first pixel compensation transistor T3A configured to connect the first pixel driving transistor T1A and the first pixel initialization transistor T4A based on a compensation gate signal GC. In such an embodiment, the Pth display region DR[P] may include a first control transistor TC1[P] configured to output a high gate voltage VGH of the compensation gate signal GC and a second control transistor TC2[P] configured to output a low gate voltage VGL of the compensation gate signal GC. The first control transistor TC1[P] and the second control transistor TC2[P] may be controlled based on the Pth display region control signal DRC[P]. Therefore, the display device 10 may drive the display regions arranged to be adjacent to each other in the row direction at different driving frequencies, respectively.

[0123] In such an embodiment, the first pixel compensation transistor T3A can be connected in series to the first pixel initialization transistor T4A. Therefore, the display device 10 can adjust the compensation gate signal GC based on the Pth display area control signal DRC[P] to drive the display areas arranged to be adjacent to each other in the row direction at different driving frequencies.

[0124] Fig. 9 is a block diagram illustrating an electronic device 1000 according to an embodiment. Fig.10 It is a diagram showing Fig. 9 The electronic device 1000 is implemented as a smart phone.

[0125] refer to Fig. 9 and Fig.10 , an embodiment of the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be Figure 1 In addition, the electronic device 1000 may further include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, and the like.

[0126] In an embodiment, if Fig.10 As shown in , the electronic device 1000 may be implemented as a smart phone. However, the electronic device 1000 is not limited thereto. For example, in alternative embodiments, the electronic device 1000 may be implemented as a cellular phone, a video phone, a smart tablet, a smart watch, a tablet personal computer (PC), a car navigation system, a computer monitor, a laptop computer, a head mounted display (HMD) device, etc.

[0127] The processor 1010 may perform various computing functions. The processor 1010 may be a microprocessor, a central processing unit (CPU), an application processor (AP), etc. The processor 1010 may be coupled to other components via an address bus, a control bus, a data bus, etc. In addition, the processor 1010 may be coupled to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0128] The memory device 1020 may store data for operation of the electronic device 1000. For example, the memory device 1020 may include at least one nonvolatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc. and / or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, etc.

[0129] The storage device 1030 may include a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, or the like.

[0130] I / O devices 1040 may include input devices such as a keyboard, a keypad, a mouse device, a touch pad, a touch screen, etc. and output devices such as a printer, a speaker, etc. In some embodiments, I / O devices 1040 may include a display device 1060 .

[0131] The power supply 1050 may provide power for the operation of the electronic device 1000 .

[0132] Display device 1060 may be connected to other components via a bus or other communication links.

[0133] The embodiments of the present application can be applied to any display device and any electronic device including a touch panel. For example, the embodiments of the present application can be applied to mobile phones, smart phones, tablet computers, digital televisions (TVs), three-dimensional (3D) TVs, PCs, home appliances, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, music players, portable game consoles, navigation devices, etc.

[0134] The present application should not be interpreted as being limited to the embodiments set forth herein. Instead, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the concept of the present application to those skilled in the art.

[0135] While the present application has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit or scope of the present application as defined by the appended claims.

Claims

1. A display panel, characterized in that: include: The first display area to the Nth display area are arranged in the row direction, wherein N is an integer of 2 or more, The display panel further includes a P-th display area, wherein P is an integer between 1 and N, and the P-th display area includes: a first pixel circuit, the first pixel circuit comprising a first pixel driving transistor, a first pixel initialization transistor receiving an initialization voltage, and a first pixel compensation transistor connected in series to the first pixel initialization transistor, wherein the first pixel compensation transistor connects the first pixel driving transistor and the first pixel initialization transistor to each other based on a compensation gate signal; as well as The Pth display area control circuit comprises a first control transistor which outputs a high gate voltage of the compensation gate signal and a second control transistor which outputs a low gate voltage of the compensation gate signal, wherein the first control transistor and the second control transistor are controlled based on the Pth display area control signal.

2. The display panel according to claim 1, characterized in that: The first control transistor includes a gate electrode receiving the P display area control signal, a first electrode receiving the high gate voltage, and a second electrode connected to the gate electrode of the first pixel compensation transistor, and The second control transistor includes a gate electrode receiving the Pth display area control signal, a first electrode receiving the low gate voltage, and a second electrode connected to the gate electrode of the first pixel compensation transistor.

3. The display panel according to claim 1, characterized in that: The Pth display area further includes a second pixel circuit, The second pixel circuit is arranged to be adjacent to the first pixel circuit in the same pixel row, and includes a second pixel driving transistor, a second pixel initialization transistor receiving the initialization voltage, and a second pixel compensation transistor connected in series to the second pixel initialization transistor, wherein the second pixel compensation transistor connects the second pixel driving transistor and the second pixel initialization transistor to each other based on the compensation gate signal.

4. The display panel according to claim 3, characterized in that: The first control transistor includes a gate electrode receiving the P display area control signal, a first electrode receiving the high gate voltage, and a second electrode connected to the gate electrode of the first pixel compensation transistor and the gate electrode of the second pixel compensation transistor, and The second control transistor includes a gate electrode receiving the Pth display area control signal, a first electrode receiving the low gate voltage, and a second electrode connected to the gate electrode of the first pixel compensation transistor and the gate electrode of the second pixel compensation transistor.

5. The display panel according to claim 1, characterized in that: The first pixel circuit further includes: a first pixel light emitting element, the first pixel light emitting element receiving a first pixel driving current of the first pixel driving transistor; a first pixel write transistor that applies a first pixel data voltage to a first electrode of the first pixel drive transistor; a first light emitting transistor of a first pixel, wherein the first light emitting transistor of the first pixel transmits a first power supply voltage to the first electrode of the first pixel driving transistor; a first pixel second light emitting transistor, wherein the first pixel second light emitting transistor connects the second electrode of the first pixel driving transistor to the anode electrode of the first pixel light emitting element; a first pixel anode initialization transistor, the first pixel anode initialization transistor applying an anode initialization voltage to the anode electrode of the first pixel light emitting element; a first pixel storage capacitor storing a voltage of a gate electrode of the first pixel driving transistor; and A first pixel holding capacitor stores a voltage of the first electrode of the first pixel driving transistor.

6. The display panel according to claim 5, characterized in that: The first pixel light emitting element includes the anode electrode connected to the fourth node of the first pixel and a cathode electrode receiving a second power supply voltage, The first pixel driving transistor includes the gate electrode connected to the first node of the first pixel, the first electrode connected to the second node of the first pixel, and the second electrode connected to the third node of the first pixel, The first pixel write transistor includes a gate electrode receiving a data write gate signal, a first electrode receiving the first pixel data voltage, and a second electrode connected to the second node of the first pixel. The first pixel compensation transistor includes a gate electrode receiving a compensation gate signal based on the P display area control signal, a first electrode connected to the third node of the first pixel, and a second electrode connected to the first node of the first pixel. The first pixel initialization transistor includes a gate electrode receiving a data initialization gate signal, a first electrode receiving the initialization voltage, and a second electrode connected to the third node of the first pixel. The first light emitting transistor of the first pixel includes a gate electrode receiving an emission signal, a first electrode receiving the first power supply voltage, and a second electrode connected to the second node of the first pixel. The second light emitting transistor of the first pixel includes a gate electrode receiving the emission signal, a first electrode connected to the third node of the first pixel, and a second electrode connected to the fourth node of the first pixel. The first pixel anode initialization transistor includes a gate electrode receiving an anode initialization gate signal, a first electrode receiving the anode initialization voltage, and a second electrode connected to the fourth node of the first pixel. The first pixel storage capacitor includes a first electrode receiving the first power supply voltage and a second electrode connected to the first pixel first node, and The first pixel holding capacitor includes a first electrode receiving the first power supply voltage and a second electrode connected to a second node of the first pixel.

Images