Semiconductor device

Abstract

A semiconductor device includes a redistribution layer configured to redistribute a plurality of connectors of a semiconductor die, wherein the redistribution layer includes a plurality of conductive pads embedded in a dielectric material. The redistribution layer includes a first conductive pad including a first boundary dimension, a second conductive pad including a second boundary dimension, and at least one conductive line perpendicular to a minimum distance between the first boundary dimension and the second boundary dimension.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, such integration density improvements come from the repeated reduction of minimum feature size (e.g., shrinking semiconductor process nodes towards sub-nanometer nodes), which enables more components to be integrated into a given area. The increasing demand for miniaturization, faster speed, greater bandwidth, lower power consumption, and lower latency of semiconductor devices requires smaller and more innovative packaging technologies for semiconductor devices. Utility Model Content

[0003] According to some embodiments of the present disclosure, a semiconductor device includes a redistribution layer configured to redistribute a connector of a semiconductor die, wherein the redistribution layer includes a plurality of conductive pads embedded in a dielectric material. The redistribution layer includes a first conductive pad, a second conductive pad, and at least one conductive line, wherein the first conductive pad includes a first boundary dimension, the second conductive pad includes a second boundary dimension, and the at least one conductive line is perpendicular to a minimum distance between the first boundary dimension and the second boundary dimension.

[0004] According to some embodiments of the present disclosure, a semiconductor device includes a metallization layer, a first conductive line, and a second conductive line. The metallization layer includes a plurality of conductive pads embedded in a dielectric material, wherein the conductive pads include a first conductive pad and a second conductive pad, the first conductive pad includes a first boundary, and the second conductive pad includes a second boundary. The first conductive line extends perpendicular to a minimum distance between the first boundary and the second boundary. The second conductive line extends perpendicular to the minimum distance between the first boundary and the second boundary and parallel to the first conductive line.

[0005] According to some embodiments of the present disclosure, a semiconductor device includes a redistribution layer, wherein the redistribution layer includes a plurality of conductive pads embedded in a dielectric material, the conductive pads including a first conductive pad bounded by a first boundary along a lateral plane and a second conductive pad bounded by a second boundary along the lateral plane. The semiconductor device includes a conductive wire located between the first conductive pad and the second conductive pad, wherein the conductive wire extends along the lateral plane and perpendicular to a minimum distance between the first boundary and the second boundary. A first connection of the conductive wire is defined at a first terminal of the conductive wire, the first connection corresponds to a net line of a netlist, and a second connection of the conductive wire is defined at a second terminal of the conductive wire, the second terminal is relative to the first terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard methods in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 A schematic diagram illustrating an example redistribution structure according to some embodiments;

[0008] Figure 2 Another schematic diagram illustrating an example redistribution structure according to some embodiments;

[0009] Figure 3A , Figure 3B and Figure 3C A schematic diagram illustrating an example conductive pad pair under operation of routing a conductive line between the conductive pad pairs according to some embodiments;

[0010] Figure 4A , Figure 4B and Figure 4C Another schematic diagram illustrating an example conductive pad pair under operation of routing a conductive line between the conductive pad pairs according to some embodiments;

[0011] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Fig. 5F , Figure 5G , Figure 5H , Fig.5I and Figure 5J A top view of a plurality of conductive pad pairs and respective routes between the conductive pad pairs is depicted according to some embodiments;

[0012] Figure 6 is a detailed view of a conductive pad pair according to some embodiments, wherein the conductive pad pair has multiple routes between them;

[0013] Fig. 7A , Figure 7B and Figure 7C is a detailed view of a conductive pad pair according to some embodiments, wherein the conductive pad pair has a plurality of conductive elements therebetween;

[0014] Figure 8 is a flow chart of a method of forming or manufacturing a semiconductor device according to some embodiments;

[0015] Fig. 9 A flow chart of a method for manufacturing a semiconductor device is shown according to some embodiments;

[0016] Fig.10 A block diagram of a system for generating a layout design is shown according to some embodiments;

[0017] Fig.11 A block diagram of a manufacturing system and a manufacturing process related to the manufacturing system are shown according to some embodiments.

[0018]

Explanation of symbols

[0019] 099: Axis

[0020] 100: Redistribution structure

[0021] 102: first conductive pad

[0022] 104: second conductive pad

[0023] 106: The First Border

[0024] 108: The Second Frontier

[0025] 110:Through hole

[0026] 112:Through hole

[0027] 114: Minimum distance

[0028] 114A: First minimum distance

[0029] 114B: Second shortest distance

[0030] 116:Thickness

[0031] 118: Gap

[0032] 120: Parallel distance

[0033] 122: Wire

[0034] 124:Route

[0035] 126: Advanced dimension line

[0036] 202: first conductive element

[0037] 204: second conductive element

[0038] 206: Clock signal line

[0039] 208: Data signal line

[0040] 300: Schematic diagram

[0041] 302: first through hole

[0042] 304: Second through hole

[0043] 306: first conductive element

[0044] 308: second conductive element

[0045] 400: Schematic diagram

[0046] 402: first conductive pad

[0047] 404: second conductive pad

[0048] 406: third conductive pad

[0049] 408: fourth conductive pad

[0050] 410: fifth conductive pad

[0051] 412:Signal line / conductive element

[0052] 600: Detail

[0053] 702: First signal line

[0054] 704: Second signal line

[0055] 706: Third signal line

[0056] 708: First signal line

[0057] 710: Second signal line

[0058] 800: Method

[0059] 802,804,806,808: Steps

[0060] 900: Method

[0061] 910,920: Steps

[0062] 1000:System

[0063] 1002: Processor

[0064] 1004: Computer readable storage medium

[0065] 1006: Computer program code

[0066] 1008: Bus

[0067] 1010:I / O interface

[0068] 1012: Network interface

[0069] 1014: Network

[0070] 1016:Layout Design

[0071] 1018: User Interface

[0072] 1020: Manufacturing unit

[0073] 1022: Manufacturing Tools

[0074] 1100: System

[0075] 1120: Design Studio

[0076] 1122: Integrated Circuit Design Layout

[0077] 1130: Masking Room

[0078] 1132: Mask data preparation

[0079] 1134:Mask Manufacturing

[0080] 1140: Integrated Circuit Manufacturing Plant

[0081] 1142:Semiconductor Wafer

[0082] 1160: Integrated circuit device

[0083] d: distance

[0084] X,Y: Direction DETAILED DESCRIPTION

[0085] In order to realize the different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. Specific examples of components, configurations, etc. are described below to simplify the present disclosure. Of course, these are merely examples and are not restrictive. For example, in the following description, forming a first feature on or above a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0086] Furthermore, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein to facilitate describing one element or feature's relationship to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0087] Generally speaking, a semiconductor device may include interlayer vias to form connections between multiple layers. The vias include or interface with conductive pads, and the vias may include keep out areas or be surrounded by keep out areas. Interlayer connections may include dense connections, making it difficult to route a netlist of the semiconductor device. Other conductive pads may also be on multiple layers of the semiconductor device, which may further restrict routing. For example, multiple signal lines such as power signal lines, data signal lines, clock signal lines, or the like may be associated with multiple signal integrity parameters, where the signal integrity parameters may correspond to the geometry of the conductive elements. For example, the resistivity of the power signal line or the characteristic impedance of the data line may correspond to the line thickness or the gap between the differential pairs, the distance to the ground plane, etc. Some conductive pads or other features of the layers of the semiconductor device (such as the redistribution layer) may include courses between each other so that the wires can pass through the courses. However, the perimeter of the conductive pad may not correspond to the center of the conductive pad, so when routing wires between intermediate points of the routing device, the routing distance can be reduced relative to the routing between the perimeters of the conductive pads. The systems and methods disclosed herein can determine the routing between the outer perimeters of at least two conductive pads or the exclusion zone associated therewith, thereby increasing the number of nets or wire thicknesses routed between the conductive pads relative to other systems and methods.

[0088] According to various embodiments, Figure 1 A cross-sectional view of an exemplary redistribution structure 100 is shown. The cross-sectional view may be along a transverse plane according to the z-axis of the semiconductor device, wherein the transverse plane may be described with reference to a plane axis 099 having an X-direction and a Y-direction. It should be understood that the cross-sectional view may be simplified for ease of illustration. Figure 1 The redistribution structure 100. Therefore, the transverse plane may include a number of any other components or features and still be within the scope of the present disclosure.

[0089] As shown, the redistribution structure 100 includes a first conductive pad 102 laterally delimited (e.g., defined) by a first boundary 106, and a second conductive pad 104 laterally delimited (e.g., defined) by a second boundary 108. The first conductive pad 102 and the second conductive pad 104 may be or may include a through hole 110, a through hole 112 (e.g., a through-interlayer-via (TIV), a terminal connector, or other element) between adjacent or non-adjacent lateral planes of the semiconductor device. For example, the first conductive pad 102 and the second conductive pad 104 may be configured to be electrically connected to the first interlayer via 110 and the second interlayer via 112, respectively. A plurality of conductive lines 122 are disposed between the first conductive pad 102 and the second conductive pad 104 according to directions described later.

[0090] An electronic design automation (EDA) tool may determine a route between a first conductive pad 102 and a second conductive pad 104. The route 124 crosses a minimum distance 114 between the first conductive pad 102 and the second conductive pad 104. More specifically, the minimum distance 114 extends between individual first boundaries 106 and second boundaries 108. As shown, such a minimum distance 114 is less than a distance between individual boundaries, where the distance between the boundaries is defined by a route between a midpoint of the first conductive pad 102 and a midpoint of the second conductive pad 104. More generally, for a non-circular plurality of conductive pads, the minimum distance between the boundaries of the first conductive pad 102 and the second conductive pad 104 may be different from the minimum distance between the midpoints. The minimum distance 114 separates the first conductive pad 102 and the second conductive pad 104 by a parallel distance 120. As shown, the parallel distance 120 is an overlap distance along the X direction of the axis 099. In various embodiments, parallel distance 120 may include a Y-direction component of axis 099, or may include more than one minimum distance or a distance variation less than a threshold, such as Figure 6 Further described.

[0091] The EDA tool may compare the minimum distance 114 with the maximum distance, wherein the maximum distance may not be a distance constrained by routing. For example, the EDA tool may compare the gap between the first conductive pad 102 and the second conductive pad 104 and a threshold value, so that the wire 122 within the minimum distance 114 may be defined for a minimum distance 114 less than the threshold value, while the wire 122 within the minimum distance 114 may not be defined for a minimum distance 114 greater than the threshold value. Such a threshold value may avoid the formation of redundant wires between separated conductive pads, wherein redundant conduction may cause routing difficulties or consume computing resources (e.g., increase memory and processor loops and increase energy usage). For some processes, such a threshold value may be between about 10 microns and about 100 microns. It will be appreciated by those skilled in the art that different threshold values ​​may be used for processes based on the number of connections, connection density, and similar conditions.

[0092] Further dimensional lines 126 in the drawings are along a direction perpendicular to route 124. The EDA tool can cause the conductive line 122 to extend along the further dimensional line 126 and perpendicularly across the route. The conductive line 122 is shown extending along a parallel distance 120. In various embodiments, the conductive line 122 can extend longer or shorter than the parallel distance 120. For example, the conductive line 122 can extend a predetermined distance equal to the thickness 116, where the thickness 116 can correspond to the minimum dimension of the process. In various embodiments, the minimum distance that the conductive line 122 can extend is greater than the parallel distance 120, such as a distance that deviates from the parallel distance 120 (e.g., 2 microns, 5 microns, or the like). In various embodiments, the conductive line 122 can extend to snap to a predetermined grid describing a semiconductor device layer (e.g., a redistribution layer). The EDA tool can cause the conductive tool to extend to a variety of lengths described herein depending on the process, settings, user selection, or the like.

[0093] In various embodiments, the conductive lines 122 may have regular thicknesses 116 and gaps 118, for example, based on process dimensions associated with the semiconductor device. For example, the route between the first conductive pad 102 and the second conductive pad 104 extends 26 microns, and each conductive line 122 has a minimum line thickness of 2 microns and a gap of 2.5 microns, thereby defining the five conductive lines 122 shown (e.g., N(2.5 microns+2 microns)+2.5 microns resolves to a maximum integer N of 5).

[0094] The multiple elements of the redistribution structure 100 can be physically assembled devices (e.g., copper or tungsten conductive elements overlying a dielectric layer of a semiconductor device), or representations generated by an EDA tool. For example, an EDA tool can define the feature sizes described herein, and a manufacturing system and device can then manufacture the device based on the design generated by the EDA tool. Fig. 9 , Fig.10 and Fig.11 Example flows are provided. The connections described herein may include connections formed by the same process (e.g., a metal deposition or etching process followed by a dielectric formation above such that the remaining metal portion is embedded within the dielectric material). For example, the formation of conductive pads, wires, and more conductive elements connecting signal lines may be based on a process that simultaneously forms multiple metal portions of a redistribution layer. Such a process still forms the various portions and connections between the portions. In practice, the multiple processes disclosed herein may be performed in a variety of sequences, including sequences that briefly overlap (i.e., simultaneously).

[0095] According to various embodiments, Figure 2 A cross-sectional view of an exemplary redistribution structure 100 is shown, wherein the redistribution structure 100 is connected to a plurality of nets of a netlist. Figure 1 The redistribution structure 100 is a redistribution structure 100, and the conductor 122 is connected to a plurality of nets of a netlist. The netlist may include circuit logical connections of a semiconductor device. For example, the netlist may include connections between at least one semiconductor die and its contact pads. The netlist may include a plurality of signal line types associated with a plurality of geometries. For example, a clock signal line may be associated with a routing requirement for a minimum distance for a high-speed data signal line, a power signal line may be associated with a routing requirement corresponding to a resistivity of a plurality of conductive element lengths and thicknesses 116, or the like.

[0096] The conductors 122 may be connected to a plurality of conductive elements corresponding to the netlist design. For example, the netlist may include a differential pair, wherein the differential pair includes a first conductive element 202 and a second conductive element 204 having a predetermined spatial relationship. The conductive elements may include one or more clock signal lines 206, data signal lines 208, or other nets of the netlist. A plurality of signal lines may connect opposite ends of the conductors to combine multiple portions of a semiconductor device. For example, a plurality of signal lines may be connected to or connect semiconductor dies, terminals, integrated passive devices, and the like. The connections may be continued to through-hole contact pads or the like to form connections between levels of a redistribution layer or between other levels of a semiconductor device.

[0097] Some of the wires 122 may not be connected to the nets of the netlist. For example, the gap shown between the first conductive pad 102 and the second conductive pad 104 includes five wires 122, but the router of the EDA tool may set a netlist with less than five nets (e.g., four nets as shown) to pass between the first conductive pad 102 and the second conductive pad 104. The unset wires 122 may be pruned (e.g., removed or otherwise marked in the design file of the EDA tool), thereby causing a gap 118 that exceeds the minimum gap. In some embodiments, another wire 122 may be adjusted based on the increased gap. For example, a signal line that is susceptible to noise may be placed, or the size of a signal line (e.g., a power signal line) may be increased to reduce resistance loss, while occupying at least a portion of the gap vacated by pruning the wires 122.

[0098] According to some embodiments, Figure 3A A schematic diagram 300 is shown of an example conductive pad pair under operation of routing a conductor between the conductive pad pair. The first conductive pad 102, the second conductive pad 104, and the plurality of depicted features may be logically formed (e.g., materialized) by an EDA tool and then mechanically formed by a back-end manufacturing facility. Each of the first conductive pad 102 and the second conductive pad 104 is configured to receive a first via 302 and a second via 304. For example, the first via 302 may extend upward through the semiconductor device to another layer, and the second via 304 may extend downward through the semiconductor device to another layer. The route 124 may extend in the illustrated layer and may extend along an axis defined between a first boundary 106 of the first conductive pad 102 and a second boundary 108 of the second conductive pad 104 based on the location of the conductive pads. In the depicted embodiment, the route 124 extends from a convex portion of the first boundary 106 to a convex portion of the second boundary 108, such that the route extends along a single point. In other words, the parallel distance 120 is zero.

[0099] The step dimension line 126 may extend perpendicular to the route 124. For example, the step dimension line 126 may be in the middle of the first conductive pad 102 and the second conductive pad 104. In some embodiments, the step dimension line 126 may be aligned with the middle point of the minimum distance 114 between the first conductive pad 102 and the second conductive pad 104. In some embodiments, the first and second step dimension lines 126, 126 may intersect the route 124 at the boundaries of each of the first and second conductive pads 102, 104, defining a rectangular area where the conductive line 122 is formed.

[0100] refer to Figure 3B, the conductor 122 is depicted parallel to the advanced dimension line 126 (e.g., perpendicular to the route 124). In the depicted embodiment, the conductor extends in the direction of the advanced dimension line 126. In some embodiments, the conductor 122 may be defined at a point along the route 124, where the conductor direction is defined at the point. In some embodiments, the conductor 122 may extend to a predetermined distance or a predetermined distance beyond the route 124. Figure 2 As described above, the number of dimension lines may correspond to the route distances between the respective first conductive pads 102 and second conductive pads 104 .

[0101] refer to Figure 3C , the first conductive element 306 is connected to opposite ends of at least one conductive line 122, wherein the conductive line 122 is formed between the first conductive pad 102 and the second conductive pad 104, so that the combination of the conductive line 122 and the first conductive element 306 can convey signals between multiple parts of the semiconductor device. Similarly, the second conductive element 308 is connected to at least another conductive line 122 parallel to the aforementioned conductive line 122. In various embodiments, there may be more or fewer conductive pads. For example, the EDA tool may route the conductive line 122 between the conductive pad and another exclusion zone (e.g., a lateral edge of the semiconductor device). Although not shown in the figure, the first conductive element 306 and the second conductive element 308 connected to the conductive line 122 may be connected to an interlayer connection (e.g., a via, a pad, or a terminal).

[0102] According to some embodiments, Figure 4A , Figure 4B and Figure 4C A schematic diagram 400 is shown of another example of a conductive pad pair in the operation of routing a wire between the conductive pad pairs. Figure 4A, depicting a plurality of conductive pads. Specifically, a first conductive pad 402, a second conductive pad 404, a third conductive pad 406, a fourth conductive pad 408, and a fifth conductive pad 410 are provided. The EDA tool may generate the conductive pads (e.g., determine the location and geometry of the conductive pads), or receive instructions for the location and geometry of the conductive pads. The EDA tool may generate routes between the first conductive pad 402, the second conductive pad 404, the third conductive pad 406, the fourth conductive pad 408, and the fifth conductive pad 410. The EDA tool may compare the distances between the first conductive pad 402, the second conductive pad 404, the third conductive pad 406, the fourth conductive pad 408, and the fifth conductive pad 410, as well as a threshold value. For example, the EDA tool may compare the distance between the first conductive pad 402 (e.g., the center or the border of the first conductive pad 402) and the third conductive pad 406 (e.g., the center or the border of the first conductive pad 402) and a threshold value, and if it is determined that the distance exceeds the threshold value, it may be avoided to form the wire 122 therebetween. The EDA tool may compare the distance between the border of the first conductive pad 402 and the border of the second conductive pad 404, and if it is determined that the distance is less than the threshold value, it may continue to determine the route 124 therebetween.

[0103] The EDA tool may continue to generate comparison results between the first conductive pad 402, the second conductive pad 404, the third conductive pad 406, the fourth conductive pad 408, and the fifth conductive pad 410. For example, as shown, the EDA tool may determine the routes 124 between the first conductive pad 402 and the second conductive pad 404, between the second conductive pad 404 and the third conductive pad 406, between the third conductive pad 406 and the fourth conductive pad 408, and between the fourth conductive pad 408 and the fifth conductive pad 410. The EDA tool may then determine the advanced dimension lines 126 corresponding to each route 124. In some embodiments, the routing engine of the EDA tool may generate the routes 124 based on adjacent routes 124, such as to minimize the angle change between the routes 124. For example, if the distance between the second conductive pad 404 and the fourth conductive pad 408 is less than a threshold, the EDA tool may omit the route 124 between the two, based on other nearby wires 122, routes 124, or the like.

[0104] refer to Figure 4B , showing that the conductive line 122 perpendicular to the line 124 is formed between the conductive pads. Figure 4C , a plurality of signal lines 412 are connected to the conductive lines 122 to electrically couple a plurality of elements (die, contact pads, terminals or the like) of the semiconductor device. Figure 4C, multiple conductive elements 412 are connected to the wires 122 to electrically couple multiple elements (die, contact pads, terminals, or the like) of the semiconductor device. For example, the conductive elements 412 shown may be connected to other conductive pads, where the other conductive pads may also include wires 122 formed between the conductive pads and connected to multiple conductive elements to transmit signals, corresponding to the net lines of the netlist. Therefore, the EDA tool can draw the layers of the semiconductor device into a netlist.

[0105] According to some embodiments, Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Fig. 5F , Figure 5G , Figure 5H , Fig.5I and Figure 5J A top view of a conductive pad pair and a route 124 between the conductive pad pairs is shown separately. Figure 5A , the first conductive pad 102 and the second conductive pad 104 are as follows Figure 3A The route 124 joins individual points of the individual boundary ridges of the first conductive pad 102 and the second conductive pad 104 (located at the minimum distance 114 between the first conductive pad 102 and the second conductive pad 104). Depending on the relative positions of the first conductive pad 102 and the second conductive pad 104, the route 124 can extend along the linear portion of the first conductive pad 102 and the second conductive pad 104 so that the parallel distance 120 can be greater than zero. Figure 5B , the first conductive pad 102 and the second conductive pad 104 are circular, so that the route 124 defined between the middle points can overlap another route 124 defined by the boundary. The EDA tool can still determine the route 124 based on the boundary, rather than based on the center of the first conductive pad 102 and the second conductive pad 104. Figure 5C , the first conductive pad 102 and the second conductive pad 104 include lateral curved portions. The route 124 extends along the center of the parallel distance 120 (eg, defined by an EDA tool). Figure 5D , the first conductive pad 102 and the second conductive pad 104 include a narrow or only one point of parallel distance 120. The wire 122 can be defined perpendicular to the route 124 (for example, defined by an EDA tool) so that the signal lines connected to the wire 122 can diverge in different directions. For example, the signal line extending to the left can extend straight or upward, while the signal line extending to the right can extend straight or downward (as shown in the figure). Figure 5E ,Will Figure 5DThe first conductive pad 102 and the second conductive pad 104 in the embodiment are offset more, so that the parallel distance 120 extends from the route in two directions. For example, the route 124 can be located in the center of the parallel distance 120.

[0106] refer to Fig. 5F , the first conductive pad 102 and the second conductive pad 104 include a polygon having a vertex in the middle of a straight portion. Fig. 5F In FIG. 1 , the minimum distance 114 between the first conductive pad 102 and the second conductive pad 104 is located between individual vertices, so that the route 124 connects multiple vertices. Figure 5G Draw the same as Fig. 5F The polygonal first conductive pad 102 and the second conductive pad 104 are arranged in parallel with each other, but have a first parallel distance including the route 124 . Figure 5H Draw the same as Fig. 5F and Figure 5G The polygonal first conductive pad 102 and the second conductive pad 104 are similar to each other, but have a second parallel distance that is smaller than the first parallel distance and includes the route 124.

[0107] refer to Fig.5I , the route 124 connects the irregularly shaped first conductive pad 102 and the second conductive pad 104. Figure 6 The irregularly shaped first conductive pad 102 and the second conductive pad 104 are shown in detail. Figure 5J , depicting different first and second conductive pads 102, 104 and a route 124 therebetween. Similarly, the plurality of conductive pads depicted herein are not limiting, and the systems and methods described herein may be applied to a variety of conductive pads, trenches, edges, or other exclusion zones according to a variety of geometries.

[0108] According to some embodiments, Figure 6 Detailed diagram 600 of a conductive pad pair (a first conductive pad 102 and a second conductive pad 104) and a plurality of routes 124 therebetween. The first conductive pad 102 and the second conductive pad 104 have irregular shapes such that a plurality of routes 124 are formed therebetween. For example, the first conductive pad 102 and the second conductive pad 104 may have the same minimum distance 114 on individual routes 124. In some embodiments, the routes 124 may be formed along different distances. For example, the first minimum distance 114A may be less than the second minimum distance 114B. The EDA tool may compare the differences between the plurality of minimum distances and the different thresholds so that a plurality of routes 124 may be formed between the plurality of first minimum distances 114A and the second minimum distance 114B, thereby facilitating routing. For example, the threshold may be less than about 1 micron. In some embodiments, the wire 122 may further include connections formed between a plurality of portions along the respective routes.

[0109] According to some embodiments, Fig. 7A , Figure 7B and Figure 7C Detailed diagram of a conductive pad pair (a first conductive pad 102 and a second conductive pad 104) and a plurality of conductive wires 122 therebetween. Fig. 7A , the wire 122 is between the first conductive pad 102 and the second conductive pad 104. The wire 122 can be defined or formed above the surface of the semiconductor device by an EDA tool. The wire 122 can extend along the minimum distance 114 between the first conductive pad 102 and the second conductive pad 104. Each wire 122 is separated by a gap 118. Figure 7B , the wire 122 is connected to other signal lines of the netlist for the semiconductor device. For example, the first signal line 702 connects the wire 122 to other elements of the semiconductor device. The second signal line 704 is connected to another wire 122, for example, in order to transmit another signal in the semiconductor device. The third signal line 706 is connected to another wire 122. The third signal line 706 can be, for example, a power or ground plane. In some embodiments, the third signal line 706 can carry the same signal as the second conductive pad 104. For example, the third signal line 706 can be connected to the second conductive pad 104, and the gap between the third signal line 706 and the second conductive pad 104 can be omitted to increase the density of the wire 122 between the first conductive pad 102 and the second conductive pad 104 or the size of the plurality of signal lines. In some embodiments, the wire 122 can be selected based on being adjacent to the first conductive pad 102 and the second conductive pad 104, wherein the signal line can be connected to a plane, and the plane is electrically connected to or surrounds the first conductive pad 102 and the second conductive pad 104.

[0110] refer to Figure 7C , the first signal line 708 is shown as Figure 7B The first signal line 702 is shown as a first signal line 702. The second signal line 710 is shown as a first signal line 702. Fig. 7A The thickness of the second signal line 704 and the third signal line 706 and the gap therebetween is equal to the thickness of the second signal line 704 and the third signal line 706 and the gap therebetween. In the illustrated embodiment, the gap between the conductive elements is occupied by the conductive line, so that the second signal line has a thickness equal to the sum of the two conductive lines and the gap therebetween. According to various embodiments, other thicknesses may be defined, such as increasing the thickness of both the first signal line 708 and the second signal line 710 to occupy the gap portion vacated by trimming the conductive line 122.

[0111] According to some embodiments, Figure 8 8 is a flow chart of a method 800 for forming or manufacturing a semiconductor device. It should be understood that Figure 8Additional steps may be performed before, during, and / or after the method 800 depicted in the drawings. In some embodiments, the method 800 is used to form a semiconductor device according to various layout designs disclosed herein.

[0112] At step 802 of method 800, a route 124 between at least two conductive pads is determined. For example, the route 124 may be determined by an EDA tool based on a dimension between the two conductive pads, where the conductive pad is a representative of the location of the conductive pads in the EDA tool. The dimension may be the smallest dimension between the respective boundaries of the at least two conductive pads. The EDA tool may determine the difference by comparing the distances between the boundaries of the conductive pads and determine the local minimum between the boundaries of the conductive pads.

[0113] The EDA tool may pre-process multiple conductive pads to reduce computational energy, such as comparing midpoints of conductive pads and thresholds or independently evaluating overlapped portions of a layout, thereby reducing memory usage, energy usage, or improving EDA tool performance relative to methods that compare each conductive pad or each edge of other features. Although the various embodiments described herein refer to conductive pads, the EDA tool may determine similar routes between multiple semiconductor features to form signal conductors between the semiconductor features.

[0114] In step 804 of method 800, a first conductive line is formed. The conductive line may be formed as a representative of a semiconductor device layer (e.g., a redistribution layer) by an EDA tool, or the formation of the conductive line may be based on receiving a design layout from an EDA tool to manufacture a portion of a semiconductor device. The conductive line may span the route determined in step 802. For example, the conductive line may span the route at a vertical angle. According to some embodiments, the conductive line may have a preset size, such as a preset thickness, or extend a preset length. For example, a plurality of conductive lines having a preset thickness may be arranged perpendicular to the determined route, and may be subsequently merged, trimmed, or otherwise adjusted (e.g., performed by an EDA tool before physically forming a metal layer above the semiconductor device). The formed conductive line may have a length corresponding to a parallel distance between the conductive pads. The parallel distance may be the same as the distance between the conductive pads or a value less than a threshold, so that slight deviations in the distance between the conductive pads may be ignored.

[0115] In step 806 of method 800, the first wire is connected to the net wire of the netlist. For example, the EDA tool can route multiple connections between the die, terminals or other components of the semiconductor device. For example, the routing engine of the EDA tool can link the logical net wires of the netlist and the physical locations corresponding to the wires. The EDA tool can then route the signal wires. Any routing that passes between the conductive pads can be connected to the wires defined in step 804. The EDA tool can connect zero, one or more signal wires to the preset wires. Relative to the system and method for routing signal wires directly between the lines, first defining the wires can increase the number of wirings that can be tolerated between the wires. For example, the EDA tool can connect the first signal wire between the conductive pads, wherein the first signal wire is non-perpendicular to the route between the conductive pads, and thus can block other signal wires from being routed between the pads. In addition, by defining the vertical direction of the wires, the EDA tool can route the wires between the conductive pads in a manner that does not conform to the design rules (e.g., at different angles).

[0116] At step 808 of method 800, the conductor size is adjusted. The EDA tool may route fewer signal lines between the conductive pads than is feasible. For example, the EDA tool may define 5 conductors and route 2 signal lines between the conductive pads, where each signal line is connected to one of the conductors. The remaining 3 conductors may be trimmed, thereby increasing the space between the remaining conductors and the conductive pads. The EDA tool may increase the conductor thickness, such as by filling the space between the conductors, to combine multiple conductors to the same signal line (e.g., to reduce the resistivity of the line), or adjust the conductor angle to reduce the curvature associated with the signal line (e.g., to improve the signal integrity of high-speed signal lines).

[0117] According to some embodiments, Fig. 9 is a flow chart of a method 900 of forming or manufacturing a semiconductor device. It should be understood that Fig. 9 Additional steps may be performed before, during, and / or after the method 900 depicted in the drawings. In some embodiments, the method 900 is used to form a semiconductor device according to various layout designs disclosed herein.

[0118] At step 910 of method 900, a layout design of a semiconductor device (eg, Figure 1 The redistribution layer layout described above). Step 910 is performed by a processing device (eg, Fig.10A processor 1002 of the embodiment of the present invention is configured to execute instructions for generating a layout design. In one embodiment, generating a layout design is a layout design of placing one or more standard cells through a user interface. In one embodiment, the layout design is automatically generated by executing a synthesis tool through the processor, wherein the synthesis tool converts a logic design (e.g., syntax Verilog) into a corresponding layout design. In some embodiments, the layout design is provided in a graphic database system (GDSII) data type. Execution may include using an EDA tool.

[0119] At step 920 of method 900 , a semiconductor device (eg, at least a portion of each package) is fabricated based on the layout design. In some embodiments, step 920 of method 900 includes fabricating at least one mask based on the layout design, and fabricating the semiconductor device based on the at least one mask.

[0120] According to some embodiments, Fig.10 1 is a schematic diagram of a system 1000 for designing and manufacturing integrated circuit (IC) layout designs. System 1000 generates or places one or more integrated circuit layout designs, as described herein. In some embodiments, system 1000 manufactures one or more semiconductor devices based on one or more integrated circuit layout designs, as described herein. System 1000 includes a hardware processor 1002 and a non-transitory computer readable storage medium 1004, wherein computer program code 1006 (e.g., a set of executable instructions) is encoded (e.g., stored) in the non-transitory computer readable storage medium 1004. Computer readable storage medium 1004 is configured to be connected to a manufacturing machine that produces semiconductor devices. Processor 1002 is electrically coupled to computer readable storage medium 1004 via bus 1008. Processor 1002 is also electrically coupled to input / output (I / O) interface 1010 via bus 1008. Network interface 1012 is also electrically connected to processor 1002 via bus 1008. The network interface 1012 is connected to the network 1014, so that the processor 1002 and the computer readable storage medium 1004 can connect to external components through the network 1014. The processor 1002 is configured to execute the computer program code 1006 encoded in the computer readable storage medium 1004, so that the system 1000 can be used to perform part or all of the steps described in the method 900.

[0121] In some embodiments, the processor 1002 is a central processing unit (CPU), a multi-processor, a distributed processing system (distributed processing system), an application specific integrated circuit (ASIC) and / or a suitable processing unit.

[0122] In some embodiments, the computer-readable storage medium 1004 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 1004 includes semiconductor or solid-state memory, magnetic tape, removable computer diskette, random access memory (RAM), read-only memory (ROM), rigid magnetic disk, and / or optical disk. In some embodiments using optical disks, the computer-readable storage medium 1004 includes compact disk-read only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0123] In some embodiments, computer program code 1006 stored in computer readable storage medium 1004 causes system 1000 to perform method 900. In some embodiments, computer readable storage medium 1004 also stores data required to perform method 900 and data generated during the performance of method 900, such as layout design 1016, user interface 1018, manufacturing unit 1020, and / or a set of executable instructions for performing the steps of method 900.

[0124] In some embodiments, computer readable storage medium 1004 stores instructions (e.g., computer program code 1006) for connecting to a manufacturing machine. The instructions (e.g., computer program code 1006) enable processor 1002 to generate manufacturing instructions readable by the manufacturing machine to effectively implement method 900 during a manufacturing process.

[0125] System 1000 includes an I / O interface 1010. I / O interface 1010 is coupled to external circuits. In some embodiments, I / O interface 1010 includes a keyboard, a keypad, a mouse, a trackball, a track pad, and / or a cursor direction key for communicating data and instructions with processor 1002.

[0126] The system 1000 also includes a network interface 1012 coupled to the processor 1002. The network interface 1012 allows the system 1000 to connect to a network 1014, which connects one or more other computer systems. The network interface 1012 includes a wireless network interface (e.g., Bluetooth, WIFI, WIMAX, GPRS, or WCDMA) or a wired network interface (e.g., Ethernet, USB, or IEEE-13154). In some embodiments, two or more systems 1000 perform the method 900, and different systems 1000 exchange data such as layout design, user interface, and manufacturing unit through the network 1014.

[0127] The system 1000 is configured to receive data regarding a layout design via the I / O interface 1010 or the network interface 1012. The bus 1008 transfers the data to the processor 1002 to determine the layout design for generating the integrated circuit. The layout design is then stored as a layout design 1016 in the computer-readable storage medium 1004. The system 1000 is configured to receive data regarding a user interface via the I / O interface 1010 or the network interface 1012. The data is stored as a user interface 1018 in the computer-readable storage medium 1004. The system 1000 is configured to receive data regarding a manufacturing unit via the I / O interface 1010 or the network interface 1012. The data is stored as a manufacturing unit 1020 in the computer-readable storage medium 1004. In some embodiments, the manufacturing unit 1020 includes manufacturing data used by the system 1000.

[0128] In some embodiments, method 900 is a separate application software executed by a processor. In some embodiments, method 900 is an application software that is part of other application software. In some embodiments, method 900 is a plug-in for application software. In some embodiments, method 900 is an application software that is part of an EDA tool. In some embodiments, method 900 is an application software used by an EDA tool. In some embodiments, the EDA tool is used to generate a layout design of an integrated circuit device. In some embodiments, the layout design is stored in a non-transitory computer readable storage medium. In some embodiments, the layout design is generated using, for example, a computer program product purchased from CADENCEDESIGN SYSTEMS. 1020 or other suitable layout generation tools. In some embodiments, the layout design is generated based on a netlist, and the netlist is manufactured based on a schematic design. In some embodiments, a manufacturing device performs method 900 to manufacture an integrated circuit using a set of masks, wherein the masks are manufactured based on one or more layout designs generated by system 1000. In some embodiments, system 1000 includes a manufacturing device (e.g., manufacturing tool 1022) to manufacture an integrated circuit using a set of masks, wherein the masks are manufactured based on one or more layout designs of the present disclosure. In some embodiments, Fig.10 The system 1000 generates a layout design of an integrated circuit that is smaller than a layout design generated by other methods. In some embodiments, Fig.10 The system 1000 generates a layout design for a semiconductor device that occupies a smaller area than a layout design generated by other methods.

[0129] According to at least one embodiment of the present disclosure, Fig.11 is a block diagram of an integrated circuit / semiconductor device manufacturing system 1100 and its related integrated circuit manufacturing process.

[0130] exist Fig.11 In the embodiment, the integrated circuit manufacturing system 1100 includes multiple entities, such as a design house 1120, a mask house 1130, and an IC manufacturer / fabricator 1140. These entities interact with each other in the design, development, and production cycle and / or service of manufacturing an integrated circuit device 1160 (semiconductor device). The entities in the system 1100 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a plurality of different networks, such as an intranet or the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to one or more other entities and / or receives services from one or more other entities. In some embodiments, two or more of the design house 1120, the mask house 1130, and the integrated circuit manufacturing plant 1140 are owned by a single company. In some embodiments, two or more of the design room 1120, the mask room 1130, and the integrated circuit fabrication plant 1140 are co-located in a common facility and use common resources.

[0131] The design office 1120 (or design team) generates an integrated circuit design layout 1122. The integrated circuit design layout 1122 includes a plurality of geometric patterns designed for the integrated circuit device 1160. The geometric patterns correspond to patterns of metal, oxide or semiconductor layers to form a plurality of components of the integrated circuit device 1160. Multiple layers are combined to form a plurality of integrated circuit features. For example, a portion of the integrated circuit design layout 1122 includes a plurality of integrated circuit features (e.g., openings for active regions, gate structures, source / drain structures, interconnect structures and bonding pads) formed in a semiconductor substrate (e.g., a silicon wafer) and a plurality of material layers disposed on the semiconductor substrate. The design office 1120 executes a suitable design program to form the integrated circuit design layout 1122. The design program includes one or more logical designs, physical designs or positioning and routing. The integrated circuit design layout 1122 is presented in one or more data files having geometric pattern information. For example, the integrated circuit design layout 1122 may be represented in a GDSII file format or a DFII file format.

[0132] The mask chamber 1130 includes mask data preparation 1132 and mask manufacturing 1134. The mask chamber 1130 uses the integrated circuit design layout 1122 to manufacture one or more masks, wherein the masks will manufacture different layers of the integrated circuit device 1160 according to the integrated circuit design layout 1122. The mask chamber 1130 performs mask data preparation 1132, wherein the integrated circuit design layout 1122 is compiled into a representative data file (RDF). The mask data preparation 1132 provides the representative data file to the mask manufacturing 1134. The mask manufacturing 1134 includes a mask writer. The mask writer converts the representative data file into an image on a substrate (such as a reticle or a semiconductor wafer) or a metal layer, wherein the formed metal layer will be selectively etched to form a redistribution layer in the back-end process of the factory. The mask data preparation 1132 manipulates the design layout to conform to the specific form of the mask writer and / or the requirements of the integrated circuit manufacturing plant 1140. In Fig.11 , mask data preparation 1132 and mask manufacturing 1134 are depicted as separate elements. In some embodiments, mask data preparation 1132 and mask manufacturing 1134 may be collectively referred to as mask data preparation.

[0133] In some embodiments, mask data preparation 1132 includes optical proximity correction (OPC), which uses lithography enhancement techniques to correct for image errors, such as image errors due to diffraction, interference, other process effects, and the like. Optical proximity correction adjusts the integrated circuit design layout 1122. In some embodiments, mask data preparation 1132 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) may also be used, which treats optical proximity correction as an inverse imaging problem.

[0134] In some embodiments, mask data preparation 1132 includes a mask rule checker (MRC) that checks an integrated circuit design layout that has been processed through a set of mask creation rules in optical proximity correction, wherein the mask creation rules contain specific geometric and / or connection connection restrictions to ensure sufficient margins to account for variability in semiconductor manufacturing processes and the like. In some embodiments, the mask rule checker modifies the integrated circuit design layout during mask creation 1134 to compensate for limitations, which can restore portions of the modifications performed by optical proximity correction in order to comply with the mask creation rules.

[0135] In some embodiments, mask data preparation 1132 includes lithography process checking (LPC), which simulates the process to be performed by the integrated circuit fabrication facility 1140 to fabricate the integrated circuit device 1160. The lithography process checking simulates this process based on the integrated circuit design layout 1122 to create a simulated fabricated device, such as the integrated circuit device 1160. Process parameters in the lithography process checking may include parameters related to multiple processes of the integrated circuit fabrication cycle, parameters related to the tools used to fabricate the integrated circuit, and / or other aspects of other fabrication processes. The lithography process checking considers various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, the like, or combinations thereof. In some embodiments, after the lithography process checking creates the simulated fabricated device, if the simulated device is not close enough in shape to meet the design rules, optical proximity correction and / or mask rule checker may be repeated to further improve the integrated circuit design layout 1122.

[0136] It should be understood that the above mask data preparation 1132 has been simplified for clarity of description. In some embodiments, the mask data preparation 1132 includes additional features such as logic operations (LOP) to modify the integrated circuit design layout according to manufacturing rules. In addition, during the mask data preparation 1132, the processes applied to the integrated circuit design layout 1122 can be performed in various different orders.

[0137] After mask data preparation 1132 and during mask manufacturing 1134, a mask or mask group is manufactured based on the modified integrated circuit design layout. In some embodiments, an electron-beam (e-beam) or multiple electron-beam mechanisms are used to form a pattern on a mask (mask or mask) based on the modified integrated circuit design layout. The mask can be formed by a variety of techniques. In some embodiments, the mask is formed using two techniques. In some embodiments, the mask pattern includes opaque areas and transparent areas. The radiation beam (e.g., ultraviolet (UV)) used to expose the image sensitive material layer (e.g., photoresist) coated on the wafer is blocked by the opaque area and passes through the transparent area. In one example, a binary mask includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque area of ​​the mask. In another example, the mask is formed using a phase shift technique. In a phase shift mask (PSM), multiple features formed in the pattern on the mask have an appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated phase shift mask or an alternating phase shift mask. The mask produced by mask manufacturing 1134 is used in various processes. For example, such a mask can be used in an ion implantation process to form a plurality of doped regions in a semiconductor wafer, can be used in an etching process to form a plurality of etched regions in a semiconductor wafer, and / or can be used in other suitable processes.

[0138] The integrated circuit manufacturing plant 1140 is an integrated circuit manufacturing entity, which includes one or more manufacturing facilities for manufacturing various integrated circuit products. In some embodiments, the integrated circuit manufacturing plant 1140 is a semiconductor factory. For example, there may be a first manufacturing facility for front-end manufacturing of various integrated circuit products (e.g., source / drain structures, gate structures), while a second manufacturing facility can provide middle-end manufacturing of interconnection (e.g., MD, VD, VG) of integrated circuit products, a third manufacturing facility can provide back-end manufacturing of interconnection and packaging (e.g., M0 row, M1 row, BM0 row, BM1 row) of integrated circuit products, and a fourth manufacturing facility can provide other services for the factory entity.

[0139] The integrated circuit fabrication facility 1140 uses a mask (or masks) fabricated by the mask chamber 1130 to fabricate the integrated circuit device 1160. Therefore, the integrated circuit fabrication facility 1140 at least indirectly uses the integrated circuit design layout 1122 to fabricate the integrated circuit device 1160. In some embodiments, the integrated circuit fabrication facility 1140 uses a mask (or masks) to fabricate a semiconductor wafer to form the integrated circuit device 1160. The semiconductor wafer 1142 includes a silicon substrate or other suitable substrate having material layers formed thereon. The semiconductor wafer further includes one or more doped regions, dielectric features, multi-layer interconnects, and the like (formed in subsequent fabrication steps).

[0140] The design room 1120, mask room 1130 and integrated circuit manufacturing plant 1140 of the system 1100 in the figure are separate components or entities. However, it should be understood that one or more of the design room 1120, mask room 1130 or integrated circuit manufacturing plant 1140 can be part of the same component or entity.

[0141] In one aspect of the present disclosure, a method for manufacturing a semiconductor device is disclosed. The method includes determining a route extending from a first conductive pad among a plurality of conductive pads to a second conductive pad among a plurality of conductive pads. The route represents a minimum distance between a first boundary of the first conductive pad and a second boundary of the second conductive pad. The method includes forming a first conductive wire across the determined route. The first conductive wire may extend in a direction perpendicular to the route.

[0142] In some embodiments, the first conductive pad and the second conductive pad are in the same metallization layer. In some embodiments, the first conductive pad and the second conductive pad are configured to receive the first interlayer via and the second interlayer via, respectively. In some embodiments, the first conductor extends a preset distance. In some embodiments, the method further includes connecting the first conductor to a plane, wherein the plane laterally surrounds at least one of the first conductive pad or the second conductive pad. In some embodiments, the method further includes forming a second conductor extending in a direction perpendicular to the route, the second conductor parallel to the first conductor. In some embodiments, the first conductor has a first thickness, the second conductor has a second thickness, and the second thickness is twice the sum of the first thickness and the distance between the first conductor and the second conductor. In some embodiments, the length of the first conductor is based on the distance between the first conductive pad and the second conductive pad. In some embodiments, the length of the first conductor extends beyond a parallel distance, and the parallel distance separates the first conductive pad and the second conductive pad along opposite ends of the route. In some embodiments, the method further includes determining a plurality of connections corresponding to a mesh of the netlist, the mesh being related to a signal type, and adjusting the thickness of the first conductor to correspond to the signal type. In some embodiments, the method further includes trimming the second conductor after connecting the first conductor to the mesh of the netlist.

[0143] In another aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a redistribution layer configured to redistribute a connector of semiconductor dies, wherein the redistribution layer includes a plurality of conductive pads embedded in a dielectric material. The redistribution layer includes a first conductive pad, the first conductive pad includes a first boundary dimension. The redistribution layer includes a second conductive pad, the second conductive pad includes a second boundary dimension. The redistribution layer includes at least one conductive wire, wherein the at least one conductive wire is perpendicular to a minimum distance between the first boundary dimension and the second boundary dimension.

[0144] In some embodiments, the conductive line is non-perpendicular to a line between a midpoint of the first conductive pad and a midpoint of the second conductive pad. In some embodiments, the semiconductor device further includes a plurality of additional conductive lines parallel to the conductive line.

[0145] In another aspect of the present disclosure, a non-transitory computer-readable medium is disclosed. The non-transitory computer-readable medium includes instructions for defining a first conductive pad, wherein the first conductive pad is bounded by a first boundary along a lateral plane of the semiconductor device. The non-transitory computer-readable medium includes instructions for defining a second conductive pad, wherein the second conductive pad is bounded by a second boundary along the lateral plane. The non-transitory computer-readable medium includes instructions for determining a route between the first boundary and the second boundary based on a minimum dimension between the first boundary and the second boundary. The non-transitory computer-readable medium includes instructions for defining a wire between the first conductive pad and the second conductive pad based on the minimum dimension, wherein the wire extends perpendicular to the route along the lateral plane. The non-transitory computer-readable medium includes instructions for defining a first connection of the wire at a first terminal of the wire, the first connection corresponding to a net line of a netlist. The non-transitory computer-readable medium includes instructions for defining a second connection of the wire at a second terminal of the wire, the second terminal being relative to the first terminal.

[0146] In some embodiments, the non-transitory computer readable medium further comprises a plurality of instructions that define an integer number of a plurality of additional conductors perpendicular to the conductor based on a distance of a minimum dimension. In some embodiments, the conductor and each of the additional conductors have the same thickness. In some embodiments, the thickness of at least one of the additional conductors is the sum of at least twice the thickness of the conductor and a gap between the conductor and at least one of the additional conductors. In some embodiments, the conductor proximate to the first conductive pad is connected to a plane that surrounds the first conductive pad along a transverse plane. In some embodiments, the non-transitory computer readable medium further comprises determining a signal type of a mesh of the netlist, and determining a thickness of the conductor based on the signal type.

[0147] In another aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a metallization layer, a first conductive line, and a second conductive line. The metallization layer includes a plurality of conductive pads embedded in a dielectric material, wherein the conductive pads include a first conductive pad and a second conductive pad, the first conductive pad includes a first boundary, and the second conductive pad includes a second boundary. The first conductive line extends perpendicular to a minimum distance between the first boundary and the second boundary. The second conductive line extends perpendicular to the minimum distance between the first boundary and the second boundary and parallel to the first conductive line.

[0148] In some embodiments, the first conductive pad and the second conductive pad are configured to receive the first interlayer via and the second interlayer via, respectively. In some embodiments, the first conductive line is connected to a plane that laterally surrounds at least one of the first conductive line or the second conductive line. In some embodiments, the first conductive line has a first thickness and the second conductive line has a second thickness that is a sum of twice the first thickness and a distance between the first conductive line and the second conductive line. In some embodiments, the length of the first conductive line extends beyond a parallel distance that separates the first conductive line and the second conductive line along opposite ends of the route.

[0149] In another aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a redistribution layer, wherein the redistribution layer includes a plurality of conductive pads embedded in a dielectric material, the conductive pads including a first conductive pad bounded by a first boundary along a transverse plane and a second conductive pad bounded by a second boundary along the transverse plane. The semiconductor device includes a conductive wire located between the first conductive pad and the second conductive pad, wherein the conductive wire extends along the transverse plane and perpendicular to a minimum distance between the first boundary and the second boundary. A first connection of the conductive wire is defined at a first terminal of the conductive wire, the first connection corresponds to a net line of a netlist, and a second connection of the conductive wire is defined at a second terminal of the conductive wire, the second terminal is relative to the first terminal.

[0150] In some embodiments, the semiconductor device further includes a plurality of additional conductive lines perpendicular to the conductive line, wherein the integer number of the additional conductive lines is based on the minimum distance.

[0151] As used herein, the terms "about" and "approximately" generally mean within plus or minus 10% of the stated value. For example, about 0.5 may include 0.45 and 0.55, about 10 may include 9 to 11, and about 1000 may include 900 to 1100.

[0152] The features of some embodiments are summarized above so that those skilled in the art can better understand the viewpoints of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: A redistribution layer configured to redistribute a plurality of connectors of a semiconductor die, wherein the redistribution layer comprises a plurality of conductive pads embedded in a dielectric material, the redistribution layer comprising: a first conductive pad including a first boundary dimension; a second conductive pad including a second boundary dimension; as well as At least one conductive line is perpendicular to a minimum distance between the first boundary dimension and the second boundary dimension. 2 . The semiconductor device as claimed in claim 1 , wherein the conductive line is non-perpendicular to a line between a middle point of the first conductive pad and a middle point of the second conductive pad. 3 . The semiconductor device of claim 1 , further comprising a plurality of additional conductive lines parallel to the conductive line.

4. A semiconductor device, characterized in that: include: A metallization layer includes a plurality of conductive pads embedded in a dielectric material, wherein the plurality of conductive pads include: a first conductive pad including a first boundary; and a second conductive pad including a second boundary; a first conductive line extending perpendicularly to a minimum distance between the first boundary and the second boundary; and A second conductive line is perpendicular to the minimum distance between the first boundary and the second boundary and extends parallel to the first conductive line. 5 . The semiconductor device as claimed in claim 4 , wherein the first conductive pad and the second conductive pad are configured to receive a first inter-layer via and a second inter-layer via, respectively. 6 . The semiconductor device as claimed in claim 4 , wherein the first conductive line is connected to a plane that laterally surrounds at least one of the first conductive pad or the second conductive pad. 7 . The semiconductor device as claimed in claim 4 , wherein the first conductive line has a first thickness, the second conductive line has a second thickness, and the second thickness is a sum of twice the first thickness and a distance between the first conductive line and the second conductive line. 8 . The semiconductor device of claim 4 , wherein a length of the first conductive line extends over a parallel distance separating the first conductive pad and the second conductive pad along opposite ends of the minimum distance.

9. A semiconductor device, characterized in that: include: A redistribution layer includes a plurality of conductive pads embedded in a dielectric material, wherein the plurality of conductive pads include: a first conductive pad bounded by a first boundary along a transverse plane; and a second conductive pad bounded by a second boundary along the transverse plane; and a conductive line located between the first conductive pad and the second conductive pad, wherein the conductive line extends along the transverse plane and perpendicular to a minimum distance between the first boundary and the second boundary, A first connection of the conductive line is defined at a first terminal of the conductive line, and the first connection corresponds to a mesh line of a netlist, and A second connection of the conductive line is defined at a second terminal of the conductive line, and the second terminal is opposite to the first terminal. 10 . The semiconductor device of claim 9 , further comprising a plurality of additional conductive lines perpendicular to the conductive line, wherein an integer number of the plurality of additional conductive lines is based on the minimum distance.

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