Test board and test structure
By designing test points exposed on the side and connected test paths, the problem of difficulty in direct testing in DDR signal design is solved, improving signal quality and maintaining impedance continuity.
Patent Information
- Application Number
- CN202421242991.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-31
- Publication Date
- 2025-01-21
- Estimated Expiration
- 2034-05-31
AI Technical Summary
The prior art is difficult to directly test in the design of double-rate synchronous dynamic random memory (DDR) signal, and due to the discontinuous impedance of high-speed signals, the reservation of test points will lead to signal abnormalities, affecting the normal operation of DDR.
A test board is designed, including a multi-layer printed board, test paths and test points. The test points extend along the side of the printed board and are exposed. They are connected through test leads and metallized holes to avoid impedance discontinuity on the signal path. .
It realizes direct contact testing, avoids signal anomalies, improves DDR signal quality, and reduces insertion loss of the test path.
Smart Images
Figure CN222380290U_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the semiconductor field, and in particular to a test board and a test structure. Background Art
[0002] In practical applications, the signal quality of double-rate synchronous dynamic random access memory (DDR) needs to be tested by a high-speed oscilloscope to evaluate whether the signal's timing, jitter, swing, eye diagram and other parameters meet the JEDEC protocol requirements.
[0003] The current signal design specification of the double-bit rate synchronous dynamic random access memory is LPDDR5X. However, the LPPDDR5X signal is designed in the inner layer and cannot be designed in the surface layer, so the oscilloscope probe cannot directly contact it for point measurement. In addition, the signal that meets the LPDDR5X design specification is a high-speed signal. If a test point is reserved on the signal path for the convenience of testing, impedance discontinuity will be introduced, resulting in signal abnormality, which will cause the double-bit rate synchronous dynamic random access memory to work abnormally. Summary of the invention
[0004] In view of this, the embodiments of the present disclosure provide a test board and a test structure to facilitate direct contact testing.
[0005] The embodiment of the present disclosure discloses a test board, comprising: a multi-layer printed circuit board, a plurality of test paths and a plurality of test points; wherein the multi-layer printed circuit boards are stacked layer by layer along a first direction, and the first direction is perpendicular to the top surface of the multi-layer printed circuit boards; the plurality of test paths are all arranged in the multi-layer printed circuit boards; the plurality of test points are all arranged on at least one side of the multi-layer printed circuit boards and are all exposed to the side of the multi-layer printed circuit boards; each of the test points is connected to the corresponding test path.
[0006] In the above solution, the length direction of the plurality of test points all extends along the first direction, and the cross-sections along the first direction all have a fan-shaped ring shape.
[0007] In the above solution, back-drilled holes are formed on both sides of each test point along the first direction; the sidewalls of the back-drilled holes along the first direction are arc-shaped, exposing the top and bottom of the test point.
[0008] In the above scheme, each of the test paths includes: a test wire and a metallized hole; the extension direction of the test wire is parallel to the top surface of the multi-layer printed circuit board; the metallized hole penetrates the multi-layer printed circuit board along the first direction; each of the test points is connected to the metallized hole through the test wire.
[0009] In the above scheme, an embedded resistor is provided on at least one layer of the multi-layer printed circuit board; the embedded resistor is connected in series in the test wire; in the extension direction of the test wire, the distance between the test point and the embedded resistor is greater than the distance between the metallized hole and the embedded resistor.
[0010] In the above solution, the length of the test point is less than the thickness of one layer of the printed circuit board.
[0011] In the above solution, the inner diameter of the back-drilled hole is larger than the inner diameter of the test point.
[0012] The disclosed embodiment also provides a test structure, comprising: a main carrier board, a first chip particle, a second chip particle, and the test board described in the above scheme; wherein the first chip particle and the test board are both arranged on the main carrier board and are both electrically connected to the main carrier board; the first chip particle and the test board are electrically connected through the main carrier board; the second chip particle is arranged on the test board and is electrically connected to the test board; the multiple test points of the test board are used to connect external test equipment.
[0013] In the above solution, the projection of the test board on the main carrier overlaps with the projection of the second chip particle on the main carrier.
[0014] In the above solution, the first chip particle includes a system-level chip; the second chip particle includes a dynamic random access memory. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 A schematic diagram of the structure of the test board provided in the embodiment of the present disclosure Figure 1 ;
[0016] Figure 2 A schematic diagram of the structure of the test board provided in the embodiment of the present disclosure Figure 2 ;
[0017] Figure 3 A schematic diagram of the structure of the test board provided in the embodiment of the present disclosure Figure 3 ;
[0018] Figure 4 A schematic diagram of the structure of the test board provided in the embodiment of the present disclosure Figure 4 ;
[0019] Figure 5 A schematic diagram of a test structure provided in an embodiment of the present disclosure Figure 1 ;
[0020] Figure 6 A schematic diagram of a test structure provided in an embodiment of the present disclosure Figure 2 . DETAILED DESCRIPTION
[0021] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below in conjunction with the drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.
[0022] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.
[0023] If similar descriptions of "first / second" appear in the application documents, the following description is added. In the following description, the terms "first / second / third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that "first / second / third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.
[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.
[0025] Figure 1 is a schematic diagram of an optional test board provided in an embodiment of the present disclosure, refer to Figure 1 The test board 100 includes a multilayer printed circuit board 10, a plurality of test paths 20 and a plurality of test points 30. It should be noted that: Figure 1 Only one test point 30 and one test path 20 are illustrated in the figure. Other test points 30 and test paths 20 can be referred to in Figure 1 For understanding as shown in.
[0026] In the embodiments of the present disclosure, reference Figure 1, the multilayer printed circuit board 10 is stacked layer by layer along a first direction Z. The first direction Z is perpendicular to the top surface of the multilayer printed circuit board 10. A plurality of test paths 20 are arranged in the multilayer printed circuit board 10. For example, the test path 20 includes a test wire 21 and a metallized hole 22. The metallized hole 22 penetrates the multilayer printed circuit board 10 along the first direction, and the test wire 21 can be arranged between two adjacent layers of printed circuit boards 10. Each test point 30 is connected to a corresponding test path 20. In the case where chip particles are arranged on the top surface or the bottom surface of the multilayer printed circuit board 10, the test point 30 can be electrically connected to the corresponding chip particles through the test path 20, and the test board 100 can lead the signal of the chip particles to the test point 30. That is, the embodiment of the present disclosure can directly use the test path inside the test board 100 for testing. In this way, the embodiment of the present disclosure does not need to re-weld the test path 20, thereby avoiding the reflection and capacitive load caused by the welding of the test path 20, and improving the signal quality of the test path 20. At the same time, the length of the test path 20 of the embodiment of the present disclosure is short, which can reduce the insertion loss of the test path 20.
[0027] In the embodiments of the present disclosure, reference Figure 1 The plurality of test points 30 are all disposed on at least one side of the multilayer printed board 10 and are all exposed to the side of the multilayer printed board 10. For example, Figure 2 As shown, test points 30 are arranged on the four edges of the multilayer printed board 10. The multiple test points 30 may protrude from the side of the multilayer printed board 10, or may be embedded in the side of the multilayer printed board 10. In other words, the multiple test points 30 are arranged on the side of the multilayer printed board 10, and are exposed to the side of the multilayer printed board 10. In this way, an external test device can directly contact the multiple test points 30 arranged on the side of the test board 100, thereby facilitating the external test device to perform a test.
[0028] In some embodiments of the present disclosure, reference Figure 1 , back-drilled holes 40 are formed on both sides of each test point 30 along the first direction Z. The sidewalls of the back-drilled holes 40 along the first direction Z are curved, exposing the top and bottom of the test point 30 .
[0029] Figure 3 is a schematic diagram of an optional test point 30 provided in an embodiment of the present disclosure. It should be noted that: Figure 3 The test point 30 shown may be made of a metallized hole disposed on the edge of the multilayer printed circuit board 10 .
[0030] In the embodiments of the present disclosure, reference Figure 3The disclosed embodiment can perform double-sided back drilling on the edge metallized holes of the multi-layer printed circuit board 10, that is, the metallized holes at the edge of the multi-layer printed circuit board 10 are back-drilled along the top and bottom surfaces of the multi-layer printed circuit board 10 respectively. The diameter of the metallized hole can be 0.5mm, and the diameter of the hole plate of the metallized hole can be 0.8mm. The spacing between adjacent metallized holes can be 1.1mm. Then, the metallized holes at the edge of the board that have completed the double-sided back drilling process are milled out, that is, half of the metallized holes at the edge of the board that have completed the double-sided back drilling process are milled off along the second direction Y. Thus, a Figure 3 Test point 30 is shown.
[0031] In the embodiments of the present disclosure, reference Figure 1 , back-drilled holes 40 are provided on the top and bottom of each test point 30. In this way, the back-drilled holes 40 expose the top and bottom of the test point 30, thereby making it easier for external test equipment to directly contact the test point 30.
[0032] In some embodiments of the present disclosure, reference Figure 1 The length directions of the multiple test points 30 all extend along the first direction Z, and the cross-sections along the first direction Z all present a fan ring shape.
[0033] In the embodiments of the present disclosure, reference Figure 1 , the length direction of the test point 30 may be the first direction Z. The cross section of the test point 30 along the first direction Z may be as follows: Figure 3 Shown as a fan-shaped ring.
[0034] In some embodiments of the present disclosure, reference Figure 1 Each test path 20 includes: a test wire 21 and a metallized hole 22. The extension direction of the test wire 21 is parallel to the top surface of the multilayer printed board 10. The metallized hole 22 penetrates the multilayer printed board 10 along the first direction Z. Each test point 30 is connected to the metallized hole 22 through the test wire 21.
[0035] In the embodiments of the present disclosure, reference Figure 1 , chip particles may be disposed on the top or bottom surface of the test board 100. Figure 5 As shown, the top surface of the test board 100 is connected to the second chip particle 203, and the bottom surface of the test board is connected to the main carrier 201. The metallized hole 22 can be used to transmit the main path signal, that is, the test board 100 is used to transmit the signal between the main carrier 201 and the second chip particle 203.
[0036] Figure 4 It is a schematic diagram of the structure of an optional test wire 21 and a test point 30 provided in an embodiment of the present disclosure. It should be noted that the top and bottom surfaces of the printed circuit board 10 are provided with copper foil, which can be regarded as grounding.
[0037] In the embodiments of the present disclosure, reference Figure 4 , the characteristic impedance of the test wire 21 can be greater than or equal to 60Ω. The avoidance dimension L2 between the test wire 21 and the ground can be greater than or equal to 6mil. The avoidance dimension L1 between the test point 30 and the ground can be greater than or equal to 10mil. In this way, the embodiment of the present disclosure performs impedance matching on the test path 20, avoids the loss caused by the transmission of the main path signal along the test wire 21, and reduces the impact of the introduction of the test path 20 and the introduction of the test point 30 on the quality of the main path signal.
[0038] In some embodiments of the present disclosure, reference Figure 1 At least one layer of the multilayer printed circuit board 10 is provided with an embedded resistor 23. The embedded resistor 23 is connected in series in the test lead 21. In the extending direction of the test lead 21, the distance between the test point 30 and the embedded resistor 23 is greater than the distance between the metallized hole 22 and the embedded resistor 23.
[0039] In the embodiments of the present disclosure, reference Figure 1 , the distance between the test point 30 and the embedded resistor 23 is greater than the distance between the metallized hole 22 and the embedded resistor 23. In other words, the embedded resistor 23 is closer to the metallized hole 22. In this way, when the metallized hole 22 transmits the main path signal, the embedded resistor 23 can avoid the loss of the main path signal transmitted along the test wire 21, thereby reducing the influence of the test path 20 on the quality of the main path signal.
[0040] In some embodiments of the present disclosure, reference Figure 1 , the length of the test point 30 is less than the thickness of one layer of the printed circuit board 10 .
[0041] In the embodiments of the present disclosure, reference Figure 2 , in the first direction Z, the length of the test point 30 is less than the thickness of one layer of the printed circuit board 10. For example, the length of the stub of the back drilling process can be controlled with an accuracy of 0.1 mm, and the length of the test point 30 can be 0.2 mm. Thus, under the premise of meeting the requirements of the back drilling process, the test point 30 can have a smaller size.
[0042] In some embodiments of the present disclosure, reference Figure 2 , the inner diameter of the back-drilled hole 40 is larger than the inner diameter of the test point 30 .
[0043] In the embodiments of the present disclosure, reference Figure 2 The inner diameter of the back-drilled hole 40 is larger than the inner diameter of the test point 30. For example, the diameter of the back-drilled hole 40 may be 0.37 mm, and the diameter of the test point 30 may be 0.25 mm. Thus, the back-drilled hole 40 can expose the top and bottom of the test point 30, which is convenient for external test equipment to directly contact.
[0044] Figure 5is a schematic diagram of an optional test structure 200 provided in an embodiment of the present disclosure, with reference to Figure 5 The test structure 200 includes: a main carrier board 201, a first chip particle 202, a second chip particle 203, and a test board 100. The first chip particle 202 and the test board 100 are both arranged on the main carrier board 201 and are both electrically connected to the main carrier board 201. The first chip particle 202 and the test board 100 are electrically connected through the main carrier board 201. The second chip particle 203 is arranged on the test board 100 and is electrically connected to the test board 100. The multiple test points of the test board 100 are used to connect external test equipment.
[0045] In the embodiments of the present disclosure, reference Figure 5 , the first chip particle 202 may include a system-on-chip (SOC). The second chip particle 203 may include a dynamic random access memory (DRAM). The external test equipment may be an oscilloscope. The multiple test points of the test board 100 may be used to connect the external test equipment. The external test equipment may test all key signals of the second chip particle 203, such as the data signal (Data Queue, DQ), the column address signal (Column Address, CA), the chip select signal (Chip Select, CS), the clock signal (Clock, CK), the write clock signal (Write Clock, WCK), and the bidirectional data isolation buffer enable signal (Read Data Strobe, RDQS) through the test board 100.
[0046] In the embodiments of the present disclosure, reference Figure 5 The first chip particle 202 and the test board 100 are both electrically connected to the main carrier board 201, and the second chip particle 203 can be connected to the main carrier board 201 by Figure 2 The pad 50 shown is electrically connected to the test board 100 , so that a main path between the first chip particle 202 and the second chip particle 203 can be established through the test board 100 and the main carrier board 201 .
[0047] In some embodiments of the present disclosure, reference Figure 5 , the projection of the test board 100 on the main carrier board 201 coincides with the projection of the second chip particle 203 on the main carrier board 100 .
[0048] Figure 6 2 is a schematic diagram of the structure of a first chip particle 202 and a second chip particle 203 provided in an embodiment of the present disclosure. It should be noted that: Figure 6In the circuit, there are usually many small components 204 such as resistors and capacitors arranged around the first chip particle 202 and the second chip particle 203. As power supply decoupling capacitors and calibration resistors, these small components 204 must be arranged close to the second chip particle 203. In the related technology, an interposer is directly inserted at the position of the second chip particle 203, and the interposer will interfere with the small components 204 such as resistors and capacitors around the second chip particle 203. At the same time, in order to ensure the signal quality, the design spacing between the first chip particle 202 and the second chip particle 203 cannot be too large, for example, 2mm. Therefore, if an interposer is directly inserted at the position of the second chip particle 203, the size of the interposer is 3 to 9mm larger than the size of the second chip particle 203. In other words, the interposer will interfere with the first chip particle 202.
[0049] In the embodiments of the present disclosure, reference Figure 5 , the projection of the test board 100 on the main carrier board 201 coincides with the projection of the second chip particle 203 on the main carrier board 100. For example, the test board 100 may be made of an adapter board. In the process of forming the test point 30, the embodiment of the present disclosure performs a milling process on the edge of the adapter board to reduce the size of the test board 100. In other words, the size of the test board 100 may be less than or equal to the size of the second chip particle 203. Thus, it is possible to avoid interference between the test board 100 and the peripheral devices 204 of the second chip particle 203 and the first chip particle 202.
[0050] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.
[0051] The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.
[0052] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.
Claims
1. A test board, characterized in that: include: Multilayer printed circuit board, multiple test paths and multiple test points; among them, The multiple layers of printed boards are stacked layer by layer along a first direction, wherein the first direction is perpendicular to the top surfaces of the multiple layers of printed boards; A plurality of the test paths are arranged in the multi-layer printed circuit board; The plurality of test points are all arranged on at least one side of the multi-layer printed circuit board and are all exposed to the side of the multi-layer printed circuit board; each of the test points is connected to the corresponding test path.
2. The test board according to claim 1, characterized in that: The length direction of the plurality of test points all extends along the first direction, and the cross-sections along the first direction all present a fan-shaped ring shape.
3. The test board according to claim 1, characterized in that: Back-drilled holes are formed on both sides of each test point along the first direction; the sidewalls of the back-drilled holes along the first direction are arc-shaped, exposing the top and bottom of the test point.
4. The test board according to claim 1, characterized in that: Each of the test paths comprises: a test wire and a metallized hole; The extension direction of the test wire is parallel to the top surface of the multi-layer printed circuit board; the metallized hole penetrates the multi-layer printed circuit board along the first direction; Each of the test points is connected to the metallized hole through the test wire.
5. The test board according to claim 4, characterized in that: An embedded resistor is provided on at least one layer of the multi-layer printed circuit board; the embedded resistor is connected in series in the test wire; In the extension direction of the test wire, the distance between the test point and the embedded resistor is greater than the distance between the metallized hole and the embedded resistor.
6. The test board according to claim 1, characterized in that: The length of the test point is less than the thickness of one layer of the printed circuit board.
7. The test board according to claim 3, characterized in that: The inner diameter of the back-drilled hole is larger than the inner diameter of the test point.
8. A test structure, characterized in that: include: A main carrier board, a first chip particle, a second chip particle, and a test board as claimed in any one of claims 1 to 7; wherein: The first chip particles and the test board are both arranged on the main carrier board and are electrically connected to the main carrier board; the first chip particles and the test board are electrically connected through the main carrier board; The second chip particles are arranged on the test board and are electrically connected to the test board; The multiple test points of the test board are used to connect external test equipment.
9. The test structure according to claim 8, characterized in that: The projection of the test board on the main carrier overlaps with the projection of the second chip particle on the main carrier.
10. The test structure according to claim 8, characterized in that: The first chip particle includes a system-level chip; the second chip particle includes a dynamic random access memory.