Circuit for preventing relay disconnection caused by abnormal working conditions

Abstract

The utility model provides a circuit for preventing relay disconnection caused by abnormal working conditions, which comprises a main control module, a latch module, an MOS driving module, a charging MOS unit and a discharging MOS unit, the main control module is connected with the latch module, the latch module is connected with the MOS driving module, the MOS driving module is respectively connected with the charging MOS unit and the discharging MOS unit, and the charging MOS unit is connected with the discharging MOS unit. An MOS driving instruction of the main control module firstly passes through the latch module and is transmitted to the MOS driving module through the output end of the latch module, finally, the charging MOS unit and the discharging MOS unit are controlled to be switched on and off, and due to the maintaining function of the latch module, even if a signal of the main control signal input end is pulled down, the charging MOS unit and the discharging MOS unit can be switched off. The charging MOS unit and the discharging MOS unit cannot be opened and still keep the closed state, and it is guaranteed that the charging MOS unit and the discharging MOS unit cannot change from the closed state to the abnormal open state when encountering abnormal working conditions in the operation process.

Description

Technical Field

[0001] The utility model relates to the technical field of battery management, and in particular to a circuit for preventing an abnormal working condition from causing a relay to be disconnected. Background Art

[0002] MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is increasingly used as a power switch on low-voltage power supply motherboards. Usually, MOSFET is controlled by an analog front end (AFE) and a microcontroller (MCU) to achieve precise drive and control of the MOSFET. AFE can monitor electrical parameters such as current and voltage, and feed back relevant information to the MCU to achieve intelligent control of the MOSFET. The MCU is responsible for controlling the on and off state of the MOSFET through the driver chip based on the data provided by the AFE to achieve precise management and protection of the power supply. Using MOSFET as a power switch can provide higher efficiency and better response speed, and it is also conducive to reducing power consumption and improving system stability. Therefore, it has been widely used on low-voltage power supply motherboards.

[0003] In the related art, the on and off of the charging MOS unit and the discharging MOS unit can be controlled by controlling the main control signal input terminal signal and the analog signal input terminal signal of the MOS driver chip. However, in practical applications, some emergencies may sometimes occur, such as chip reset, which may cause the main control signal input terminal signal to be abnormally pulled low, thereby causing the MOS unit to be abnormally disconnected during the reset process, affecting the normal operation of the system. Utility Model Content

[0004] In view of the above problems, an embodiment of the utility model provides a circuit for preventing abnormal working conditions from causing the relay to disconnect, and the circuit for preventing abnormal working conditions from causing the relay to disconnect includes: a main control module, a latch module, a MOS drive module, a charging MOS unit and a discharging MOS unit, wherein the main control module is connected to the latch module, the latch module is connected to the MOS drive module, and the MOS drive module is respectively connected to the charging MOS unit and the discharging MOS unit.

[0005] In a possible implementation, the latch module includes a latch chip, and the latch chip includes a data input terminal, a data output terminal, an output enable terminal and a latch enable terminal, wherein the data input terminal is connected to the main control module, and the data output terminal is connected to the MOS driver module.

[0006] In a possible implementation manner, the output enable terminal is connected to ground.

[0007] In a possible implementation, the latch chip is a 74HC573 chip.

[0008] In a possible implementation, the MOS driving module includes a MOS driving chip U7, the input end of the MOS driving chip U7 is connected to a main control signal input end and an analog signal input end, the discharge MOS unit includes a MOS tube M13, the gate of the MOS tube M13 is connected to a short-circuit protection signal pin, the source of the MOS tube M13 is connected to the main control signal input end and the analog signal input end, and the drain of the MOS tube M13 is respectively connected to the short-circuit protection signal pin and the ground end of the MOS driving chip U7.

[0009] In a possible implementation, the MOS driving module includes a MOS driving chip U6 , and an input end of the MOS driving chip U6 is connected to a main control signal input end and an analog signal input end.

[0010] In a possible implementation, the model of the MOS driver chip U7 and the MOS driver chip U6 is AUIR3241S.

[0011] The circuit for preventing the relay from being disconnected due to abnormal working conditions provided by the embodiment of the utility model comprises a main control module, a latch module, a MOS driving module, a charging MOS unit and a discharging MOS unit. The MOS driving instruction of the main control module first passes through the latch module, and is given to the MOS driving module by the output end of the latch module, and finally controls the charging MOS unit and the discharging MOS unit to be disconnected. Due to the holding function of the latch module, even if the signal at the main control signal input end is pulled low, the charging MOS unit and the discharging MOS unit will not be opened and will remain in a closed state, thereby ensuring that the charging MOS unit and the discharging MOS unit will not change from a closed state to an abnormal disconnected state when encountering abnormal working conditions during operation, so that the system is always in a normal power supply state. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a module block diagram of an embodiment of the utility model;

[0013] Figure 2 A schematic diagram of the circuit principle of an embodiment of the utility model;

[0014] Figure 3 A schematic diagram of the circuit principle of an embodiment of the utility model;

[0015] Figure 4 A schematic diagram of a latch chip according to an embodiment of the utility model;

[0016] Figure 5 The figure is a schematic diagram of the truth value representation of the latch chip according to the embodiment of the present utility model.

[0017] Description of reference numerals: 100, main control module; 200, latch module; 300, MOS driving module; 400, charging MOS unit; 500, discharging MOS unit. DETAILED DESCRIPTION

[0018] The overall idea of ​​the technical solution provided by the utility model is as follows:

[0019] See also Figure 1 , a circuit for preventing a relay from disconnecting due to abnormal operating conditions, comprising:

[0020] A main control module 100, a latch module 200, a MOS driving module 300, a charging MOS unit 400 and a discharging MOS unit 500, wherein the main control module 100 is connected to the latch module 200, the latch module 200 is connected to the MOS driving module 300, and the MOS driving module 300 is respectively connected to the charging MOS unit 400 and the discharging MOS unit 500. The MOS driving instruction of the main control module 100 first passes through the latch module 200, and is given to the MOS driving module 300 by the output end of the latch module 200, and finally controls the charging MOS unit 400 and the discharging MOS unit 500 to be disconnected. Due to the holding function of the latch module 200, even if the signal at the main control signal input end is pulled low, the charging MOS unit 400 and the discharging MOS unit 500 will not be opened and will remain in a closed state, ensuring that the charging MOS unit 400 and the discharging MOS unit 500 will not change from a closed state to an abnormal disconnected state when encountering abnormal conditions during operation, so that the system is always in a normal power supply state.

[0021] Specifically, the latch module 200 is a storage unit circuit that is sensitive to pulse levels and can change state under the action of a specific input pulse level. Latching is to temporarily store a signal to maintain a certain level state. The latch module 200 is used to latch the current state so that the input data remains latched at the output end of the interface circuit for a period of time and the state does not change until the latch is released. A high level at the latch enable end indicates a pass-through state, and a low level indicates a latched state. The latch enable end can be controlled to control the output data of the back end of the latch module 200.

[0022] In order to make the purpose, technical solution and advantages of the embodiment of the utility model clearer, the technical solution in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model. Obviously, the described embodiment is a part of the embodiment of the utility model, not all of the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0023] Further, the latch module 200 includes a latch chip, and the latch chip includes a data input terminal, a data output terminal, an output enable terminal and a latch enable terminal, wherein the data input terminal is connected to the main control module 100, and the data output terminal is connected to the MOS driver module 300. Optionally, the latch chip model is 74HC573. Figure 4 For the pin layout of the latch chip model 74HC573, please refer to Figure 4 , where D0~D7 are data input terminals, Q0~Q7 are data output terminals, OE (Output Enable) is the output enable terminal, and LE (Latch Enable) is the latch enable terminal.

[0024] Further, the output enable terminal is connected to ground, see Figure 5 , Figure 5 This is the positive value representation of the latch chip of model 74HC573. It can be seen from the truth table that when the output enable terminal is high, no matter what level the latch enable terminal and the data input terminal are in, its output is in high impedance state. At this time, the chip is in an uncontrollable state, so when designing the circuit, we directly ground the output enable terminal, that is, the latch chip is always in the enabled state. When the output enable terminal is low and the latch enable terminal is high, the data input terminal and the data output terminal are both high or low. When the latch enable terminal is low, no matter what level the data input terminal is, the data output terminal maintains the last data state. The latch chip latches the current state so that the input data remains latched at the output terminal of the interface circuit for a period of time and the state does not change until the latch is released. The high level of the latch enable terminal indicates the pass-through state, and the low level indicates the latch state. The output data of the back end of the latch chip can be controlled by controlling the latch enable terminal.

[0025] See also Figure 2 The MOS driving module 300 includes a MOS driving chip U7, the input end of the MOS driving chip U7 is connected to the main control signal input end and the analog signal input end, the discharge MOS unit 500 includes a MOS tube M13, the gate of the MOS tube M13 is connected to the short-circuit protection signal pin, the source of the MOS tube M13 is connected to the main control signal input end and the analog signal input end, the drain of the MOS tube M13 is respectively connected to the short-circuit protection signal pin and the ground end of the MOS driving chip U7, and the MOS driving chip U7 is used to receive signals from the main control module 100 and the analog signal module input end, and control the operation of the discharge MOS unit 500 according to the input main control signal and analog signal.

[0026] For details, please refer to Figure 2The main control signal input end of the MOS driver chip U7 includes the DI_DSG_EN_MCU pin, the analog signal input end includes the DI_DSG_EN_AFE pin, and the short-circuit protection signal pin includes the DI_SCP_EN_DSGMOS pin. The DI_DSG_EN_MCU pin is used to receive an instruction from the main control module 100 to control the on-off of the charging MOS unit 400. The DI_DSG_EN_AFE pin is used to receive an instruction from the analog signal module to control the on-off of the charging MOS unit 400. The DI_SCP_EN_DSGMOS pin is pulled high when the hardware is short-circuited to control the on-off of the discharge MOS unit 500.

[0027] For example, when the discharge MOS unit 500 is disconnected, either the DI_DSG_EN_MCU pin or the DI_DSG_EN_AFE pin becomes low level, and the DI_SCP_EN_DSGMOS pin becomes high level; when the discharge MOS unit 500 is closed, either the DI_DSG_EN_MCU pin or the DI_DSG_EN_AFE pin is high level and the DI_SCP_EN_DSGMOS pin becomes low level.

[0028] For further information, see Figure 3 The MOS driver module 300 includes a MOS driver chip U6, and the input end of the MOS driver chip U6 is connected to the signal input end and the analog signal input end of the main control module 100. Specifically, the main control signal input end of the MOS driver chip U6 includes a DI_CHG_EN_MCU pin, and the analog signal input end includes a DI_CHG_EN_AFE pin. The DI_CHG_EN_MCU pin is used to receive an instruction from the main control module 100 to control the on and off of the charging MOS unit 400, and the DI_CHG_EN_AFE pin is used to receive an instruction from the analog signal module to control the on and off of the charging MOS unit 400.

[0029] Preferably, the model of the MOS driver chip U7 and the MOS driver chip U6 is AUIR3241S.

[0030] Furthermore, the MOS driving instruction of the main control module 100 first passes through the latch chip of the latch module 200, and is given to the MOS driving module 300 by the output end of the latch chip, and finally realizes the disconnection control of the charging MOS unit 400 and the discharging MOS unit 500. The specific output signal of each pin in each state is described below through a complete power-on and power-off process;

[0031] MCU_EN_MOS is the pin for the main control module 100 to output MOS drive instructions.

[0032] When power is turned on, the charging MOS unit 400 and the discharging MOS unit 500 need to be closed, then:

[0033] MCU_EN_MOS=1 (high level, charging and discharging MOS closed);

[0034] Out Enable = 0 (low level);

[0035] Latch Enable = 0 (low level);

[0036] When an abnormal situation occurs during operation, such as software program crashes, MCU reset, etc., the status of each pin is:

[0037] MCU_EN_MOS=0(low level);

[0038] Out_Enable = 0 (low level, because low level is the default state);

[0039] Latch_Enable = 0 (low level);

[0040] Due to the holding function of the latch, even if MCU_EN_MOS=0, the charging MOS unit 400 and the discharging MOS unit 500 will not be opened and will remain in a closed state;

[0041] When power is turned off, the charging MOS unit 400 and the discharging MOS unit 500 need to be disconnected, then:

[0042] MCU_EN_MOS=0(low level);

[0043] Out Enable = 0 (low level);

[0044] Latch Enable = 1 (high level).

[0045] In summary, the embodiment of the utility model adds a latch module 200 to the circuit of the traditional design, and uses the latch function of the latch module 200 to ensure that the charging MOS unit 400 and the discharging MOS unit 500 will not change from the closed state to the open state due to abnormal conditions during operation, so that the system is always in a normal power supply state.

[0046] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present invention.

[0047] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations of the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A circuit for preventing a relay from disconnecting due to abnormal operating conditions, characterized in that: include: A main control module, a latch module, a MOS driving module, a charging MOS unit and a discharging MOS unit, wherein the main control module is connected to the latch module, the latch module is connected to the MOS driving module, and the MOS driving module is respectively connected to the charging MOS unit and the discharging MOS unit.

2. A circuit for preventing a relay from disconnecting due to abnormal working conditions according to claim 1, characterized in that: The latch module includes a latch chip, and the latch chip includes a data input terminal, a data output terminal, an output enable terminal and a latch enable terminal, wherein the data input terminal is connected to the main control module, and the data output terminal is connected to the MOS driving module.

3. A circuit for preventing a relay from disconnecting due to abnormal working conditions according to claim 2, characterized in that: The output enable terminal is connected to the ground.

4. A circuit for preventing a relay from disconnecting due to abnormal working conditions according to claim 2, characterized in that: The model of the latch chip is 74HC573.

5. A circuit for preventing a relay from disconnecting due to abnormal working conditions according to claim 1, characterized in that: The MOS driving module includes a MOS driving chip U7, the input end of the MOS driving chip U7 is connected to a main control signal input end and an analog signal input end, the discharging MOS unit includes a MOS tube M13, the gate of the MOS tube M13 is connected to a short-circuit protection signal pin, the source of the MOS tube M13 is connected to the main control signal input end and the analog signal input end, and the drain of the MOS tube M13 is respectively connected to the short-circuit protection signal pin and the ground end of the MOS driving chip U7.

6. A circuit for preventing a relay from disconnecting due to abnormal working conditions according to claim 5, characterized in that: The MOS driving module includes a MOS driving chip U6 , and an input end of the MOS driving chip U6 is connected to a main control signal input end and an analog signal input end.

7. A circuit for preventing a relay from disconnecting due to abnormal working conditions according to claim 6, characterized in that: The models of the MOS driver chip U7 and the MOS driver chip U6 are AUIR3241 S.

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