Computer communication electrical port adjustable switch

Abstract

The utility model discloses a computer communication electrical port adjustable switch, belongs to the technical field of communication, and solves the problem that once a wireless network card is damaged, data interaction between the switch and a computer is disconnected. Comprising a PHY chip, an RJ45 interface, and a transformer connected between the RJ45 interface and the PHY chip. The wireless router also comprises a POE separator, the POE separator is coupled with the RJ45 interface, and the POE separator is coupled with four wireless network cards through a switching circuit. During actual work, a data packet is transmitted to the switch through the wireless network card, is decoded by the PHY chip after passing through the PoE separator and the transformer, and then is processed and forwarded by the ASIC, the master control processor executes advanced functions, the PoE separator supplies power to the wireless network card, if the wireless network card fails, the microcontroller controls the relay to switch to the standby network card, and if the wireless network card fails, the relay switches to the standby network card. And the counting circuit notifies all network card faults.

Description

Technical Field

[0001] The utility model relates to the technical field of communication, in particular to a switch with adjustable electrical ports for computer communication. Background Art

[0002] A switch is a key network device that plays a pivotal role in data forwarding in modern communication networks. By connecting multiple devices through physical ports, the switch uses its internal switching matrix and cache to achieve fast exchange of data packets between different network nodes. Its core function is to intelligently forward data packets to the correct output port based on the destination MAC address of the data packet, effectively avoiding broadcast storms and data congestion in the network.

[0003] Modern switches usually have a wealth of advanced features, including but not limited to virtual local area network (VLAN) division, port mirroring, link aggregation, quality of service (QoS), network security functions such as access control lists (ACLs) and network address translation (NAT), and support for IPv4 and IPv6. These features not only enhance the flexibility and scalability of the network, but also improve the efficiency and security of data transmission.

[0004] The switch also supports remote monitoring and management through the Simple Network Management Protocol (SNMP), allowing network administrators to easily perform tasks such as configuration, monitoring network status, and traffic analysis. In addition, some high-end switches support software-defined networking (SDN) technology, allowing network administrators to control network behavior programmatically, further improving the intelligence and automation level of the network.

[0005] As network technology continues to evolve, switches are also integrating more advanced hardware and software technologies, such as supporting higher-speed Ethernet standards, integrating PoE (Power over Ethernet) power supply functions, and providing more complex traffic engineering and analysis tools. Switches are indispensable in building enterprise-level networks, data centers, service provider networks, and home networks. They are key components to ensure stable network operation and efficient data transmission.

[0006] At present, switches are actually used to communicate with computers through RJ45 interfaces and cables. In order to reduce the amount of cable wiring between the two and avoid the clutter of cables between the two, wireless network cards are used to perform wireless communication between the two. However, once the wireless network card is damaged, the data exchange between the switch and the computer will be disconnected.

[0007] Therefore, a computer communication electrical port adjustable switch is proposed to solve or alleviate the above problems. Utility Model Content

[0008] The purpose of the utility model is to solve the shortcomings existing in the prior art, and a computer communication electrical port adjustable switch is proposed. When working, the data packet is transmitted from the wireless network card to the switch, and is decoded by the PHY chip through the PoE separator and the transformer. Then the switch chip processes and forwards it. The main control processor is responsible for executing complex network functions. At the same time, the PoE separator supplies power to the wireless network card. If a wireless network card failure is detected, the microcontroller will automatically switch to the spare wireless network card, and send a notification through the counting circuit when all network cards fail.

[0009] In order to achieve the above purpose, the utility model adopts the following technical solutions:

[0010] A computer communication electrical port adjustable switch, comprising a PHY chip, an RJ45 interface, and a transformer connected between the RJ45 interface and the PHY chip;

[0011] It also includes a POE separator, which is coupled to the RJ45 interface. The POE separator is coupled to four wireless network cards through a switching circuit. The switching circuit is coupled to a wireless receiver for receiving signals sent by the wireless network cards. The switching circuit receives signals transmitted by the wireless receiver and keeps a wireless network card powered on.

[0012] Preferably, it also includes a counting circuit, the input end of the counting circuit is coupled to the switching circuit, the output end of the counting circuit is coupled to the PHY chip, and the counting circuit records the switching times of the switching circuit and transmits the switching times to the PHY chip.

[0013] Preferably, the switching circuit includes a microcontroller and a plurality of relays, the number of the relays is the same as the number of wireless network cards, the output end of the microcontroller is coupled to the controlled end of the relay, the relay controls the wireless network card to power off, the output end of the wireless receiver is coupled to the input end of the microcontroller, and the output end of the microcontroller is coupled to the input end of the counting circuit.

[0014] Preferably, the counting circuit comprises four D flip-flops, and the four D flip-flops are cascaded.

[0015] Preferably, it also includes a main control processor and a switching chip coupled thereto, and the switching chip is coupled to the PHY chip.

[0016] Preferably, the switching chip has a main control processor interface, and the main control processor interface is used to connect to the main control processor.

[0017] Preferably, the microcontroller is a STM32F103C8T6 controller.

[0018] The utility model has the following beneficial effects:

[0019] When the utility model is actually working, the data packet passes through the wireless network card to the switch, is decoded by the PHY chip after passing through the PoE splitter and the transformer, and is then processed and forwarded by the AS IC. The main control processor executes advanced functions, and the PoE splitter supplies power to the wireless network card. If the wireless network card fails, the microcontroller controls the relay to switch to the backup network card, and the counting circuit notifies all network cards of the failure. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the utility model, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the utility model and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 It is a structural block diagram of the utility model;

[0022] Figure 2 It is a structural block diagram of the switching circuit in the utility model;

[0023] Figure 3 It is the wiring diagram of the counting circuit in the utility model.

[0024] 1. Main control processor; 2. Switching chip; 3. PHY chip; 4. Transformer; 5. RJ45 interface; 6. POE separator; 7. Switching circuit; 701. Microcontroller; 702. Relay; 8. Wireless network card; 9. Wireless receiver; 10. Counting circuit. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical scheme and advantages of the embodiments of the utility model clearer, the technical scheme in the embodiments of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiments of the utility model. Obviously, the described embodiments are part of the embodiments of the utility model, not all of the embodiments. Generally, the components of the embodiments of the utility model described and shown in the drawings here can be arranged and designed in various different configurations.

[0026] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the present invention to be protected, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0028] In the description of the present utility model, it should be understood that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the utility model product is conventionally placed when in use, or are the orientations or positional relationships conventionally understood by those skilled in the art. They are only for the convenience of describing the present utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present utility model.

[0029] Furthermore, the terms “first”, “second”, “third”, etc. are merely used for distinguishing descriptions and are not to be understood as indicating or implying relative importance.

[0030] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0031] A computer communication electrical port adjustable switch, such as Figure 1 As shown, it includes a main control processor 1, a switching chip 2 coupled thereto, a PHY chip 3, an RJ45 interface 5, and a transformer 4 connected between the RJ45 interface 5 and the PHY chip 3, and the switching chip 2 is coupled to the PHY chip 3;

[0032] It also includes a POE splitter 6 and a counting circuit 10. The POE splitter 6 is coupled to the RJ45 interface 5. The POE splitter 6 is coupled to four wireless network cards 8 through a switching circuit 7. The switching circuit 7 is coupled to a wireless receiver 9 for receiving signals from the wireless network cards 8. The switching circuit 7 receives the signal transmitted by the wireless receiver 9 and keeps a certain wireless network card 8 powered on. The input end of the counting circuit 10 is coupled to the switching circuit 7. The output end of the counting circuit 10 is coupled to the PHY chip 3. The counting circuit 10 records the number of switching times of the switching circuit 7 and transmits the number of switching times to the PHY chip 3. When the number of switching times is greater than n times, the PHY chip 3 sends damage information. In a possible embodiment, n=4.

[0033] like Figure 2 As shown, the switching circuit 7 includes a microcontroller 701 which is a STM32F103C8T6 controller, and a plurality of relays 702, the number of the relays 702 is the same as the number of the wireless network card 8, the output end of the microcontroller 701 is coupled to the controlled end of the relay 702, the relay 702 controls the power on and off of the wireless network card 8, the output end of the wireless receiver 9 is coupled to the input end of the microcontroller 701, and the output end of the microcontroller 701 is coupled to the input end of the counting circuit 10.

[0034] like Figure 3 As shown, the counting circuit 10 includes four D flip-flops, and the four D flip-flops are cascaded.

[0035] One of the core functions of a counter circuit is to record the number of input pulse signals, and a single flip-flop can usually only store one binary number. By cascading multiple flip-flops, a multi-bit counter can be combined. Each flip-flop updates its output based on its input and current state under the action of a clock signal. In a cascade setting, the output of the previous flip-flop is usually used as the input or clock signal of the next flip-flop, thereby achieving cumulative counting from low to high bits.

[0036] In one possible embodiment, a 4-bit binary counter is formed by cascading four D flip-flops. When the clock signal arrives, the state of the first flip-flop is updated according to the input signal and the current state. If the state of the first flip-flop changes from 0 to 1, it triggers the update of the second flip-flop, and so on, eventually realizing the counting function of the 4-bit binary counter. This cascade method not only realizes the multi-bit counting function, but also optimizes the overall performance of the circuit through reasonable layout and signal transmission path.

[0037] When the data packet is transmitted to the switch through the wireless network card 8, it is first transmitted to the RJ45 interface 5 by the POE separator 6. After the voltage is adjusted to a suitable voltage by the transformer 4, the PHY chip 3 will receive the data packet, convert the electrical signal or optical signal into a format suitable for processing by the network device, and decode it. The decoded data packet is sent to the switching chip 2, where the data packet is identified according to its source and destination MAC addresses. The switching chip 2 uses the internal routing table or MAC address table to determine the forwarding path of the data packet. If the destination is in the same LAN, the data packet will be forwarded to the corresponding port; if the destination is in a different network, the data packet may be forwarded to the port connected to the router, and the switching chip 2 will quickly forward the data packet to the correct port. This process may involve an internal switching matrix to ensure that the data packet is efficiently transmitted between different ports. Before the data packet is forwarded, the main control processor 1 may also perform some access control and advanced functions, such as ACL checking, QoS management, VLAN tag processing, etc. It should be noted that the POE separator 6 will separate the data and signal transmitted from the RJ45 interface 5, so that the power transmitted by the POE separator 6 can power the wireless network card 8 through the switching circuit 7. If the first wireless network card 8 itself can perform data transmission normally, then the wireless receiver 9 can also receive the data from the wireless network card 8, and the wireless receiver 9 will send it The signal is transmitted to the microcontroller 701, and the microcontroller 701 controls the relay 702 to remain in its original state. If the first wireless network card 8 cannot send a signal, the wireless receiver 9 cannot receive it. The microcontroller 701 then controls the second relay 702 to turn on the circuit where the second wireless network card 8 is located and energize it. Similarly, after the wireless network card 8 can receive the signal, the microcontroller 701 controls the second relay 702 to remain in its original state. On the contrary, if the second wireless network card 8 is also damaged, the third wireless network card 8 repeats the above action. If it occurs again, the fourth wireless network card 8 repeats the above action. If it occurs for the fifth time, there is no more action. In this process, the counting circuit 10 counts. After the count reaches 4 times, a counting signal is sent to the PHY chip 3, and the PHY chip 3 encodes the signal and transmits it to the main control processor 1, so that the user can understand that all the wireless network cards 8 are damaged.

[0038] On the contrary, when the switch's main control processor 1 receives instructions from the network or user configuration, it determines the output port of the data packet based on the internally maintained routing table or MAC address table. The switch chip 2 then receives the data packet from the main control processor 1 and uses its high-speed forwarding capability to send the data packet to the PHY chip 3 of the designated port.

[0039] The PHY chip 3 is responsible for converting the electrical signal of the data packet into a format suitable for transmission through the wireless network and ensuring the integrity and stability of the signal. Subsequently, the data packet passes through the RJ45 interface 5, and the switch passes the data packet to the wireless network card 8 through the POE splitter 6, and the wireless network card 8 transmits it to the next network device, such as a computer. During the whole process, the internal circuit of the switch ensures that the data packet is transmitted with minimal delay and maximum efficiency. At the same time, the main control processor 1 may also perform advanced functions such as access control, QoS management and VLAN processing on the data packet to ensure the security and priority of data transmission.

[0040] The above description is only the preferred embodiment of the utility model, and is not intended to limit the utility model. For those skilled in the art, the utility model can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the utility model shall be included in the protection scope of the utility model.

Claims

1. A computer communication electrical port adjustable switch, characterized in that: It comprises a PHY chip (3), an RJ45 interface (5), and a transformer (4) connected between the RJ45 interface (5) and the PHY chip (3); The invention also comprises a POE separator (6), wherein the POE separator (6) is coupled to the RJ45 interface (5), wherein the POE separator (6) is coupled to four wireless network cards (8) via a switching circuit (7), wherein the switching circuit (7) is coupled to a wireless receiver (9) for receiving signals sent by the wireless network card (8), and wherein the switching circuit (7) receives signals transmitted by the wireless receiver (9) and keeps a certain wireless network card (8) powered on.

2. A computer communication electrical port adjustable switch according to claim 1, characterized in that: The invention also comprises a counting circuit (10), wherein an input end of the counting circuit (10) is coupled to the switching circuit (7), and an output end of the counting circuit (10) is coupled to the PHY chip (3). The counting circuit (10) records the number of switching times of the switching circuit (7) and when the number of switching times is greater than 4 times, the PHY chip (3) issues damage information.

3. A computer communication electrical port adjustable switch according to claim 1, characterized in that: The switching circuit (7) comprises a microcontroller (701) and a plurality of relays (702), wherein the number of the relays (702) is the same as the number of the wireless network card (8), the output end of the microcontroller (701) is coupled to the controlled end of the relay (702), the relay (702) controls the power on and off of the wireless network card (8), the output end of the wireless receiver (9) is coupled to the input end of the microcontroller (701), and the output end of the microcontroller (701) is coupled to the input end of the counting circuit (10).

4. A computer communication electrical port adjustable switch according to claim 2, characterized in that: The counting circuit (10) comprises four D flip-flops, and the four D flip-flops are cascaded.

5. A computer communication electrical port adjustable switch according to claim 1, characterized in that: It also includes a main control processor (1) and a switching chip (2) coupled thereto, wherein the switching chip (2) is coupled to a PHY chip (3).

6. A computer communication electrical port adjustable switch according to claim 3, characterized in that: The microcontroller (701) is a STM32F103C8T6 controller.

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