Display device

Abstract

A display device includes: a substrate including a display area in which a display element is arranged; a first sub-pixel circuit unit in the display area and including a first sub-pixel circuit, a second sub-pixel circuit, and a third sub-pixel circuit; a first scan line extending from one side of the first sub-pixel circuit unit in a first direction; a second scan line extending from the other side of the first sub-pixel circuit unit in the first direction; a first branch line extending from the first scan line in a second direction crossing the first direction; and a first compensation line extending in the first direction from the first branch line toward the first sub-pixel circuit adjacent to the second scan line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0039211 filed on March 24, 2023, in the Korean Intellectual Property Office and No. 10-2023-0077061 filed on June 15, 2023, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Aspects of the present disclosure relate to a display device. Background Art

[0004] A display device displays data in a visual manner. A display device may be configured to provide an image using light emitting diodes. Display devices have been used for various purposes, and various designs have been tried to improve the quality of display devices. Utility Model Content

[0005] Aspects of some embodiments relate to a display device with improved reliability and quality. However, this is only an example, and the technical objectives of the embodiments are not limited thereto.

[0006] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the embodiments presented in the disclosure.

[0007] According to some embodiments of the present disclosure, a display device is provided, comprising: a substrate, comprising a display area, in which display elements are arranged; a first sub-pixel circuit unit, in the display area, and comprising a first sub-pixel circuit, a second sub-pixel circuit, and a third sub-pixel circuit; a first scan line, extending from one side of the first sub-pixel circuit unit in a first direction; a second scan line, extending from the other side of the first sub-pixel circuit unit in the first direction; a first branch line, extending from the first scan line in a second direction intersecting the first direction; and a first compensation line, extending from the first branch line in the first direction toward the first sub-pixel circuit adjacent to the second scan line.

[0008] In some embodiments, the first sub-pixel circuit includes: a first thin film transistor, which is in the display area and includes a first semiconductor layer and a first gate electrode insulated from the first semiconductor layer; and a second thin film transistor, which is in the display area and includes a second semiconductor layer and a second gate electrode insulated from the second semiconductor layer.

[0009] In some embodiments, a minimum distance between the first thin film transistor and the second scan line in the second direction is smaller than a minimum distance between the second thin film transistor and the second scan line in the second direction.

[0010] In some embodiments, the first sub-pixel circuit is adjacent to the second scan line, the third sub-pixel circuit is adjacent to the first scan line, and the second sub-pixel circuit is between the first sub-pixel circuit and the third sub-pixel circuit.

[0011] In some embodiments, at least a portion of the first branch line is integrally formed in the first gate electrode of the first thin film transistor.

[0012] In some embodiments, at least a portion of the first branch line is integrally formed in the second gate electrode of the second thin film transistor.

[0013] In some embodiments, the first compensation line is at the same layer as the first branch line and includes a same material as that of the first branch line.

[0014] In some embodiments, the first compensation line is between the second scan line and the first thin film transistor, and extends from the first branch line in the first direction.

[0015] In some embodiments, the first compensation line is between the first thin film transistor and the second thin film transistor, and extends from the first branch line in the first direction.

[0016] In some embodiments, the display device further includes a second compensation line extending from the first branch line toward the second sub-pixel circuit in the first direction.

[0017] In some embodiments, the second compensation line is at the same layer as the first branch line and includes a same material as that of the first branch line.

[0018] According to some embodiments of the present disclosure, a display device is provided, which includes: a substrate, including a display area, in which display elements are arranged; a second sub-pixel circuit unit, in the display area, and including a first sub-pixel circuit, a second sub-pixel circuit, and a third sub-pixel circuit; a first scan line, extending from one side of the second sub-pixel circuit unit in a first direction; a second scan line, extending from the other side of the second sub-pixel circuit unit in the first direction; a second branch line, extending from the second scan line in a second direction intersecting the first direction; and a third compensation line, extending from the second branch line in the first direction toward the third sub-pixel circuit adjacent to the first scan line.

[0019] In some embodiments, the third sub-pixel circuit includes: a third thin film transistor, which is in the display area and includes a third semiconductor layer and a third gate electrode insulated from the third semiconductor layer; and a fourth thin film transistor, which is in the display area and includes a fourth semiconductor layer and a fourth gate electrode insulated from the fourth semiconductor layer.

[0020] In some embodiments, a minimum distance between the third thin film transistor and the first scan line in the second direction is smaller than a minimum distance between the fourth thin film transistor and the first scan line in the second direction.

[0021] In some embodiments, the second branch line is integrally formed in the third gate electrode of the third thin film transistor.

[0022] In some embodiments, the second branch line is integrally formed in the fourth gate electrode of the fourth thin film transistor.

[0023] In some embodiments, the third compensation line is at the same layer as the second branch line and includes a same material as that of the second branch line.

[0024] In some embodiments, the third compensation line is between the first scan line and the third thin film transistor, and extends from the second branch line in the first direction.

[0025] In some embodiments, the third compensation line is between the third thin film transistor and the fourth thin film transistor, and extends from the second branch line in the first direction.

[0026] In some embodiments, the display device further includes a fourth compensation line extending from the second branch line toward the second sub-pixel circuit in the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0028] Figure 1 and Figure 2 are perspective views each schematically showing a display device according to some embodiments of the present disclosure;

[0029] Figure 3 is an equivalent circuit diagram schematically showing any sub-pixel circuit provided in a display device according to some embodiments of the present disclosure;

[0030] Figure 4 is a cross-sectional view schematically showing a display device according to some embodiments of the present disclosure;

[0031] Figure 5 is a top plan view schematically showing a sub-pixel provided in a display device according to some embodiments of the present disclosure;

[0032] Figure 6 and Figure 7 are top plan views each schematically illustrating a sub-pixel circuit provided in a display device according to some embodiments of the present disclosure; and

[0033] Figure 8 and Fig. 9 are top plan views each schematically illustrating a sub-pixel circuit provided in a display device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0034] Reference will now be made in detail to embodiments, examples of which are shown in the accompanying drawings, wherein the same reference numerals refer to the same elements throughout the text. In this regard, these embodiments may have different forms and should not be construed as being limited to the description set forth herein. Accordingly, embodiments are described below with reference only to the accompanying drawings to explain various aspects of the present description.

[0035] It will be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, without departing from the spirit and scope of the present disclosure, the first element, component, region, layer or section discussed below may be referred to as a second element, component, region, layer or section.

[0036] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", and "upper" may be used herein to describe the relationship between an element or feature and another element (or other elements) or feature (or other features) as shown in the figure. It will be understood that, in addition to the orientation depicted in the figure, spatially related terms are also intended to cover different orientations of the device in use or operation. For example, if the device in the figure is turned over, the element described as "below" or "below" or "below" other elements or features will be oriented as "above" other elements or features. Therefore, the example terms "below" and "below" can cover both the above and below orientations. The device can be oriented in other ways (e.g., rotated 90 degrees or oriented in other directions), and the spatially relative descriptors used in this article should be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as "between" two layers, it can be the only layer between the two layers, or there can also be one or more intervening layers.

[0037] The terms used herein are for the purpose of describing specific embodiments and are not intended to limit the present disclosure. Unless the context clearly indicates otherwise, as used herein, the singular forms "a" and "one (kind / person)" are also intended to include plural forms. It will also be understood that when used in this specification, the terms "include, including", "comprises, comprising", "has, have and having" illustrate the presence of stated features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their groups.

[0038] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, the expression "A and / or B" means A, B, or A and B. Expressions such as "one or more of..." and "at least one of..." when following a list of elements modify the entire list of elements without modifying the individual elements of the list. For example, the expressions "one or more of A, B, and C," "at least one of A, B, and C," and "at least one of the group consisting of A, B, and C" mean only A, only B, only C, both A and B, both A and C, both B and C, or all of A, B, and C.

[0039] Additionally, the use of “may” when describing embodiments of the present disclosure refers to “one or more embodiments of the present disclosure.” Additionally, the term “exemplary” is intended to indicate an example or illustration.

[0040] It will be understood that when an element or layer is referred to as being "on," "connected to," "coupled to," or "adjacent to" another element or layer, the element or layer may be directly on, connected to, coupled to, or adjacent to the other element or layer, or there may be one or more intervening elements or layers. When an element or layer is referred to as being "directly on," "directly connected to," "directly coupled to," "in contact with," "directly in contact with," or "immediately adjacent to" another element or layer, there are no intervening elements or layers.

[0041] As used herein, the terms "substantially," "about," and similar terms are used as terms of approximation, rather than terms of degree, and are intended to account for the inherent variations in measurements or calculations that would be recognized by one of ordinary skill in the art. In addition, specific amounts or ranges recited in this written description or claims may also encompass the inherent variations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0042] As used herein, the terms "use," "using," and "used" may be considered synonymous with the terms "utilize," "utilizing," and "utilized," respectively.

[0043] When one or more embodiments may be implemented differently, the specific process order may be performed differently from the order described. For example, (i) the disclosed operations of the process are only examples and may involve various additional operations that are not explicitly covered, and (ii) the temporal order of the operations may be changed.

[0044] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will also be understood that, unless expressly defined as such herein, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense.

[0045] The display device and / or any other related device or component according to the embodiment of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application specific integrated circuit), software, or a suitable combination of software, firmware and hardware. For example, the various components of the display device can be formed on an integrated circuit (IC) chip, or formed on a plurality of separated IC chips. In addition, the various components of the display device can be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on the same substrate. In addition, the various components of the display device can be in one or more computing devices, running on one or more processors, executing computer program instructions and interacting with other system components to perform various functions described herein. Processes or threads. Computer program instructions are stored in a memory, which can be implemented in a computing device using a standard memory device (such as, for example, a random access memory (RAM)). Computer program instructions can also be stored in other non-temporary computer-readable media, such as, for example, a read-only compact disk memory (CD-ROM) or a flash drive, etc. In addition, those skilled in the art should recognize that the functions of various computing devices may be combined or integrated into a single computing device, or the functions of a particular computing device may be distributed on one or more other computing devices without departing from the scope of the exemplary embodiments of the present invention.

[0046] In the drawings, the size of the elements may be enlarged or reduced for ease of description. For example, since the size and thickness of each element are arbitrarily shown in the drawings for ease of description, the present disclosure is not necessarily limited to those shown.

[0047] When some embodiments may be implemented differently, a specific process order may be performed in a manner different from the order described. For example, two processes described in succession may be performed substantially simultaneously, or may be performed in an order opposite to the order described.

[0048] In this specification, when it is mentioned that a film, region and component are connected to another film, region and component, the film, region and component may be directly connected to the other film, region and component, or may be indirectly connected to another film, region and component between them. For example, when it is mentioned that a film, region and component is electrically connected to another film, region and component, the film, region and component may be directly electrically connected to the other film, region and component, or may be indirectly electrically connected to the other film, region and component with another film, region and component between them.

[0049] The x-direction, y-direction, and z-direction are not limited to the three axes on the orthogonal coordinate system, and can be interpreted as a broad meaning including the orthogonal coordinate system. For example, the x-direction, y-direction, and z-direction can be orthogonal to each other, but can also refer to different directions that are not orthogonal to each other.

[0050] Figure 1 and Figure 2 are perspective views each schematically showing a display device 1 according to some embodiments of the present disclosure.

[0051] Reference Figure 1 and Figure 2 , the display device 1 may include a display area DA and a non-display area NDA located outside the display area DA. The display area DA may be configured to display an image through sub-pixels P arranged in the display area DA. The non-display area NDA is an area that is arranged outside the display area DA and does not display an image, and it may completely surround the display area DA. A driver configured to provide an electrical signal or power to the display area DA may be arranged in the non-display area NDA. A pad is an element to which an electronic device or a printed circuit board can be electrically connected, and it may be arranged in the non-display area NDA.

[0052] In some embodiments, Figure 1 The display area DA is shown to have a polygonal shape (eg, a rectangular shape) on a plane, wherein the length in the x direction is smaller than the length in the y direction. However, in some other embodiments, Figure 2 The display area DA is shown to have a polygonal shape (eg, a rectangular shape) on a plane, in which the length in the y direction is smaller than the length in the x direction. Figure 1 and Figure 2 The display area DA is shown to have an approximately rectangular shape on a plane, but the embodiments of the present disclosure are not limited thereto. In some other examples, the display area DA may have various suitable shapes on a plane, such as other N-sided shapes (where N is a natural number equal to or greater than three), a circle, or an ellipse, etc. Figure 1 and Figure 2 The display area DA is shown to have a shape in which a corner portion of the display area DA includes a vertex where two straight lines intersect each other on a plane, but in some other examples, the display area DA may have a polygonal shape having a rounded corner portion.

[0053] Hereinafter, for the sake of convenience of explanation, the case where the display device 1 includes an electronic device (e.g., a smart phone) will be described, but the display device 1 according to the embodiment is not limited thereto. For example, the display device 1 can be applied to various products such as televisions, notebook computers, monitors, billboards, and Internet of Things (IoT) devices, as well as mobile electronic devices such as mobile phones, smart phones, tablet personal computers, mobile communication terminals, electronic manuals, electronic books, portable multimedia players, navigation systems, and ultra-mobile personal computers (PCs). In addition, the display device 1 according to some embodiments is used for wearable devices such as smart watches, watch phones, and head-mounted displays (HMDs). The display device 1 according to some examples may include a central information display (CID) arranged on a dashboard or a central dashboard of a vehicle, may include an in-vehicle mirror display instead of a side mirror of the vehicle, and may be used as a display screen arranged on the rear surface of a front seat as an entertainment facility for passengers in the rear seat of the vehicle.

[0054] Figure 3 Schematically shows an equivalent circuit diagram of any sub-pixel circuit PC provided in the display device 1 according to some embodiments of the present disclosure. The display device 1 mentioned here and below can refer to Figure 1 The display device 1 shown in FIG.

[0055] Reference Figure 3 , the sub-pixel circuit PC may include a plurality of thin film transistors and at least one capacitor. In some embodiments, the sub-pixel circuit PC includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3 and a storage capacitor Cst.

[0056] Each of the first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor T3 may include: an oxide semiconductor thin film transistor including a semiconductor layer including an oxide semiconductor; or a silicon semiconductor thin film transistor including a semiconductor layer including polycrystalline silicon. Each of the first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor T3 may include a first electrode and a second electrode, and depending on the type of the thin film transistor, the first electrode may include one of a source electrode and a drain electrode, and the second electrode may include the other of a source electrode and a drain electrode. In addition, each of the first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor may include a gate electrode.

[0057] The first thin film transistor T1 may include a driving thin film transistor. A first electrode of the first thin film transistor T1 may be connected to a driving voltage line VDL configured to provide a driving power supply voltage ELVDD, and a second electrode of the first thin film transistor T1 may be connected to a pixel electrode of the organic light emitting diode OLED. A gate electrode of the first thin film transistor T1 may be connected to a first node N1. The first thin film transistor T1 may be configured to control an amount of power (e.g., an amount of current) flowing from the driving power supply voltage ELVDD through the organic light emitting diode OLED in response to a voltage of the first node N1.

[0058] The second thin film transistor T2 may include a switching thin film transistor. A first electrode of the second thin film transistor T2 may be connected to the data line DL, and a second electrode of the second thin film transistor T2 may be connected to the first node N1. A gate electrode of the second thin film transistor T2 may be connected to the scan line SL. The second thin film transistor T2 may be turned on when a scan signal is provided from the scan line SL, and may electrically connect the data line DL and the first node N1.

[0059] The third thin film transistor T3 may include an initialization thin film transistor and / or a sensing thin film transistor. A first electrode of the third thin film transistor T3 may be connected to the second node N2, and a second electrode of the third thin film transistor T3 may be connected to the initialization voltage line INL. A gate electrode of the third thin film transistor T3 may be connected to the scan line SL.

[0060] The third thin film transistor T3 may be turned on when a scan signal is provided from the scan line SL, and may electrically connect the initialization voltage line INL and the second node N2. In some embodiments, the third thin film transistor T3 is turned on in response to a signal transmitted through the scan line SL, and may initialize a pixel electrode of the organic light emitting diode OLED using an initialization voltage from the initialization voltage line INL.

[0061] In some embodiments, the third thin film transistor T3 is turned on when a scan signal is provided from the scan line SL, and characteristic information of the organic light emitting diode OLED can be sensed. The third thin film transistor T3 can have all or any one of the functions of an initialization thin film transistor or a sensing thin film transistor. The initialization operation and the sensing operation of the third thin film transistor T3 can be performed separately or in parallel (e.g., simultaneously). When the third thin film transistor T3 has the function of a sensing thin film transistor, the initialization voltage line INL can be referred to as a sensing line.

[0062] The storage capacitor Cst may be connected between the first node N1 and the second node N2. For example, a first capacitor plate (e.g., a first capacitor electrode) of the storage capacitor Cst may be connected to the gate electrode of the first thin film transistor T1, and a second capacitor plate (e.g., a second capacitor electrode) of the storage capacitor Cst may be connected to the pixel electrode of the organic light emitting diode OLED.

[0063] The counter electrode of the organic light emitting diode OLED may be connected to a common voltage line VSL configured to provide a common power voltage ELVSS.

[0064] Although Figure 3 The sub-pixel circuit PC is shown to include three thin film transistors and one storage capacitor, but the embodiments of the present disclosure are not limited thereto. In some other embodiments, the number of thin film transistors or the number of storage capacitors can be modified in various ways in a suitable manner according to the design of the sub-pixel circuit PC.

[0065] Figure 4 is a cross-sectional view schematically showing a display device 1 according to some embodiments of the present disclosure. More specifically, Figure 4 is schematically shown along Figure 1 1 is a cross-sectional view of the display panel 10 of the display device 1 taken along line II′.

[0066] Reference Figure 4 , the display panel 10 may include a substrate 100, a buffer layer 111, an inorganic insulating layer IIL, an organic insulating layer OIL, a sub-pixel circuit PC, a connection electrode CM, an organic light emitting diode OLED, a pixel defining film 118, a spacer 119, an encapsulation layer 300, and an input sensing layer 40. In other words, the substrate 100, the buffer layer 111, the inorganic insulating layer IIL, the organic insulating layer OIL, the sub-pixel circuit PC, the connection electrode CM, the organic light emitting diode OLED, the pixel defining film 118, the spacer 119, the encapsulation layer 300, and the input sensing layer 40 may be arranged in the display area DA of the display panel 10.

[0067] The substrate 100 may include a first base layer 100a, a first barrier layer 100b, a second base layer 100c, and a second barrier layer 100d. In some embodiments, the first base layer 100a, the first barrier layer 100b, the second base layer 100c, and the second barrier layer 100d are sequentially stacked in the thickness direction of the substrate 100 (eg, along the z direction).

[0068] At least one of the first base layer 100a and the second base layer 100c may include a polymer resin such as polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, cellulose acetate propionate, or the like.

[0069] The first barrier layer 100b and the second barrier layer 100d as barrier layers for preventing or substantially reducing the penetration of foreign matter may each include a single layer or a multilayer including silicon nitride (SiN x ), silicon oxide (SiO 2 ) or silicon oxynitride (SiO x N y ) and other inorganic materials.

[0070] The buffer layer 111 may be disposed on the substrate 100. The buffer layer 111 may include a SiN x 、SiO x N y or SiO 2 and the like, and may include a single layer or multiple layers containing the aforementioned inorganic insulating materials.

[0071] The inorganic insulating layer IIL may be disposed on the buffer layer 111. The inorganic insulating layer IIL may include a first gate insulating layer 112, a second gate insulating layer 113, and an interlayer insulating layer 114.

[0072] The sub-pixel circuit PC may be arranged in the display area DA. The sub-pixel circuit PC may include a thin film transistor TFT and a storage capacitor Cst. The thin film transistor TFT may include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0073] The semiconductor layer Act may be disposed on the buffer layer 111. The semiconductor layer Act may include polysilicon and / or the like. In some examples, the semiconductor layer Act may include amorphous silicon, an oxide semiconductor, and / or an organic semiconductor, etc. The semiconductor layer Act may include a channel region, and may further include a drain region and a source region disposed at both sides (e.g., opposite sides) of the channel region.

[0074] The gate electrode GE may be disposed above the semiconductor layer Act. The gate electrode GE may overlap the channel region. The gate electrode GE may include a low-resistance metal material. The gate electrode GE may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and may include a multilayer or a single layer including the foregoing materials.

[0075] The first gate insulating layer 112 may be disposed between the semiconductor layer Act and the gate electrode GE. The first gate insulating layer 112 may include an inorganic insulating material such as SiO 2 、SiN x 、SiO x N y 、Alumina (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or zinc oxide (ZnO x , which can be ZnO or ZnO 2 )wait.

[0076] The second gate insulating layer 113 may be disposed on the gate electrode GE. The second gate insulating layer 113 may be provided to cover the gate electrode GE. The second gate insulating layer 113 may include an inorganic insulating material such as SiO 2 、SiN x 、SiO x N y 、Al 2 O 3 、TiO 2 、 2 O 5 , HfO 2 or ZnO x (ZnO or ZnO 2 )wait.

[0077] The second capacitor plate (e.g., second capacitor electrode) CE2 of the storage capacitor Cst may be disposed on the second gate insulating layer 113. The second capacitor plate CE2 may overlap the gate electrode GE disposed thereunder. In this case, the gate electrode GE and the second capacitor plate CE2 overlapping each other and the second gate insulating layer 113 therebetween may form a storage capacitor Cst. In other words, the gate electrode GE may function as a first capacitor plate (e.g., first capacitor electrode) CE1 of the storage capacitor Cst.

[0078] In this way, the storage capacitor Cst and the thin film transistor TFT may be formed in an overlapping manner. However, the embodiments of the present disclosure are not limited thereto. For example, the storage capacitor Cst may be formed so as not to overlap with the thin film transistor TFT. In other words, the first capacitor plate CE1 of the storage capacitor Cst may be a component separated from the gate electrode GE of the thin film transistor TFT, and may be provided separately from the gate electrode GE of the thin film transistor TFT.

[0079] The second capacitor plate CE2 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and / or copper (Cu), etc., and may include a single layer or multiple layers containing the aforementioned materials.

[0080] The interlayer insulating layer 114 may be disposed on the second capacitor plate CE2. The interlayer insulating layer 114 may cover the second capacitor plate CE2. The interlayer insulating layer 114 may include SiO 2 、SiN x 、SiO x N y 、Al 2 O 3 、TiO 2 、 2 O 5 , HfO 2 and / or ZnO x (ZnO or ZnO 2 ) etc. The interlayer insulating layer 114 may include a single layer or a plurality of layers including the aforementioned inorganic insulating material.

[0081] Each of the drain electrode DE and the source electrode SE may be disposed on the interlayer insulating layer 114. The drain electrode DE and the source electrode SE may each be connected to the semiconductor layer Act through a contact hole provided in the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 114. The drain electrode DE and the source electrode SE may include a highly conductive material. The drain electrode DE and the source electrode SE may include a conductive material including Ti, Mo, Al, and / or Cu, etc., and may each include a multilayer or a single layer including the foregoing materials. For example, the drain electrode DE and the source electrode SE may each have a multilayer structure including Ti / Al / Ti.

[0082] The organic insulating layer OIL may be disposed on the inorganic insulating layer IIL. The organic insulating layer OIL may include a first organic insulating layer 115 and a second organic insulating layer 116. Figure 6 It is shown that the organic insulating layer OIL is provided as two organic insulating layers, but the embodiments of the present disclosure are not limited thereto. The organic insulating layer OIL may also be provided as three or four organic insulating layers.

[0083] The first organic insulating layer 115 may cover the drain electrode DE and the source electrode SE. The first organic insulating layer 115 may include an organic insulating material, for example, a general polymer such as polystyrene (PS), polymethyl methacrylate (PMMA), a polymer derivative having a phenol group, an acrylic polymer, an imide polymer, an aromatic ether polymer, an amide polymer, a fluoride polymer, a p-xylene polymer, a vinyl alcohol polymer, or a mixture thereof.

[0084] The connection electrode CM may be disposed on the first organic insulating layer 115. In this case, the connection electrode CM may be connected to the drain electrode DE or the source electrode SE through a contact hole in the first organic insulating layer 115. The electrode CM may include a highly conductive material. The connection electrode CM may include a conductive material including Mo, Al, Cu, and / or Ti, etc., and may include a multilayer or a single layer including the foregoing materials. For example, the connection electrode CM may have a multilayer structure including Ti / Al / Ti.

[0085] The second organic insulating layer 116 may be disposed on the connection electrode CM. The second organic insulating layer 116 may cover the connection electrode CM. The second organic insulating layer 116 may include a material that is the same as or different from that of the first organic insulating layer 115 .

[0086] A light emitting diode may be disposed on the second organic insulating layer 116. For example, an organic light emitting diode OLED may be disposed on the second organic insulating layer 116. In some examples, an inorganic light emitting diode or the like may be disposed on the second organic insulating layer 116.

[0087] The organic light emitting diode OLED may be configured to emit red, green, or blue light, or to emit red, green, blue, or white light. The organic light emitting diode OLED may include a first electrode 211, an emission layer 212b, a functional layer 212f, a second electrode 213, and a capping layer 215. The first electrode 211 may include a pixel electrode (e.g., an anode) of the organic light emitting diode OLED, and the second electrode 213 may include a counter electrode (e.g., a cathode) of the organic light emitting diode OLED.

[0088] The first electrode 211 may be disposed on the second organic insulating layer 116. The first electrode 211 may be electrically connected to the connection electrode CM through a contact hole defined in the second organic insulating layer 116. The first electrode 211 may include a conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3), indium gallium oxide (IGO) or aluminum zinc oxide (AZO), etc.). In some embodiments, the first electrode 211 includes a reflective film, and the reflective film includes silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or their compounds. In some embodiments, the first electrode 211 also includes ITO, IZO, ZnO and / or In on / below the aforementioned reflective film. 2 O 3 For example, the first electrode 211 may have a multi-layer structure including ITO / Ag / ITO.

[0089] A pixel defining film 118 may be disposed on the first electrode 211, and an opening exposing at least a portion of the first electrode 211 is defined in the pixel defining film 118. An emission region of light emitted from the organic light emitting diode OLED may be defined by the opening defined in the pixel defining film 118. For example, the width of the opening may correspond to the width of the emission region.

[0090] The pixel definition film 118 may include an organic insulating material. In some examples, the pixel definition film 118 may include an organic insulating material such as SiN x 、SiO x N y or SiO 2 Inorganic insulating materials such as organic insulating materials and inorganic insulating materials. In some examples, the pixel defining film 118 may include an organic insulating material and an inorganic insulating material. In some embodiments, the pixel defining film 118 includes a shading material. The shading material may include a resin or paste containing carbon black, carbon nanotubes, a black dye, metal (e.g., Ni, Al, Mo and their alloys) particles, metal oxide (e.g., chromium oxide) particles, or metal nitride (e.g., chromium nitride) particles. When the pixel defining film 118 includes a shading material, the reflection of external light caused by the metal structure disposed under the pixel defining film 118 can be reduced.

[0091] The spacer 119 may be disposed on the pixel definition film 118. The spacer 119 may include an organic insulating material such as polyimide. In some examples, the spacer 119 may include an organic insulating material such as SiN x or SiO 2 The material may include an inorganic insulating material such as an organic insulating material or an inorganic insulating material.

[0092] In some embodiments, the spacer 119 includes a material that is the same as or substantially the same as that of the pixel defining film 118. In this case, the pixel defining film 118 and the spacer 119 may be formed together in a mask process using a half-tone mask, etc. In some examples, the spacer 119 and the pixel defining film 118 may include different materials, respectively.

[0093] The emission layer 212b may be disposed in the opening of the pixel defining film 118. The emission layer 212b may include a high-molecular or low-molecular organic material that emits light having a specific color.

[0094] The functional layer 212f may include a first functional layer 212a and a second functional layer 212c. The first functional layer 212a may be disposed between the first electrode 211 and the emission layer 212b, and the second functional layer 212c may be disposed between the emission layer 212b and the second electrode 213. However, at least one of the first functional layer 212a and the second functional layer 212c may be omitted. Hereinafter, the case where the first functional layer 212a and the second functional layer 212c are arranged separately is mainly described in detail.

[0095] The first functional layer 212a may include a hole transport layer (HTL) or a hole injection layer (HIL). The second functional layer 212c may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The first functional layer 212a and / or the second functional layer 212c may include a common layer formed to substantially cover the substrate 100, such as a second electrode 213 to be described below.

[0096] The second electrode 213 may be disposed on the functional layer 212f. The second electrode 213 may include a conductive material having a small work function. For example, the second electrode 213 may include a (semi) transparent layer, the (semi) transparent layer including Au, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca or an alloy thereof. In some examples, the second electrode 213 may also include a conductive material including ITO, IZO, ZnO or In on the (semi) transparent layer including the aforementioned materials. 2 O 3 Etc. layers.

[0097] In some embodiments, the capping layer 215 is disposed on the second electrode 213. The capping layer 215 may include an inorganic material (eg, LiF) and / or an organic material.

[0098] The encapsulation layer 300 may be disposed on the organic light emitting diode OLED. The encapsulation layer 300 may cover the organic light emitting diode OLED. The encapsulation layer 300 may be disposed on the second electrode 213 and / or the cover layer 215. In some embodiments, the encapsulation layer 300 includes at least one inorganic film layer and at least one organic film layer. Figure 4 It is shown that the encapsulation layer 300 includes a first inorganic film layer 310 , an organic film layer 320 , and a second inorganic film layer 330 which are sequentially stacked.

[0099] The first inorganic film layer 310 and the second inorganic film layer 330 may include at least one inorganic material selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The first inorganic film layer 310 and the second inorganic film layer 330 may include a single layer or multiple layers containing the aforementioned materials. The organic film layer 320 may include a polymer-based material. The polymer-based material may include an acrylic resin, an epoxy resin, a polyimide, and / or polyethylene, etc. In some embodiments, the organic film layer 320 includes acrylate, etc.

[0100] The input sensing layer 40 may be disposed on the encapsulation layer 300. The input sensing layer 40 may include a first touch insulating layer 410, a second touch insulating layer 420, a first conductive layer 430, a third touch insulating layer 440, a second conductive layer 450, and a planarization layer 460.

[0101] In some embodiments, the first touch insulating layer 410 is disposed on the second inorganic film layer 330, and the second touch insulating layer 420 is disposed on the first touch insulating layer 410. In some embodiments, the first touch insulating layer 410 and the second touch insulating layer 420 may each include an inorganic insulating layer and / or an organic insulating layer. For example, the first touch insulating layer 410 and the second touch insulating layer 420 may include an inorganic insulating layer such as silicon oxide, silicon nitride, or silicon oxynitride.

[0102] In some embodiments, at least one of the first touch insulating layer 410 and the second touch insulating layer 420 is omitted. For example, the first touch insulating layer 410 may be omitted. In this case, the second touch insulating layer 420 may be disposed above the second inorganic film layer 330, and the first conductive layer 430 may be disposed on the second touch insulating layer 420.

[0103] The first conductive layer 430 may be disposed on the second touch insulating layer 420, and the third touch insulating layer 440 may be disposed on the first conductive layer 430. In some embodiments, the third touch insulating layer 440 includes an inorganic insulating material and / or an organic insulating material. For example, the third touch insulating layer 440 may include an inorganic insulating material (such as silicon oxide, silicon nitride, and / or silicon oxynitride, etc.).

[0104] The second conductive layer 450 may be disposed on the third touch insulating layer 440. The touch electrode TE of the input sensing layer 40 may be provided as a structure in which the first conductive layer 430 and the second conductive layer 450 are in contact with each other. In some examples, the touch electrode TE may be formed in any one of the first conductive layer 430 and the second conductive layer 450, and may include a metal wire provided in the corresponding conductive layer. The first conductive layer 430 and the second conductive layer 450 may include at least one of aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), and indium tin oxide (ITO), and may each include a single layer or multiple layers including the foregoing materials. For example, the first conductive layer 430 and the second conductive layer 450 may each have a three-layer structure including a titanium layer, an aluminum layer, and a titanium layer.

[0105] In some embodiments, the planarization layer 460 covers the second conductive layer 450. The planarization layer 460 may include an organic insulating material.

[0106] Figure 5 is a top plan view schematically showing a sub-pixel circuit unit PCs provided in the display device 1 according to some embodiments of the present disclosure.

[0107] Reference Figure 5 , the display device 1 may include a plurality of sub-pixel circuit units PCs. The plurality of sub-pixel circuit units PCs are shown as a first sub-pixel circuit unit PCs1 and a second sub-pixel circuit unit PCs2. The first sub-pixel circuit unit PCs1 may include a 1-1 sub-pixel circuit PC1-1, a 1-2 sub-pixel circuit PC1-2, and a 1-3 sub-pixel circuit PC1-3. The second sub-pixel circuit unit PCs2 may include a 2-1 sub-pixel circuit PC2-1, a 2-2 sub-pixel circuit PC2-2, and a 2-3 sub-pixel circuit PC2-3. In addition, the display device 1 may include a Figure 3 Various wirings of the sub-pixel circuit PC, such as a scan line SL, a plurality of data lines DL, a branch line BL, an initialization voltage line INL, a driving voltage line VDL and a compensation line IL.

[0108] The first scan line SL1 and the second scan line SL2 may extend in a first direction (e.g., an x ​​direction or a -x direction). The plurality of data lines DL may extend in a second direction (e.g., a y direction or a -y direction) intersecting the first direction (e.g., the x direction or the -x direction). The driving voltage line VDL and the initialization voltage line INL may extend in a second direction (e.g., the y direction or the -y direction). The first branch line BL1 connected from the first scan line SL1 may extend in a second direction (e.g., the y direction or the -y direction), and the first compensation line IL1 connected from the first branch line BL1 may extend in a first direction (e.g., the x direction or the -x direction). The second branch line BL2 connected from the second scan line SL2 may extend in a second direction (e.g., the y direction or the -y direction), and the second compensation line IL2 connected from the second branch line BL2 may extend in a first direction (e.g., the x direction or the -x direction).

[0109] In some embodiments, the scan line SL includes a first scan line SL1 and a second scan line SL2. The first scan line SL1 and the second scan line SL2 may extend in a first direction (e.g., an x ​​direction or a -x direction). For example, the first scan line SL1 may extend from one side of the first sub-pixel circuit unit PCs1 in the first direction. The second scan line SL2 may extend from the other side of the first sub-pixel circuit unit PCs1 in the first direction (e.g., an x ​​direction or a -x direction). The first scan line SL1 and the second scan line SL2 may be arranged separately from each other in a second direction (e.g., a y direction or a -y direction), and the first sub-pixel circuit unit PCs1 is located between the first scan line SL1 and the second scan line SL2. The first scan line SL1 may be configured to provide a scan signal to the 1-1 sub-pixel circuit PC1-1, the 1-2 sub-pixel circuit PC1-2, and the 1-3 sub-pixel circuit PC1-3 of the first sub-pixel circuit unit PCs1. For example, the first scan line SL1 can be electrically connected to the first branch line BL1 extending from the first scan line SL1 in the second direction and provide a scan signal to the 1-1 sub-pixel circuit PC1-1, the 1-2 sub-pixel circuit PC1-2 and the 1-3 sub-pixel circuit PC1-3 of the first sub-pixel circuit unit PCs1.

[0110] In some embodiments, the first scan line SL1 extends from one side of the second sub-pixel circuit unit PCs2 in a first direction (e.g., the x direction or the -x direction). The second scan line SL2 may extend from the other side of the second sub-pixel circuit unit PCs2 in the first direction. The first scan line SL1 and the second scan line SL2 may be arranged separately from each other in a second direction (e.g., the y direction or the -y direction), and the second sub-pixel circuit unit PCs2 is located between the first scan line SL1 and the second scan line SL2. The second scan line SL2 may be configured to provide a scan signal to the 2-1 sub-pixel circuit PC2-1, the 2-2 sub-pixel circuit PC2-2, and the 2-3 sub-pixel circuit PC2-3 of the second sub-pixel circuit unit PCs2. For example, the second scan line SL2 may be electrically connected to the second branch line BL2 extending from the second scan line SL2 in the second direction, and provide a scan signal to the 2-1 sub-pixel circuit PC2-1, the 2-2 sub-pixel circuit PC2-2, and the 2-3 sub-pixel circuit PC2-3 of the second sub-pixel circuit unit PCs2.

[0111] The 1-1 sub-pixel circuit PC1-1, the 1-2 sub-pixel circuit PC1-2, and the 1-3 sub-pixel circuit PC1-3 may be arranged in series in the second direction (e.g., the y direction or the -y direction). For example, the 1-1 sub-pixel circuit PC1-1 may be arranged adjacent to the second scan line SL2, and the 1-3 sub-pixel circuit PC1-3 may be arranged adjacent to the first scan line SL1. The 1-2 sub-pixel circuit PC1-2 may be arranged between the 1-1 sub-pixel circuit PC1-1 and the 1-3 sub-pixel circuit PC1-3. In addition, the 2-1 sub-pixel circuit PC2-1, the 2-2 sub-pixel circuit PC2-2, and the 2-3 sub-pixel circuit PC2-3 may be arranged in series in the second direction. For example, the 2-1 sub-pixel circuit PC2-1 may be arranged adjacent to the second scan line SL2, and the 2-3 sub-pixel circuit PC2-3 may be arranged adjacent to the first scan line SL1. The 2-2 sub-pixel circuit PC2 - 2 may be disposed between the 2-1 sub-pixel circuit PC2 - 1 and the 2-3 sub-pixel circuit PC2 - 3 .

[0112] A plurality of data lines DL may be arranged to extend at one side of the first sub-pixel circuit unit PCs1 in the second direction. A plurality of data lines DL may be arranged to extend at one side of the second sub-pixel circuit unit PCs2 in the second direction. A plurality of data lines DL may include, for example, a first data line DL1, a second data line DL2, and a third data line DL3, and the first data line DL1, the second data line DL2, and the third data line DL3 may be arranged adjacent to the initialization voltage line INL in a state adjacent to each other. The first data line DL1, the second data line DL2, and the third data line DL3 may be configured to apply a separate data signal to the 1-1 sub-pixel circuit PC1-1, the 1-2 sub-pixel circuit PC1-2, and the 1-3 sub-pixel circuit PC1-3, respectively. In addition, the first data line DL1, the second data line DL2, and the third data line DL3 may be configured to apply a separate data signal to the 2-1 sub-pixel circuit PC2-1, the 2-2 sub-pixel circuit PC2-2, and the 2-3 sub-pixel circuit PC2-3, respectively.

[0113] The initialization voltage line INL may be disposed between the first branch line BL1 and the data line DL. In some examples, the initialization voltage line INL may be disposed between the second branch line BL2 and the data line DL. The branch line BL may be disposed opposite to the data line DL with respect to the initialization voltage line INL.

[0114] Figure 5 The arrangement of the first data line DL1, the second data line DL2 and the third data line DL3, the initialization voltage line INL, and the branch line BL shown in FIG. 1 is only an example, and the embodiments of the present disclosure are not limited thereto, and the arrangement may be appropriately modified and corrected according to the design of the sub-pixel circuit PC.

[0115] The display device 1 may include Figure 5 The structure shown in FIG. 1 is a structure repeated in the x direction and the y direction. Accordingly, the plurality of scan lines SL and the plurality of drive voltage lines VDL provided in the display device 1 may form a grid structure on a plane. Here, the term “on a plane” may mean “on a plane that is parallel to the substrate 100 (see, for example, FIG. 1 ) of the display device 1. Figure 4 )’.

[0116] On a plane, a plurality of thin film transistors (e.g., a first thin film transistor T1, a second thin film transistor T2, and a third thin film transistor T3) and a storage capacitor Cst may be arranged in a space surrounded by a scan line SL, a drive voltage line VDL, and an initialization voltage line INL adjacent to each other. A plurality of thin film transistors (i.e., a first thin film transistor T1, a second thin film transistor T2, and a third thin film transistor T3) and a storage capacitor Cst may form a sub-pixel circuit PC. For example, Figure 5The 1-1 sub-pixel circuit PC1-1, 1-2 sub-pixel circuit PC1-2, 1-3 sub-pixel circuit PC1-3, 2-1 sub-pixel circuit PC2-1, 2-2 sub-pixel circuit PC2-2 and 2-3 sub-pixel circuit PC2-3 shown in the figure may each include a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3 and a storage capacitor Cst. In the following, for the convenience of explanation, the structure and arrangement of the plurality of thin film transistors (i.e., the first thin film transistor T1, the second thin film transistor T2 and the third thin film transistor T3) and the storage capacitor Cst provided in the 1-1 sub-pixel circuit PC1-1 will be mainly described. Except that the 1-2 sub-pixel circuit PC1-2 and the 1-3 sub-pixel circuit PC1-3 are respectively connected to the second data line DL2 and the third data line DL3, the 1-2 sub-pixel circuit PC1-2 and the 1-3 sub-pixel circuit PC1-3 have the same or substantially the same structure and arrangement as the above-mentioned 1-1 sub-pixel circuit PC1-1. Accordingly, the same description of the 1-2 sub-pixel circuit PC1-2 and the 1-3 sub-pixel circuit PC1-3 will not be repeated. Likewise, except for the difference in the scan line SL connected to the second sub-pixel circuit unit PCs2, the second sub-pixel circuit unit PCs2 has the same or substantially the same structure and arrangement as the first sub-pixel circuit unit PCs1, and the description of the second sub-pixel circuit unit PCs2 will not be provided.

[0117] Each of the first thin film transistor T1, the second thin film transistor T2 and the third thin film transistor T3 of the 1-1 sub-pixel circuit PC1-1 may include a semiconductor layer (e.g., a first semiconductor layer A1, a second semiconductor layer A2, a third semiconductor layer A3) and a gate electrode (e.g., a first gate electrode G1, a second gate electrode G2 and a third gate electrode G3) overlapping with at least a portion of the semiconductor layer (e.g., the first semiconductor layer A1, the second semiconductor layer A2 and the third semiconductor layer A3).

[0118] The first thin film transistor T1 may include a first semiconductor layer A1 and a first gate electrode G1 overlapping at least a portion of the first thin film transistor T1. The first semiconductor layer A1 may include an oxide semiconductor or a silicon-based semiconductor. The first semiconductor layer A1 may include a channel region, and may also include a source region and a drain region arranged at both sides of the channel region. The source region and the drain region having a resistance smaller than that of the channel region may be formed by a process of doping impurities or a conductive process. The source region and the drain region may correspond to the source electrode and the drain electrode of the thin film transistor, respectively. Hereinafter, for convenience, the terms "source region" and "drain region" will be used instead of "source electrode" and "drain electrode". The first gate electrode G1 may overlap with the channel region of the first semiconductor layer A1.

[0119] Any one of the source region and the drain region of the first semiconductor layer A1 may be electrically connected to the driving voltage line VDL, and the other may be electrically connected to the storage capacitor Cst. For example, the first semiconductor layer A1 may be connected to the fourth connection line CL4 through the first contact hole CNT1, and the fourth connection line CL4 may be electrically connected to the driving voltage line VDL through the tenth contact hole CNT10. In addition, the first semiconductor layer A1 may be electrically connected to the storage capacitor Cst through the second contact hole CNT2. For example, the first semiconductor layer A1 may be connected to the second capacitor plate CE2 of the storage capacitor Cst through the second contact hole CNT2.

[0120] The second thin film transistor T2 may include a second semiconductor layer A2 and a second gate electrode G2 overlapping at least a portion of the second semiconductor layer A2. The second semiconductor layer A2 may include an oxide semiconductor or a silicon-based semiconductor. The second semiconductor layer A2 may include a channel region, and may also include a source region and a drain region arranged at both sides (e.g., opposite sides) of the channel region. The second gate electrode G2 may overlap the channel region of the second semiconductor layer A2. The second gate electrode G2 may correspond to a portion of the first branch line BL1. In other words, the second gate electrode G2 and at least a portion of the first branch line BL1 may be formed integrally (e.g., as a single body).

[0121] Any one of the source region and the drain region of the second semiconductor layer A2 may be electrically connected to the storage capacitor Cst, and the other may be electrically connected to the data line DL. For example, the second semiconductor layer A2 may be connected to the first connection line CL1 through the fourth contact hole CNT4, and the first connection line CL1 may be connected to the first capacitor plate CE1 of the storage capacitor Cst through the third contact hole CNT3. In addition, the second semiconductor layer A2 may be connected to the second connection line CL2 through the fifth contact hole CNT5, and the second connection line CL2 may be connected to the first data line DL1 through the sixth contact hole CNT6.

[0122] The third thin film transistor T3 may include a third semiconductor layer A3 and a third gate electrode G3 overlapping at least a portion of the third semiconductor layer A3. The third semiconductor layer A3 may include an oxide semiconductor or a silicon-based semiconductor. The third semiconductor layer A3 may include a channel region, and may also include a source region and a drain region respectively arranged at both sides (e.g., opposite sides) of the channel region. The third gate electrode G3 may overlap the channel region of the third semiconductor layer A3. The third gate electrode G3 may correspond to a portion of the first branch line BL1. In other words, the third gate electrode G3 and at least a portion of the first branch line BL1 may be formed integrally (e.g., as a whole).

[0123] Any one of the source region and the drain region of the third semiconductor layer A3 may be electrically connected to the initialization voltage line INL, and the other may be electrically connected to the storage capacitor Cst. For example, the third semiconductor layer A3 may be connected to the third connection line CL3 through the eighth contact hole CNT8, and the third connection line CL3 may be connected to the initialization voltage line INL through the seventh contact hole CNT7. In addition, the third semiconductor layer A3 may be connected to the second capacitor plate CE2 of the storage capacitor Cst through the ninth contact hole CNT9.

[0124] The storage capacitor Cst may include at least two capacitor plates (e.g., electrodes) overlapping each other. For example, the storage capacitor Cst may include a first capacitor plate (e.g., a first capacitor electrode) CE1 and a second capacitor plate (e.g., a second capacitor electrode) CE2 overlapping each other. In some embodiments, the storage capacitor Cst also includes a third capacitor plate CE3 overlapping the first capacitor plate CE1 and the second capacitor plate CE2.

[0125] The first capacitor plate CE1 may be formed integrally with the first gate electrode G1. In other words, a portion of the first capacitor plate CE1 may correspond to the first gate electrode G1. In a cross-sectional view, the second capacitor plate CE2 may be disposed on the first capacitor plate CE1 and may correspond to a portion of the node connection line NCL. In other words, the node connection line NCL may include the second capacitor plate CE2. In a cross-sectional view, the third capacitor plate CE3 may be disposed below the first capacitor plate CE1 and may correspond to a portion of the bottom metal layer BML. In other words, the bottom metal layer BML may include the third capacitor plate CE3. The second capacitor plate CE2 may be electrically connected to the third capacitor plate CE3 through the eleventh contact hole CNT11. Here, the term "in a cross-sectional view" may mean "in a cross-sectional view in contact with the substrate 100 (see, e.g., Figure 4 ) on a virtual side view orthogonal to the original image.

[0126] The node connection line NCL can connect the first thin film transistor T1 to the organic light emitting diode OLED (see for example Figure 4 ) is electrically connected to the pixel electrode of the organic light emitting diode OLED. For example, the node connection line NCL may contact the first thin film transistor T1 through the second contact hole CNT2, and the first electrode 211 (see, for example, Figure 4 ) may contact the node connection line NCL through the contact hole and / or the connection electrode. In addition, the node connection line NCL may also be electrically connected to the third thin film transistor T3. For example, the node connection line NCL may contact the third thin film transistor T3 through the ninth contact hole CNT9. The node connection line NCL may correspond to the above Figure 3 The second node N2 is shown in FIG.

[0127] In some embodiments, the first compensation line IL1 extends from the first branch line BL1 toward the 1-1 sub-pixel circuit PC1-1 adjacent to the second scan line SL2 in a first direction (e.g., the x direction or the -x direction). The first compensation line IL1 may extend from the first branch line BL1 and may be formed integrally with the first branch line BL1 (e.g., as a whole). In other words, the first compensation line IL1 may be arranged at the same layer as the first branch line BL1 and may include the same material as the first branch line BL1. The minimum distance between the second thin film transistor T2 of the 1-1 sub-pixel circuit PC1-1 and the second scan line SL2 in the second direction (e.g., the y direction or the -y direction) may be less than the minimum distance between the third thin film transistor T3 of the 1-1 sub-pixel circuit PC1-1 and the second thin film transistor T2 in the second direction. In other words, the second thin film transistor T2 of the 1-1 sub-pixel circuit PC1-1 may be arranged more adjacent to the second scan line SL2 than the third thin film transistor T3 (e.g., the second thin film transistor T2 may be positioned closer to the second scan line SL2 than the third thin film transistor T3). For example, the first compensation line IL1 may be disposed between the second scan line SL2 and the second thin film transistor T2 to extend from the first branch line BL1 in the first direction.

[0128] The first scan line SL1 extending from one side of the first sub-pixel circuit unit PCs1 in the first direction may be configured to provide a scan signal to the first sub-pixel circuit PC1-1, the second sub-pixel circuit PC1-2, and the third sub-pixel circuit PC1-3 of the first sub-pixel circuit unit PCs1. The first branch line BL1 and the first scan line SL1 may be electrically connected to each other through the twelfth contact hole CNT12. For example, the first scan line SL1 may provide a scan signal to the first sub-pixel circuit unit PCs1 through the first branch line BL1 extending in the second direction (e.g., the y direction or the -y direction).

[0129] In addition, the second scan line SL2 extending from the other side of the first sub-pixel circuit unit PCs1 in the first direction (e.g., the x direction or the -x direction) can be configured to provide a scan signal to the 2-1 sub-pixel circuit PC2-1, the 2-2 sub-pixel circuit PC2-2, and the 2-3 sub-pixel circuit PC2-3 of the second sub-pixel circuit unit PCs2. The second branch line BL2 and the second scan line SL2 can be electrically connected to each other through the thirteenth contact hole CNT13. For example, the second scan line SL2 can provide a scan signal to the second sub-pixel circuit unit PCs2 through the second branch line BL2 extending from the second scan line SL2 in the second direction (e.g., the y direction or the -y direction).

[0130] When a scan signal is provided to the second sub-pixel circuit unit PCs2 through the second scan line SL2 and the second branch line BL2, a kickback voltage may be generated at the first gate electrode G1 of the first electrode of the first thin film transistor T1 of the 2-1 sub-pixel circuit PC2-1. For example, a kickback voltage may be generated between the first gate electrode G1 of the first electrode of the first thin film transistor T1 of the 2-1 sub-pixel circuit PC2-1 and the second scan line SL2 extending in the first direction and adjacent to the first gate electrode G1. In addition, a kickback voltage may be generated between the first gate electrode G1 of the first thin film transistor T1 of the 2-1 sub-pixel circuit PC2-1 and the second branch line BL2 extending in the second direction and adjacent to the first gate electrode G1.

[0131] When a scan signal is provided to the first sub-pixel circuit unit PCs1 through the first scan line SL1 and the first branch line BL1, a kickback voltage may also be generated at the first gate electrode G1 of the first thin film transistor T1 of the 1-1 sub-pixel circuit PC1-1. For example, a kickback voltage may be generated between the first gate electrode G1 of the first thin film transistor T1 of the 1-1 sub-pixel circuit PC1-1 and the first branch line BL1 extending in the second direction (e.g., the y direction or the -y direction) and adjacent to the first gate electrode G1. In addition, a kickback voltage may be generated between the first gate electrode G1 of the first thin film transistor T1 of the 1-1 sub-pixel circuit PC1-1 and the first compensation line IL1 extending in the first direction (e.g., the x direction) and adjacent to the first gate electrode G1.

[0132] Since the first compensation line IL1 is arranged to extend from the first branch line BL1 in the first direction, the kickback voltage generated at the first gate electrode G1 of the first thin film transistor T1 of the 1-1 sub-pixel circuit PC1-1 and the kickback voltage generated at the first gate electrode G1 of the first thin film transistor T1 of the 2-1 sub-pixel circuit PC2-1 may be similar to each other. Figure 4 ) and the light emitted from the organic light emitting diode OLED electrically connected to the 2-1 sub-pixel circuit PC2-1 may have the same color. Since the kickback voltage generated at the first gate electrode G1 of the first thin film transistor T1 of the 1-1 sub-pixel circuit PC1-1 and the kickback voltage generated at the first gate electrode G1 of the first thin film transistor T1 of the 2-1 sub-pixel circuit PC2-1 are similar to each other, it is possible to prevent or substantially reduce the occurrence of spots due to the difference between the kickback voltages of pixels that are electrically connected to each other and emit light having the same or substantially the same color.

[0133] In some embodiments, the second compensation line IL2 extends from the second branch line BL2 toward the 2-3 sub-pixel circuit PC2-3 adjacent to the first scan line SL1 in the first direction. The second compensation line IL2 may extend from the second branch line BL2 and may be formed integrally with the second branch line BL2 (e.g., as a whole). In other words, the second compensation line IL2 may be arranged at the same layer as the second branch line BL2 and may include the same material as the material of the second branch line BL2. The minimum distance between the second thin film transistor T2 of the 2-3 sub-pixel circuit PC2-3 and the first scan line SL1 in the second direction (e.g., the y direction or the -y direction) may be less than the minimum distance between the third thin film transistor T3 and the first scan line SL1 in the second direction. In other words, the second thin film transistor T2 of the 2-3 sub-pixel circuit PC2-3 may be arranged more adjacent to the first scan line SL1 than the third thin film transistor T3. For example, the second compensation line IL2 may be arranged between the first scan line SL1 and the second thin film transistor T2 to extend from the second branch line BL2 in the first direction (e.g., the x direction or the -x direction).

[0134] As described above, the first scan line SL1 and the first branch line BL1 extending from the first scan line SL1 in the second direction may be configured to provide a scan signal to the first sub-pixel circuit unit PCs1. When the scan signal is provided to the first sub-pixel circuit unit PCs1 through the first scan line SL1 and the first branch line BL1, a kickback voltage may be generated at the first gate electrode G1 of the first thin film transistor T1 of the 1-3 sub-pixel circuit PC1-3. For example, a kickback voltage may be generated between the first gate electrode G1 of the first thin film transistor T1 of the 1-3 sub-pixel circuit PC1-3 and the first scan line SL1 adjacent to the first gate electrode G1 and extending in the first direction. In addition, a kickback voltage may be generated between the first gate electrode G1 of the first thin film transistor T1 of the 1-3 sub-pixel circuit PC1-3 and the first branch line BL1 adjacent to the first gate electrode G1 and extending in the second direction (e.g., the y direction or the -y direction).

[0135] When a scan signal is provided to the second sub-pixel circuit unit PCs2 through the second scan line SL2 and the second branch line BL2, a kickback voltage may also be generated at the first gate electrode G1 of the first thin film transistor T1 of the 2-3 sub-pixel circuit PC2-3. For example, a kickback voltage may be generated between the first gate electrode G1 of the first thin film transistor T1 of the 2-3 sub-pixel circuit PC2-3 and the second branch line BL2 adjacent to the first gate electrode G1 and extending in the second direction. In addition, a kickback voltage may be generated between the first gate electrode G1 of the first thin film transistor T1 of the 2-3 sub-pixel circuit PC2-3 and the second compensation line IL2 adjacent to the first gate electrode G1 and extending in the first direction (e.g., the x direction or the -x direction).

[0136] Since the second compensation line IL2 is arranged to extend from the second branch line BL2 in the first direction, the kickback voltage generated at the first gate electrode G1 of the first thin film transistor T1 of the 1-3 sub-pixel circuit PC1-3 and the kickback voltage generated at the first gate electrode G1 of the first thin film transistor T1 of the 2-3 sub-pixel circuit PC2-3 may be similar to each other. Light emitted from the organic light emitting diode OLED electrically connected to the 1-3 sub-pixel circuit PC1-3 and light emitted from the organic light emitting diode OLED electrically connected to the 2-3 sub-pixel circuit PC2-3 may have the same or substantially the same color. Since the kickback voltage generated at the first gate electrode G1 of the first thin film transistor T1 of the 1-3 sub-pixel circuit PC1-3 and the kickback voltage generated at the first gate electrode G1 of the first thin film transistor T1 of the 2-3 sub-pixel circuit PC2-3 are similar to each other, it is possible to prevent or substantially reduce the occurrence of spots due to the difference between the kickback voltages between pixels electrically connected to each other and configured to emit light having the same or substantially the same color.

[0137] Figure 6 and Figure 7 are top plan views each schematically illustrating a sub-pixel circuit unit provided in the display device 1 according to some embodiments of the present disclosure. More specifically, Figure 6 is a top plan view schematically illustrating a first sub-pixel circuit unit PCs1 according to some embodiments, and Figure 7 is a top plan view schematically illustrating a second sub-pixel circuit unit PCs2 according to some embodiments.

[0138] Reference Figure 6 , as referenced above Figure 5As described, the first sub-pixel circuit unit PCs1 may include a 1-1 sub-pixel circuit PC1-1, a 1-2 sub-pixel circuit PC1-2, and a 1-3 sub-pixel circuit PC1-3. The 1-1 sub-pixel circuit PC1-1 may be arranged adjacent to the second scan line SL2, and the 1-3 sub-pixel circuit PC1-3 may be arranged adjacent to the first scan line SL1. The 1-2 sub-pixel circuit PC1-2 may be arranged between the 1-1 sub-pixel circuit PC1-1 and the 1-3 sub-pixel circuit PC1-3.

[0139] The minimum distance between the second thin film transistor T2 of the 1-1 sub-pixel circuit PC1-1 and the second scan line SL2 in the second direction (e.g., the y direction or the -y direction) may be smaller than the minimum distance between the third thin film transistor T3 and the second scan line SL2 in the second direction. In other words, the second thin film transistor T2 of the 1-1 sub-pixel circuit PC1-1 may be arranged more adjacent to the second scan line SL2 than the third thin film transistor T3 (e.g., the second thin film transistor T2 may be positioned closer to the second scan line SL2 than the third thin film transistor T3).

[0140] In some embodiments, the third compensation line IL3 extends from the first branch line BL1 toward the 1-1 sub-pixel circuit PC1-1 in a first direction (e.g., the x direction or the -x direction). In other words, the third compensation line IL3 may be arranged to extend between the second thin film transistor T2 and the third thin film transistor T3 of the 1-1 sub-pixel circuit PC1-1 in the first direction. The third compensation line IL3 may be arranged at the same layer as the first branch line BL1, and may include the same material as that of the first branch line BL1.

[0141] When the third compensation line IL3 is arranged between the second thin film transistor T2 and the third thin film transistor T3 of the 1-1 sub-pixel circuit PC1-1, a kickback voltage may be generated at the first gate electrode G1 of the first thin film transistor T1 of the 1-1 sub-pixel circuit PC1-1 and the first branch line BL1 adjacent to the first gate electrode G1 and extending in the second direction (e.g., the y direction or the -y direction). In addition, a kickback voltage may be generated between the first gate electrode G1 of the first thin film transistor T1 of the 1-1 sub-pixel circuit PC1-1 and the third compensation line IL3 adjacent to the first gate electrode G1 and extending in the first direction (e.g., the x direction or the -x direction). Accordingly, the kickback voltage generated at the first gate electrode G1 of the first thin film transistor T1 of the 1-1 sub-pixel circuit PC1-1 and the kickback voltage generated at the first gate electrode G1 of the first thin film transistor T1 of the 2-1 sub-pixel circuit PC2-1 may be similar to each other, and the 1-1 sub-pixel circuit PC1-1 and the 2-1 sub-pixel circuit PC2-1 may be electrically connected to pixels configured to emit light having the same or substantially the same color. Therefore, it is possible to prevent or substantially reduce the occurrence of spots due to differences between kickback voltages of pixels configured to emit light having the same or substantially the same color.

[0142] Reference Figure 7 Combined with Figure 6 , as referenced above Figure 5 As described, the second sub-pixel circuit unit PCs2 may include a 2-1 sub-pixel circuit PC2-1, a 2-2 sub-pixel circuit PC2-2, and a 2-3 sub-pixel circuit PC2-3. The 2-1 sub-pixel circuit PC2-1 may be arranged adjacent to the second scan line SL2, and the 2-3 sub-pixel circuit PC2-3 may be arranged adjacent to the first scan line SL1. The 2-2 sub-pixel circuit PC2-2 may be arranged between the 2-1 sub-pixel circuit PC2-1 and the 2-3 sub-pixel circuit PC2-3.

[0143] The minimum distance between the second thin film transistor T2 of the 2-3 sub-pixel circuit PC2-3 and the first scan line SL1 in the second direction (e.g., the y direction or the -y direction) may be smaller than the minimum distance between the third thin film transistor T3 and the first scan line SL1 in the second direction. In other words, the second thin film transistor T2 of the 2-3 sub-pixel circuit PC2-3 may be arranged closer to the first scan line SL1 than the third thin film transistor T3.

[0144] In some embodiments, the fourth compensation line IL4 extends from the second branch line BL2 toward the 2-3 sub-pixel circuit PC2-3 in the first direction (e.g., the x direction or the -x direction). In other words, the fourth compensation line IL4 may be arranged to extend between the second thin film transistor T2 and the third thin film transistor T3 of the 2-3 sub-pixel circuit PC2-3 in the first direction. The fourth compensation line IL4 may be arranged at the same layer as the second branch line BL2, and may include the same material as that of the second branch line BL2.

[0145] When the fourth compensation line IL4 is arranged between the second thin film transistor T2 and the third thin film transistor T3 of the 2-3 sub-pixel circuit PC2-3, a kickback voltage may be generated between the first gate electrode G1 of the first thin film transistor T1 of the 2-3 sub-pixel circuit PC2-3 and the second branch line BL2 adjacent to the first gate electrode G1 and extending in the second direction. In addition, a kickback voltage may be generated between the first gate electrode G1 of the first thin film transistor T1 of the 2-3 sub-pixel circuit PC2-3 and the fourth compensation line IL4 adjacent to the first gate electrode G1. Accordingly, the kickback voltage generated at the first gate electrode G1 of the first thin film transistor T1 of the 2-3 sub-pixel circuit PC2-3 and the kickback voltage generated at the first gate electrode G1 of the first thin film transistor T1 of the 1-3 sub-pixel circuit PC1-3 may be similar to each other, and the 2-3 sub-pixel circuit PC2-3 and the 1-3 sub-pixel circuit PC1-3 may be electrically connected to pixels configured to emit light having the same or substantially the same color. Therefore, it is possible to prevent or substantially reduce the occurrence of spots caused by the difference between kickback voltages of pixels configured to emit light having the same or substantially the same color.

[0146] Figure 8 and Fig. 9 are top plan views each schematically illustrating a sub-pixel circuit unit provided in the display device 1 according to some embodiments of the present disclosure. More specifically, Figure 8 is a top plan view schematically illustrating a first sub-pixel circuit unit PCs1 according to some embodiments, and Fig. 9 is a top plan view schematically illustrating a second sub-pixel circuit unit PCs2 according to some embodiments.

[0147] Reference Figure 8 , the fifth compensation line IL5 may be arranged to extend from the first branch line BL1 toward the 1-2 sub-pixel circuit PC1-2 in a first direction (e.g., the x direction or the -x direction). The fifth compensation line IL5 may be arranged at the same layer as the first branch line BL1, and may include the same material as that of the first branch line BL1. The fifth compensation line IL5 and the first branch line BL1 may be integrally formed (e.g., as a whole).

[0148] When a scan signal is provided from the first scan line SL1 to the first sub-pixel circuit unit PCs1, a kickback voltage may also be generated at the first gate electrode G1 of the first thin film transistor T1 of the 1-2 sub-pixel circuit PC1-2. For example, a kickback voltage may be generated between the first gate electrode G1 of the first thin film transistor T1 of the 1-2 sub-pixel circuit PC1-2 and the first branch line BL1 adjacent to the first gate electrode G1 and extending in the second direction (e.g., the y direction or the -y direction). In addition, a kickback voltage may be generated between the first gate electrode G1 of the first thin film transistor T1 of the 1-2 sub-pixel circuit PC1-2 and the fourth compensation line IL4 adjacent to the first gate electrode G1 and extending in the first direction (e.g., the x direction or the -x direction). Due to the fourth compensation line IL4 and the first compensation line IL1, the kickback voltage generated at the first gate electrode G1 of the first thin film transistor T1 of the 1-1 sub-pixel circuit PC1-1, the 1-2 sub-pixel circuit PC1-2, and the 1-3 sub-pixel circuit PC1-3 may have a similar magnitude.

[0149] Reference Fig. 9 Combined with Figure 8 , the sixth compensation line IL6 may be arranged to extend from the second branch line BL2 toward the 2-2 sub-pixel circuit PC2-2 in the first direction. The sixth compensation line IL6 may be arranged at the same layer as the second branch line BL2, and may include the same material as the second branch line BL2. The sixth compensation line IL6 and the second branch line BL2 may be formed integrally (e.g., as a whole).

[0150] When a scan signal is provided from the second scan line SL2 to the second sub-pixel circuit unit PCs2, a kickback voltage may also be generated at the first gate electrode G1 of the first thin film transistor T1 of the 2-2 sub-pixel circuit PC2-2. For example, a kickback voltage may be generated between the first gate electrode G1 of the first thin film transistor T1 of the 2-2 sub-pixel circuit PC2-2 and the second branch line BL2 adjacent to the first gate electrode G1 and extending in the second direction (e.g., the y direction or the -y direction). In addition, a kickback voltage may be generated between the first gate electrode G1 of the first thin film transistor T1 of the 2-2 sub-pixel circuit PC2-2 and the sixth compensation line IL6 adjacent to the first gate electrode G1 and extending in the first direction (e.g., the x direction or the -x direction). Due to the sixth compensation line IL6 and the second compensation line IL2, the kickback voltage generated at the first gate electrode G1 of the first thin film transistor T1 of the 2-1 sub-pixel circuit PC2-1, the 2-2 sub-pixel circuit PC2-2, and the 2-3 sub-pixel circuit PC2-3 may have a similar magnitude.

[0151] In some embodiments, the first compensation line IL1 extends in the first direction from the first branch line BL1 toward the 1-1 sub-pixel circuit PC1-1 of the first sub-pixel circuit unit PCs1. A kickback voltage may be generated between the first gate electrode G1 of the first thin film transistor T1 of the 1-1 sub-pixel circuit PC1-1, the first branch line BL1 extending in the second direction (e.g., the y direction or the -y direction), and the first branch line BL1 extending in the first direction. In addition, a kickback voltage may also be generated between the first gate electrode G1 of the first thin film transistor T1 of the 2-1 sub-pixel circuit PC2-1, the second scan line SL2, and the second branch line BL2 of the second sub-pixel circuit unit PCs2. Since the kick-back voltage generated at the first gate electrode G1 of the first thin film transistor T1 of the 1-1 sub-pixel circuit PC1-1 and the kick-back voltage generated at the first gate electrode G1 of the first thin film transistor T1 of the 2-1 sub-pixel circuit PC2-1 have similar sizes, when the 1-1 sub-pixel circuit PC1-1 and the 2-1 sub-pixel circuit PC2-1 are electrically connected to sub-pixels configured to emit light having the same or substantially the same color, it is possible to prevent or substantially reduce the occurrence of spots due to the difference between the kick-back voltages of pixels configured to emit light having the same or substantially the same color.

[0152] In addition, the second compensation line IL2 may extend from the second branch line BL2 toward the 2-3 sub-pixel circuit PC2-3 of the second sub-pixel circuit unit PCs2 in the first direction (e.g., the x direction or the -x direction). A kickback voltage may be generated between the first gate electrode G1 of the first thin film transistor T1 of the 2-3 sub-pixel circuit PC2-3, the second branch line BL2 extending in the second direction, and the second compensation line IL2 extending in the first direction. In addition, a kickback voltage may also be generated between the first gate electrode G1 of the first thin film transistor T1 of the 1-3 sub-pixel circuit PC1-3, the first scan line SL1, and the first branch line BL1 of the first sub-pixel circuit unit PCs1. Since the kick-back voltage generated at the first gate electrode G1 of the first electrode of the first thin film transistor T1 of the 2-3 sub-pixel circuit PC2-3 and the kick-back voltage generated at the first gate electrode G1 of the first thin film transistor T1 of the 1-3 sub-pixel circuit PC1-3 have similar magnitudes, when the 2-3 sub-pixel circuit PC2-3 and the 1-3 sub-pixel circuit PC1-3 are electrically connected to sub-pixels configured to emit light having the same color, it is possible to prevent or substantially reduce the occurrence of spots due to the difference between the kick-back voltages of pixels configured to emit light having the same or substantially the same color.

[0153] According to the above-described embodiments, a display device having improved reliability and quality may be implemented. However, the scope of the embodiments is not limited thereto.

[0154] It should be understood that the embodiments described herein should be considered only as descriptive and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered as applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims and their equivalents.

Claims

1. A display device, characterized in that: The display device comprises: a substrate including a display region in which display elements are arranged; A first sub-pixel circuit unit, in the display area, and comprising a first sub-pixel circuit, a second sub-pixel circuit and a third sub-pixel circuit; A first scan line extending from one side of the first sub-pixel circuit unit in a first direction; a second scanning line extending from the other side of the first sub-pixel circuit unit in the first direction; a first branch line extending from the first scan line in a second direction intersecting the first direction; and The first compensation line extends from the first branch line toward the first sub-pixel circuit adjacent to the second scan line in the first direction.

2. The display device according to claim 1, characterized in that The first sub-pixel circuit comprises: a first thin film transistor in the display region and comprising a first semiconductor layer and a first gate electrode insulated from the first semiconductor layer; and The second thin film transistor is in the display region and includes a second semiconductor layer and a second gate electrode insulated from the second semiconductor layer.

3. The display device according to claim 2, characterized in that: A minimum distance between the first thin film transistor and the second scan line in the second direction is smaller than a minimum distance between the second thin film transistor and the second scan line in the second direction.

4. The display device according to claim 1, characterized in that The first sub-pixel circuit is adjacent to the second scanning line, The third sub-pixel circuit is adjacent to the first scan line, and Wherein, the second sub-pixel circuit is between the first sub-pixel circuit and the third sub-pixel circuit.

5. The display device according to claim 1, characterized in that The first compensation line is at the same layer as the first branch line and includes a same material as that of the first branch line.

6. The display device according to claim 2, characterized in that: The first compensation line is between the second scan line and the first thin film transistor, and extends from the first branch line in the first direction; or The first compensation line is between the first thin film transistor and the second thin film transistor, and extends from the first branch line in the first direction.

7. The display device according to claim 1, characterized in that: The display device further includes a second compensation line extending from the first branch line toward the second sub-pixel circuit in the first direction.

8. A display device, characterized in that: The display device comprises: a substrate including a display region in which display elements are arranged; A second sub-pixel circuit unit, in the display area, and comprising a first sub-pixel circuit, a second sub-pixel circuit and a third sub-pixel circuit; A first scan line extending from one side of the second sub-pixel circuit unit in a first direction; a second scanning line extending from the other side of the second sub-pixel circuit unit in the first direction; a second branch line extending from the second scan line in a second direction crossing the first direction; and The third compensation line extends from the second branch line toward the third sub-pixel circuit adjacent to the first scan line in the first direction.

9. The display device according to claim 8, characterized in that: The third sub-pixel circuit comprises: a third thin film transistor in the display region and comprising a third semiconductor layer and a third gate electrode insulated from the third semiconductor layer; and The fourth thin film transistor is in the display region and includes a fourth semiconductor layer and a fourth gate electrode insulated from the fourth semiconductor layer.

10. The display device according to claim 9, characterized in that: A minimum distance between the third thin film transistor and the first scan line in the second direction is smaller than a minimum distance between the fourth thin film transistor and the first scan line in the second direction.

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