Array substrate and display device

Abstract

The utility model discloses an array substrate and a display device. The array substrate comprises one or more grid electrode driving ICs and one or more source electrode driving ICs. The plurality of gate driving ICs are respectively and sequentially connected with gate lines of the array substrate in a staggered manner; and the plurality of source electrode driving ICs are respectively and sequentially connected with the source electrode data lines of the array substrate in a staggered manner. A gate driving IC is connected with a gate line in a staggered manner, or a source driving IC is connected with a source data line in a staggered manner, or the gate line and the source data line corresponding to the gate driving IC and the source driving IC are connected in a staggered manner, so that the RC Loading difference problem of the gate line or the source gate line is avoided; the problem of left-right screen splitting or up-down screen splitting caused by a plurality of driving ICs of the display device is solved.

Description

Technical Field

[0001] The utility model relates to the technical field of display screens, and in particular to an array substrate and a display device. Background Art

[0002] Display devices have been widely used, but the size of existing display screens is getting larger and larger. Large-size display screens may have more than one driver IC, and may use multiple gate driver ICs (G-ICs), multiple source ICs (S-ICs), or both.

[0003] like Figure 1-4 As shown in the figure, the display panel has two gate driver ICs, G1-IC and G2-IC, which are arranged vertically. G1-IC is responsible for driving the upper half of the display panel, while G2-IC is responsible for driving the lower half of the display panel. Due to differences in ICs and differences in RC loading in the wiring of the two ICs, the display may appear split up and down.

[0004] At the same time, the display panel has two source driver ICs, S1-IC and S2-IC, which are arranged on the left and right sides and are responsible for the source drive of the left and right halves of the display panel respectively. Similarly, due to differences in ICs and differences in RC loading in the wiring of the two ICs, the display screen may appear split left and right. There may also be a phenomenon of splitting the screen up, down, left, and right.

[0005] In summary, due to the differences between multiple ICs and the differences in RC loading of the display panel wiring, the display screen will be split at the junction of the wiring, which reduces the display quality.

[0006] Therefore, a driving solution that can solve the above problems is needed to improve the display image quality. Utility Model Content

[0007] Existing display panels use different ICs. In addition, the RC loading of the display panel wiring is different, which causes the display screen to split at the junction of the wiring.

[0008] In view of the above problems, an array substrate and a display device are proposed. By interlacing the gate driver IC with the gate line, or by interlacing the source driver IC with the source data line, or by interlacing the gate line and the source data line corresponding to the gate driver IC and the source driver IC respectively, the RC Loading difference problem of the gate line or the source gate line is avoided, and the left-right split screen or the top-bottom split screen problem caused by multiple driver ICs of the display device is solved.

[0009] In a first aspect, an array substrate includes:

[0010] Multiple gate driver ICs;

[0011] Source driver IC;

[0012] The plurality of gate driving ICs are respectively and sequentially connected to the gate lines of the array substrate in an interlaced manner;

[0013] The source driving ICs are respectively connected to the source data lines of the array substrate in sequence.

[0014] In combination with the array substrate described in the first aspect of the utility model, in a first possible implementation manner, the number of the gate driver ICs is an even number, and:

[0015] The connections with the gate lines are arranged in a staggered manner.

[0016] In a second aspect, an array substrate includes:

[0017] Gate driver IC;

[0018] Multiple source driver ICs;

[0019] The plurality of source driver ICs are respectively and sequentially connected to the source data lines of the array substrate in an interlaced manner;

[0020] The gate driving ICs are respectively connected to the gate lines of the array substrate in sequence.

[0021] In combination with the array substrate described in the second aspect of the utility model, in a first possible implementation manner, the number of the source driver ICs is an even number, and:

[0022] The connections to the source data lines are arranged in a staggered manner.

[0023] In a third aspect, an array substrate includes:

[0024] Multiple gate driver ICs;

[0025] Multiple source driver ICs;

[0026] The plurality of gate driving ICs are respectively and sequentially connected to the gate lines of the array substrate in an interlaced manner;

[0027] The plurality of source driver ICs are respectively and sequentially connected to the source data lines of the array substrate in an interlaced manner.

[0028] In combination with the array substrate described in the second aspect of the utility model, in a first possible implementation manner, the number of the source driver ICs is an even number, and the connection between the source driver ICs and the source data lines is staggered in pairs;

[0029] The number of the gate driving ICs is an even number, and the gate lines are connected in pairs in an alternating arrangement.

[0030] In a fourth aspect, a display device includes:

[0031] The array substrate according to the first aspect;

[0032] or

[0033] The array substrate according to the second aspect;

[0034] or

[0035] The array substrate described in the second aspect.

[0036] The array substrate and display device described in the present invention are implemented by interlacing the gate driver IC with the gate line, or by interlacing the source driver IC with the source data line, or by interlacing the gate line and the source data line corresponding to the gate driver IC and the source driver IC respectively, thereby avoiding the RC Loading difference problem of the gate line or the source gate line, and solving the left-right split screen or top-down split screen problem caused by multiple driver ICs of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0038] Figure 1 It is a schematic diagram of driver IC connection in the prior art;

[0039] Figure 2 It is a schematic diagram of the upper and lower split screen in the prior art;

[0040] Figure 3 It is a schematic diagram of left and right split screen in the prior art;

[0041] Figure 4 It is a schematic diagram of cross-screen splitting in the prior art;

[0042] Figure 5 This is a schematic diagram of the connection of the driver IC of Example 1 of the present utility model;

[0043] Figure 6 This is a schematic diagram of driver IC connection in Example 2 of the present utility model;

[0044] Figure 7 This is a schematic diagram of the connection of the driver IC in Example 3 of the present utility model. DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the utility model to clearly and completely describe the technical solution in the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, other embodiments obtained by ordinary technicians in this field without creative work are all within the scope of protection of the utility model.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the technical field of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0047] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0048] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0049] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0050] The existing display panels use different ICs. At the same time, the RC loading of the display panel wiring is different, which causes the display screen to split at the junction of the wiring. Figure 1-Figure 4 , Figure 1 It is a schematic diagram of driver IC connection in the prior art. Figure 2 It is a schematic diagram of the upper and lower split screen in the prior art, Figure 3 Schematic diagram of left-right split screen in the prior art. Figure 4 It is a schematic diagram of cross-screen splitting in the prior art.

[0051] In view of the above problems, an array substrate and a display device are proposed.

[0052] First, as Figure 5 , Figure 5 This is a schematic diagram of the driver IC connection of Example 1 of the utility model; an array substrate, including multiple gate driver ICs (Gn-ICs) and source driver ICs (Sn-ICs); multiple gate driver ICs (Gn-ICs) are respectively and sequentially connected to the gate lines of the array substrate in an interlaced manner; source driver ICs (Sn-ICs) are respectively and sequentially connected to the source data lines of the array substrate. By interlacing the gate driver ICs (Gn-ICs) with the gate lines, the RC Loading difference problem of the gate lines is avoided, and the left-right split screen or top-down split screen problem caused by multiple driver ICs of the display device is solved.

[0053] like Figure 5 The gate lines in the array substrate are arranged horizontally, and the source data lines are arranged vertically.

[0054] Preferably, the number of gate driver ICs (Gn-ICs) is an even number, and the connections between two gate driver ICs and gate lines are arranged in a staggered manner. Figure 5 There are two gate drive ICs, namely G1-IC and G2-IC.

[0055] When there is an even number of gate driving ICs, the gate lines may be connected in two symmetrically staggered connections, for example, G1-IC and G2-IC may be connected in a symmetrically staggered connection, and G3-IC and G4-IC may be connected in a symmetrically staggered connection.

[0056] Second, as Figure 6 , Figure 6 This is a schematic diagram of the driver IC connection of Example 2 of the utility model; an array substrate, including a gate driver IC (Gn-IC), a plurality of source driver ICs (Sn-ICs); the plurality of source driver ICs (Sn-ICs) are respectively and sequentially connected to the source data lines of the array substrate in an interlaced manner; the gate driver ICs (Gn-ICs) are respectively and sequentially connected to the gate lines of the array substrate. By interlacing the source driver ICs (Sn-ICs) with the source data lines, the RC Loading difference problem of the source gate lines is avoided, and the left-right split screen or top-down split screen problem caused by multiple driver ICs of the display device is solved.

[0057] like Figure 6 The gate lines in the array substrate are arranged horizontally, and the source data lines are arranged vertically.

[0058] Preferably, the number of source driver ICs (Sn-ICs) is an even number, and the connections between two of them and the gate lines are arranged in a staggered manner. Figure 6There are two source driver ICs, namely S1-IC and S2-IC.

[0059] When there is an even number of source driver ICs, two gate lines may be connected in a symmetrical and staggered manner, for example, S1-IC and S2-IC may be connected in a symmetrical and staggered manner, and S3-IC and S4-IC may be connected in a symmetrical and staggered manner.

[0060] Thirdly, Figure 7 , Figure 7 This is a schematic diagram of the driver IC connection of Example 3 of the utility model. An array substrate includes multiple gate driver ICs (Gn-ICs) and multiple source driver ICs (Sn-ICs); multiple gate driver ICs (Gn-ICs) are respectively and sequentially staggered connected with the gate lines of the array substrate; multiple source driver ICs (Sn-ICs) are respectively and sequentially staggered connected with the source data lines of the array substrate. By staggering the gate lines and source data lines corresponding to the gate driver ICs (Gn-ICs) and the source driver ICs (Sn-ICs), the RC Loading difference problem of the gate lines and the source gate lines is avoided, and the left-right split screen or top-down split screen problem caused by multiple driver ICs of the display device is solved.

[0061] Preferably, the number of source driver ICs (Sn-ICs) is an even number, and the connections with the source data lines are arranged in an alternating manner; the number of gate driver ICs (Gn-ICs) is an even number, and the connections with the gate lines are arranged in an alternating manner. The gate lines in the array substrate are arranged horizontally, and the source data lines are arranged vertically.

[0062] like Figure 7 , there are 2 gate driver ICs, namely G1-IC and G2-IC. When there are an even number of gate driver ICs, two gate lines can be symmetrically staggered, such as G1-IC and G2-IC are symmetrically staggered, and G3-IC and G4-IC are symmetrically staggered. When there are an even number of source driver ICs, two gate lines can be symmetrically staggered, such as S1-IC and S2-IC are symmetrically staggered, and S3-IC and S4-IC are symmetrically staggered.

[0063] In a fourth aspect, a display device includes:

[0064] The array substrate in Embodiment 1 may also include only the array substrate in Embodiment 2, or may also include only the array substrate in Embodiment 3.

[0065] The array substrate and display device of the utility model are implemented by interlacing the gate driving IC (Gn-IC) with the gate lines, or by interlacing the source driving IC (Sn-IC) with the source data lines, or by interlacing the gate lines and source data lines corresponding to the gate driving IC (Gn-IC) and the source driving IC (Sn-IC), respectively, thereby avoiding the RC Loading difference problem of the gate lines or the source gate lines, and solving the left-right split screen or top-bottom split screen problem caused by multiple driving ICs of the display device.

[0066] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. An array substrate, characterized in that it comprises: Multiple gate driver ICs; Source driver IC; The plurality of gate driving ICs are respectively and sequentially connected to the gate lines of the array substrate in an interlaced manner; The source driving ICs are respectively connected to the source data lines of the array substrate in sequence.

2. The array substrate according to claim 1, characterized in that: The number of the gate driver ICs is an even number, and: The connections with the gate lines are arranged in a staggered manner.

3. An array substrate, characterized in that: include: Gate driver IC; Multiple source driver ICs; The plurality of source driver ICs are respectively and sequentially connected to the source data lines of the array substrate in an interlaced manner; The gate driving ICs are respectively connected to the gate lines of the array substrate in sequence.

4. The array substrate according to claim 3, characterized in that: The number of the source driver ICs is an even number, and: The connections to the source data lines are arranged in a staggered manner.

5. An array substrate, characterized in that: include: Multiple gate driver ICs; Multiple source driver ICs; The plurality of gate driving ICs are respectively and sequentially connected to the gate lines of the array substrate in an interlaced manner; The plurality of source driver ICs are respectively and sequentially connected to the source data lines of the array substrate in an interlaced manner.

6. The array substrate according to claim 5, characterized in that: The number of the source driver ICs is an even number, and the connection between two of them and the source data lines is staggered; The number of the gate driving ICs is an even number, and the gate lines are connected in pairs in an alternating arrangement.

7. A display device, characterized in that: include: The array substrate according to claim 1 or 2; or The array substrate according to claim 3 or 4; or The array substrate according to claim 5 or 6.

Images