PCB structure for improving clock signal backflow path

Abstract

The utility model discloses a PCB structure for improving a clock signal backflow path, which comprises a PCB body, the PCB body comprises a surface wiring layer and a plurality of internal wiring layers which are arranged from top to bottom, the surface wiring layer is provided with a clock signal layer changing hole and GND backflow holes distributed at two sides of the clock signal layer changing hole, and the GND backflow holes are communicated with the internal wiring layers. The center distance between the GND backflow hole and the clock signal layer change hole is smaller than or equal to 3 mm. According to the design, the backflow path of the clock signal is obviously optimized, so that the stable backflow path of the clock signal in the transmission process can be ensured, attenuation and distortion of the clock signal can be reduced, the stability and accuracy of the clock signal can be improved, and the GND backflow hole not only provides the stable backflow path, but also improves the reliability of the clock signal. And electromagnetic radiation generated in the clock signal transmission process is effectively absorbed through the metal grounding property, so that interference to other circuits and systems is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of circuit boards, and more particularly to a PCB structure for improving a clock signal return path. Background Art

[0002] Printed Circuit Board (PCB), also known as printed circuit board, is an important component of electronic products' physical support and signal transmission. In the application process of high-speed circuit PCB, with the increasing density of integrated circuits, whether the clock signal can be transmitted completely from the transmitter to the receiver has become a key issue that must be faced and considered.

[0003] The clock signal synchronizes data transmission, synchronizing the sending and receiving clocks to ensure accurate and stable data transmission. Clock signal synchronization prevents time distortion or loss during data transmission, ensuring data integrity and availability. Clock signal synchronization also prevents other factors from interfering with data transmission, ensuring proper system operation. Therefore, the clock signal plays a crucial role in data transmission.

[0004] However, the GND return of the clock signal is a key factor affecting clock signal integrity. Improper clock signal return can damage the return signal, ultimately preventing complete signal transmission. Conventional designs don't adequately consider clock signal return. Furthermore, when inner-layer clock signals reference the power plane, power supply noise can interfere at the layer transition hole. Utility Model Content

[0005] In order to overcome the deficiencies of the prior art, the present invention provides a PCB structure for improving the return path of a clock signal, so as to solve the problem of clock signal waveform distortion caused by insufficient GND return path.

[0006] The technical solution of the present utility model is as follows: A PCB structure for improving the clock signal return path includes a PCB board body, the PCB board body includes a surface routing layer and several internal routing layers arranged from top to bottom, the surface routing layer is provided with a clock signal layer switching hole and GND return holes distributed on both sides of the clock signal layer switching hole, and the center distance between the GND return hole and the clock signal layer switching hole is less than or equal to 3mm.

[0007] Furthermore, the aperture of the clock signal layer switching hole is equal to the aperture of the GND return hole.

[0008] Furthermore, the aperture of the clock signal layer switching hole and the aperture of the GND return hole are both 0.3 mm.

[0009] Furthermore, the center distance between the GND return hole and the clock signal layer switching hole is 1 mm.

[0010] Furthermore, the surface routing layer is provided with a first ground copper foil, and the first ground copper foil is provided on the periphery of the GND return hole and the clock signal layer switching hole.

[0011] Furthermore, two power holes, a first filter capacitor and a second filter capacitor are provided on the surface routing layer, the first pin of the first filter capacitor is connected to the adjacent power hole, the second pin of the first filter capacitor is connected to the adjacent GND return hole, the first pin of the second filter capacitor is connected to the adjacent power hole, and the second pin of the second filter capacitor is connected to the adjacent GND return hole.

[0012] Furthermore, a plurality of evenly distributed GND holes are provided on the first ground copper sheet.

[0013] Furthermore, the center distance between any two adjacent GND holes is 10 mm to 20 mm.

[0014] The present invention according to the above scheme has the following beneficial effects: the present invention provides a PCB structure for improving the clock signal return path, including a PCB board body, the PCB board body including a surface routing layer and several internal routing layers arranged from top to bottom, the surface routing layer being provided with a clock signal layer change hole and GND return holes distributed on both sides of the clock signal layer change hole, the center distance between the GND return hole and the clock signal layer change hole being less than or equal to 3mm. This design significantly optimizes the clock signal return path, thereby ensuring that the clock signal has a stable return path during transmission, helping to reduce clock signal attenuation and distortion, and improving the stability and accuracy of the clock signal. Secondly, the GND return hole not only provides a stable return path, but also effectively absorbs the electromagnetic radiation generated during the clock signal transmission process through its metal grounding properties, which can significantly reduce the EMI level, thereby reducing interference with other circuits and systems and improving the electromagnetic compatibility (EMC) of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0016] Figure 1 This is one of the structural schematic diagrams of a PCB structure for improving a clock signal return path in an embodiment of the present invention;

[0017] Figure 2 This is a second structural schematic diagram of a PCB structure for improving the clock signal return path in an embodiment of the present invention.

[0018] In the figure, 1. Clock signal layer switching hole; 2. GND return hole; 3. First ground copper foil; 4. Power hole; 5. First filter capacitor; 6. Second filter capacitor; 7. GND hole; 8. PCB board body. DETAILED DESCRIPTION

[0019] The following detailed description of the embodiments of the present invention is provided in conjunction with the accompanying drawings and examples. The following detailed description of the embodiments and the accompanying drawings are used to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention. That is, the present invention is not limited to the described embodiments.

[0020] In order to better understand the present invention, the present invention is further described below with reference to the accompanying drawings and embodiments:

[0021] See also Figures 1 and 2 As shown, an embodiment of the present invention provides a PCB structure for improving the return path of a clock signal, comprising a PCB board body 8, wherein the PCB board body 8 comprises a surface routing layer and several internal routing layers arranged from top to bottom, wherein a clock signal layer switching hole 1 and GND return holes 2 distributed on both sides of the clock signal layer switching hole 1 are provided on the surface routing layer, and the center distance between the GND return hole 2 and the clock signal layer switching hole 1 is less than or equal to 3 mm. This design significantly optimizes the return path of the clock signal, thereby ensuring that the clock signal has a stable return path during transmission, helping to reduce clock signal attenuation and distortion, and improving the stability and accuracy of the clock signal. Secondly, the GND return hole 2 not only provides a stable return path, but also effectively absorbs the electromagnetic radiation generated during the transmission of the clock signal through its metal grounding properties, which can significantly reduce the EMI level, thereby reducing interference with other circuits and systems, and improving the electromagnetic compatibility (EMC) of the system.

[0022] In this embodiment, when the clock signal changes layers in a multi-layer circuit board, the reference plane may be a power plane (such as VCC or VDD) or a ground (GND) copper plane.

[0023] The first scenario involves the reference plane being the power plane. This plane may generate noise due to power supply fluctuations, noise, or coupling with other circuit modules. This noise can enter the clock signal line through capacitive, inductive, or electromagnetic coupling, causing jitter, skew, or other quality issues in the clock signal. Due to the reference power plane, the clock signal's return path is longer. Furthermore, because the ground (GND) plane is not located on an adjacent layer, this increases clock signal delay and distortion. Taking a 6-layer board as an example, high-speed differential signals need to be routed from the L1 layer to the L3 layer through a hole. The above-described solution of this embodiment is employed, namely, a clock signal layer change hole 1 and GND return holes 2 are provided on both sides of the clock signal layer change hole 1 on the surface routing layer. The center-to-center distance between the GND return hole 2 and the clock signal layer change hole 1 is less than or equal to 3 mm. This design ensures a good clock signal return flow and standardizes the spacing between the GND return hole 2 and the clock signal layer change hole 1. When the clock signal runs on the L3 layer and the L4 layer is the power plane, there will be power noise interference near the clock signal layer switching hole 1. In order to solve this problem, this embodiment proposes to add two filter capacitors near the clock signal layer switching hole 1 of the L1 layer, namely the first filter capacitor 5 and the second filter capacitor 6. At the same time, two power holes 4 are provided on the surface routing layer, the first pin of the first filter capacitor 5 is connected to the adjacent power hole 4, the second pin of the first filter capacitor 5 is connected to the adjacent GND return hole 2, the first pin of the second filter capacitor 6 is connected to the adjacent power hole 4, and the second pin of the second filter capacitor 6 is connected to the adjacent GND return hole 2.

[0024] The second case: The reference plane is the ground (GND) copper plane. The ground (GND) copper plane is mainly used to provide a stable reference potential for various circuits on the circuit board and serve as a return path. Since it does not directly carry power supply noise, the noise level of the ground (GND) copper plane is lower than that of the power plane. In this case, no additional filtering capacitor is required. It is only necessary to set a clock signal layer change hole 1 and GND return holes 2 distributed on both sides of the clock signal layer change hole 1 on the surface routing layer, and ensure that the center distance between the GND return hole 2 and the clock signal layer change hole 1 is less than or equal to 3mm.

[0025] Preferably, the aperture of the clock signal layer switching hole 1 is equal to the aperture of the GND return hole 2 .

[0026] Preferably, the aperture of the clock signal layer switching hole 1 and the aperture of the GND return hole 2 are both 0.3 mm.

[0027] Preferably, the center distance between the GND return hole 2 and the clock signal layer switching hole 1 is 1 mm.

[0028] Preferably, the surface routing layer is provided with a first ground copper foil 3 , and the first ground copper foil 3 is arranged on the periphery of the GND return hole 2 and the clock signal layer switching hole 1 .

[0029] Preferably, a plurality of evenly distributed GND holes 7 are provided on the first ground copper foil 3 .

[0030] Preferably, the center distance between any two adjacent GND holes 7 is 10 mm to 20 mm.

[0031] It's worth mentioning that, because clock signals are relatively sensitive, GND copper wrapping is required for clock traces to ensure stability and reduce interference. Regardless of whether the clock trace is located on the bottom or inner layers, it must be wrapped. Furthermore, to further enhance the wrapping effect, GND holes 7 are added every 10mm to 20mm. GND holes 7 provide an additional ground path for the clock signal, further reducing interference.

[0032] By enclosing the GND copper ground and adding GND hole 7, interference with the clock signal from other signals on the single front layer (i.e., the routing layer) can be prevented. Furthermore, this prevents the clock signal from interfering with other signals, thereby ensuring signal stability and reliability across the entire PCB, effectively improving the performance and reliability of the electronic system.

[0033] The indicated orientation or position relationship is based on the orientation or position relationship shown in the accompanying drawings, or the orientation or position relationship in which the product of the application is typically placed when in use, or the orientation or position relationship commonly understood by those skilled in the art, or the orientation or position relationship commonly placed when the product of the application is in use. It is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0034] It should be understood that those skilled in the art can make improvements or changes based on the above description, and all such improvements and changes should fall within the scope of protection of the claims attached to this utility model.

[0035] The above is an exemplary description of the present utility model patent in conjunction with the accompanying drawings. It is obvious that the implementation of the present utility model patent is not limited to the above-mentioned method. As long as various improvements are made using the method concept and technical solution of the present utility model patent, or the concept and technical solution of the present utility model patent are directly applied to other occasions without improvement, they are all within the scope of protection of the present utility model.

Claims

1. A PCB structure for improving a clock signal return path, characterized in that: The invention comprises a PCB board body (8), wherein the PCB board body (8) comprises a surface wiring layer and a plurality of internal wiring layers arranged from top to bottom, wherein the surface wiring layer is provided with a clock signal layer switching hole (1) and GND return holes (2) distributed on both sides of the clock signal layer switching hole (1), and the center distance between the GND return hole (2) and the clock signal layer switching hole (1) is less than or equal to 3 mm.

2. A PCB structure for improving a clock signal return path as claimed in claim 1, characterized in that: The aperture of the clock signal layer switching hole (1) is equal to the aperture of the GND return hole (2).

3. A PCB structure for improving a clock signal return path as claimed in claim 1, characterized in that: The aperture of the clock signal layer switching hole (1) and the aperture of the GND return hole (2) are both 0.3 mm.

4. A PCB structure for improving a clock signal return path as claimed in claim 1, characterized in that: The center distance between the GND return hole (2) and the clock signal layer switching hole (1) is 1 mm.

5. A PCB structure for improving a clock signal return path as claimed in claim 1, characterized in that: The surface wiring layer is provided with a first ground copper sheet (3), and the first ground copper sheet (3) is arranged on the periphery of the GND return hole (2) and the clock signal layer switching hole (1).

6. A PCB structure for improving a clock signal return path as claimed in claim 5, characterized in that: The surface routing layer is also provided with two power holes (4), a first filter capacitor (5) and a second filter capacitor (6), wherein the first pin of the first filter capacitor (5) is connected to the adjacent power hole (4), the second pin of the first filter capacitor (5) is connected to the adjacent GND return hole (2), the first pin of the second filter capacitor (6) is connected to the adjacent power hole (4), and the second pin of the second filter capacitor (6) is connected to the adjacent GND return hole (2).

7. A PCB structure for improving a clock signal return path as claimed in claim 5, characterized in that: The first ground copper sheet (3) is provided with a plurality of evenly distributed GND holes (7).

8. A PCB structure for improving a clock signal return path as claimed in claim 7, characterized in that: The center distance between any two adjacent GND holes (7) is 10 mm to 20 mm.

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