Display panel and display device

Abstract

The utility model discloses a display panel and a display device, and belongs to the field of display equipment. The display panel includes: a substrate; the shading layer is positioned on one side of the substrate; the buffer layer is located on the side, away from the substrate, of the shading layer and comprises a first insulating layer and a second insulating layer which are arranged in a stacked mode; the buffer layer is located on the substrate, the thin film transistors are located on the side, away from the substrate, of the buffer layer, at least one thin film transistor in the thin film transistors comprises a polycrystalline silicon layer, and the orthographic projection of the shading layer on the substrate and the orthographic projection of the polycrystalline silicon layer on the substrate are at least partially overlapped; the first insulating layer covers the surface and the side face, away from the substrate, of the shading layer, the first insulating layer comprises a plurality of first insulating patterns, and the first insulating patterns correspond to the thin film transistors one to one; the orthographic projection of the polycrystalline silicon layer on the substrate is within the orthographic projection of the first insulating pattern on the substrate.

Description

Technical Field

[0001] The present disclosure generally relates to the technical field of display devices, and more particularly to a display panel and a display apparatus. Background Art

[0002] As display technology develops, display panels are also constantly evolving.

[0003] In order to solve the problem of reddening of the display panel at a large viewing angle, the interlayer dielectric layer (ILD) above the substrate in the display panel is thickened, and a silicon oxide layer is provided as a buffer layer between the substrate and the interlayer dielectric layer.

[0004] However, since the dielectric constant of the silicon oxide layer is low, as the usage time increases, the conductive particles in the substrate will easily separate from the substrate and move up to the TFT channel layer through the silicon oxide layer and finally reach the TFT channel, causing the TFT leakage to increase and affecting the display effect of the display panel. Utility Model Content

[0005] In view of the above defects or deficiencies in the related art, it is desirable to provide a display panel and a display device that can solve the problem that due to the low dielectric constant of the silicon oxide layer, as the use time increases, the conductive particles in the substrate will easily separate from the substrate and move up to the TFT channel layer through the silicon oxide layer, and finally reach the TFT channel, causing the TFT leakage to increase, thus affecting the display effect of the display panel.

[0006] In a first aspect, a display panel is provided, the display panel comprising:

[0007] A substrate, a light shielding layer located on one side of the substrate, a buffer layer located on a side of the light shielding layer away from the substrate, the buffer layer comprising a first insulating layer and a second insulating layer stacked; and a plurality of thin film transistors located on a side of the buffer layer away from the substrate, at least one of the plurality of thin film transistors comprising a polysilicon layer, wherein an orthographic projection of the light shielding layer on the substrate at least partially overlaps with an orthographic projection of the polysilicon layer on the substrate;

[0008] The first insulating layer covers the surface and side of the light shielding layer away from the substrate, the first insulating layer comprises a plurality of first insulating patterns, and the plurality of first insulating patterns correspond to the plurality of thin film transistors one by one;

[0009] An orthographic projection of the polysilicon layer on the substrate is within an orthographic projection of the first insulating pattern on the substrate.

[0010] In the present application, the display panel includes a substrate, a light shielding layer located on one side of the substrate, a buffer layer located on the side of the light shielding layer away from the substrate (the buffer layer includes a first insulating layer and a second insulating layer stacked), and a plurality of thin film transistors located on the side of the buffer layer away from the substrate. Among the plurality of Harima transistors, at least one thin film transistor includes a polysilicon layer, and the orthographic projection of the light shielding layer on the substrate and the orthographic projection of the polysilicon layer on the substrate at least partially overlap. The first insulating layer covers the surface and side of the light shielding layer away from the substrate, the first insulating layer includes a plurality of first insulating patterns, the plurality of insulating patterns correspond one-to-one to the plurality of thin film transistors, and the orthographic projection of the polysilicon layer on the substrate is within the orthographic projection of the first insulating pattern on the substrate. In this way, by setting a first insulating layer with a first insulating pattern on the portion other than the contact surface between the light-shielding layer and the substrate, and making the orthographic projection of the polysilicon layer on the substrate within the orthographic projection of the first insulating layer on the substrate, the first insulating layer can be used to prevent the conductive particles of the substrate layer from moving up into the channel of the thin-film transistor to cause leakage of the thin-film transistor to the greatest extent, thereby improving the service life of the thin-film transistor as well as the service life and display effect of the display panel.

[0011] In a second aspect, a display device is provided, comprising the display panel described in the first aspect.

[0012] Additional aspects and advantages of the present invention will be given in part in the following description and in part will become apparent from the following description or will be learned through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0014] Figure 1 This is one of the schematic diagrams of the display panel structure in the related technology of this application;

[0015] Figure 2 This is the second schematic diagram of the display panel structure in the related technology of this application;

[0016] Figure 3 One of the schematic diagrams of the display panel structure provided in the embodiment of the present application;

[0017] Figure 4 The second schematic diagram of the display panel structure provided in the embodiment of the present application;

[0018] Figure 5 The third schematic diagram of the display panel structure provided in the embodiment of the present application;

[0019] Figure 6The fourth schematic diagram of the display panel structure provided in the embodiment of the present application;

[0020] Figure 7 The fifth structural diagram of the display panel provided in the embodiment of the present application;

[0021] Figure 8 The sixth schematic diagram of the display panel structure provided in the embodiment of the present application;

[0022] Fig. 9 The seventh schematic diagram of the display panel structure provided in the embodiment of the present application;

[0023] Fig.10 The eighth schematic diagram of the structure of the display panel provided in the embodiment of the present application;

[0024] Fig.11 This is the ninth schematic diagram of the display panel structure provided in the embodiment of the present application. DETAILED DESCRIPTION

[0025] The present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant utility model, rather than to limit the utility model. It is also necessary to explain that, for ease of description, only the parts related to the utility model are shown in the accompanying drawings.

[0026] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The following is an explanation of the usage scenarios of the embodiments of the present application.

[0027] As display technology develops, display panels are also constantly evolving.

[0028] like Figure 1 and Figure 2 As shown, Figure 1 and Figure 2 It is used to demonstrate the display panel structure in the related art before this application, wherein: Figure 1 To show the front view of the panel section, Figure 2 The cross-sectional top view of the display panel. Figure 1 and Figure 2 It can be seen that in order to ensure the display effect, the thickness of the interlayer dielectric layer (ILD) is often set to be thinner. Under the interlayer dielectric layer (ILD), the following Figure 1 The substrate 11 , the light shielding layer 12 , the silicon nitride layer 13 , the silicon oxide layer 14 and the polysilicon layer 15 are shown.

[0029] However, if Figure 3As shown in the figure, according to the wide-angle simulation results of different interlayer dielectric layer (ILD) thicknesses, it can be seen that the thinner the ILD film thickness, the more the wide-angle white point coordinates will shift toward the red direction, and this simulation result has also been confirmed in practical applications. According to the simulation test results, if you want to improve the wide-angle red problem, you need to increase the ILD film thickness. After increasing the ILD film thickness, in order to ensure the transmittance of the buffer layer (Buffer layer), the silicon nitride layer (SiN layer) originally set in the Buffer layer needs to be removed accordingly.

[0030] After removing the SiN layer in the Buffer layer, Figure 4 The TFT characteristic test data in the display panel shown clearly shows that when the Buffer layer is not provided with a SiN layer, after a certain period of use, especially after a certain period of use in a high-brightness, high-temperature environment, the optical performance of the display panel is poor, and afterimages and crosstalk are prone to occur. The reason is that when the Buffer layer is not provided with a SiN layer, only a silicon oxide layer (SiO layer) is provided in the Buffer layer. Since the dielectric constant of the SiO layer is low, as the working time of the display panel increases, the charged impurity ions of the glass material in the substrate will gradually move upward and enter the channel of the thin-film transistor (TFT) switch above the Buffer layer, thereby causing TFT leakage, and the product will present problems such as afterimages and crosstalk that cannot meet customer specifications.

[0031] In order to solve the problem of reddening of the display panel at a large viewing angle, the interlayer dielectric layer (ILD) above the substrate in the display panel is thickened, and a silicon oxide layer is provided as a buffer layer between the substrate and the interlayer dielectric layer.

[0032] However, since the dielectric constant of the silicon oxide layer is low, as the usage time increases, the conductive particles in the substrate will easily separate from the substrate and move up to the TFT channel layer through the silicon oxide layer and finally reach the TFT channel, causing the TFT leakage to increase and affecting the display effect of the display panel.

[0033] Based on this, the present application proposes a display panel and a display device, which can solve the problem that due to the low dielectric constant of the silicon oxide layer, as the usage time increases, the conductive particles in the substrate will easily separate from the substrate and move up to the TFT channel layer through the silicon oxide layer and finally reach the TFT channel, causing the TFT leakage level to increase, thereby affecting the display effect of the display panel.

[0034] Figure 5 This is a schematic diagram of the structure of a display panel according to an embodiment of the present application. Figure 5The display panel includes a substrate; a light-shielding layer located on one side of the substrate; a buffer layer located on a side of the light-shielding layer away from the substrate, the buffer layer including a first insulating layer and a second insulating layer stacked in layers; and a plurality of thin-film transistors located on a side of the buffer layer away from the substrate, at least one of the plurality of thin-film transistors including a polysilicon layer, wherein an orthographic projection of the light-shielding layer on the substrate at least partially overlaps with an orthographic projection of the polysilicon layer on the substrate.

[0035] In the embodiment of the present application, the substrate may be made of glass.

[0036] In the embodiment of the present application, the light-shielding layer may be a metal light-shielding layer.

[0037] In the embodiment of the present application, the first insulating layer and the second insulating layer may be made of different insulating materials. For example, the first insulating layer is a silicon oxide layer, and the second insulating layer is a silicon nitride layer.

[0038] In the embodiment of the present application, the polysilicon layer may be a phosphorus-doped polysilicon layer (POLY layer).

[0039] In the embodiment of the present application, a plurality of thin film transistors are included, wherein the thin film transistors may include transistors whose bottom layer is a polysilicon layer, and may also include transistors of other forms, which are not limited in the embodiment of the present application.

[0040] In the embodiment of the present application, the orthographic projection of the light shielding layer on the backplane corresponds to the orthographic projection of the thin film transistor on the backplane.

[0041] Furthermore, in the case where the bottom layer of the thin film transistor is a polycrystalline silicon layer, the orthographic projection of the light-shielding layer on the substrate layer at least partially overlaps with the orthographic projection of the polycrystalline silicon layer on the substrate, which may include: the orthographic projection of the light-shielding layer on the substrate layer and the orthographic projection of the polycrystalline silicon layer on the substrate completely overlap, that is, the orthographic projection of the light-shielding layer on the substrate layer is in a state where the orthographic projection of the polycrystalline silicon layer on the substrate layer completely overlaps.

[0042] It can be understood that, from the above content, the orthographic projection of the light shielding layer on the backplane corresponds to the orthographic projection of the thin film transistor on the backplane, that is, the positions of the light shielding layer and the thin film transistor are corresponding. In this case, the positions of the light shielding layer and the polysilicon layer in the thin film transistor are also corresponding, that is, the orthographic projections of the two on the backplane can partially overlap or completely overlap.

[0043] like Figure 5 As shown, in Figure 5The cross-sectional view of a thin film transistor region in the display panel includes a backplane 51, a metal light shielding layer 52 (also the light shielding layer), a SiN layer 53 (also the first insulating layer), and a SiO layer 54 (also the second insulating layer). The SiN layer 53 and the SiO layer 54 together constitute a buffer layer. A thin film transistor is arranged above the buffer layer. Figure 5 Only the thin film transistor whose bottom layer is a phosphorus-doped polysilicon layer (POLY layer) is shown, and only the POLY layer 55 (ie, the above-mentioned polysilicon layer) is shown.

[0044] Correspondingly, such as Figure 6 As shown, Figure 6 For Figure 5 The corresponding top view of the cross-sectional view of a region where a thin film transistor is located in the display panel, Figure 6 In order to show the relative position relationship between different stacking layers in the embodiment of the present application, Figure 5 The SiO layer 54 and the back plate 51 in the Figure 6 It can be seen that the phosphorus-doped polysilicon layer 55 and the metal light shielding layer 52 are partially overlapped. Figure 6 The shapes of the phosphorus-doped polysilicon layer 55 and the metal light-shielding layer 52 shown are the shapes of the orthographic projection of the metal light-shielding layer 52 and the orthographic projection of the phosphorus-doped polysilicon layer 55 on the substrate.

[0045] In an embodiment of the present application, the first insulating layer covers the surface and side of the light-shielding layer away from the substrate, and the first insulating layer includes a plurality of first insulating patterns, and the plurality of first insulating patterns correspond one-to-one to the plurality of thin-film transistors.

[0046] In the embodiment of the present application, an orthographic projection of the polysilicon layer on the substrate is within an orthographic projection of the first insulating pattern on the substrate.

[0047] In the embodiment of the present application, the first insulating layer covers the surface of the light shielding layer other than the surface in contact with the substrate, that is, the surface and side surfaces of the light shielding layer away from the substrate.

[0048] In the embodiment of the present application, the first insulating layer does not need to cover the entire display panel, but only covers the area of ​​the plurality of first insulating patterns.

[0049] It can be understood that, from the foregoing content, in the related technologies before the embodiments of the present application, since the environmental parameters such as temperature will change during the use of the display panel, and the dielectric constant of the second insulating layer is small, it is easy for the conductive particles in the substrate in the embodiments of the present application to move up to the channel in the thin film transistor and cause leakage. Therefore, in order to prevent leakage, two structural improvements are provided in the embodiments of the present application. On the one hand, the first insulating layer is covered on the surface and side of the light-shielding layer away from the substrate, that is, the light-shielding layer is fully covered; on the other hand, the setting position of the first insulating layer and the position of the thin film transistor are corresponded one by one. At the same time, when the bottom layer of the thin film transistor is a polycrystalline silicon layer, the orthographic projection of the polycrystalline silicon layer on the substrate is set within the orthographic projection of the first insulating pattern on the substrate, that is, the polycrystalline silicon layer is completely indirectly covered by the first insulating layer.

[0050] Further, by Figure 5 It can be seen that the POLY layer 55 (i.e., the polysilicon layer) and the SiN layer 53 (i.e., the first insulating layer) are not actually adjacent layers. However, when the SiN layer 53 does not completely cover the substrate 51, the conductive particles in the substrate 51 actually continuously move upward through the SiO layer 54 (i.e., the second insulating layer). Therefore, in order to further ensure that the conductive particles in the substrate 51 penetrate the SiO layer 54 to reach the Poly layer 55 and then enter the channel of the thin film transistor, it is necessary to make the orthographic projection of the SiN layer 53 wrap the Poly layer 55 in the orthographic projection direction relative to the substrate, so that the conductive particles in the resistance substrate 51 continuously penetrate the SiO layer 54 to reach the Poly layer 55 and then enter the channel of the thin film transistor.

[0051] Furthermore, in order to ensure that the first insulating layer does not affect the light extraction efficiency of the display panel, the first insulating layer is provided with a plurality of insulating patterns rather than being covered as a whole layer.

[0052] Optionally, in an embodiment of the present application, the first insulating pattern includes at least one pattern type.

[0053] It can be understood that the pattern type of the first insulating pattern can be a pattern with the same shape as the outline of the polysilicon layer, or a pattern with a shape different from the outline of the polysilicon layer, for example, a square or a circle.

[0054] like Figure 6 As shown, Figure 6 The first insulating pattern 53 is a pattern with the same contour shape as the polysilicon layer, which can ensure that the orthographic projection of the polysilicon layer on the substrate is within the orthographic projection of the first insulating pattern on the substrate, and at the same time, the first insulating layer covers the surface and side of the light-shielding layer away from the substrate.

[0055] like Figure 7 As shown, Figure 7 The first insulating pattern 53 is different from the contour shape of the polysilicon layer and is square, which can ensure that the orthographic projection of the polysilicon layer on the substrate is within the orthographic projection of the first insulating pattern on the substrate, and at the same time, the first insulating layer covers the surface and side of the light-shielding layer away from the substrate.

[0056] Optionally, in an embodiment of the present application, a shape of the first insulating pattern in the first insulating layer is the same as a contour shape of the polysilicon layer.

[0057] Exemplarily, as described above, the shape of the first insulating pattern in the first insulating layer may be set to be the same as the outline shape of the polysilicon layer.

[0058] It can be understood that when the shape of the first insulating pattern in the first insulating layer is set to be the same as the contour shape of the polysilicon layer, then in the process of generating the first insulating layer of the first insulating pattern, if it is generated by a mask process, there is no need to make a new mask (Mask) for the first insulating layer, and it can use the existing mask of the polysilicon layer. In this way, the cost of using the mask for the first insulating layer can be saved.

[0059] Optionally, in an embodiment of the present application, a center point of the first insulation pattern in the first insulation layer coincides with a center point of a contour of the polysilicon layer.

[0060] Exemplarily, in order to ensure that the setting position of the first insulating layer having the first insulating pattern can correspond to the polysilicon layer, and at the same time ensure that the orthographic projection of the first insulating layer having the first insulating pattern on the back plate can surround the orthographic projection of the polysilicon layer on the back plate, the center point of the first insulating pattern in the first insulating layer can coincide with the center point of the outline of the above-mentioned polysilicon layer.

[0061] Optionally, in an embodiment of the present application, the shortest distance between any point of the outline boundary of the first insulation pattern in the first insulation layer and the outline boundary of the polysilicon layer is constant.

[0062] It can be understood that, from the foregoing content, the first insulating layer having the first insulating pattern can surround the orthographic projection of the polysilicon layer on the back plate, and it is necessary to make the area of ​​the orthographic projection of the first insulating pattern on the back plate larger than the area of ​​the orthographic projection of the polysilicon layer on the back plate. At the same time, the orthographic projection of the polysilicon layer on the back plate is within the orthographic projection of the first insulating pattern on the back plate.

[0063] Therefore, the distance between any point of the contour boundary in the first insulating pattern and any point between the contour boundary of the polysilicon layer is greater than the preset shortest distance, and the shortest distance between any point of the contour boundary in the first insulating pattern and any point between the contour boundary of the polysilicon layer is constant.

[0064] like Figure 6 As shown, Figure 6 In the figure, the contour boundary in the first insulating pattern is the boundary of 53, and the boundary of the POLY layer is the boundary of 55, wherein the shortest distance between the two is A, and the shortest distance A is a constant value, and the distances between the contour boundary and the boundary of the POLY layer in the remaining first insulating patterns are all greater than A.

[0065] like Figure 7 As shown, Figure 7 In the figure, the contour boundary in the first insulating pattern is the boundary of 53, and the boundary of the POLY layer is the boundary of 55, wherein the shortest distance between the two is B, and the shortest distance B is a constant value, and the distances between the contour boundary and the boundary of the POLY layer in the remaining first insulating patterns are all greater than B.

[0066] Optionally, in an embodiment of the present application, an orthographic projection of the first insulating pattern in the first insulating layer on the substrate is within an orthographic projection of the thin film transistor on the substrate.

[0067] It can be understood that in order to ensure that the first insulating layer does not affect the display effect of the display panel, the orthographic projection of the first insulating pattern in the first insulating layer on the substrate is within the orthographic projection of the thin film transistor on the substrate.

[0068] Generally, the first insulating layer has a certain refractive index, which will affect the light transmission effect of the lower layer of the substrate. However, by arranging the first insulating layer within the range where the thin film transistor is located, this problem of affecting light transmission can be avoided.

[0069] The display panel provided by the present application includes a substrate, a light shielding layer located on one side of the substrate, a buffer layer located on the side of the light shielding layer away from the substrate (the buffer layer includes a first insulating layer and a second insulating layer stacked), and a plurality of thin film transistors located on the side of the buffer layer away from the substrate. Among them, at least one thin film transistor among the plurality of Harima transistors includes a polysilicon layer, and the orthographic projection of the light shielding layer on the substrate and the orthographic projection of the polysilicon layer on the substrate at least partially overlap. The first insulating layer covers the surface and side of the light shielding layer away from the substrate, and the first insulating layer includes a plurality of first insulating patterns, and the plurality of insulating patterns correspond one-to-one to the plurality of thin film transistors, and the orthographic projection of the polysilicon layer on the substrate is within the orthographic projection of the first insulating pattern on the substrate. In this way, by setting a first insulating layer with a first insulating pattern on the portion other than the contact surface between the light-shielding layer and the substrate, and making the orthographic projection of the polysilicon layer on the substrate within the orthographic projection of the first insulating layer on the substrate, the first insulating layer can be used to prevent the conductive particles of the substrate layer from moving up into the channel of the thin-film transistor to cause leakage of the thin-film transistor to the greatest extent, thereby improving the service life of the thin-film transistor as well as the service life and display effect of the display panel.

[0070] Optionally, in the embodiment of the present application, the display panel further includes an interlayer dielectric layer.

[0071] Exemplarily, when the thickness of the interlayer dielectric layer is greater than a first preset threshold, the thickness of the first insulating layer is less than a second preset threshold, and the thickness of the first insulating layer is inversely proportional to the thickness of the interlayer dielectric layer.

[0072] Exemplarily, the first preset threshold may be user-defined or preset by the display panel.

[0073] It can be understood that, from the above content, when the thickness of the interlayer dielectric layer (ILD) is thin, the display panel is prone to the problem of reddening at a large viewing angle. Therefore, in order to avoid the problem of reddening at a large viewing angle, the thickness of the interlayer dielectric layer (ILD) is set to be greater than the first preset threshold. After the thickness of the interlayer dielectric layer (ILD) is set to be greater than the first preset threshold, in order to ensure the thickness coordination and display effect of the overall display panel, the thickness of the first insulating layer can be correspondingly set to be less than the second preset threshold. That is, the thickness of the first insulating layer is inversely proportional to the thickness of the interlayer dielectric layer.

[0074] Optionally, in an embodiment of the present application, a ratio of the sum of the thickness of the first insulating layer, the thickness of the light shielding layer and the thickness of the interlayer dielectric layer to the thickness of the display panel is within a preset ratio range.

[0075] Exemplarily, when the thickness of the above-mentioned interlayer dielectric layer is a predetermined thickness, the thickness of the corresponding first insulating layer and the thickness of the light-shielding layer also need to be matched accordingly. Specifically, the sum of the thickness of the above-mentioned first insulating layer, the thickness of the light-shielding layer and the thickness of the above-mentioned interlayer dielectric layer needs to be within a preset ratio range of the thickness of the display panel.

[0076] Exemplarily, the preset ratio range may be preset by the display panel or may be user-defined, which is not limited in the embodiments of the present application.

[0077] The embodiment of the present application also provides a display device, which includes the above-mentioned display panel. The display panel includes: a substrate; a light shielding layer located on one side of the substrate; a buffer layer located on the side of the light shielding layer away from the substrate, the buffer layer including a first insulating layer and a second insulating layer stacked; and a plurality of thin film transistors located on the side of the buffer layer away from the substrate, at least one of the plurality of thin film transistors including a polysilicon layer, wherein the orthographic projection of the light shielding layer on the substrate at least partially overlaps with the orthographic projection of the polysilicon layer on the substrate; the first insulating layer covers the surface and side of the light shielding layer away from the substrate, the first insulating layer including a plurality of first insulating patterns, the plurality of first insulating patterns corresponding to the plurality of thin film transistors one by one; the orthographic projection of the polysilicon layer on the substrate is within the orthographic projection of the first insulating pattern on the substrate.

[0078] In a possible example, a shape of the first insulating pattern in the first insulating layer is the same as a contour shape of the polysilicon layer.

[0079] In a possible example, a center point of the first insulation pattern in the first insulation layer coincides with a center point of a contour of the polysilicon layer.

[0080] In a possible example, the shortest distance between any point of the outline boundary of the first insulation pattern in the first insulation layer and the outline boundary of the polysilicon layer is constant.

[0081] In a possible example, an orthographic projection of the first insulating pattern in the first insulating layer on the substrate is within an orthographic projection of the thin film transistor on the substrate.

[0082] In a possible example, the display panel further includes an interlayer dielectric layer;

[0083] When the thickness of the interlayer dielectric layer is greater than a first preset threshold, the thickness of the first insulating layer is less than a second preset threshold, and the thickness of the first insulating layer is inversely proportional to the thickness of the interlayer dielectric layer.

[0084] In a possible example, a ratio of the sum of the thickness of the first insulating layer, the thickness of the light shielding layer and the thickness of the interlayer dielectric layer to the thickness of the display panel is within a preset ratio range.

[0085] In a possible example, the first insulating pattern includes at least one pattern type.

[0086] The following is a description of the display panel generation process:

[0087] like Figure 8 As shown, Fig. 9The device includes a substrate 51 and a metal light shielding layer 52 (ie the light shielding layer mentioned above), wherein the metal light shielding layer 52 is attached to one side of the substrate 51 according to preset parameters.

[0088] like Fig. 9 As shown, in Fig. 9 After the substrate 51 and the metal shading layer 52 are generated in the same manner, a SiN layer 53 (i.e., the first insulating layer) is covered on the surface and side of the metal shading layer 52 above the substrate 51 away from the back plate 51, so that the positive projection of the SiN layer 53 on the back plate 51 is the same as the contour of the back plate 51.

[0089] like Fig.10 As shown, in Fig.10 As shown, after a metal shading layer 52 covers a SiN layer 53 on the surface and side away from the back plate 51 above the substrate 51, the SiN layer 53 is etched according to a first etching parameter so that the orthographic projection of the SiN layer 53 on the back plate is a first insulating pattern. At the same time, the orthographic projection of the subsequently generated polysilicon layer on the above-mentioned substrate 51 is within the orthographic projection of the above-mentioned first insulating pattern on the above-mentioned substrate 51.

[0090] like Fig.11 As shown, in Fig.11 As shown, the SiN layer 53 is etched according to the first etching parameters, so that after the SiN layer 52 is projected on the back plate as a first insulating pattern, the SiO layer 54 (that is, the second insulating layer mentioned above) is covered on the SiN layer 53, wherein the orthographic projection of the SiO layer 54 on the back plate has the same shape and size as the back plate.

[0091] In this way, by changing the covering structure of the first insulating layer, on the basis of ensuring that the first insulating layer covers the shading layer, the first insulating layer is removed from the non-corresponding area of ​​the thin film transistor on the backplane, thereby improving the transmittance of the display panel and improving the display effect of the display panel.

[0092] It is understandable that in the above Fig.11 As shown, in Fig.10 As shown, after the metal light shielding layer 52 covers the SiN layer 53 on the surface and side of the back plate 51 away from the substrate 51, the SiN layer 53 is etched according to the first etching parameter. In the process of etching the SiN layer 53, since the shape of the first insulating pattern of the SiN layer is the same as the contour shape of the polysilicon layer, the same mask process as the polysilicon layer can be used without using a new mask, thereby eliminating the need to increase the mask cost.

[0093] When the SiN layer 53 is etched according to the first etching parameters so that the profile of the SiN layer 53 is the same as the profile of the polysilicon layer, as shown in FIG. Figure 6 As shown, Figure 6 The profile of the SiN layer 53 is the same as the profile of the polysilicon layer 55.

[0094] It should be noted that for details not disclosed in the display device of the embodiment of the present application, please refer to the details disclosed in the above embodiments of the present application, which will not be repeated here.

[0095] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the aforementioned disclosed concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other to form a technical solution.

Claims

1. A display panel, characterized in that: The display panel comprises: substrate; a light shielding layer located on one side of the substrate; a buffer layer located on a side of the light shielding layer away from the substrate, the buffer layer comprising a first insulating layer and a second insulating layer stacked; and a plurality of thin film transistors located on a side of the buffer layer away from the substrate, at least one of the plurality of thin film transistors comprising a polysilicon layer, wherein an orthographic projection of the light shielding layer on the substrate at least partially overlaps with an orthographic projection of the polysilicon layer on the substrate; The first insulating layer covers the surface and side of the light shielding layer away from the substrate, the first insulating layer comprises a plurality of first insulating patterns, and the plurality of first insulating patterns correspond to the plurality of thin film transistors one by one; An orthographic projection of the polysilicon layer on the substrate is within an orthographic projection of the first insulating pattern on the substrate.

2. The display panel according to claim 1, characterized in that: The shape of the first insulating pattern in the first insulating layer is the same as the outline shape of the polysilicon layer.

3. The display panel according to claim 2, characterized in that: A center point of the first insulating pattern in the first insulating layer coincides with a center point of a contour of the polysilicon layer.

4. The display panel according to claim 2, characterized in that: The shortest distance between any point of the outline boundary of the first insulation pattern in the first insulation layer and the outline boundary of the polysilicon layer is constant.

5. The display panel according to claim 1, characterized in that: An orthographic projection of a first insulating pattern in the first insulating layer on the substrate is within an orthographic projection of the thin film transistor on the substrate.

6. The display panel according to claim 1, characterized in that: The display panel also includes an interlayer dielectric layer; When the thickness of the interlayer dielectric layer is greater than a first preset threshold, the thickness of the first insulating layer is less than a second preset threshold, and the thickness of the first insulating layer is inversely proportional to the thickness of the interlayer dielectric layer.

7. The display panel according to claim 6, characterized in that: A ratio of the sum of the thickness of the first insulating layer, the thickness of the light shielding layer and the thickness of the interlayer dielectric layer to the thickness of the display panel is within a preset ratio range.

8. The display panel according to any one of claims 1 to 7, characterized in that: The first insulating pattern includes at least one pattern type.

9. A display device, characterized in that: The display device comprises the display panel according to any one of claims 1 to 8.

Images