Gate drive circuit, display substrate and display device

Abstract

The utility model provides a gate drive circuit, a display substrate and a display device, and relates to the technical field of display. The gate driving circuit comprises a first driving unit electrically connected to a clock end, and the first driving unit is configured to output a first scanning signal in a blanking period under the control of a clock signal from the clock end and an initial signal from an initial end; and the second driving unit is electrically connected to the clock end, and the second driving unit is configured to output a second scanning signal in the display period under the control of the first scanning signal and the clock signal.

Description

Technical Field

[0001] The utility model relates to the field of display technology, and in particular to a gate drive circuit, a display substrate and a display device. Background Art

[0002] The display panel may include a display area and a non-display area. For example, the display area is scanned during a display period of a display frame, and the non-display area is scanned during a blanking period of a display frame.

[0003] There is a large difference between the load of the display panel during the display period and the load of the blanking period, which causes the power supply voltage received by the driving circuit to be unstable. As a result, the capacitor connected to the power line in the circuit board will vibrate, resulting in capacitor howling, affecting the user experience. Utility Model Content

[0004] The utility model provides a grid drive circuit, a display substrate and a display device.

[0005] According to a first aspect, the utility model provides a gate drive circuit, comprising: a first drive unit, electrically connected to a clock terminal; the first drive unit is configured to output a first scan signal during a blanking period under the control of a clock signal from the clock terminal and a start signal from a start terminal; and a second drive unit, electrically connected to the clock terminal, the second drive unit is configured to output a second scan signal during a display period under the control of the first scan signal and the clock signal.

[0006] For example, the clock end includes 2N clock ends, and the first driving unit is electrically connected to the 2N clock ends; the first driving unit includes M cascaded first shift registers, and the first input end of the m-th stage first shift register in the first driving unit is electrically connected to the starting end, N≥m≥1, M is an integer multiple of 2N, and m, N and M are all positive integers.

[0007] For example, the first input terminal of the mth level first shift register is electrically connected to the output terminal of the mNth level first shift register, the first reset terminal of the mth level first shift register is electrically connected to the output terminal of the m+Nth level first shift register, the second reset terminal of the mth level first shift register is electrically connected to the output terminal of the m+N+1th level first shift register, MN>m>N.

[0008] For example, the first reset terminal of the mth level first shift register is electrically connected to the output terminal of the m-M+Nth level first shift register, and the second reset terminal of the mth level first shift register is electrically connected to the output terminal of the m-M+N+1th level first shift register, M≥m≥M-N+1 and M≥4N.

[0009] For example, the second input terminal of the mth stage first shift register is electrically connected to the output terminal of the m+MNth stage first shift register, N≥m≥1 and M≥4N.

[0010] For example, the second driving unit is electrically connected to 2N clock terminals; wherein the second driving unit includes Q cascaded second shift registers, the output terminal of the m-th level first shift register is electrically connected to the first reset terminal of the m+QN-th level second shift register, the output terminal of the m-th level first shift register is electrically connected to the second reset terminal of the m+QN-1-th level second shift register, N≥m≥1, Q>N, and Q is a positive integer.

[0011] For example, the second driving unit includes Q cascaded second shift registers, a first input end of the m-th first shift register and an output end of the m+QN-th second shift register, N≥m≥1.

[0012] For example, the third input terminal of the m-th stage first shift register is electrically connected to the starting terminal, and N≥m≥1.

[0013] For example, the qth-level second shift register in the cascaded Q second shift registers includes a shift register unit, Q≥q≥1, q is a positive integer; and the mth-level first shift register includes a shift register unit, a first transistor and a second transistor, N≥m≥1; wherein the shift register unit of the mth-level first shift register is electrically connected to a first power supply, a second power supply, a third power supply, a first input terminal, a first reset terminal, a second reset terminal and an output terminal; the control electrode of the first transistor is electrically connected to the third input terminal, the first electrode of the first transistor is electrically connected to the shift register unit, and the second electrode of the first transistor is electrically connected to the third power supply; the control electrode and the first electrode of the second transistor are electrically connected to the second input terminal, and the first electrode of the second transistor is electrically connected to the first electrode of the first transistor.

[0014] For example, the m-th stage first shift register includes shift register units, M≥m>N.

[0015] For example, the first timing change of the start signal is consistent with the second timing change of the start signal, wherein the first timing change is the timing change of the start signal during the period when the level of the first clock signal among the 2N clock signals in the blanking period is maintained at the first level for the first time, and the second timing change is the timing change of the start signal during the period when the level of the first clock signal in the blanking period is maintained at the first level for the (M / (2N))+1th time.

[0016] For example, in the blanking period, when the first clock signal changes from the first level to the second level for the M / (2N)th time, the start signal changes from the second level to the first level.

[0017] For example, during the display time period, when the first clock signal among 2N clock signals changes from the second level to the first level for the first time, the start signal changes from the second level to the first level, and the duration of the first level of the start signal is (MN) / N times the duration of the first level of the first clock signal in one scanning cycle.

[0018] According to the second aspect, the utility model provides a display substrate, comprising: a timing control circuit, configured to output a data enable signal under the control of a power supply voltage; a compensation circuit, configured to compensate a first initial voltage and output a first drive voltage under the control of the data enable signal; and a gate drive circuit provided in an embodiment of the utility model, configured to output a first scan signal and a second scan signal under the control of the first drive voltage.

[0019] For example, the display substrate further includes: a source driving circuit configured to output a data signal under the control of a second driving voltage, wherein the second driving voltage is determined by the compensation circuit based on the second initial voltage.

[0020] For example, the compensation circuit includes a first resistor, a second resistor, a first switch tube and a second switch tube; wherein, the first end of the first resistor is electrically connected to the first end of the second resistor, and the second end of the first resistor is electrically connected to the gate drive circuit; the second end of the second resistor is electrically connected to the control electrode of the first switch tube; the first electrode of the first switch tube is electrically connected to the first end of the first resistor, and the second electrode of the first switch tube is electrically connected to the second end of the first resistor; and the control electrode of the second switch tube is electrically connected to the timing control circuit, the first electrode of the second switch tube is electrically connected to the first end of the first resistor, and the second electrode of the second switch tube is electrically connected to the fourth power supply.

[0021] According to a third aspect, the utility model provides a display device, including a display panel; and a display substrate as provided in an embodiment of the utility model, configured to output a first scan signal, a second scan signal and a data signal to the display panel.

[0022] For example, the display panel includes a first pixel circuit located in a non-display area and a second pixel circuit located in a display area; wherein the first pixel circuit is electrically connected to a first driving unit in a gate driving circuit included in the display substrate, and the second pixel circuit is electrically connected to a second driving unit in the gate driving circuit included in the display substrate.

[0023] For example, the first timing change of the start signal is consistent with the second timing change of the start signal, wherein the first timing change is the timing change of the start signal during the period when the level of the first clock signal among the 2N clock signals in the blanking period is maintained at the first level for the first time, and the second timing change is the timing change of the start signal during the period when the level of the first clock signal in the blanking period is maintained at the first level for the (M / (2N))+1th time.

[0024] For example, in the blanking period, when the first clock signal changes from the first level to the second level for the M / (2N)th time, the start signal changes from the second level to the first level.

[0025] For example, during the display time period, when the first clock signal among 2N clock signals changes from the second level to the first level for the first time, the start signal changes from the second level to the first level, and the duration of the first level of the start signal is (MN) / N times the duration of the first level of the first clock signal in one scanning cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a schematic structural diagram of a gate drive circuit according to an embodiment of the utility model;

[0027] Figure 2 is a schematic structural diagram of a first driving unit according to an embodiment of the utility model;

[0028] Figure 3A is a structural schematic diagram of a first driving unit according to another embodiment of the utility model;

[0029] Figure 3B is a schematic structural diagram of a gate drive circuit according to another embodiment of the utility model;

[0030] Figure 4 is a signal timing diagram of a gate driving circuit according to an embodiment of the utility model;

[0031] Figure 5 is a structural schematic diagram of a first driving unit according to another embodiment of the utility model;

[0032] Figure 6 is a signal timing diagram of a gate driving circuit according to another embodiment of the utility model;

[0033] Figure 7 is a structural schematic diagram of a first driving unit according to another embodiment of the utility model;

[0034] Figure 8 is a schematic structural diagram of a first shift register according to an embodiment of the utility model;

[0035] Fig. 9is a signal timing diagram of a gate driving circuit according to another embodiment of the utility model;

[0036] Fig.10 is a schematic structural diagram of a display substrate according to an embodiment of the utility model;

[0037] Fig.11 is a schematic structural diagram of a display substrate according to another embodiment of the utility model;

[0038] Fig.12 is a schematic diagram of a power supply voltage according to an embodiment of the utility model;

[0039] Fig.13A is a schematic structural diagram of a display device according to an embodiment of the utility model;

[0040] Fig. 13B is a schematic structural diagram of a display device according to another embodiment of the utility model;

[0041] Fig.14 is a flow chart of a driving method according to an embodiment of the utility model; and

[0042] Fig.15 is a flow chart of a driving method according to another embodiment of the utility model. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical scheme and advantages of the embodiment of the utility model clearer, the technical scheme in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model. Obviously, the described embodiment is a part of the embodiment of the utility model, not all of it. Based on the described embodiment of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work belong to the scope of protection of the utility model. It should be noted that throughout the drawings, the same elements are represented by the same or similar figure marks.

[0044] In the following description, some specific embodiments are only used for illustrative purposes and should not be understood as any limitation to the present invention, but are merely examples of embodiments of the present invention. Conventional structures or configurations will be omitted when they may cause confusion in understanding the present invention. It should be noted that the shapes and sizes of the components in the figures do not reflect the actual size and proportion, but only illustrate the contents of the embodiments of the present invention.

[0045] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present invention should have the usual meanings understood by those skilled in the art. The words "first", "second" and similar words used in the embodiments of the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components.

[0046] In addition, in the description of the embodiments of the present invention, the term "connected" or "connected to" may refer to two components being directly connected, or may refer to two components being connected via one or more other components. In addition, the two components may be connected or coupled via a wired or wireless method.

[0047] The source and drain of the switch transistor used in the embodiment of the utility model are symmetrical, so the source and drain can be interchanged. In the embodiment of the utility model, according to its function, the gate can be called the control electrode, one of the source and the drain can be called the first electrode, and the other of the source and the drain can be called the second electrode.

[0048] In addition, in the description of the embodiments of the present invention, the terms "first power supply voltage", "second power supply voltage", "third power supply voltage" and "fourth power supply voltage" are only used to distinguish the difference in amplitude between the two power supply voltages. For example, the following description is based on the example that the "first power supply voltage" and the "second power supply voltage" are relatively high voltages, and the "third power supply voltage" and the "fourth power supply voltage" are relatively low voltages. It can be understood by those skilled in the art that the present invention is not limited to this.

[0049] It should be noted that in the description of the embodiments of the present utility model, the symbol DOUT can represent both an output signal and the level of the output signal. Similarly, the symbol INPUT can represent both an input signal and the level of the input signal, the symbol CLK can represent both a clock terminal and the voltage of a clock signal, and VDD and VSS can represent both a power terminal and the power voltage provided by the power terminal. The following embodiments are the same, and similar parts will not be repeated.

[0050] During the scanning time for a frame, the load of the display panel changes greatly during the display period and the blanking period, making the power supply voltage received by the driving circuit unstable. The voltage value of the power supply voltage should be stable, but simulation of the actual power supply voltage shows that there will be large ripples on the voltage value change curve of the power supply voltage.

[0051] A bypass or decoupling capacitor is connected to the power line for providing the power supply voltage on the printed circuit board (PCB). For example, these capacitors can be ceramic capacitors, which are welded on the PCB. Ceramic capacitors have an inverse piezoelectric effect. When the power supply voltage is unstable, the ceramic capacitor will be affected by an AC signal of a certain frequency and amplitude, which will cause elastic strain. Strong elastic strain will generate vibration, which will be transmitted to the PCB board to drive the PCB resonance. When the vibration reaches a certain frequency, the sound generated by the vibration will fall into the audible range of the human ear, and the capacitor will whistle, affecting the user experience.

[0052] In one example, anti-howling capacitors can be used, but the cost of anti-howling capacitors is relatively high. For example, the cost of tantalum capacitors is more than 10 times that of ordinary ceramic capacitors, and the cost of bracket capacitors is more than 50 times that of ordinary ceramic capacitors. This leads to a significant increase in the cost of display substrates and a decrease in product cost competitiveness.

[0053] In view of the above problems, the utility model provides a driving circuit, designs a gate driving circuit (Gate on Array, GOA) for the non-display area of ​​the display panel and the timing of the signal driving the GOA, so that the transistors of the pixel rows in the non-display area can be turned on row by row during the blanking period, and the data signal can charge the pixels in the non-display area, so that the difference between the load of the display panel during the display period and the blanking period is reduced, thereby improving the stability of the power supply voltage, reducing the ripple of the power supply voltage change caused by the load change, and improving the capacitor howling problem.

[0054] Figure 1 It is a structural schematic diagram of a gate driving circuit according to an embodiment of the utility model.

[0055] like Figure 1 As shown, the gate driving circuit 100 includes a first driving unit 110 and a second driving unit 120 .

[0056] In the embodiment of the present invention, the first driving unit 110 and the second driving unit 120 are both electrically connected to the clock terminal CLK.

[0057] Under the control of the clock signal CLK from the clock terminal CLK and the start signal SVT1 from the start terminal SVT1, the first driving unit 110 outputs the first scanning signal DOUT in the blanking period. Under the control of the first scanning signal DOUT and the clock signal CLK, the second driving unit 120 outputs the second scanning signal OUT in the display period.

[0058] In an embodiment of the utility model, a first scan signal DOUT is provided to a dummy pixel (dummy Pixel), and the dummy pixel is located in a non-display area of ​​a display panel. The dummy pixel is invisible to a user. For example, the dummy pixel is shielded by a frame of a display device so that the dummy pixel is invisible, and the area where the dummy pixel is located forms a non-display area of ​​a display panel. For another example, a shading layer such as a black matrix (BM) is used to shield the dummy pixel so that the dummy pixel is invisible. For another example, a structure such as a backplane is used to shield the dummy pixel so that the dummy pixel is invisible.

[0059] In an embodiment of the present invention, the second scan signal OUT is provided to the light-emitting pixel. The light-emitting pixel is located in the display area of ​​the display panel. The light-emitting pixel is visible to the user.

[0060] In the embodiment of the utility model, the display process of a frame includes a display period and a blanking period. Under the control of the clock signal CLK, the second driving unit 120 provides the second scanning signal OUT to the luminous pixel during the display period to realize the row-by-row scanning of the pixel row composed of the luminous pixel. The pixel row composed of the luminous pixel during the display period displays the frame of the picture, and enters the blanking period after the display period ends. Under the control of the clock signal CLK and the start signal STV1, the first driving unit 110 provides the first scanning signal DOUT to the virtual pixel during the blanking period to realize the row-by-row scanning of the pixel row composed of the virtual pixel.

[0061] The first scan signal DOUT may be provided to the second drive unit 120. Under the control of the first scan signal DOUT, the second drive unit 120 may be reset during the blanking period to output the second scan signal OUT for the next frame to the light-emitting pixel during the display period for the next frame. For example, during the blanking period, the level of the first scan signal DOUT provided to the second drive unit 120 switches between a high level and a low level, and the second drive unit 120 is reset under the control of the high level of the first scan signal DOUT. During the display period, when the second drive unit 120 outputs the second scan signal OUT having a high level, the level of the first scan signal DOUT provided to the second drive unit 120 may be maintained at a low level.

[0062] In the embodiment of the utility model, during the display period, the second scanning signal OUT scans the luminescent pixel so that the data signal charges the luminescent pixel. During the blanking period, the first scanning signal DOUT scans the dummy pixel so that the data signal can charge the dummy pixel. This can reduce the difference between the load of the display panel during the display period and the blanking period.

[0063] In the embodiment of the utility model, under the control of the start signal STV1, the first driving unit 110 can scan the virtual pixels multiple times. For example, after the first scanning signal DOUT completes the scanning of the last pixel row in the pixel row composed of virtual pixels, if the reset of all the luminous pixels is not completed, the first driving unit 110 can be triggered again by the start signal STV1, so that the first driving unit 110 outputs the first scanning signal OUT again to scan the virtual pixels, thereby providing sufficient time for the reset of the luminous pixels.

[0064] For example, by controlling the duration of the blanking period, all luminous pixels can be reset during the blanking period. During the blanking period, the start signal STV1 is used to trigger the first drive unit 110 to output the first scanning signal DOUT multiple times, so as to realize cyclic scanning of the pixel rows composed of virtual pixels. This can ensure that during the blanking period, the data signal can continuously charge the virtual pixels, thereby reducing the difference between the load of the display panel during the display period and the blanking period, improving the stability of the power supply voltage, reducing the ripple of the power supply voltage change caused by the load change, and improving the capacitor howling problem.

[0065] Figure 2 It is a structural schematic diagram of a first driving unit according to an embodiment of the utility model.

[0066] like Figure 2 As shown, the first driving unit 210 includes M cascaded first shift registers D1-DM, and the first driving unit 210 outputs the first scanning signals DOUT(1)-DOUT(M) to M rows of virtual pixels in the display panel to drive the M rows of virtual pixels. The clock end includes 2N clock ends CLK1-CLK2N. The M first shift registers D1-DM are electrically connected to the 2N clock ends CLK1-CLK2N, where N and M are positive integers.

[0067] In the embodiment of the utility model, the first input terminal INPUT1 of the m-th stage first shift register is electrically connected to the starting terminal STV1, N≥m≥1, M is an integer multiple of 2N, and N and M are positive integers. For example, the first input terminal INPUT1 of the 1st stage first shift register D1 is electrically connected to the starting terminal STV1. Under the control of the starting signal STV1, the first N stages of the first shift registers D1~DN output the first scanning signals DOUT(1)~DOUT(N). The first scanning signals output by the first N stages of the first shift registers D1~DN are provided to the first shift registers of the next stage of the respective cascade connection, thereby driving the first shift registers of the next stage of the respective cascade connection to output the first scanning signals.

[0068] In the embodiment of the utility model, by controlling the timing of the start signal STV1, the first N-stage first shift registers are controlled to output the corresponding first scanning signal DOUT, so that the M first shift registers D1-DM included in the first driving unit 210 can be controlled to output the corresponding first scanning signal. For example, after the M first shift registers D1-DM complete the scanning of the M rows of virtual pixels, the first N-stage first shift registers are triggered again based on the start signal STV1 to output the corresponding first scanning signal DOUT, so that the M first shift registers D1-DM are used to realize the cyclic scanning of the M rows of virtual pixels.

[0069] In the embodiment of the utility model, the number of first shift registers included in the first driving unit 210 can be an integer multiple of the number of clock terminals, that is, M is an integer multiple of 2N. The cascaded M first shift registers D1~DM are electrically connected to 2N clock terminals CLK1~CLK2N respectively. For example, each 2N-level first shift register in the cascaded M first shift registers D1~DM is electrically connected to 2N clock terminals CLK1~CLK2N respectively. For example, the 1st-level first shift register D1 and the 1+2N-level first shift register are electrically connected to the clock terminal CLK1, the 2nd-level first shift register and the 2+2N-level first shift register are electrically connected to the clock terminal CLK2, ..., the 2N-level first shift register and the 4N-level first shift register are electrically connected to the clock terminal CLK2N.

[0070] In the embodiment of the utility model, the first input terminal INPUT1 of the m-th level first shift register Dm of the first driving unit 210 is electrically connected to the output terminal DOUT of the mN-th level first shift register Dm-N, the first reset terminal RST1 of the m-th level first shift register Dm is electrically connected to the output terminal DOUT of the m+N-th level first shift register Dm+N, the second reset terminal RST2 of the m-th level first shift register Dm is electrically connected to the output terminal DOUT of the m+N+1-th level first shift register Dm+N+1, MN>m>N, M and m are positive integers.

[0071] In the embodiment of the utility model, the first N stages of first shift registers in the first driving unit 210 receive the start signal STV1. When the display period enters the blanking period, under the control of the start signal STV1, the first N stages of first shift registers respectively output their own first scanning signals and drive their own cascaded next stage of first shift registers.

[0072] For example, during the blanking period, the first scanning signal DOUT(mN) output by the mNth-level first shift register Dm-N is used as the input signal of the mth-level first shift register Dm, driving the mth-level first shift register Dm to output the first scanning signal DOUT(m). The first scanning signal DOUT(m+N) output by the m+Nth-level first shift register Dm+N and the first scanning signal DOUT(m+N+1) output by the m+N+1th-level first shift register Dm+N+1 reset the mth-level first shift register Dm, so that the mth-level first shift register Dm performs scanning of the next frame.

[0073] In the embodiment of the utility model, the m-th stage first shift register Dm is also electrically connected to the first power supply VDD1, the second power supply VDD2 and the third power supply VSS. The first power supply VDD1, the second power supply VDD2 and the third power supply VSS provide the first power supply voltage VDD1, the second power supply voltage VDD2 and the third power supply voltage VSS for the cascaded M first shift registers D1-DM in the first driving unit 210.

[0074] In the embodiment of the utility model, when entering the blanking period from the display period, the first driving unit 210 is driven by the start signal STV1, so that the first driving unit 210 can output the first scanning signal DOUT to the virtual pixel in the non-display area during the blanking period. The transistors of the virtual pixel row in the non-display area can be turned on row by row during the blanking period, and the data signal can charge the virtual pixel in the non-display area, reducing the difference between the load of the display panel in the display period and the blanking period, thereby improving the stability of the power supply voltage, reducing the ripple of the power supply voltage change caused by the load change, and improving the capacitor howling problem.

[0075] Take N=3, M=6 as an example, combined with Figure 3A The first driving unit is described as an example.

[0076] Figure 3A It is a structural schematic diagram of a first driving unit according to another embodiment of the utility model.

[0077] like Figure 3A As shown, the first driving unit 310 is electrically connected to six clock terminals CLK1-CLK6. The first driving unit 310 includes six first shift registers D1-D6 connected in cascade.

[0078] In the embodiment of the utility model, the first input terminal INPUT1 of the first shift register D1 of the first stage, the first shift register D2 of the second stage, and the first shift register D3 of the third stage is electrically connected to the starting terminal STV1. The starting signal STV1 from the starting terminal STV1 is used as the input signal of the first shift register D1 of the first stage, the first shift register D2 of the second stage, and the first shift register D3 of the third stage, so that the first shift register D1 of the first stage, the first shift register D2 of the second stage, and the first shift register D3 of the third stage generate the first scanning signal DOUT to drive the first shift registers of the next stage of the respective cascade connection.

[0079] By controlling the timing of the start signal STV1, after the 6th-stage first shift register D6 outputs the first scanning signal DOUT(6), the start signal STV1 re-drives the 1st-stage first shift register D1, the 2nd-stage first shift register D2 and the 3rd-stage first shift register D3. This enables the 1st-stage first shift register D1, the 2nd-stage first shift register D2 and the 3rd-stage first shift register D3 to be re-driven when the 6th-stage first shift register D6 outputs the first scanning signal DOUT(6) but the blanking period has not ended, thereby realizing the cyclic scanning of the cascaded 6 first shift registers D1 to D6 by the first driving unit 210 until the blanking period is switched to the display period.

[0080] For example, the first scanning signal DOUT(1) output by the first shift register D1 of the first stage is used as the input signal of the first shift register D4 of the fourth stage, driving the first shift register D4 of the fourth stage to output the first scanning signal DOUT(4). The first scanning signal DOUT(4) output by the first shift register D4 of the fourth stage and the first scanning signal DOUT(5) output by the first shift register D5 of the fifth stage reset the first shift register D1 of the first stage, so that the first shift register D1 of the first stage scans the next frame.

[0081] For example, the first scanning signal DOUT(2) output by the second-stage first shift register D2 is used as the input signal of the fifth-stage first shift register D5, driving the fifth-stage first shift register D5 to output the first scanning signal DOUT(5). The first scanning signal DOUT(5) output by the fifth-stage first shift register D5 and the first scanning signal DOUT(6) output by the sixth-stage first shift register D6 reset the second-stage first shift register D2, so that the second-stage first shift register D2 scans the next frame.

[0082] For example, the first scanning signal DOUT(3) output by the third-stage first shift register D3 is used as the input signal of the sixth-stage first shift register D6, driving the sixth-stage first shift register D6 to output the first scanning signal DOUT(6). The first scanning signal DOUT(5) output by the fifth-stage first shift register D5 resets the third-stage first shift register D3, causing the third-stage first shift register D3 to scan the next frame.

[0083] In the following, N=3, M=6, Figure 3B The gate drive circuit structure shown in the figure is taken as an example. Figure 4 The signal timing diagram shown describes the working process of the gate driving circuit provided by the embodiment of the present invention.

[0084] Figure 3B It is a structural schematic diagram of a gate driving circuit according to another embodiment of the utility model.

[0085] like Figure 3B As shown, the gate driving circuit 300 includes a first driving power supply 310 and a second driving unit 320 .

[0086] In the embodiment of the present utility model, Figure 3B The first driving unit 310 shown in FIG. Figure 3A The first driving unit 310 described in the above will not be described in detail for the sake of brevity.

[0087] In the embodiment of the utility model, the second driving unit 320 is electrically connected to the six clock terminals CLK1-CLK6. The second driving unit 320 includes Q cascaded second shift registers G1-GQ, where Q>N and Q is a positive integer. The second driving unit 320 outputs the second scanning signals OUT(1)-OUT(Q) to the light-emitting pixels in the display area of ​​the display panel, and the display screen displayed by the light-emitting pixels in the display area is visible to the user.

[0088] For example, the number of second shift registers included in the second driving unit 320 can be an integer multiple of the number of clock terminals. The cascaded Q second shift registers G1 to GQ are electrically connected to the six clock terminals CLK1 to CLK6, respectively. For example, each six-stage second shift register in the cascaded Q second shift registers G1 to GQ are electrically connected to the six clock terminals CLK1 to CLK6, respectively. For example, the first-stage second shift register Q1 and the seventh-stage second shift register are electrically connected to the clock terminal CLK1, the second-stage second shift register and the eighth-stage second shift register are electrically connected to the clock terminal CLK2, ..., the Qth to the sixth-stage second shift registers and the Qth-stage second shift register are electrically connected to the clock terminal CLK6.

[0089] In the embodiment of the utility model, the cascaded Q second shift registers G1-GQ are also electrically connected to the first power supply VDD1, the second power supply VDD2 and the third power supply VSS. The first power supply VDD1, the second power supply VDD2 and the third power supply VSS provide the cascaded Q second shift registers G1-GQ with the first power supply voltage VDD1, the second power supply voltage VDD2 and the third power supply voltage VSS. The first-stage second shift register G1 is also electrically connected to the starting terminal STV0, and the starting terminal STV0 provides the first-stage second shift register G1 with the starting signal STV0.

[0090] In the embodiment of the utility model, the cascade relationship between the Q second shift registers G1-GQ included in the second driving unit 320 is similar to the cascade relationship between the M first shift registers D1-DM included in the first driving power supply 310, which will not be repeated for simplicity.

[0091] In the embodiment of the utility model, the first N stages of the first shift register of the first driving unit 310 are electrically connected to the second shift register in the second driving unit 320. The output end of the m-th stage first shift register is electrically connected to the first reset end of the m+QN-th stage second shift register, and the output end of the m-th stage first shift register is electrically connected to the second reset end of the m+QN-1-th stage second shift register, N≥m≥1.

[0092] For example, the first reset terminal RST1 of the Q-th stage second shift register GQ is electrically connected to the output terminal DOUT of the 3-th stage first shift register D3, and the second reset terminal RST2 of the Q-th stage second shift register GQ is electrically connected to the output terminal DOUT of the 4-th stage first shift register D4. The output terminal DOUT of the 1-th stage first shift register D1 is electrically connected to the first reset terminal RST1 of the Q-2-th stage second shift register, and the output terminal of the 1-th stage first shift register D1 is electrically connected to the second reset terminal RST2 of the Q-3-th stage second shift register.

[0093] In the embodiment of the utility model, the first four stages of the first driving unit 310 are used to reset the Q-3th stage second shift register, the Q-2th stage second shift register, the Q-1th stage second shift register and the Qth stage second shift register GQ in the second driving unit 320.

[0094] In the embodiment of the utility model, after the Q-th stage second shift register GQ outputs the second scan signal OUT(Q), the start signal STV1 triggers the 1st stage first shift register D1, the 2nd stage first shift register D2 and the 3rd stage first shift register D3 to output their respective first scan signals.

[0095] Figure 4 4 is a signal timing diagram of a gate driving circuit according to an embodiment of the present utility model. Figure 4 The timing waveforms of the respective signals are shown.

[0096] Figure 4 The display period P1, blanking period P2 and display period P3 are shown. For example, the scanning time of the first frame display picture may include the display period P1 and the blanking period P2, and the scanning time of the second frame display picture may include the display period P2. The end of the blanking period P2 indicates the end of scanning the first frame display picture. Entering the display period P3 indicates the start of scanning the second frame display picture.

[0097] like Figure 4 As shown, the data enable signal DE indicates the type of the scanning period. For example, when the data enable signal DE is at a high level, the current scanning period is a display period. Figure 3BThe second driving unit 320 shown in FIG. 1 scans the light-emitting pixels in the display area. When the data enable signal DE is at a low level, the current scanning period is a blanking period. Figure 3B The first driving unit 310 is shown to scan virtual pixels in the non-display area.

[0098] In the embodiment of the utility model, under the control of six clock signals CLK1~CLK6 from six clock terminals CLK1~CLK6, six first scanning signals DOUT(1)~DOUT(6) are output through six cascaded first shift registers D1~D6, and Q second scanning signals OUT(1)~OUT(Q) are output through Q cascaded second shift registers G1~GQ.

[0099] like Figure 4 As shown, the first levels of the six clock signals CLK1 to CLK6 are shifted and output in sequence. For example, the first level is a high level, and the six clock signals CLK1 to CLK6 are sequentially changed to a high level. There are periods of high level among the clock signals CLK1, CLK2 and CLK3, and there are periods of high level among the clock signals CLK4, CLK5 and CLK6. Among the six clock signals, the clock signals CLK1 and CLK4 are not high level at the same time, the clock signals CLK2 and CLK5 are not high level at the same time, and the clock signals CLK3 and CLK6 are not high level at the same time. For example, when the clock signal CLK1 is high level, the clock signal CLK3 is low level, and when the clock signal CLK1 is low level, the clock signal CLK3 is high level.

[0100] In the embodiment of the present invention, the level variation rules of the six clock signals CLK1-CLK6 in the display period P1, the blanking period P2 and the display period P3 are consistent. In the blanking period P2, the six clock signals CLK1-CLK6 are continuously output.

[0101] In the first stage 1 of the display period P1, the data enable signal DE is at a high level, the start signal STV0 is at a high level, and the clock signal CLK1 is at a low level. In the second stage 2 of the display period P1, the data enable signal DE is at a high level, the start signal STV0 is at a high level, and the clock signal CLK1 is at a high level. In the third stage 3 of the display period P1, the data enable signal DE is at a high level, the start signal STV0 is at a low level, and the clock signal CLK1 is at a high level. In the fourth stage 4 of the display period P1, the data enable signal DE is at a high level, the start signal STV0 is at a low level, the start signal STV1 is at a high level, and the clock signal CLK1 is at a low level.

[0102] In the fifth stage 5 of the blanking period P2, the data enable signal DE is at a low level, the start signal STV1 is at a high level, and the clock signal CLK1 is at a high level. In the sixth stage 6 of the blanking period P2, the data enable signal DE is at a low level, the start signal STV1 is at a low level, and the clock signal CLK1 is at a high level. In the seventh stage 7 of the blanking period P2, the data enable signal DE is at a low level, the start signal STV1 is at a high level, and the clock signal CLK1 is at a low level. In the eighth stage 8 of the blanking period P2, the data enable signal DE is at a low level, the start signal STV1 is at a high level, and the clock signal CLK1 is at a high level.

[0103] In the embodiment of the utility model, the change rules of the start signal STV0 and the clock signal CLK1 in the first stage 1, the second stage 2 and the third stage 3 are the same as the change rules of the start signal STV1 and the clock signal CLK1 in the fourth stage 4, the fifth stage 5 and the sixth stage 6.

[0104] For example, the duration of the high level in one cycle of the clock signal CLK1 is 3H and the duration of the low level is 3H. The duration of the high level of the start signal STV0 is 5H, and the duration of the high level in one cycle of the start signal STV1 is 5H. Relative to the clock signal CLK1, the start signal STV0 is set high 3H in advance. When the start signal STV0 is high, the start signal STV0 triggers the first-stage second shift register G1 to output the second scanning signal OUT(1).

[0105] Relative to the first high level of the clock signal CLK1 in the blanking period P2, the start signal STV1 is set high 3H in advance. In the fifth stage 5 of the blanking period P2, the high level of the start signal STV1 lasts for 2H. When the start signal STV1 is at a high level in the fifth stage 5 of the blanking period P2, the start signal STV1 triggers the first shift register D1 of the first stage to output the first scanning signal DOUT(1). Since the first three stages of the first shift registers all receive the start signal STV1 as the output signal, under the control of the start signal STV1 from the start end STV1, the first three stages of the first shift registers each output to the next stage of the cascaded first shift register.

[0106] For example, when M=6 and N=3, the first shift register D1 of the first stage shifts to the first shift register D4 of the fourth stage. After the first shift register D4 of the fourth stage, the first shift register D5 of the fifth stage, and the first shift register D6 of the sixth stage sequentially output the first scanning signal, the first driving unit 310 realizes one-time driving of all virtual pixels in the non-display area of ​​the display panel.

[0107] If the data enable signal DE remains at a low level after completing one drive of all virtual pixels, the start signal STV1 needs to be set high again so that the start signal STV1 triggers the first shift register D1 of the first stage, the first shift register D2 of the second stage and the first shift register D3 of the third stage to output the first scanning signal again.

[0108] The first-stage first shift register D1 is electrically connected to the clock terminal CLK1, and the fourth-stage first shift register D4 is electrically connected to the clock terminal CLK4.

[0109] In the fifth stage 5 and the sixth stage 6 of the blanking period P2, the clock signal CLK1 is at a high level. Under the control of the clock signal CLK1 and the start signal STV1, the first-stage first shift register D1 outputs the first scanning signal DOUT(1) (the first first scanning signal DOUT(1) output under the control of the first high level of the clock signal CLK1 in the blanking period P2). In the seventh stage 7, under the control of the clock signal CLK4 and the first scanning signal DOUT(1), the fourth-stage first shift register D4 outputs the first scanning signal DOUT(4) (the first first scanning signal DOUT(4) output under the control of the first high level of the clock signal CLK4 in the blanking period P2).

[0110] In the embodiment of the utility model, when the virtual pixel needs to be scanned and driven again, the timing of the start signal STV1 in the fifth stage 5 can be repeated in the eighth stage 8, so that the first-stage first shift register D1 outputs the first scanning signal DOUT(1) with a high level again in the eighth stage 8.

[0111] Based on this situation, in order to ensure that the signal timing when the start signal STV1 is set high for the second time is consistent with the signal timing when it is set high for the first time, during the blanking period P2, when the clock signal CLK1 changes from a high level to a low level for the first time, the start signal STV1 changes from a low level to a high level, thereby realizing the re-setting of the start signal STV1.

[0112] For example, N=3, M=6, and the number of first shift registers included in the first driving unit 310 is twice the number of clock terminals. The first high level of the clock signal CLK1 in the blanking period P2 controls the first shift register D1 of the first stage to output the first scanning signal DOUT(1) with a high level, and the first high level of the clock signal CLK4 in the blanking period P2 controls the first shift register D4 of the fourth stage to output the first scanning signal DOUT(4) with a high level.

[0113] When the virtual pixel needs to be cyclically scanned, the second high level of the clock signal CLK1 in the blanking period P2 controls the first shift register D1 of the first stage to output the first scanning signal DOUT(1) with a high level. In order to ensure that the high level of the start signal STV1 is consistent with the signal change rule of the clock signal CLK1, it is necessary to control the start signal STV1 from a low level to a high level when the clock signal CLK1 changes from a high level to a low level for the first time in the blanking period P2. At this time, the period of the start signal STV1 is 1 times the period of the clock signal CLK1.

[0114] In the embodiment of the utility model, the number of the first shift registers is M / (2N) times the number of the clock terminals. The clock terminal CLK1 is electrically connected to the M / (2N) first shift registers among the M first shift registers. Therefore, when the virtual pixel needs to be scanned and driven again, the first-stage first shift register D1 can be driven to output the first scanning signal DOUT(1) with a high level under the control of the (M / (2N))+1th high level of the clock signal CLK1. At this time, the first timing change of the start signal is consistent with the second timing change of the start signal STV1, wherein the first timing change is the timing change of the start signal during the period when the level of the first clock signal in the blanking period is maintained at the first level for the first time, and the second timing change is the timing change of the start signal during the period when the level of the first clock signal in the blanking period is maintained at the first level for the (M / (2N))+1th time.

[0115] Since the start signal STV1 is set to a high level for the first time 3H before the clock signal CLK1 is set to a high level for the first time in the blanking period P2, and the duration of the high level and the low level of the clock signal CLK1 are both 3H, therefore, in the blanking period, when the first clock signal changes from a high level to a low level for the M / (2N)th time, the start signal STV1 changes from a low level to a high level. At this time, the period of the start signal STV1 is M / (2N) times the period of the clock signal CLK1.

[0116] For example, the high level duration in one cycle of the clock signal CLK1 is 3H and the low level duration is 3H. The high level duration in one cycle of the start signal STV1 is 5H and the low level duration in one cycle of the start signal STV1 is 1H.

[0117] In the embodiment of the utility model, after each cycle (6H) of the start signal STV1, the level of the data enable signal DE can be detected. If it is detected that the data enable signal DE is still at a low level, the start signal STV1 is set high again, so that the first drive unit 310 drives the virtual pixel circuit again. If the data enable signal DE is always at a low level, the start signal STV1 can be set high cyclically, so as to realize the cyclic scanning drive of the virtual pixel circuit by the first drive unit 310. If it is detected that the data enable signal DE jumps from a low level to a high level, the start signal STV1 can be set high and low, and the start signal STV1 is kept at a low level.

[0118] In the embodiment of the utility model, under the drive of the clock signal CLK1 to the clock signal CLK6, the Q second shift registers G1 to GQ included in the second driving unit 320 sequentially output the second scanning signal OUT(1) to the second scanning signal OUT(Q). The high level of the second scanning signal OUT(1) to the second scanning signal OUT(Q) is shifted and output, and the scanning signal OUT(1) to the scanning signal OUT(Q) sequentially jumps to the high level.

[0119] When the data enable signal DE changes from low level to high level, the blanking period P2 ends and the display period P3 begins. The changing rules of the signals in the display period P3 are similar to those in the display period P1, and will not be described for simplicity.

[0120] In an embodiment of the utility model, the timing of the start signal STV1 is designed so that the start signal STV1 is set high at a specific moment, which enables the virtual pixels to be cyclically scanned during the blanking period P2, so that the data signal can continuously charge the virtual pixels during the blanking period P2, thereby reducing the difference between the load of the display panel during the display period and the blanking period, improving the stability of the power supply voltage, reducing the ripple of the power supply voltage caused by the load change, and improving the capacitor howling problem.

[0121] In the following, N=3, M=12, Figure 5 As an example, the structure of the first drive unit shown in FIG. Figure 6 The signal timing diagram shown describes the working process of the first driving unit provided by the embodiment of the present invention.

[0122] Figure 5 It is a structural schematic diagram of a first driving unit according to another embodiment of the utility model.

[0123] like Figure 5 As shown, the first driving unit 510 is electrically connected to six clock terminals CLK1-CLK6. The first driving unit 510 includes 12 first shift registers D1-D12 connected in cascade.

[0124] In the embodiment of the present utility model, Figure 5 The connection relationship between the cascaded first shift registers D1 to D9 is similar to the connection relationship shown in FIG. 3 , and will not be repeated here for the sake of simplicity of the present invention. Figure 3B The connection relationship between the first driving unit 310 and the second driving unit 320 is similar, and will not be repeated here for the sake of simplicity of the present invention.

[0125] In an embodiment of the utility model, the first reset terminal RST1 of the mth level first shift register is electrically connected to the output terminal DOUT of the m-M+Nth level first shift register, and the second reset terminal RST2 of the mth level first shift register is electrically connected to the output terminal DOUT of the m-M+N+1th level first shift register, M≥m≥M-N+1 and M≥4N.

[0126] For example, the first reset terminal RST1 of the mth stage first shift register is electrically connected to the output terminal DOUT of the m-9th stage first shift register, and the second reset terminal RST2 of the mth stage first shift register is electrically connected to the output terminal DOUT of the m-8th stage first shift register, 12≥m≥10.

[0127] For example, the first reset terminal RST1 of the 12th-stage first shift register D12 is electrically connected to the output terminal DOUT of the 3rd-stage first shift register D3, and the second reset terminal RST2 of the 12th-stage first shift register D12 is electrically connected to the output terminal DOUT of the 4th-stage first shift register D4.

[0128] For example, the first reset terminal RST2 of the 11th-stage first shift register D11 is electrically connected to the output terminal DOUT of the 2nd-stage first shift register D2, and the second reset terminal RST2 of the 11th-stage first shift register D11 is electrically connected to the output terminal DOUT of the 3rd-stage first shift register D3.

[0129] For example, the first reset terminal RST2 of the 10th-stage first shift register D10 is electrically connected to the output terminal DOUT of the 1st-stage first shift register D1, and the second reset terminal RST2 of the 10th-stage first shift register D10 is electrically connected to the output terminal DOUT of the 2nd-stage first shift register D2.

[0130] In the embodiment of the utility model, the first scan signals DOUT(1)-DOUT(3) outputted by the first three stages of the first shift register are used to reset the last three stages of the first shift register, which can improve the pull-down effect in the last three stages of the first shift register.

[0131] Figure 64 is a signal timing diagram of a gate driving circuit according to another embodiment of the present invention. Figure 6 The timing waveforms of the respective signals are shown.

[0132] In the embodiment of the present utility model, Figure 6 A display period P1, a blanking period P2, and a display period P3 are shown. Figure 6 Shows the timing change rules of the six clock signals CLK1 to CLK6 Figure 4 The change rules shown are the same and will not be repeated for simplicity. Under the control of the six clock signals CLK1-CLK6 from the six clock terminals CLK1-CLK6, the cascaded 12 first shift registers D1-D12 output 12 first scanning signals DOUT(1)-DOUT(12). The cascaded Q second shift registers G1-GQ output Q second scanning signals OUT(1)-OUT(Q).

[0133] In the embodiment of the utility model, when M=12 and N=3, the first shift register D1 of the first stage outputs the first scanning signal to the first shift register D4 of the fourth stage, the first shift register D4 of the fourth stage outputs the first scanning signal to the first shift register D7 of the seventh stage, and the first shift register D7 of the seventh stage outputs the first scanning signal to the first shift register D10 of the tenth stage. When the first shift register D10 of the tenth stage, the first shift register D11 of the eleventh stage, and the first shift register D12 of the twelfth stage sequentially output the first scanning signal, the first driving unit 510 realizes one-time driving of all virtual pixels in the non-display area of ​​the display panel.

[0134] If the data enable signal DE remains at a low level after driving all virtual pixels once, the start signal STV1 needs to be set high again, so that the start signal STV1 triggers the first shift register D1 of the first stage to output the first scanning signal again.

[0135] The first-stage first shift register D1 and the seventh-stage first shift register D7 are both electrically connected to the clock terminal CLK1, and the fourth-stage first shift register D4 and the tenth-stage first shift register D10 are both electrically connected to the clock terminal CLK4.

[0136] In the first phase 1 of the blanking period P2, the clock signal CLK1 is at a high level. Under the control of the clock signal CLK1 and the start signal STV1, the first shift register D1 of the first stage outputs the first scanning signal DOUT(1) having a high level. In the second phase 2 of the blanking period P2, the clock signal CLK4 is at a high level. Under the control of the clock signal CLK4 and the first scanning signal DOUT(1), the first shift register D4 of the fourth stage outputs the first scanning signal DOUT(4) having a high level. In the third phase 3 of the blanking period P2, the clock signal CLK1 is at a high level. Under the control of the clock signal CLK1 and the first scanning signal DOUT(4), the first shift register D7 of the seventh stage outputs the first scanning signal DOUT(7) having a high level. In the fourth phase 4 of the blanking period P2, the clock signal CLK4 is at a high level. Under the control of the clock signal CLK4 and the first scanning signal DOUT(7), the first shift register D10 of the tenth stage outputs the first scanning signal DOUT(10) having a high level.

[0137] In an embodiment of the utility model, when the virtual pixel needs to be scanned and driven again, the timing of the start signal STV1 in the first stage 1 can be repeated in the fifth stage 5, so that the first-stage first shift register D1 outputs the first scanning signal DOUT(1) with a high level again in the fifth stage 5.

[0138] Based on this situation, in order to determine that the signal timing of the second high setting of the start signal STV1 is consistent with the signal timing of the first high setting, that is, the timing change of the start signal STV1 during the period when the level of the clock signal CLK1 is maintained at a high level for the first time in the blanking period is consistent with the timing change of the start signal STV1 during the period when the level of the clock signal CLK1 is maintained at a high level for the third time in the blanking period. Therefore, in the blanking period P2, when the clock signal CLK1 changes from a high level to a low level for the second time, the start signal STV1 changes from a low level to a high level, and the start signal STV1 is set high again.

[0139] For example, N=3, M=12, at this time, the number of first shift registers included in the first driving unit 510 is twice the number of clock terminals. The first high level of the clock signal CLK1 in the blanking period P2 controls the first shift register D1 of the first stage to output the first scanning signal DOUT(1) with a high level, and the second high level of the clock signal CLK1 in the blanking period P2 controls the first shift register D7 of the seventh stage to output the first scanning signal DOUT(7) with a high level. The first high level of the clock signal CLK4 in the blanking period P2 controls the first shift register D4 of the fourth stage to output the first scanning signal DOUT(4) with a high level, and the second high level of the clock signal CLK4 in the blanking period P2 controls the first shift register D10 of the tenth stage to output the first scanning signal DOUT(10) with a high level.

[0140] When the virtual pixel needs to be cyclically scanned, the third high level of the clock signal CLK1 in the blanking period P2 controls the first shift register D1 of the first stage to output the first scanning signal DOUT(1) with a high level. In order to ensure that the high level of the start signal STV1 is consistent with the signal change rule of the clock signal CLK1, it is necessary to control the start signal STV1 from a low level to a high level when the clock signal CLK1 changes from a high level to a low level for the second time in the blanking period P2. At this time, the period of the start signal STV1 is twice the period of the clock signal CLK1.

[0141] Figure 7 It is a structural schematic diagram of a first driving unit according to another embodiment of the utility model.

[0142] like Figure 7 As shown, the first driving unit 710 is electrically connected to six clock terminals CLK1-CLK6. The first driving unit 710 includes 12 first shift registers D1-D12 connected in cascade.

[0143] In the embodiment of the present utility model, Figure 7 The connection relationship between the cascaded first shift registers D3 to D12 is shown. Figure 5 The connection relationships shown are similar and will not be described again for the sake of simplicity of the present invention.

[0144] The connection relationship between the output terminals of the first stage first shift register D1, the second stage first shift register D2 and the third stage first shift register D3 of the first driving unit 710 and the second driving unit can be referred to as Figure 3B The connection relationship between the output terminals of the first-stage first shift register D1, the second-stage first shift register D2 and the third-stage first shift register D3 and the second driving unit 320 is shown, which will not be described in detail for the sake of simplicity of the present invention.

[0145] In an embodiment of the utility model, the first input terminal INPUT1 of the m-th level first shift register is electrically connected to the output terminal of the m+QN-th level second shift register, the second input terminal INPUT2 of the m-th level first shift register is electrically connected to the output terminal of the m+MN-th level first shift register, and the third input terminal INPUT3 of the m-th level first shift register is electrically connected to the starting terminal STV1, N≥m≥1 and M≥4N.

[0146] For example, the second input terminal INPUT2 of the 1st-level first shift register D1 is electrically connected to the output terminal DOUT of the 10th-level first shift register D10, the second input terminal INPUT2 of the 2nd-level first shift register D2 is electrically connected to the output terminal DOUT of the 11th-level first shift register D11, and the second input terminal INPUT2 of the 3rd-level first shift register D3 is electrically connected to the output terminal DOUT of D12 of the 12th-level first shift register.

[0147] In an embodiment of the utility model, the output terminal DOUT of the last N-stage first shift register is electrically connected to the second input terminal INPUT2 of the first N-stage first shift register, so that the M first shift registers are connected end to end, and the first scanning signal output by the last N-stage first shift register is used to drive the first N-stage first shift register, thereby realizing the cyclic scanning of the first driving unit 710.

[0148] For example, when entering the blanking period from the display period, the Q-2nd stage second shift register, the Q-1st stage second shift register and the Q-th stage second shift register of the second driving unit respectively output the second scanning signal to the first input terminal INPUT1 of the first stage first shift register D1, the first input terminal INPUT1 of the second stage first shift register D2 and the first input terminal INPUT1 of the third stage first shift register D3. Based on the second scanning signal provided by the Q-2nd stage second shift register, the Q-1st stage second shift register and the Q-th stage second shift register, the first driving unit 710 performs a first round of scanning on the virtual pixels.

[0149] If the data enable signal DE remains at a low level after completing one drive of all virtual pixels, the first scanning signals output by the 10th-level first shift register D10, the 11th-level first shift register D11 and the 12th-level first shift register D12 can be driven to the second input terminal INPUT2 of the 1st-level first shift register D1, the second input terminal INPUT2 of the 2nd-level first shift register D2 and the second input terminal INPUT2 of the 3rd-level first shift register D3 respectively, so that the 1st-level first shift register D1, the 2nd-level first shift register D2 and the 3rd-level first shift register D3 start the second round of scanning of the virtual pixels based on the first scanning signals output by the 10th-level first shift register D10, the 11th-level first shift register D11 and the 12th-level first shift register D12.

[0150] In the embodiment of the utility model, the second input terminal of the first N-stage first shift register is electrically connected to the output terminal of the last N-stage first shift register, and the structure of the first N-stage first shift register may be different from the structure of the first shift registers of the N+1st to Mth stages. For example, the structure of the first-stage first shift register D1, the second-stage first shift register D2 and the third-stage first shift register D3 is different from the structure of the first shift registers of the 4th to 12th stages.

[0151] In an embodiment of the utility model, the m-th level first shift register includes a shift register unit, a first transistor and a second transistor, N≥m≥1. The m-th level first shift register includes a shift register unit, M≥m>N. The q-th level second shift register in the cascaded Q second shift registers includes a shift register unit, Q≥q≥1, and q is a positive integer.

[0152] For example, the first shift registers of the 4th to 12th stages include a shift register unit, the second shift register includes a shift register unit, and the first three stages of the first shift register include a shift register unit, a first transistor, and a second transistor. The first transistor and the second transistor can be used to control the input of the start signal STV1 and the input of the signal received by the second input terminal INPUT2, respectively.

[0153] Figure 8 It is a schematic structural diagram of a first shift register according to an embodiment of the utility model. Figure 8 The structure of the first shift register D1 in the first driving unit is shown in FIG. Fig. 9 The signal timing diagram shown describes the working process of the first shift register provided by the embodiment of the present invention.

[0154] like Figure 8 As shown, the first shift register D1 includes a shift register unit 801, a first transistor M1 and a second transistor M2.

[0155] In the embodiment of the utility model, the shift register unit is electrically connected to the first power supply VDD1, the second power supply VDD2, the third power supply VSS, the first input terminal INPUT1, the first reset terminal RST1, the second reset terminal RST2 and the output terminal DOUT. The control electrode of the first transistor M1 is electrically connected to the third input terminal INPUT3, the first electrode of the first transistor M1 is electrically connected to the shift register unit 801, and the second electrode of the first transistor M1 is electrically connected to the third power supply VSS. The control electrode and the first electrode of the second transistor M2 are electrically connected to the second input terminal INPUT2, and the first electrode of the second transistor M2 is electrically connected to the first electrode of the first transistor M1.

[0156] In the embodiment of the present invention, the shift register unit 801 includes a third transistor M3 to an eighteenth transistor M18 and a capacitor C1.

[0157] A first electrode of the first transistor M1 and a first electrode of the second transistor M2 are electrically connected to a node PU.

[0158] A control electrode of the third transistor M3 is electrically connected to the node PU, a first electrode of the third transistor M3 is electrically connected to the clock terminal CLK1 , and a second electrode of the third transistor M3 is electrically connected to the output terminal DOUT.

[0159] A control electrode of the fourth transistor M4 is electrically connected to the first reset terminal RST1 , a first electrode of the fourth transistor M4 is electrically connected to the output terminal DOUT, and a second electrode of the fourth transistor M4 is electrically connected to the third power supply VSS.

[0160] A control electrode of the fifth transistor M5 is electrically connected to the node PD_CN1 , a first electrode of the fifth transistor M5 is electrically connected to the first power source VDD1 , and a second electrode of the fifth transistor M5 is electrically connected to the node PD1 .

[0161] A control electrode of the sixth transistor M6 is electrically connected to the node PU, a first electrode of the sixth transistor M6 is electrically connected to the node PD1, and a second electrode of the sixth transistor M6 is electrically connected to the third power supply VSS.

[0162] A control electrode of the seventh transistor M7 is electrically connected to the second reset terminal RST2 , a first electrode of the seventh transistor M7 is electrically connected to the node PU, and a second electrode of the seventh transistor M7 is electrically connected to the third power supply VSS.

[0163] A control electrode of the eighth transistor M8 is electrically connected to the node PU, a first electrode of the eighth transistor M8 is electrically connected to the node PD_CN1 , and a second electrode of the eighth transistor M8 is electrically connected to the third power source VSS.

[0164] The control electrode and the first electrode of the ninth transistor M9 are electrically connected to the first power source VDD1 , and the second electrode of the ninth transistor M9 is electrically connected to the node PD_CN1 .

[0165] A control electrode of the tenth transistor M10 is electrically connected to the node PD1 , a first electrode of the tenth transistor M10 is electrically connected to the node PU, and a second electrode of the tenth transistor M10 is electrically connected to the third power source VSS.

[0166] A control electrode of the eleventh transistor M11 is electrically connected to the node PD1 , a first electrode of the eleventh transistor M11 is electrically connected to the output terminal DOUT, and a second electrode of the eleventh transistor M11 is electrically connected to the third power source VSS.

[0167] The control electrode and the first electrode of the twelfth transistor M12 are electrically connected to the first input terminal INPUT1 , and the second electrode of the twelfth transistor M12 is electrically connected to the node PU.

[0168] A control electrode of the thirteenth transistor M13 is electrically connected to the node PD_CN2 , a first electrode of the thirteenth transistor M13 is electrically connected to the second power source VDD2 , and a second electrode of the thirteenth transistor M13 is electrically connected to the node PD2 .

[0169] A control electrode of the fourteenth transistor M14 is electrically connected to the node PU, a first electrode of the fourteenth transistor M14 is electrically connected to the node PD_CN2 , and a second electrode of the fourteenth transistor M14 is electrically connected to the third power source VSS.

[0170] A control electrode of the fifteenth transistor M15 is electrically connected to the node PU, a first electrode of the fifteenth transistor M15 is electrically connected to the node PD2, and a second electrode of the fifteenth transistor M15 is electrically connected to the third power supply VSS.

[0171] The control electrode and the first electrode of the sixteenth transistor M16 are electrically connected to the second power source VDD2 , and the second electrode of the sixteenth transistor M16 is electrically connected to the node PD_CN2 .

[0172] A control electrode of the seventeenth transistor M17 is electrically connected to the node PD2 , a first electrode of the seventeenth transistor M17 is electrically connected to the node PU, and a second electrode of the seventeenth transistor M17 is electrically connected to the third power source VSS.

[0173] A control electrode of the eighteenth transistor M18 is electrically connected to the node PD2 , a first electrode of the eighteenth transistor M18 is electrically connected to the output terminal DOUT, and a second electrode of the eighteenth transistor M18 is electrically connected to the third power supply VSS.

[0174] A first terminal of the capacitor C1 is electrically connected to the node PU, and a second terminal of the capacitor C1 is electrically connected to the output terminal DOUT.

[0175] Combination Fig. 9 right Figure 7 The first driving unit 710 and Figure 8 The working process of the first shift register D1 shown is described.

[0176] The first input terminal INPUT1 of the first shift register D1 receives the second scan signal OUT(Q-2) output by the second shift register of the Q-2 stage, and the second input terminal INPUT2 of the first shift register D1 receives the first scan signal DOUT(10). When the second scan signal OUT(Q-2) and the first scan signal DOUT(10) are at a high level, the clock signal CLK4 is at a high level and the clock signal CLK1 is at a low level.

[0177] For example, in the first phase 1 of the blanking period P2, when the first scan signal DOUT(10) is at a high level, the second transistor M2 or the twelfth transistor M12 is turned on, and the second scan signal OUT(Q-2) is applied to the node PU through the twelfth transistor M12 or the first scan signal DOUT(10) is applied to the node PU through the second transistor M2, and the capacitor C1 is charged. At this time, the potential of the node PU is at a high level.

[0178] Under the control of the high potential of the node PU, the sixth transistor M6, the eighth transistor M8, the fourteenth transistor M14, and the fifteenth transistor M15 are turned on. The third power supply voltage VSS from the third power supply VSS passes through the sixth transistor M6, the eighth transistor M8, the fourteenth transistor M14, and the fifteenth transistor M15, respectively pulling down the potentials of the nodes PD1, PD_CN1, PD_CN2, and PD2. Under the control of the low level of the nodes PD1, PD_CN1, PD_CN2, and PD2, the eleventh transistor M11, the fifth transistor M5, the thirteenth transistor M13, and the eighteenth transistor M18 are turned off.

[0179] Under the control of the high potential of the node PU, the transistor M3 is turned on. At this time, the clock signal CLK1 is output to the output terminal DOUT through the third transistor M3, and the first scanning signal DOUT(1) outputted from the output terminal DOUT is a low level signal.

[0180] In the second phase 2 of the blanking period P2, the clock signal CLK1 is at a high level, the second scanning signal OUT(Q-2) and the first scanning signal DOUT(10) are both at a low level, and the second transistor M2 and the twelfth transistor M12 are turned off. The node PU is kept at a high level under the action of the first capacitor C1, and the transistor M3 is kept in a conducting state at this time. The clock signal CLK1 is output to the output terminal DOUT through the third transistor M3, and the first scanning signal DOUT(1) outputted from the output terminal DOUT is a high level signal.

[0181] In the third stage 3 of the blanking period P2, the clock signal CLK1 is at a low level, and the first scanning signal DOUT(4) is at a high level, so the signal received by the first reset terminal RST1 is at a high level. Under the control of the high level of the first scanning signal DOUT(4), the fourth transistor M4 is turned on, and the third power supply voltage VSS is provided to the output terminal DOUT through the fourth transistor M4. The first scanning signal DOUT(1) output by the output terminal DOUT is a low level signal. Due to the bootstrap effect of the capacitor C1, the level of the node PU is pulled down.

[0182] In the third phase 3 of the blanking period P2, when the first scanning signal DOUT(5) jumps to a high level, the signal received by the second reset terminal RST2 is a high level. Under the control of the high level of the first scanning signal DOUT(5), the seventh transistor M7 is turned on, and the third power supply voltage VSS is provided to the node PU through the seventh transistor M7, and the level of the node PU is pulled down again.

[0183] Under the control of the low potential of the node PU, the sixth transistor M6, the eighth transistor M8, the fourteenth transistor M14, and the fifteenth transistor M15 are turned off.

[0184] Under the control of the high potential of the first power supply voltage VDD1 and the second power supply voltage VDD2, the ninth transistor M9 and the sixteenth transistor M16 are turned on, and the first power supply voltage VDD1 and the second power supply voltage VDD2 pass through the ninth transistor M9 and the sixteenth transistor M16 respectively, so that the potentials of the nodes PD_CN1 and PD_CN2 are pulled high. Under the control of the high potentials of the nodes PD_CN1 and PD_CN2, the fifth transistor M5 and the thirteenth transistor M13 are turned on, and the potentials of the nodes PD1 and PD2 are pulled high.

[0185] Under the control of the high potential of the node PD1 and the node PD2, the eleventh transistor M11 and the eighteenth transistor M18 are turned on, and the third power supply voltage VSS is provided to the output terminal DOUT through the eleventh transistor M11 and the eighteenth transistor M18. The first scanning signal DOUT(1) outputted from the output terminal DOUT is stably maintained as a low level signal.

[0186] The tenth transistor M10 is turned on under the control of the node PD1 , and the third power supply voltage VSS is provided to the node PU through the tenth transistor M3 , so that the potential of the node PU is stably maintained at a low level.

[0187] In the fourth phase 4 of the display period P3 , the start signal STV1 is at a high level, and the clock signal CLK1 is at a high level.

[0188] Under the control of the high level of the start signal STV1, the seventh transistor M1 is turned on, and the potential of the node PU is pulled low. Under the control of the low potential of the node PU, the third transistor M3 is turned off, and the first scanning signal DOUT(1) outputted by the output terminal DOUT is stably maintained as a low level signal.

[0189] When the level of the start signal STV1 remains at a high level, the first scanning signal DOUT(1) outputted from the output terminal DOUT remains stably at a low level. When the first scanning signal DOUT(1) outputted from the output terminal DOUT of the first-stage first shift register D1 remains at a low level, the first scanning signal DOUT(4) outputted from the fourth-stage first shift register D4 also remains at a low level.

[0190] The timing change of the first scanning signal output by the second-stage first shift register D2 and the third-stage first shift register D3 is similar to the timing change of the first scanning signal output by the first-stage first shift register D1. Therefore, when the first scanning signals output by the first-stage first shift register D1, the second-stage first shift register D2 and the third-stage first shift register D3 are all continuously maintained at a low level, the first scanning signals output by the fourth-stage to twelfth-stage first shift registers are also continuously at a low level, that is, the first driving unit 710 ends the scanning drive of the virtual pixel.

[0191] In the embodiment of the utility model, when entering the display period P3 from the blanking period P2, the first driving unit 710 may still be in the state of scanning the virtual pixel. In order to reduce the driving power consumption, the timing of the start signal STV1 can be designed so that the first driving unit 710 stops scanning the virtual pixel in the display period P3.

[0192] In an embodiment of the utility model, when it is detected that the first-stage second shift register of the second driving unit outputs a high level, the start signal STV1 is synchronously set high, so that the first-stage first shift register D1, the second-stage first shift register D2 and the third-stage first shift register D3 output a low-level first scanning signal.

[0193] For example, if the start signal STV1 is pulled high and any one of the first-stage first shift register D1, the second-stage first shift register D2 and the third-stage first shift register D3 is outputting a high-level signal, the high level of the start signal STV1 can control the first-stage first shift register D1, the second-stage first shift register D2 and the third-stage first shift register D3 to output a low-level signal, thereby causing the first driving unit 710 to stop scanning the virtual pixels in the display period P3.

[0194] For example, if the start signal STV1 is pulled high and any one of the first shift registers from level 4 to level 12 is outputting a high level signal, the duration of the high level of the start signal STV1 can be controlled so that the high level of the start signal STV1 can control the first shift register to output a low level signal.

[0195] For example, if the start signal STV1 is pulled high and a high-level signal is output from the first shift register of the N+1th level, the demand for the duration of the high level of the start signal STV1 is the greatest, so that during the duration of the high level of the start signal STV1, the first scanning signal can be shifted and output in sequence from the first shift registers of the N+1th level to the Mth level, and circulate until the first scanning signal is output by the first shift register of the 1st level.

[0196] For example, the clock signal CLKn and the clock signal CLKn+N are not at high level at the same time, so the duration of the high level and the low level of the clock signal CLKn can be NH. The level of the clock signal CLKn is set high 1H earlier than the level of the clock signal CLKn+1, so the level of the first scanning signal DOUT(m) is set high 1H earlier than the level of the first scanning signal DOUT(m+1). In the cyclic scanning process of the first driving unit 710, it can be considered that the first shift register of the first stage is the first shift register of the M+1th stage, so the level of the first scanning signal DOUT(N+1) output by the first shift register of the N+1th stage is set high at least (MN)H earlier than the level of the first scanning signal DOUT(1) output by the first shift register of the first stage.

[0197] Therefore, during the display period, when the clock signal CLK1 changes from a low level to a high level for the first time, the start signal STV1 changes from a low level to a high level synchronously, and the duration of the high level of the start signal STV1 is at least (MN) / N times the duration of the high level of the clock signal CLK1 in one scanning cycle.

[0198] For example, N=3, M=12, the duration of the high level of the start signal STV1 is at least 3 times the duration of the high level of the clock signal CLK1 in one scanning cycle, and the duration of the high level of the start signal STV1 is at least 9H.

[0199] exist Figure 8In the example, the first transistor M1 to the eighteenth transistor T18 are all M-type transistors, such as thin film transistors whose active layers are low temperature doped polysilicon (LTPS). Those skilled in the art can understand that according to the embodiment of the utility model, the first transistor M1 to the eighteenth transistor T18 can also be P-type transistors, such as thin film transistors whose active layers are indium gallium zinc oxide (IGZO), and the level of the gate turn-on signal of each transistor can be changed accordingly.

[0200] In addition, those skilled in the art will appreciate that the capacitors may be implemented as a single capacitor or a plurality of capacitor units connected in parallel or in series, as long as they can achieve their corresponding functions.

[0201] It should be noted that the node PU, the node PD1, the node PD2, the node PD_CN1 and the node PD_CN2 do not represent actual existing components, but represent the junction points of related circuit connections in the circuit diagram.

[0202] Fig.10 It is a schematic structural diagram of a display substrate according to an embodiment of the utility model.

[0203] like Fig.10 As shown, the display substrate 1000 includes a timing controller 1010 , a compensation circuit 1020 and a gate driving circuit 1030 .

[0204] In the embodiment of the present invention, the gate driving circuit 1030 may be at least one of the gate driving circuit 100 , the gate driving circuit 200 , the gate driving circuit 300 , the gate driving circuit 500 and the gate driving circuit 700 described above.

[0205] In the embodiment of the utility model, under the control of the power supply voltage, the timing control circuit 1010 outputs the data enable signal DE. Under the control of the data enable signal DE, the compensation circuit 1020 compensates the first initial voltage V1 and outputs the first driving voltage Vd1. Under the control of the first driving voltage Vd1, the gate driving circuit 1030 outputs the first scanning signal and the second scanning signal.

[0206] In the embodiment of the utility model, the first initial voltage V1 may be a power supply voltage provided by a power management integrated circuit (PMIC) to the gate drive circuit 1030. The first initial voltage V1 is load compensated by the compensation circuit 1020 to obtain the first drive voltage Vd1. The power supply voltage is the power supply voltage provided by the PMIC to the timing control circuit 1010.

[0207] The first driving voltage Vd1 may be the first power supply voltage VDD1 or the second power supply voltage VDD2 received by the gate driving circuit 1030 in the blanking period. The first initial voltage V1 may be the first power supply voltage VDD1 or the second power supply voltage VDD2 received by the gate driving circuit 1030 in the display period.

[0208] In the embodiment of the utility model, the display substrate 1000 further includes a source driving circuit. Under the control of a second driving voltage, the source driving circuit outputs a data signal, wherein the second driving voltage is determined by the compensation circuit 1020 based on the second initial voltage. The second driving voltage may be a relatively high power supply voltage received by the source driving circuit in the blanking period. The second initial voltage may be a relatively high power supply voltage received by the source driving circuit in the display period. Supply voltage.

[0209] In the embodiment of the present invention, the PMIC outputs a power supply voltage, and the timing control circuit 1010 works under the drive of the power supply voltage and outputs a data enable signal DE. The power supply voltage output by the PMIC may also be a relatively low power supply voltage provided to the source driving circuit.

[0210] In the embodiment of the utility model, since the load of the display panel in the blanking period is less than the load of the display panel in the display period, the load of the display panel in the blanking period is compensated by the compensation circuit 1020, so that the load of the display panel in the blanking period can be increased. By reducing the difference between the load of the display panel in the blanking period and the load of the display panel in the display period, the ripple of the power supply voltage change caused by the load change can be reduced, and the capacitor howling problem can be improved.

[0211] Fig.11 It is a structural schematic diagram of a display substrate according to another embodiment of the utility model.

[0212] like Fig.11 As shown, the display substrate 1100 includes a timing controller 1110 , a compensation circuit 1120 and a gate driving circuit 1130 .

[0213] In the embodiment of the present invention, the compensation circuit 1120 includes a first resistor R1, a second resistor R2, a first switch tube T1 and a second switch tube T2.

[0214] In the embodiment of the utility model, the first end of the first resistor R1 is electrically connected to the first end of the second resistor R2, and the second end of the first resistor R1 is electrically connected to the gate driving circuit 1130. The second end of the second resistor R2 is electrically connected to the control electrode of the first switch tube T1. The first electrode of the first switch tube T1 is electrically connected to the first end of the first resistor R1, and the second electrode of the first switch tube T1 is electrically connected to the second end of the first resistor R1. The control electrode of the second switch tube T2 is electrically connected to the timing control circuit 1110, the first electrode of the second switch tube T2 is electrically connected to the first end of the first resistor R1, and the second electrode of the second switch tube T2 is electrically connected to the fourth power supply GND, which can be grounded.

[0215] In the embodiment of the utility model, the first switch tube T1 may be a PMOS tube. By controlling the on and off states of the PMOS tube, it is possible to control whether the first resistor R1 is connected to the circuit.

[0216] In the embodiment of the utility model, the second switch tube T2 can be a transistor, for example, the transistor is an NPN transistor, the base of the transistor is electrically connected to the timing control circuit 1110, the collector of the transistor is electrically connected to the second end of the second resistor R2, and the emitter of the transistor is electrically connected to the fourth power supply GND. The data enable signal DE output by the timing control circuit 1110 is provided to the base of the transistor. Since the level of the data enable signal DE is relatively low and the turn-on voltage of the transistor is relatively low, the conduction of the transistor is controlled based on the data enable signal DE, thereby controlling the potential of the control electrode of the PMOS tube.

[0217] In the embodiment of the present invention, the load in the display panel during the display period is recorded as LoadingA, and the load in the display panel during the blanking period is recorded as LoadingB.

[0218] During the display period, the data enable signal DE is at a high level, the second switch tube T2 is turned on, and the voltage of the control electrode of the first switch tube T1 is 0V. Since the potential of the first electrode of the first switch tube T1 is V1, the gate-source voltage Vgs of the first switch tube T1 is -V1. Under the control of the low level, the first switch tube T1 is turned on, so the first resistor R1 is short-circuited. At this time, the load in the circuit is LoadingA.

[0219] During the blanking period, the data enable signal DE is at a low level, the second switch tube T2 is turned off, and the second end of the second resistor R2 is in an open circuit state. The first initial signal V1 is provided to the control electrode of the first switch tube T1 through the second resistor R2. Since the potential of the first electrode of the first switch tube T1 is V1, the gate-source voltage Vgs of the first switch tube T1 is 0. Since the threshold voltage Vth of the PMOS tube is less than 0, and since the gate-source voltage Vgs is greater than the threshold voltage Vt, the first switch tube T1 is turned off, and the first resistor R1 is connected to the circuit. At this time, the load in the circuit is LoadingB+R1.

[0220] Since LoadingA>LoadingB, the difference between the load of the display device in the display period and the blanking period can be reduced by setting the resistance value of the first resistor R1. The load of the display device includes the load connected to the display panel and the load connected to the display substrate.

[0221] In the embodiment of the utility model, the resistance value of the second resistor R2 is greater than or equal to 10KΩ. By setting the second resistor R2 with a larger resistance value, the influence of the shunting effect of the second resistor R2 on the current in the back-end circuit can be reduced.

[0222] In the embodiment of the present invention, when the first resistor R1 is connected to the path where the first initial voltage V1 is provided to the gate driving circuit 1130, the first resistor R1 divides the first initial voltage V1, so the voltage of the first driving voltage Vd1 is lower than the first initial voltage V1.

[0223] In the embodiment of the present invention, the load compensation process for the source driving circuit is similar to the load compensation process for the gate driving circuit, and will not be described in detail for the sake of simplicity.

[0224] Fig.12 Schematic diagram of power supply voltage according to an embodiment of the utility model.

[0225] Fig.12 The load curve shown represents the load change in the circuit during the display period and the blanking period, for example, the load in the circuit includes the load in the display panel and the load in the display substrate. The solid line curve of load Loading represents the load change in the circuit when the gate drive circuit and / or display substrate provided by the utility model drives the display panel, and the dotted line curve of load Loading can represent the load change in the circuit when the display panel is driven based on the existing gate drive circuit and / or display substrate.

[0226] Fig.12The curve of the power supply voltage V1 shown represents the change in the voltage value of the power supply voltage provided by the power line during the display period and the blanking period. For example, the power line is used to provide the power supply voltage V1. The solid line curve of the power supply voltage V1 represents the change in the voltage value of the power supply voltage provided by the power line when the display panel is driven by the gate drive circuit and / or display substrate provided by the utility model. The dotted line curve of the power supply voltage V1 can represent the change in the voltage value of the power supply voltage provided by the power line when the display panel is driven by the existing gate drive circuit and / or display substrate.

[0227] like Fig.12 As shown, the data enable signal DE in the display period P1 is at a high level, and the data enable signal DE in the blanking period P2 is at a low level. Compared with the dotted curve of load Loading, the solid curve of load Loading shows a smaller difference between the load voltages in the display period and the blanking period. Compared with the dotted curve of the power supply voltage V1, the solid curve of the power supply voltage V1 shows a smaller ripple Ripp1e.

[0228] In an embodiment of the utility model, by driving a display panel based on the gate drive circuit and / or display substrate provided by the utility model, the difference between the load of the display panel during the display period and the blanking period can be reduced, thereby improving the stability of the power supply voltage, reducing the ripple of the power supply voltage change caused by the load change, and improving the capacitor howling problem.

[0229] Fig.13A It is a schematic structural diagram of a display device according to an embodiment of the utility model.

[0230] like Fig.13A As shown, the display device 1300 a includes a display panel 1310 and a display substrate 1320 .

[0231] In the embodiment of the present invention, the display substrate 1320 outputs a first scan signal, a second scan signal and a data signal to the display panel 1310 .

[0232] In the embodiment of the present invention, the display substrate 1320 may be at least one of the display substrate 1000 and the display substrate 1100 described above.

[0233] Fig. 13B It is a structural schematic diagram of a display device according to another embodiment of the utility model.

[0234] like Fig. 13B As shown, the display device 1300b includes a display panel 1310 and a display substrate 1320. The display panel 1310 includes a first pixel circuit 1311 located in a non-display area and a second pixel circuit 1312 located in a display area. The display substrate 1320 is integrated with a first driving unit 1321 and a second driving unit 1322.

[0235] In the embodiment of the utility model, the first pixel circuit 1311 is electrically connected to a first driving unit 1321 in a gate driving circuit included in the display substrate 1320 , and the second pixel circuit 1312 is electrically connected to a second driving unit 1322 in a gate driving circuit included in the display substrate 1320 .

[0236] In the embodiment of the utility model, the first driving unit 1321 can refer to the first driving unit 110, the first driving unit 210, the first driving unit 310, the first driving unit 510 and the first driving unit 710 described above. The second driving unit 1322 can refer to the second driving unit 120 and the second driving unit 320 described above. For the sake of simplicity, they are not repeated here.

[0237] For example, the first pixel circuit 1311 includes M rows of virtual pixels arranged in an array. The first driving unit 1321 includes M cascaded first shift registers that output M first scanning signals to the M rows of virtual pixels, thereby realizing scanning of the M rows of virtual scanning. The second pixel circuit 1312 includes Q rows of luminous pixels arranged in an array. The second driving unit 1322 includes Q cascaded second shift registers that output Q second scanning signals to the Q rows of luminous pixels, thereby realizing scanning of the Q rows of luminous pixels.

[0238] It should be noted that Fig. 13B It is only schematically shown that the first driving unit 1321 and the second driving unit 1322 are arranged at one side of the first pixel circuit 1311 and the second pixel circuit 1312 to start scanning from one end of the first pixel circuit 1311 and the second pixel circuit 1312. The first driving unit 1321 and the second driving unit 1322 can also be arranged at both sides of the first pixel circuit 1311 and the second pixel circuit 1312 to synchronously scan from both ends of the first pixel circuit 1311 and the second pixel circuit 1312.

[0239] Fig.14 It is a flow chart of a driving method according to an embodiment of the utility model.

[0240] like Fig.14 As shown, the driving method can be applied to at least one of the gate driving circuit 100 and the gate driving circuit 300 described above.

[0241] In the embodiment of the present invention, the driving method may include operations S1410 to S1420.

[0242] In operation S1410, a first scan signal is output in a blank period through a first driving unit under the control of a clock signal and a start signal.

[0243] In operation S1420, a second scan signal is output during a display period through a second driving unit under control of the first scan signal and the clock signal.

[0244] In the embodiment of the present utility model, S1410 is similar to the operation performed by the first driving unit 110 described above, and S1420 is similar to the operation performed by the second driving unit 120 described above, which will not be repeated here.

[0245] In an embodiment of the utility model, the clock signal may include 2N clock signals, the first levels of the 2N clock signals are shifted and output in sequence, the nth clock signal and the n+Nth clock signal among the 2N clock signals are not at the first level at the same time, the first level is a high level, n is a positive integer, N≥n≥1.

[0246] In an embodiment of the utility model, operation S1410 outputs a first scanning signal during a blanking period through the first driving unit under the control of the clock signal and the start signal, including: under the control of the start signal and the first N clock signals of the 2N clock signals, outputting N first scanning signals through the first N stages of the cascaded M first shift registers included in the first driving circuit.

[0247] Those skilled in the art may also set the first level to a low level and the second level to a high level accordingly according to the type of transistors in the shift register.

[0248] In the embodiment of the utility model, under the control of the start signal from the start end, the first N stages of first shift registers among the cascaded M first shift registers output N first scanning signals.

[0249] In an embodiment of the utility model, the first timing change of the start signal is consistent with the second timing change of the start signal, wherein the first timing change is the timing change of the start signal during the period when the level of the first clock signal in the blanking period is maintained at the first level for the first time, and the second timing change is the timing change of the start signal during the period when the level of the first clock signal in the blanking period is maintained at the first level for the (M / (2N))+1th time.

[0250] In the embodiment of the present invention, in the blanking period, when the first clock signal changes from the first level to the second level for the M / (2N)th time, the start signal changes from the second level to the first level.

[0251] In an embodiment of the utility model, during the display time period, when the first clock signal changes from the second level to the first level for the first time, the start signal changes from the second level to the first level, and the duration of the first level of the start signal is (MN) / N times the duration of the first level of the first clock signal in one scanning cycle.

[0252] Fig.15 is a flow chart of a driving method according to another embodiment of the utility model.

[0253] like Fig.15 As shown, the driving method may be applied to at least one of the display substrate 1000 and the display substrate 1100 described above.

[0254] In the embodiment of the present invention, the driving method may include operations S1510 to S1520.

[0255] In operation S1510, under the control of a data enable signal, a first initial voltage is compensated and a first driving voltage is output.

[0256] In operation S1520, under the control of the first driving voltage, a first scan signal and a second scan signal are output.

[0257] In the embodiment of the present invention, operations S1510 to S1520 are similar to the operations performed by the display substrate 1000 and the display substrate 1100 described above, and are not described in detail herein.

[0258] In an embodiment of the utility model, during the display period, the data enable signal has a first level; during the blanking period, the data enable signal has a second level; the voltage value of the first driving voltage output based on the data enable signal with the second level is less than the voltage value of the first driving voltage output based on the data enable signal with the first level.

[0259] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the utility model. In this regard, each box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the above-mentioned module, program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flow chart, and the combination of the boxes in the block diagram or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0260] It will be understood by those skilled in the art that the features described in the various embodiments and / or claims of the present invention may be combined and / or combined in various ways, even if such combinations and / or combinations are not explicitly described in the present invention. In particular, the features described in the various embodiments and / or claims of the present invention may be combined and / or combined in various ways without departing from the spirit and teachings of the present invention. All of these combinations and / or combinations fall within the scope of the present invention.

[0261] The embodiments of the present invention are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present invention. Although the embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage. The scope of the present invention is defined by the attached claims and their equivalents. Without departing from the scope of the present invention, a person skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A gate drive circuit, characterized in that: include: a first driving unit, electrically connected to the clock terminal, the first driving unit being configured to output a first scanning signal in a blanking period under the control of a clock signal from the clock terminal and a start signal from the start terminal; as well as The second driving unit is electrically connected to the clock terminal, and is configured to output a second scanning signal in a display period under the control of the first scanning signal and the clock signal.

2. The gate driving circuit according to claim 1, characterized in that: The clock end includes 2N clock ends, and the first driving unit is electrically connected to the 2N clock ends; The first driving unit comprises M cascaded first shift registers, the first input end of the mth stage first shift register is electrically connected to the starting end, N≥m≥1, M is an integer multiple of 2N, and m, N and M are all positive integers.

3. The gate driving circuit according to claim 2, characterized in that: The first input terminal of the mth-level first shift register is electrically connected to the output terminal of the mNth-level first shift register, the first reset terminal of the mth-level first shift register is electrically connected to the output terminal of the m+Nth-level first shift register, the second reset terminal of the mth-level first shift register is electrically connected to the output terminal of the m+N+1th-level first shift register, MN>m>N.

4. The driving circuit according to claim 2, characterized in that: The first reset terminal of the mth level first shift register is electrically connected to the output terminal of the m-M+Nth level first shift register, and the second reset terminal of the mth level first shift register is electrically connected to the output terminal of the m-M+N+1th level first shift register, M≥m≥M-N+1 and M≥4N.

5. The gate driving circuit according to claim 2, characterized in that: The second input terminal of the mth stage first shift register is electrically connected to the output terminal of the m+MNth stage first shift register, N≥m≥1 and M≥4N.

6. The gate driving circuit according to claim 2, characterized in that: The second driving unit is electrically connected to the 2N clock terminals; Wherein, the second driving unit includes Q cascaded second shift registers, the output end of the m-th first shift register is electrically connected to the first reset end of the m+QN-th second shift register, the output end of the m-th first shift register is electrically connected to the second reset end of the m+QN-1-th second shift register, N≥m≥1, Q>N, and Q is a positive integer.

7. The gate driving circuit according to claim 2, characterized in that: The second driving unit includes Q second shift registers connected in cascade; The first input terminal of the m-th stage first shift register is electrically connected to the output terminal of the m+QN-th stage second shift register, N≥m≥1.

8. The gate driving circuit according to claim 7, characterized in that: The third input terminal of the m-th stage first shift register is electrically connected to the starting terminal, N≥m≥1.

9. The gate driving circuit according to claim 8, characterized in that: The qth stage second shift register in the cascaded Q second shift registers comprises a shift register unit, Q≥q≥1, q is a positive integer; as well as The m-th stage first shift register comprises the shift register unit, a first transistor and a second transistor, N≥m≥1; Wherein, the shift register unit of the m-th stage first shift register is electrically connected to the first power supply, the second power supply, the third power supply, the first input terminal, the first reset terminal, the second reset terminal and the output terminal; The control electrode of the first transistor is electrically connected to the third input terminal, the first electrode of the first transistor is electrically connected to the shift register unit, and the second electrode of the first transistor is electrically connected to a third power supply; The control electrode and the first electrode of the second transistor are electrically connected to the second input terminal, and the first electrode of the second transistor is electrically connected to the first electrode of the first transistor.

10. The gate driving circuit according to claim 9, characterized in that: The m-th stage first shift register includes the shift register unit, M≥m>N.

11. The gate driving circuit according to claim 2, characterized in that: The first timing change of the start signal is consistent with the second timing change of the start signal; Among them, the first timing change is the timing change of the starting signal during the period when the level of the first clock signal among the 2N clock signals in the blanking period is maintained at the first level for the first time, and the second timing change is the timing change of the starting signal during the period when the level of the first clock signal in the blanking period is maintained at the first level for the (M / (2N))+1th time.

12. The gate driving circuit according to claim 11, wherein: In the blanking period, when the first clock signal changes from the first level to the second level for the M / (2N)th time, the start signal changes from the second level to the first level.

13. The gate driving circuit according to claim 2, wherein: During the display time period, when the first clock signal among the 2N clock signals changes from the second level to the first level for the first time, the start signal changes from the second level to the first level, and the duration of the first level of the start signal is (MN) / N times the duration of the first level of the first clock signal in one scanning cycle.

14. A display substrate, characterized in that: include: A timing control circuit is configured to output a data enable signal; a compensation circuit configured to compensate the first initial voltage and output a first driving voltage under the control of the data enable signal; as well as The gate driving circuit according to any one of claims 1 to 13 is configured to output a first scanning signal and a second scanning signal under the control of the first driving voltage.

15. The display substrate according to claim 14, characterized in that: The display substrate further comprises: The source driving circuit is configured to output a data signal under the control of a second driving voltage, wherein the second driving voltage is determined by the compensation circuit based on the second initial voltage.

16. The display substrate according to claim 14, characterized in that: The compensation circuit includes a first resistor, a second resistor, a first switch tube and a second switch tube; wherein the first end of the first resistor is electrically connected to the first end of the second resistor, and the second end of the first resistor is electrically connected to the gate driving circuit; The second end of the second resistor is electrically connected to the control electrode of the first switch tube; A first electrode of the first switch tube is electrically connected to a first end of the first resistor, and a second electrode of the first switch tube is electrically connected to a second end of the first resistor; and The control electrode of the second switch tube is electrically connected to the timing control circuit, the first electrode of the second switch tube is electrically connected to the first end of the first resistor, and the second electrode of the second switch tube is electrically connected to a fourth power supply.

17. A display device, characterized in that: include: Display panel; as well as The display substrate according to any one of claims 14 to 16, configured to output a first scanning signal, a second scanning signal and a data signal to the display panel.

18. The display device according to claim 17, characterized in that: The display panel includes a first pixel circuit located in a non-display area and a second pixel circuit located in a display area; The first pixel circuit is electrically connected to a first driving unit in a gate driving circuit included in the display substrate, and the second pixel circuit is electrically connected to a second driving unit in a gate driving circuit included in the display substrate.

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