Display panel

Abstract

A display panel includes: an element layer including a light emitting element; and a circuit layer including: a first transistor connected between the first driving voltage line and the light emitting element and operating according to a potential of a first node; a second transistor connected between the data line and a second node; a third transistor connected between the first transistor and the first node; a first capacitor electrode connected to the first node; a second capacitor electrode connected to the second node and facing the first capacitor electrode to form a first capacitor; a third capacitor electrode facing the second capacitor electrode to form a second capacitor and connected to the first driving voltage line; a first bridge electrode electrically connecting the first capacitor electrode and the third transistor; and a second bridge electrode electrically connecting the second capacitor electrode and the second transistor.

Description

Technical Field

[0001] Aspects of some embodiments of the present disclosure described herein relate to display panels. Background Art

[0002] Among display devices, an emissive display device displays images using a light emitting diode that generates light through recombination of electrons and holes. An emissive display device generally has a relatively high response speed and can be driven with relatively low power consumption.

[0003] An emissive display device generally includes a display panel in which pixels connected to data lines and scan lines are arranged. Generally, each of the pixels includes a light emitting diode and a pixel circuit for controlling the amount of current flowing to the light emitting diode. In response to a data signal, the pixel circuit controls the amount of current flowing from a first drive voltage line to a second drive voltage line via the light emitting diode. At this time, light with a set brightness or a predetermined brightness can be generated depending on the amount of current flowing through the light emitting diode.

[0004] The above information disclosed in this Background section is only for enhancement of understanding of the background technology and therefore, the information discussed in this Background section does not necessarily constitute prior art. Utility Model Content

[0005] Aspects of some embodiments of the present disclosure described herein relate to a display panel, and, for example, to a display panel having a relatively high resolution.

[0006] Aspects of some embodiments of the present disclosure include a display panel applied to a display device having a relatively high resolution and operating in a variable frequency mode.

[0007] According to some embodiments, a display panel includes: an element layer including a light emitting element; and a circuit layer including a pixel circuit connected to the light emitting element.

[0008] According to some embodiments, the circuit layer includes: a first transistor, connected between a first driving voltage line and a light-emitting element and operating depending on the potential of a first node; a second transistor, connected between a data line and a second node; a third transistor, connected between the first transistor and the first node; a first capacitor electrode, connected to the first node; a second capacitor electrode, connected to the second node, and facing the first capacitor electrode to form a first capacitor; a third capacitor electrode, facing the second capacitor electrode to form a second capacitor, and connected to the first driving voltage line; a first bridge electrode, electrically connecting the first capacitor electrode and the third transistor; and a second bridge electrode, electrically connecting the second capacitor electrode and the second transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects and features according to embodiments of the present disclosure will become more apparent by describing aspects of some embodiments of the present disclosure in more detail with reference to the accompanying drawings.

[0010] Figure 1 is a block diagram of a display device according to some embodiments of the present disclosure.

[0011] Figure 2A is a circuit diagram of a pixel according to some embodiments of the present disclosure.

[0012] Figure 2B is a circuit diagram of a pixel according to some embodiments of the present disclosure.

[0013] Figure 2C is a timing diagram for illustrating the operation of a pixel according to some embodiments of the present disclosure.

[0014] Figure 3A is a timing diagram for illustrating a display device operating at a first driving frequency in a variable frequency mode according to some embodiments of the present disclosure.

[0015] Figure 3B is a timing diagram for illustrating a display device operating at a second driving frequency in a variable frequency mode according to some embodiments of the present disclosure.

[0016] Figure 4 is a cross-sectional view of a display panel according to some embodiments of the present disclosure.

[0017] FIG. 5A to FIG. 5G is a plan view illustrating the layout of layers stacked in a display panel according to some embodiments of the present disclosure.

[0018] Figure 6 is a plan view illustrating the arrangement of voltage lines and pixel circuits according to some embodiments of the present disclosure.

[0019] Figure 7 is a plan view illustrating a layout of horizontal voltage lines and vertical voltage lines according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0020] In this specification, when a component (or region, layer, part, etc.) is referred to as being "on," "connected to" or "coupled to" another component, this means that the component may be directly on, directly connected to or directly coupled to the other component, or a third component may exist between them.

[0021] The same reference numerals refer to the same components. In addition, in the drawings, the thickness, proportion and size of the components are exaggerated for effective description. As used herein, the term "and / or" includes all combinations in one or more combinations defined by the relevant components.

[0022] Terms such as first and second etc. can be used to describe various components, but the components should not be limited by the terms. Terms can be used only to distinguish one component from other components. For example, without departing from the scope of the present disclosure, a first component can be referred to as a second component, and similarly, a second component can also be referred to as a first component. Unless otherwise specified, a term in the singular form can include a plural form.

[0023] In addition, terms such as "below", "under", "above", and "over" are used to describe the relationship of components illustrated in the drawings. The terms are relative concepts and are described based on the directions illustrated in the drawings.

[0024] It should be understood that when used herein, terms such as “includes,” “comprising,” and “having” specify the presence of stated features, quantities, steps, operations, components, parts, or a combination thereof, but do not exclude the presence or addition of one or more other features, quantities, steps, operations, components, parts, or a combination thereof.

[0025] Unless otherwise defined, all terms (including technical or scientific terms) used in this article have the same meaning as those generally understood by those skilled in the art to which the present disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having the same meaning as the context in the relevant technical field, and should not be interpreted as having an ideal or overly formal meaning unless explicitly defined as having such a meaning in this application.

[0026] Hereinafter, aspects of some embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0027] Figure 1 is a block diagram of a display device according to some embodiments of the present disclosure.

[0028] refer to Figure 1 , the display device DD can be activated according to the electrical signal and can display an image. The display device DD can be applied to electronic devices such as smart watches, tablet computers, notebook computers, computers, or smart TVs.

[0029] The display device DD includes a display panel DP and a panel driver PDD driving the display panel DP. According to some embodiments of the present disclosure, the panel driver PDD may include a driving controller 100, a data driver 200, a scan driver 300, a light emitting driver 350, and a voltage generator 400.

[0030] The driving controller 100 receives the image signal RGB and the control signal CTRL and generates the image data DATA by converting the data format of the image signal RGB according to the interface specification with the data driver 200. The driving controller 100 outputs the scanning control signal SCS, the data control signal DCS and the emission driving control signal ECS.

[0031] The data driver 200 receives a data control signal DCS and image data DATA from the driving controller 100. The data driver 200 converts the image data DATA into data signals and outputs the data signals to a plurality of data lines DL1 to DLm to be described below. The data signals are analog data voltages corresponding to grayscale values ​​of the image data DATA.

[0032] The voltage generator 400 generates voltages required for the operation of the display panel DP. According to some embodiments of the present disclosure, the voltage generator 400 generates a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT, and a second initialization voltage AINT. The first initialization voltage VINT and the second initialization voltage AINT may have different voltage levels. According to some embodiments of the present disclosure, the voltage generator 400 may additionally generate a bias voltage Vbias (reference voltage VBIAS) supplied to the display panel DP. Figure 2A ).

[0033] The scan driver 300 receives a scan control signal SCS from the drive controller 100. The scan control signal SCS may include a start signal and a plurality of clock signals to start the operation of the scan driver 300. The scan driver 300 generates a plurality of scan signals and sequentially outputs the plurality of scan signals to scan lines to be described below. The light emitting driver 350 may output a light emitting control signal to light emitting control lines EML1 to EMLn to be described below in response to a light emitting drive control signal ECS from the drive controller 100. According to some embodiments, the scan driver 300 and the light emitting driver 350 may be integrated into one circuit.

[0034] The scan driver 300 outputs initialization scan signals to the initialization scan lines GIL1 to GILn of the display panel DP, and outputs compensation scan signals to the compensation scan lines GCL1 to GCLn of the display panel DP. The scan driver 300 outputs write scan signals to the write scan lines GWL1 to GWLn of the display panel DP, and outputs black scan signals to the black scan lines GBL1 to GBLn of the display panel DP.

[0035] The display panel DP includes initialization scan lines GIL1 to GILn, compensation scan lines GCL1 to GCLn, write scan lines GWL1 to GWLn, black scan lines GBL1 to GBLn, light emission control lines EML1 to EMLn, data lines DL1 to DLm, and pixels PX. The display panel DP has a display area DA and a non-display area NDA defined therein. The initialization scan lines GIL1 to GILn, the compensation scan lines GCL1 to GCLn, the write scan lines GWL1 to GWLn, the black scan lines GBL1 to GBLn, the light emission control lines EML1 to EMLn, the data lines DL1 to DLm, and the pixels PX may be located in the display area DA. The initialization scan lines GIL1 to GILn, the compensation scan lines GCL1 to GCLn, the write scan lines GWL1 to GWLn, the black scan lines GBL1 to GBLn, and the light emission control lines EML1 to EMLn extend in the first direction DR1 and are arranged in the second direction DR2 so as to be spaced apart from each other. The data lines DL1 to DLm extend in the second direction DR2 and are arranged in the first direction DR1 to be spaced apart from each other.

[0036] The scan driver 300 and the light emitting driver 350 may be located in the non-display area NDA of the display panel DP. According to some embodiments of the present disclosure, the scan driver 300 is located at or adjacent to a first side of the display area DA, and the light emitting driver 350 is located adjacent to a second side of the display area DA opposite to the first side. Figure 1 In the illustrated embodiment, the scan driver 300 and the light emitting driver 350 are located at opposite sides of the display area DA, but the embodiments of the present disclosure are not limited thereto. For example, the scan driver 300 and the light emitting driver 350 may be located adjacent to one of the first side and the second side of the display panel DP.

[0037] The plurality of pixels PX are electrically connected to initialization scan lines GIL1 to GILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn, black scan lines GBL1 to GBLn, emission control lines EML1 to EMLn, and data lines DL1 to DLm, respectively. Each of the plurality of pixels PX may be electrically connected to four scan lines and one emission control line. For example, Figure 1As illustrated in FIG. 1 , the first row of pixels may be connected to the first initialization scan line GIL1, the first compensation scan line GCL1, the first write scan line GWL1, the first black scan line GBL1, and the first emission control line EML1. In addition, the second row of pixels may be connected to the second initialization scan line GIL2, the second compensation scan line GCL2, the second write scan line GWL2, the second black scan line GBL2, and the second emission control line EML2. However, this is not limited thereto, and the number of scan lines and the number of emission control lines connected to each pixel PX may be changed.

[0038] Each of the plurality of pixels PX includes a light emitting element ED (refer to Figure 2A ) and a pixel circuit unit (or pixel circuit) PXC (reference Figure 2A ). The pixel circuit unit PXC may include one or more transistors and one or more capacitors. The scan driver 300 and the light emitting driver 350 may be directly formed in the non-display area NDA of the display panel DP by the same process as the transistors of the pixel circuit unit PXC.

[0039] Each of the plurality of pixels PX receives the first driving voltage ELVDD, the second driving voltage ELVSS, and the first and second initialization voltages VINT and AINT from the voltage generator 400. Alternatively, each of the plurality of pixels PX may additionally receive a bias voltage Vbias from the voltage generator 400.

[0040] Figure 2A and Figure 2B is a circuit diagram of a pixel according to an embodiment of the present disclosure, and Figure 2C is a timing diagram for illustrating the operation of a pixel according to some embodiments of the present disclosure.

[0041] Figure 1 The pixel PX illustrated in FIG. 1 may have the same configuration. Figure 2A and Figure 2B The configuration of one pixel PXij or PXij_a among the pixels PX is described, and description of the configurations of the remaining pixels will be omitted.

[0042] refer to Figure 2A , the pixel PXij is connected to Figure 1 The j-th initialization scan line GILj among the initialization scan lines GIL1 to GILn, the j-th compensation scan line GCLj among the compensation scan lines GCL1 to GCLn, the j-th write scan line GWLj among the write scan lines GWL1 to GWLn, and the j-th black scan line GBLj among the black scan lines GBL1 to GBLn are shown in FIG. In addition, the pixel PXij is connected to Figure 1The i-th data line DLi among the data lines DL1 to DLm illustrated in FIG. 8 is connected to the j-th light emitting control line EMLj among the light emitting control lines EML1 to EMLn.

[0043] refer to Figure 2A , the pixel PXij according to some embodiments includes a pixel circuit unit PXC and a light emitting element ED. According to some embodiments of the present disclosure, the pixel circuit unit PXC may include ten transistors and two capacitors. Hereinafter, the ten transistors are referred to as the first transistor to the tenth transistor T1, T2, T3, T4, T5, T6, T7, T8, T9 and T10, and the two capacitors are referred to as the first capacitor C1 and the second capacitor C2. The embodiments according to the present disclosure are not limited to the above-mentioned components, and according to some embodiments, the pixel circuit unit PXC may include additional components or fewer components without departing from the spirit and scope of the embodiments according to the present disclosure.

[0044] According to some embodiments, each of the first to tenth transistors T1 to T10 is a P-type transistor having a low temperature polycrystalline silicon (LTPS) semiconductor layer. Alternatively, each of the first to tenth transistors T1 to T10 may be an N-type transistor. In another case, at least one of the first to tenth transistors T1 to T10 may be an N-type transistor, and the remaining transistors may be P-type transistors. At least one of the first to tenth transistors T1 to T10 may be a transistor having an oxide semiconductor layer. For example, some of the first to tenth transistors T1 to T10 may be oxide semiconductor transistors, and the remaining transistors may be LTPS transistors.

[0045] The circuit configuration of the pixel PXij according to some embodiments of the present disclosure is not limited to Figure 2A The circuit structure shown in the figure. Figure 2A The pixel PXij illustrated in FIG. 1 is merely illustrative, and various changes and modifications may be made to the circuit configuration of the pixel PXij.

[0046] The jth initialization scan line GILj supplies the jth initialization scan signal GIj (or the first scan signal) to the pixel PXij. The jth write scan line GWLj supplies the jth write scan signal GWj to the pixel PXij, and the jth compensation scan line GCLj supplies the jth compensation scan signal GCj (or the second scan signal) to the pixel PXij. The jth emission control line EMLj supplies the jth emission control signal EMj to the pixel PXij, and the i-th data line DLi transmits the i-th data voltage Vdata to the pixel PXij. The i-th data voltage Vdata may have a value similar to that input to the display device DD (reference Figure 1 )'s voltage level corresponding to the image data DATA.

[0047] The pixel PXij may be connected to a first driving voltage line VL1, a second driving voltage line VL2, a first initialization voltage line VIL, a second initialization voltage line AVIL, and a bias voltage line VBL.

[0048] The first driving voltage line VL1 will Figure 1 1 and 2. The first driving voltage ELVDD supplied by the voltage generator 400 shown in the figure is transmitted to the pixel PXij, and the second driving voltage line VL2 transmits the second driving voltage ELVSS supplied from the voltage generator 400 to the pixel PXij. The first initialization voltage line VIL and the second initialization voltage line AVIL receive the first initialization voltage VINT and the second initialization voltage AINT from the voltage generator 400, respectively, and transmit the first initialization voltage VINT and the second initialization voltage AINT to the pixel PXij, respectively. The bias voltage line VBL receives the bias voltage Vbias from the voltage generator 400, and transmits the bias voltage Vbias to the pixel PXij.

[0049] Each of the first to tenth transistors T1 to T10 may include an input electrode (or source electrode), an output electrode (or drain electrode), and a control electrode (or gate electrode). In this specification, for convenience, the input electrode, the output electrode, and the control electrode may be referred to as a first electrode, a second electrode, and a third electrode, respectively.

[0050] The first transistor T1 (or referred to as a driving transistor) may be provided between the first driving voltage line VL1 and the light emitting element ED. For example, the first transistor T1 includes a first electrode electrically connected to the first driving voltage line VL1, a second electrode electrically connected to the light emitting element ED, and a third electrode connected to the first node N1. The first transistor T1 may receive a first driving voltage ELVDD through the first driving voltage line VL1. The first electrode of the first transistor T1 may be connected to the first driving voltage line VL1 via an eighth transistor T8, and the second electrode of the first transistor T1 may be electrically connected to the anode of the light emitting element ED via a sixth transistor T6.

[0051] The second transistor T2 may be connected between the i-th data line DLi and the second node N2. For example, the second transistor T2 includes a first electrode connected to the i-th data line DLi, a second electrode connected to the second node N2, and a third electrode receiving the j-th write scan signal GWj through the j-th write scan line GWLj. Figure 2C), the second transistor T2 is turned on in response to the jth write scan signal GWj supplied to the jth write scan line GWLj. The i-th data line DLi and the second node N2 may be electrically connected by the turned-on second transistor T2, and the i-th data voltage Vdata applied to the i-th data line DLi may be applied to the second node N2 through the turned-on second transistor T2. The data write period AP5 may be referred to as a fifth activation period AP5.

[0052] The first capacitor C1 is connected between the first node N1 and the second node N2, and the second capacitor C2 is connected between the second node N2 and the first driving voltage line VL1. The first capacitor C1 includes a first electrode electrically connected to the first node N1 and a second electrode electrically connected to the second node N2. The second capacitor C2 includes a first electrode electrically connected to the first driving voltage line VL1 and a second electrode electrically connected to the second node N2.

[0053] The third transistor T3 is connected between the second electrode of the first transistor T1 and the third electrode of the first transistor T1. For example, the third transistor T3 includes a first electrode electrically connected to the second electrode of the first transistor T1, a second electrode electrically connected to the first node N1, and a third electrode receiving the jth compensation scan signal GCj through the jth compensation scan line GCLj. Figure 2C ), the third transistor T3 is turned on in response to the jth compensation scan signal GCj supplied to the jth compensation scan line GCLj. During the compensation periods AP3 and AP4, the first transistor T1 may be diode-connected by the turned-on third transistor T3. The compensation periods AP3 and AP4 may include a third activation period AP3 and a fourth activation period AP4.

[0054] The fourth transistor T4 (or referred to as the first initialization transistor) is electrically connected between the first node N1 and the first initialization voltage line VIL. For example, the fourth transistor T4 includes a first electrode electrically connected to the first node N1, a second electrode electrically connected to the first initialization voltage line VIL, and a third electrode receiving the jth initialization scan signal GIj through the jth initialization scan line GILj. The first initialization voltage VINT may be applied to the first initialization voltage line VIL. During the initialization periods AP1 and AP2 (reference Figure 2C ), the fourth transistor T4 is turned on in response to the jth initialization scan signal GIj supplied to the jth initialization scan line GILj. During the initialization periods AP1 and AP2, the first node N1 may be initialized to the first initialization voltage VINT by the turned-on fourth transistor T4. The initialization periods AP1 and AP2 may include a first activation period AP1 and a second activation period AP2.

[0055] The fifth transistor T5 may be electrically connected between the second node N2 and the first driving voltage line VL1. The fifth transistor T5 includes a first electrode connected to the first driving voltage line VL1, a second electrode electrically connected to the second node N2, and a third electrode receiving the jth compensation scan signal GCj through the jth compensation scan line GCLj. During the compensation periods AP3 and AP4, the fifth transistor T5 is turned on in response to the jth compensation scan signal GCj provided to the jth compensation scan line GCLj. The first driving voltage line VL1 and the second node N2 are electrically connected by the turned-on fifth transistor T5. That is, during the compensation periods AP3 and AP4, the first driving voltage ELVDD may be applied to the second node N2.

[0056] According to some embodiments of the present disclosure, the third electrode of the third transistor T3 and the third electrode of the fifth transistor T5 are commonly connected to the j-th compensation scan line GCLj. However, the embodiments of the present disclosure are not limited thereto. That is, the third electrode of the third transistor T3 and the third electrode of the fifth transistor T5 can be connected to different scan lines and can receive different scan signals.

[0057] The sixth transistor T6 (or referred to as the first light emission control transistor) is connected between the second electrode of the first transistor T1 and the anode of the light emitting element ED. For example, the sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode electrically connected to the anode of the light emitting element ED, and a third electrode electrically connected to the j-th light emission control line EMLj. During the non-light emission period NEP, the sixth transistor T6 may be turned on by the j-th light emission control signal EMj provided to the j-th light emission control line EMLj.

[0058] The seventh transistor T7 (or referred to as the second initialization transistor) is connected between the second initialization voltage line AVIL and the anode of the light emitting element ED. The seventh transistor T7 includes a first electrode connected to the anode of the light emitting element ED, a second electrode connected to the second initialization voltage line AVIL, and a third electrode receiving the jth black scan signal GBj (or referred to as the initialization control signal) through the jth black scan line GBLj. The second initialization voltage AINT may be applied to the second initialization voltage line AVIL. According to some embodiments of the present disclosure, the second initialization voltage AINT has a voltage level different from the voltage level of the first initialization voltage VINT. During the black period AP6 (reference Figure 2C), the seventh transistor T7 is turned on in response to the jth black scan signal GBj provided to the jth black scan line GBLj. During the black period AP6, the anode of the light emitting element ED may be initialized to the second initialization voltage AINT by the turned-on seventh transistor T7. Alternatively, the third electrode of the seventh transistor T7 may be connected to the j+1th write scan line and may receive the j+1th write scan signal as the jth black scan signal GBj. The black period AP6 may be referred to as the sixth activation period AP6.

[0059] The eighth transistor T8 (or referred to as the first light emission control transistor) may be electrically connected between the first transistor T1 and the first driving voltage line VL1. For example, the eighth transistor T8 includes a first electrode electrically connected to the first driving voltage line VL1, a second electrode electrically connected to the first electrode of the first transistor T1, and a third electrode receiving the jth light emission control signal EMj through the jth light emission control line EMLj. During the non-light emission period NEP, the eighth transistor T8 may be turned on by the jth light emission control signal EMj provided to the jth light emission control line EMLj.

[0060] The ninth transistor T9 may be electrically connected between the first transistor T1 and the bias voltage line VBL. For example, the ninth transistor T9 includes a first electrode electrically connected to the bias voltage line VBL, a second electrode electrically connected to the first electrode of the first transistor T1, and a third electrode receiving the jth black scan signal GBj through the jth black scan line GBLj. During the black period AP6, the ninth transistor T9 is turned on in response to the jth black scan signal GBj provided to the jth black scan line GBLj. During the black period AP6, the bias voltage Vbias may be applied to the first electrode of the first transistor T1 through the turned-on ninth transistor T9.

[0061] The tenth transistor T10 may be electrically connected between the first transistor T1 and the first driving voltage line VL1. For example, the tenth transistor T10 includes a first electrode electrically connected to the first driving voltage line VL1, a second electrode electrically connected to the first electrode of the first transistor T1, and a third electrode receiving the jth compensation scan signal GCj through the jth compensation scan line GCLj. The third electrode of the tenth transistor T10 and the third electrode of the fifth transistor T5 are commonly connected to the jth compensation scan line GCLj. During the compensation periods AP3 and AP4, the tenth transistor T10 is turned on in response to the jth compensation scan signal GCj provided to the jth compensation scan line GCLj. The first driving voltage line VL1 and the first electrode of the first transistor T1 are electrically connected to the tenth transistor T10 to which the first electrode is turned on. That is, during the compensation periods AP3 and AP4, the first driving voltage ELVDD may be applied to the first electrode of the first transistor T1.

[0062] The light emitting element ED may be electrically connected between the sixth transistor T6 and the second driving voltage line VL2. The anode of the light emitting element ED is connected to the second electrode of the sixth transistor T6, and the cathode of the light emitting element ED is connected to the second driving voltage line VL2. The second driving voltage ELVSS may be applied to the second driving voltage line VL2. The second driving voltage ELVSS has a lower level than the first driving voltage ELVDD. Accordingly, the light emitting element ED may emit light depending on a voltage corresponding to a difference between the signal transmitted through the sixth transistor T6 and the second driving voltage EVLSS.

[0063] The pixel PXij includes ten transistors T1 to T10 and two capacitors C1 and C2. The circuit area of ​​the pixel PXij can be minimized by minimizing the number of transistors in the pixel PXij. The pixel PXij is connected to four voltage lines for receiving a first drive voltage ELVDD, a second drive voltage ELVSS, a first initialization voltage VINT, and a bias voltage Vbias. In addition, the pixel PXij operates in response to four scan lines GILj, GCLj, GWLj, and GBLj and one light emitting control line EMLj. By minimizing the number of voltage lines, scan lines, and light emitting control lines connected to the pixel PXij, the area occupied by the pixel circuit unit PXC can be reduced, and therefore, the resolution of the display panel DP can be improved.

[0064] refer to Figure 2B , according to some embodiments, the pixel PXij_a includes a pixel circuit unit PXCa and a light emitting element ED. According to some embodiments of the present disclosure, the pixel circuit unit PXCa may include ten transistors and two capacitors. Hereinafter, the ten transistors are referred to as the first transistor to the tenth transistor T1, T2a, T3a, T4a, T5a, T6, T7, T8, T9 and T10, and the two capacitors are referred to as the first capacitor C1 and the second capacitor C2. The pixel circuit unit PXCa may further include at least one node capacitor. According to some embodiments of the present disclosure, the pixel circuit unit PXCa includes four node capacitors. However, the number of node capacitors is not particularly limited. Hereinafter, the four node capacitors are referred to as the first node capacitor to the fourth node capacitor NC1, NC2, NC3 and NC4.

[0065] According to some embodiments of the present disclosure, among the first transistor T1 to the tenth transistor T10, at least one transistor may have a structure including a plurality of sub-transistors connected in series (e.g., a dual-transistor structure). When at least one of the first transistor T1 to the tenth transistor T10 has a dual-transistor structure, leakage current during the cut-off period may be reduced. Alternatively, at least one of the first transistor T1 to the tenth transistor T10 may have a dual-gate structure including two third electrodes (i.e., gate electrodes).

[0066] The fifth transistor T5a may include a plurality of first sub-transistors connected in series between the first driving voltage line VL1 and the second node N2. Figure 2B Two first sub-transistors are illustrated in FIG, but the number of the first sub-transistors is not particularly limited. The two first sub-transistors may be referred to as the fifth-first transistor T5-1 and the fifth-second transistor T5-2. The node to which the fifth-first transistor T5-1 and the fifth-second transistor T5-2 are coupled may be referred to as the first intermediate node CN1. The fifth-first transistor T5-1 is connected between the first driving voltage line VL1 and the first intermediate node CN1, and the fifth-second transistor T5-2 is connected between the first intermediate node CN1 and the second node N2. The fifth-first transistor T5-1 includes a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first intermediate node CN1, and a third electrode connected to the j-th compensation scan line GCLj. The fifth-second transistor T5-2 includes a first electrode connected to the first intermediate node CN1, a second electrode connected to the second node N2, and a third electrode connected to the j-th compensation scan line GCLj.

[0067] The first node capacitor NC1 may be connected to the first intermediate node CN1. For example, the first node capacitor electrode NCE1 (reference Figure 5B ) may have a shape extending from the first electrode of the fifth-second transistor T5-2.

[0068] The third transistor T3a may include a plurality of second sub-transistors connected in series between the second electrode of the first transistor T1 and the first node N1. Figure 2BTwo second sub-transistors are illustrated in the figure, but the number of the second sub-transistors is not particularly limited. The two second sub-transistors may be referred to as the third-first transistor T3-1 and the third-second transistor T3-2. The node to which the third-first transistor T3-1 and the third-second transistor T3-2 are coupled may be referred to as the second intermediate node CN2. The third-first transistor T3-1 is connected between the second electrode of the first transistor T1 and the second intermediate node CN2, and the third-second transistor T3-2 is connected between the second intermediate node CN2 and the first node N1. The third-first transistor T3-1 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the second intermediate node CN2, and a third electrode connected to the j-th compensation scan line GCLj. The third-second transistor T3-2 includes a first electrode connected to the second intermediate node CN2, a second electrode connected to the first node N1, and a third electrode connected to the j-th compensation scan line GCLj.

[0069] The second node capacitor NC2 may be connected to the second intermediate node CN2. For example, the second node capacitor electrode NCE2 (reference Figure 5B ) may have a shape extending from the first electrode of the third-second transistor T3-2.

[0070] The second transistor T2a may include a plurality of third sub-transistors connected in series between the i-th data line DLi and the second node N2. Figure 2B Two third sub-transistors are illustrated in the figure, but the number of the third sub-transistors is not particularly limited. The two third sub-transistors may be referred to as the second-first transistor T2-1 and the second-second transistor T2-2. The node to which the second-first transistor T2-1 and the second-second transistor T2-2 are coupled may be referred to as the third intermediate node CN3. The second-first transistor T2-1 is connected between the i-th data line DLi and the third intermediate node CN3, and the second-second transistor T2-2 is connected between the third intermediate node CN3 and the second node N2. The second-first transistor T2-1 includes a first electrode connected to the i-th data line DLi, a second electrode connected to the third intermediate node CN3, and a third electrode connected to the j-th write scan line GWLj. The second-second transistor T2-2 includes a first electrode connected to the third intermediate node CN3, a second electrode connected to the second node N2, and a third electrode connected to the j-th write scan line GWLj.

[0071] The third node capacitor NC3 may be connected to the third intermediate node CN3. For example, the third node capacitor electrode NCE3 (reference Figure 5B ) may have a shape extending from the first electrode of the second-second transistor T2-2.

[0072] The fourth transistor T4a may include a plurality of fourth sub-transistors connected in series between the first initialization voltage line VIL and the first node N1. Figure 2B , two fourth sub-transistors are illustrated, but the number of the fourth sub-transistors is not particularly limited. The two fourth sub-transistors may be referred to as the fourth-first transistor T4-1 and the fourth-second transistor T4-2. The node to which the fourth-first transistor T4-1 and the fourth-second transistor T4-2 are coupled may be referred to as the fourth intermediate node CN4. The fourth-first transistor T4-1 is connected between the first node N1 and the fourth intermediate node CN4, and the fourth-second transistor T4-2 is connected between the fourth intermediate node CN4 and the first initialization voltage line VIL. The fourth-first transistor T4-1 includes a first electrode connected to the first node N1, a second electrode connected to the fourth intermediate node CN4, and a third electrode connected to the j-th initialization scan line GILj. The fourth-second transistor T4-2 includes a first electrode connected to the fourth intermediate node CN4, a second electrode connected to the initialization voltage line VIL, and a third electrode connected to the j-th initialization scan line GILj.

[0073] The fourth node capacitor NC4 may be connected to the fourth intermediate node CN4. For example, the fourth node capacitor electrode NCE4 (reference Figure 5B ) may have a shape extending from the first electrode of the fourth-second transistor T4-2.

[0074] As described above, by additionally forming a node capacitor at the middle node of a transistor having a dual-transistor structure, the leakage current blocking effect of the corresponding transistor can be further improved.

[0075] Although only Figure 2C The j-th scan signals GIj, GCj, GWj, and GBj and the j-th light emitting control signal EMj are illustrated in FIG. 1 , but the remaining scan signals and the remaining light emitting control signals also operate similarly, and thus, a detailed description thereof will be omitted.

[0076] refer to FIG. 2A to FIG. 2C , the jth light emitting control signal EMj includes a non-light emitting period NEP. According to some embodiments of the present disclosure, the non-light emitting period NEP may be defined as an inactive period (i.e., a high level period) of the jth light emitting control signal EMj. The low level period of the jth light emitting control signal EMj may be defined as a light emitting period.

[0077] The jth initialization scan signal GIj may have a first activation period AP1 and a second activation period AP2 (i.e., a low level period) during the non-light emitting period NEP. The jth initialization scan signal GIj is supplied to the fourth transistor T4 through the jth initialization scan line GILj, and the fourth transistor T4 is turned on during the first activation period AP1 and the second activation period AP2 in which the jth initialization scan signal GIj is activated. During the first activation period AP1 and the second activation period AP2, the potential of the first node N1 may be initialized to the first initialization voltage VINT by the turned-on fourth transistor T4. That is, since the jth initialization scan signal GIj includes two activation periods AP1 and AP2, the first node N1 may be initialized twice within the non-light emitting period NEP. Each of the first activation period AP1 and the second activation period AP2 may be defined as an initialization period. The number of activation periods generated in the non-light emitting period NEP of the jth initialization scan signal GIj is not particularly limited.

[0078] Among the j-th scan signals GIj, GCj, GWj, and GBj, the j-th compensation scan signal GCj may have the third and fourth activation periods AP3 and AP4 during the non-emission period NEP.

[0079] When the j-th compensation scan signal GCj is supplied to the third transistor T3, the fifth transistor T5 and the tenth transistor T10 through the j-th compensation scan line GCLj, the third transistor T3, the fifth transistor T5 and the tenth transistor T10 are turned on in the third activation period AP3 and the fourth activation period AP4. The first transistor T1 is diode-connected by the turned-on third transistor T3 and is forward biased. Then, the compensation voltage "ELVDD-Vth" obtained by subtracting the threshold voltage Vth of the first transistor T1 from the first driving voltage ELVDD may be applied to the first node N1. That is, the potential of the first node N1 may be compensated by the compensation voltage "ELVDD-Vth" in the third activation period AP3 and the fourth activation period AP4. During the third activation period AP3 and the fourth activation period AP4, the first driving voltage ELVDD is applied to the second node N2 through the turned-on fifth transistor T5, and the first driving voltage ELVDD is applied to the first electrode of the first transistor T1 through the turned-on tenth transistor T10.

[0080] The third activation period AP3 and the fourth activation period AP4 may be defined as a compensation period. The duration of each of the third activation period AP3 and the fourth activation period AP4 may be equal to the duration of each of the first activation period AP1 and the second activation period AP2.

[0081] Among the jth scan signals GIj, GCj, GWj, and GBj, the jth write scan signal GWj may have a fifth activation period AP5 during the non-emission period NEP, and the jth black scan signal GBj may have a sixth activation period AP6 during the non-emission period NEP.

[0082] The jth write scan signal GWj is supplied to the second transistor T2 through the jth write scan line GWLj, and the second transistor T2 is turned on in the fifth activation period AP5. The i-th data voltage Vdata may be applied to the second node N2 through the turned-on second transistor T2. Then, the potential of the second node N2 is changed from the first drive voltage ELVDD to the i-th data voltage Vdata. The change amount (Vdata-ELVDD) of the voltage of the second node N2 may be transmitted to the first node N1 through the coupling of the first capacitor C1. Since the voltage of the first node N1 in the third activation period AP3 and the fourth activation period AP4 is "ELVDD-Vth", the voltage of the first node N1 in the fifth activation period AP5 is changed to "ELVDD-Vth+(Vdata-ELVDD)". The fifth activation period AP5 may be referred to as a data write period in which a voltage corresponding to the i-th data voltage Vdata is stored in the first capacitor C1.

[0083] The jth black scan signal GBj is supplied to the seventh transistor T7 and the ninth transistor T9 through the jth black scan line GBLj, and the seventh transistor T7 and the ninth transistor T9 are turned on during the sixth activation period AP6. During the sixth activation period AP6, the second initialization voltage AINT may be applied to the anode of the light emitting element ED through the turned-on seventh transistor T7. Then, the anode of the light emitting element ED may be initialized to the second initialization voltage AINT. In addition, during the sixth activation period AP6, the bias voltage Vbias may be applied to the first electrode of the first transistor T1 through the turned-on ninth transistor T9. As described above, by providing the bias voltage Vbias to the first electrode of the first transistor T1, the hysteresis effect depending on the change of the threshold voltage (Vth) characteristic of the first transistor T1 can be minimized.

[0084] The sixth activation period AP6 may be referred to as a black period. The duration of the sixth activation period AP6 may be greater than the duration of the fifth activation period AP5. Alternatively, the sixth activation period AP6 may include a plurality of sub-activation periods, and the duration of each of the sub-activation periods may be equal to the duration of the fifth activation period AP5.

[0085] The duration of each of the first to fourth activation periods AP1 to AP4 may be greater than or equal to the duration of each of the fifth and sixth activation periods AP5 and AP6. Figure 2C An example is illustrated in which the duration of each of the first to fourth activation periods AP1 to AP4 is four times the duration of the fifth activation period AP5, but the embodiments of the present disclosure are not limited thereto. Alternatively, the duration of each of the first to fourth activation periods AP1 to AP4 may be two or three times the duration of the fifth activation period AP5.

[0086] Figure 3A is a timing diagram for illustrating a display device operating at a first driving frequency in a variable frequency mode according to some embodiments of the present disclosure, and Figure 3B is a timing diagram for illustrating a display device operating at a second driving frequency in a variable frequency mode according to some embodiments of the present disclosure.

[0087] refer to Figure 1 , Figure 3A and Figure 3B , the display device DD may operate in a normal frequency mode (or first mode) in which the driving frequency is fixed (i.e., not changed), or may operate in a variable frequency mode (or second mode) in which the driving frequency is changed. In the variable frequency mode, the driving frequency may be changed depending on the frame rate. Figure 3A The diagram shows a case where the display device DD operates at a first driving frequency in a variable frequency mode, and Figure 3B The diagram shows a case where the display device DD operates at a second driving frequency in a variable frequency mode. According to some embodiments of the present disclosure, the first driving frequency may be the highest driving frequency at which the display device DD can operate. For example, the first driving frequency may be 240 Hz or 480 Hz. The first driving frequency may be referred to as a reference frequency or a maximum frequency. The second driving frequency may be a frequency lower than the first driving frequency. According to some embodiments of the present disclosure, the second driving frequency may be a frequency corresponding to one of the compensation frequencies preset in the panel driver PDD (e.g., the drive controller 100).

[0088] like Figure 1 and Figure 3AAs illustrated in FIG. 1 , when the display device DD operates at a first driving frequency in a variable frequency mode, the scan signals GIj, GCj, GWj, and GBj and the light emitting control signal EMj may be activated within a first driving frame DF1. According to some embodiments of the present disclosure, an activation period in which each of the scan signals GIj, GCj, GWj, and GBj and the light emitting control signal EMj is activated may be defined as a low level period, and a non-activation period in which each of the scan signals GIj, GCj, GWj, and GBj and the light emitting control signal EMj is deactivated may be defined as a high level period. According to some embodiments of the present disclosure, the first driving frame DF1 may include a first write frame WF1. The first write frame WF1 may include a first cycle segment CYP1 and a second cycle segment CYP2.

[0089] Among the scan signals GIj, GCj, GWj and GBj, the scan signals GIj, GCj and GWj may be activated only in the first cycle segment CYP1, and may be maintained in a deactivated state in the second cycle segment CYP2. According to some embodiments of the present disclosure, the black scan signal GBj and the light emitting control signal EMj may be activated in the first cycle segment CYP1 and the second cycle segment CYP2. The jth initialization scan signal GIj, the jth compensation scan signal GCj and the jth write scan signal GWj may be activated only in the first cycle segment CYP1. That is, the jth black scan signal GBj and the jth light emitting control signal EMj are activated in units of one cycle segment, and the jth initialization scan signal GIj, the jth compensation scan signal GCj and the jth write scan signal GWj are activated in units of one first write frame WF1. Accordingly, the frequency of the jth black scan signal GBj and the frequency of the jth light emitting control signal EMj may be greater than the frequency of the jth initialization scan signal GIj, the frequency of the jth compensation scan signal GCj and the frequency of the jth write scan signal GWj.

[0090] like Figure 1 , Figure 2B and Figure 3B As shown in FIG. 2 , the display device DD may be operated at a second driving frequency different from the first driving frequency in a variable frequency mode. According to some embodiments of the present disclosure, the second driving frequency may be a frequency lower than the first driving frequency. For example, the second driving frequency may be about 48 Hz or about 96 Hz. When the display device DD is operated at the second driving frequency, the scanning signals GIj, GCj, GWj and GBj and the light emitting control signal EMj may be activated within the second driving frame DF2.

[0091] According to some embodiments of the present disclosure, the second drive frame DF2 may include a second write frame WF2 and at least one hold frame HF2. The duration of the second write frame WF2 may be equal to the duration of the first write frame WF1. The duration of the hold frame HF2 may be equal to the duration of the second write frame WF2. The number of hold frames HF2 included in the second drive frame DF2 may vary depending on the size of the second drive frequency.

[0092] Among the scan signals GIj, GCj, GWj and GBj, the scan signals GIj, GCj and GWj may be activated only in the second write frame WF2, and may be maintained in a deactivated state in the hold frame HF2. The second write frame WF2 may include a first cycle segment CYP1 and a second cycle segment CYP2. The hold frame HF2 may include a first hold cycle segment HCYP1 and a second hold cycle segment HCYP2. According to some embodiments of the present disclosure, each of the first hold cycle segment HCYP1 and the second hold cycle segment HCYP2 may have the same duration as the first cycle segment CYP1 and the second cycle segment CYP2.

[0093] Among the scan signals GIj, GCj, GWj and GBj, the scan signals GIj, GCj and GWj may be activated only in the first cycle segment CYP1 of the second write frame WF2, and remain in the deactivated state in the second cycle segment CYP2. The jth black scan signal GBj and the jth light emission control signal EMj may be activated within the second write frame WF2 and the hold frame HF2. That is, the jth black scan signal GBj and the jth light emission control signal EMj are activated in units of one cycle segment, and the jth initialization scan signal GIj, the jth compensation scan signal GCj and the jth write scan signal GWj are activated in units of one second write frame WF2. Accordingly, the frequency of the jth black scan signal GBj and the frequency of the jth light emission control signal EMj may be greater than the frequency of the jth initialization scan signal GIj, the frequency of the jth compensation scan signal GCj and the frequency of the jth write scan signal GWj.

[0094] Figure 4 is a cross-sectional view of a display panel according to some embodiments of the present disclosure.

[0095] refer to Figure 4 , the display panel DP may include a base layer BL, a circuit layer DP_CL and an element layer DP_ED.

[0096] The base layer BL may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. For example, the synthetic resin layer may be a polyimide resin layer, and its material is not particularly limited. The synthetic resin layer may include at least one of acrylic resin, methacrylic resin, polyisoprene resin, vinyl resin, epoxy resin, polyurethane resin, cellulose resin, siloxane resin, polyamide resin, and perylene resin. In addition, the base layer BL may include a glass substrate, a metal substrate, or an organic / inorganic composite substrate.

[0097] At least one inorganic layer may be formed on the upper surface of the base layer BL. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed of a plurality of layers. A plurality of inorganic layers may constitute a barrier layer and / or a buffer layer. The barrier layer and the buffer layer may be selectively arranged.

[0098] The barrier layer prevents penetration of foreign matter from the outside. The barrier layer may include a silicon oxide layer and a silicon nitride layer. A plurality of silicon oxide layers and a plurality of silicon nitride layers may be provided. The silicon oxide layers and the silicon nitride layers may be alternately stacked on each other.

[0099] The buffer layer may be located on the barrier layer. The buffer layer improves the coupling force between the base layer and the semiconductor pattern and / or the conductive pattern. The buffer layer may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked on each other. The barrier layer and the buffer layer may be omitted.

[0100] The circuit layer DP_CL is located on the base layer BL. The circuit layer DP_CL includes first to third semiconductor patterns located on the base layer BL. The first to third semiconductor patterns may include silicon semiconductors. The first to third semiconductor patterns may include polycrystalline silicon. However, not limited thereto, the first to third semiconductor patterns may include amorphous silicon or oxide semiconductors.

[0101] The first to third semiconductor patterns have different electrical characteristics depending on whether the first to third semiconductor patterns are doped. Each of the first to third semiconductor patterns may include a doped region and an undoped region. The doped region may be doped with an N-type dopant or a P-type dopant. The P-type transistor includes a doped region doped with a P-type dopant, and the N-type transistor includes a doped region doped with an N-type dopant.

[0102] The doped region has a higher conductivity than the undoped region and substantially acts as an electrode or a signal line. The undoped region substantially corresponds to a channel portion of a transistor. In other words, a portion of each of the first to third semiconductor patterns may be a channel portion of a transistor, another portion may be a source or drain of the transistor, and another portion may be a connection signal line (or a connection electrode).

[0103] like Figure 4 As shown in FIG. 1 , the first electrode S1, the channel portion A1, and the second electrode D1 of the first transistor T1 are formed by the first semiconductor pattern. The first electrode S1 and the second electrode D1 of the first transistor T1 extend from the channel portion A1 in opposite directions. The first electrode S2, the channel portion A2, and the second electrode D2 of the second transistor T2 are formed by the second semiconductor pattern. The first electrode S2 and the second electrode D2 of the second transistor T2 extend from the channel portion A2 in opposite directions. The first electrode S3, the channel portion A3, and the second electrode D3 of the third transistor T3 are formed by the third semiconductor pattern. The first electrode S3 and the second electrode D3 of the third transistor T3 extend from the channel portion A3 in opposite directions. The first electrode S3 of the third transistor T3 and the second electrode D1 of the first transistor T1 may be formed integrally with each other.

[0104] The first insulating layer 10 (or gate insulating layer) is located on the base layer BL. The first insulating layer 10 overlaps with the plurality of pixels PX together and covers the first semiconductor pattern to the third semiconductor pattern. The first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. According to some embodiments, the first insulating layer 10 may be a single silicon oxide layer. Not only the first insulating layer 10 but also the insulating layer of the circuit layer DP_CL to be described below may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of the above materials.

[0105] The third electrode G1 of the first transistor T1, the third electrode G2 of the second transistor T2, and the third electrode G3 of the third transistor T3 are located on the first insulating layer 10. The third electrode G1 of the first transistor T1 overlaps with the channel portion A1 of the first transistor T1, the third electrode G2 of the second transistor T2 overlaps with the channel portion A2 of the second transistor T2, and the third electrode G3 of the third transistor T3 overlaps with the channel portion A3 of the third transistor T3.

[0106] The first capacitor electrode CE1 is additionally located on the first insulating layer 10. The first capacitor electrode CE1 may extend from the third electrode G1 of the first transistor T1 and may be integrally formed with the third electrode G1 of the first transistor T1. The third electrode G1 of the first transistor T1 and the first capacitor electrode CE1 may be Figure 5B A portion of the first gate pattern layer 120 is shown in FIG.

[0107] The second insulating layer 20 covering the third electrode G1 of the first transistor T1 and the first capacitor electrode CE1 is located on the first insulating layer 10. The second insulating layer 20 overlaps with the plurality of pixels PX in common. The second insulating layer 20 may be an inorganic layer and / or an organic layer and may have a single layer structure or a multilayer structure. According to some embodiments, the second insulating layer 20 may be a single silicon oxide layer.

[0108] The second capacitor electrode CE2 may be located on the second insulating layer 20. The second capacitor electrode CE2 faces the first capacitor electrode CE1 with the second insulating layer 20 between the first capacitor electrode CE1 and the second capacitor electrode CE2 to form the first capacitor C1. The second capacitor electrode CE2 may be Figure 5C A portion of the second gate pattern layer 130 is shown in FIG.

[0109] The third insulating layer 30 covering the second capacitor electrode CE2 is located on the second insulating layer 20. According to some embodiments, the third insulating layer 30 may be a single silicon oxide layer.

[0110] The third capacitor electrode CE3 of the second capacitor C2 may be located on the third insulating layer 30. The third capacitor electrode CE3 faces the second capacitor electrode CE2 with the third insulating layer 30 between the second capacitor electrode CE2 and the third capacitor electrode CE3 to form the second capacitor C2. The third capacitor electrode CE3 may be Figure 5D A portion of the additional pattern layer 135 is illustrated in FIG. In this cross section, the first capacitor C1 may be located between the second capacitor C2 and the first transistor T1.

[0111] The first bridge electrode BE1 and the second bridge electrode BE2 are located on the fourth insulating layer 40. The first bridge electrode BE1 may be an electrode connecting the third electrode G1 (or the first capacitor electrode CE1) of the first transistor T1 and the second electrode D3 of the third transistor T3. The first bridge electrode BE1 is connected to the third electrode G1 (or the first capacitor electrode CE1) of the first transistor T1 through a contact hole penetrating the second insulating layer to the fourth insulating layer 20, 30 and 40. In addition, the first bridge electrode BE1 is connected to the second electrode D3 of the third transistor T3 through a contact hole penetrating the first insulating layer to the fourth insulating layer 10, 20, 30 and 40. The second bridge electrode BE2 may be an electrode connecting the second capacitor electrode CE2 and the second electrode D2 of the second transistor T2. The second bridge electrode BE2 is connected to the second capacitor electrode CE2 through a contact hole penetrating the third insulating layer 30 and the fourth insulating layer 40, and is connected to the second electrode D2 of the second transistor T2 through a contact hole penetrating the first insulating layer to the fourth insulating layer 10, 20, 30 and 40. In the present disclosure, the first bridge electrode BE1 may be connected to Figure 2A The second bridge electrode BE2 may correspond to the first node N1 shown in FIG. Figure 2A Corresponding to the second node N2 shown in FIG.

[0112] The first connection electrode CNE1 and the second connection electrode CNE2 are additionally disposed on the fourth insulating layer 40. The first connection electrode CNE1 is an electrode for connecting the third capacitor electrode CE3 to the first driving voltage line VL1. The second connection electrode CNE2 is an electrode for connecting the first electrode S2 of the second transistor T2 to the data line (ie, the i-th data line DLi).

[0113] The first connection electrode CNE1 is connected to the third capacitor electrode CE3 through a contact hole penetrating the fourth insulating layer 40 , and the second connection electrode CNE2 is connected to the first electrode S2 of the second transistor T2 through a contact hole penetrating the first to fourth insulating layers 10 , 20 , 30 and 40 .

[0114] The first and second bridge electrodes BE1 and BE2 and the first and second connection electrodes CNE1 and CNE2 may be Figure 5E A portion of the first data pattern layer 140 is shown in FIG.

[0115] The fifth insulating layer 50 is arranged to cover the first and second bridge electrodes BE1 and BE2 and the first and second connection electrodes CNE1 and CNE2. The first driving voltage line VL1 and the data line DLi-1 (reference Fig. 5F ), DLi and DLi+1 (reference Fig. 5F ) may be located on the fifth insulating layer 50.

[0116] The first driving voltage line VL1 is connected to the first link electrode CNE1 through a contact hole formed through the fifth insulating layer 50 , and the data lines DLi- 1 , DLi, and DLi+1 are connected to the second link electrode CNE2 through a contact hole formed through the fifth insulating layer 50 .

[0117] The element connection electrode P_CNE to be connected to the light emitting element ED may be additionally located on the fifth insulating layer 50. The element connection electrode P_CNE may be connected to the anode AE ​​of the light emitting element ED. The first driving voltage line VL1, the data lines DLi-1, DLi and DLi+1, and the element connection electrode P_CNE may be Fig. 5F A portion of the second data pattern layer 150 is shown in FIG.

[0118] The sixth insulating layer 60 covering the first driving voltage line VL1 and the data lines DLi-1, DLi, and DLi+1 is located on the fifth insulating layer 50. According to some embodiments, the sixth insulating layer 60 may include a silicon oxide layer and a silicon nitride layer.

[0119] The sixth insulating layer 60 may include a plurality of silicon oxide layers and a plurality of silicon nitride layers alternately stacked on each other.

[0120] The element layer DP_ED is located on the circuit layer DP_CL. The element layer DP_ED may include a light emitting element ED and a pixel defining layer PDL. The light emitting element ED includes an anode AE, an emission layer EL, and a cathode CCE.

[0121] The pixel defining layer PDL may include an opening OP defined therein to correspond to the light emitting element ED. The opening OP exposes at least a portion of the anode AE ​​of the light emitting element ED. The opening OP of the pixel defining layer PDL may define an emission area PXA. For example, a plurality of pixels PX (refer to Figure 1 ) may be located on the display panel DP (reference Figure 1 ) plane. A region where a plurality of pixels PX are located may be defined as a pixel region, and one pixel region may include an emission region PXA and a non-emission region NPXA adjacent to the emission region PXA. The non-emission region NPXA may surround the emission region PXA.

[0122] The emission layer EL is arranged to correspond to the opening OP defined in the pixel definition layer PDL. Although a patterned emission layer EL is illustrated, the embodiments of the present disclosure are not limited thereto. A common emission layer may be arranged for a plurality of pixels PX in common. In this case, the common emission layer may generate white light or blue light.

[0123] The cathode CCE is located on the emission layer EL. The cathode CCE is commonly arranged for a plurality of pixels PX.

[0124] The display panel DP may further include an encapsulation layer that seals the element layer DP_ED. The encapsulation layer may include at least one organic layer and at least one inorganic layer. The inorganic layer may include an inorganic material and may protect the element layer DP_ED from moisture / oxygen. The inorganic layer may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, but is not particularly limited thereto. The organic layer may include an organic material and may protect the element layer DP_ED from foreign matter such as dust particles.

[0125] FIG. 5A to FIG. 5G is a plan view illustrating the layout of layers stacked in a display panel. For example, Figure 5A is a plan view illustrating a semiconductor pattern layer located on a base layer, and Figure 5B is a plan view illustrating a first gate pattern layer located on a base layer and a semiconductor pattern layer. Figure 5C is a plan view illustrating a second gate pattern layer located on the first gate pattern layer, and Figure 5D is a plan view illustrating an additional pattern layer located on the second gate pattern layer. Figure 5E is a plan view illustrating a first data pattern layer located on an additional pattern layer, and Fig. 5F is a plan view illustrating a second data pattern layer located on the first data pattern layer. Figure 5G is a plan view illustrating an anode electrode layer located on the second data pattern layer.

[0126] refer to Figure 4 and Figure 5A , the semiconductor pattern and the conductive pattern may be repeatedly arranged on the base layer BL according to a rule (eg, a set rule or a predetermined rule). FIG. 5A to FIG. 5G The figure shows three pixel circuit units PXCa (refer to Figure 2B )’s floor plan.

[0127] refer to Figure 5A , a semiconductor pattern layer 110 is illustrated. The semiconductor pattern layer 110 may be located on the base layer BL. The semiconductor pattern layer 110 may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon or polycrystalline silicon. For example, the semiconductor pattern layer 110 may include low temperature polycrystalline silicon (LTPS).

[0128] The semiconductor pattern layer 110 includes semiconductor patterns of transistors (ie, first to tenth transistors T1 to T10 ) included in each pixel circuit unit PXCa.

[0129] refer to Figure 4 and Figure 5B, the first insulating layer 10 may be located on the semiconductor pattern layer 110, and the first gate pattern layer 120 may be located on the first insulating layer 10. The first gate pattern layer 120 may be a layer formed by subjecting the first gate metal layer to patterning. The first gate pattern layer 120 may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material. For example, the first gate pattern layer 120 may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), indium tin oxide (ITO), or indium zinc oxide (IZO), but is not particularly limited thereto.

[0130] The first gate pattern layer 120 may include a plurality of gate patterns GP1, GP2, GP3, GP4, and GP5 to form third electrodes of transistors (i.e., first to tenth transistors T1 to T10) included in each pixel circuit unit PXCa. The first to tenth transistors T1 to T10 may be formed in each pixel circuit unit PXCa by the plurality of gate patterns GP1, GP2, GP3, GP4, and GP5 and the semiconductor pattern layer 110.

[0131] The first gate pattern layer 120 further includes a first node capacitor electrode NCE1, a second node capacitor electrode NCE2, a third node capacitor electrode NCE3, and a fourth node capacitor electrode NCE4. The first node capacitor electrode NCE1 extends from the fifth-first transistor T5-1 and the fifth-second transistor T5-2, and defines Figure 2B The second node capacitor electrode NCE2 extends from the third-first transistor T3-1 and the third-second transistor T3-2 and defines Figure 2B The third node capacitor electrode NCE3 extends from the second-first transistor T2-1 and the second-second transistor T2-2, and defines Figure 2B The fourth node capacitor electrode NCE4 extends from the fourth-first transistor T4-1 and the fourth-second transistor T4-2, and defines Figure 2B The fourth intermediate node CN4 is shown in FIG.

[0132] The first to fourth node capacitor electrodes NCE1 , NCE2 , NCE3 , and NCE4 are provided at the same layer as the first capacitor electrode CE1 .

[0133] The first gate pattern layer 120 further includes a first capacitor electrode CE1 and a j-th black scan line GBLj. The first capacitor electrode CE1 is an electrode for forming a first capacitor C1 included in each pixel circuit unit PXCa. The j-th black scan line GBLj may be connected to a third electrode G7 of a seventh transistor T7 and a third electrode G9 of a ninth transistor T9 included in each pixel circuit unit PXCa.

[0134] refer to Figure 4 and Figure 5C , the second insulating layer 20 may be located on the first insulating layer 10 to cover the first gate pattern layer 120. The second gate pattern layer 130 may be located on the second insulating layer 20. The second gate pattern layer 130 may be a layer formed by subjecting the second gate metal layer to patterning. The second gate pattern layer 130 may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material.

[0135] The second gate pattern layer 130 may include a second capacitor electrode CE2. The second capacitor electrode CE2 is arranged to overlap the first capacitor electrode CE1 on a plane. The first capacitor C1 may be formed in each pixel circuit unit PXCa by the first capacitor electrode CE1 and the second capacitor electrode CE2.

[0136] The second gate pattern layer 130 further includes a first common node capacitor electrode C_NCE1 and a second common node capacitor electrode C_NCE2. The first common node capacitor electrode C_NCE1 may overlap the first node capacitor electrode NCE1 and the second node capacitor electrode NCE2. The first common node capacitor electrode C_NCE1 faces the first node capacitor electrode NCE1 and the second insulating layer 20 is between the first common node capacitor electrode C_NCE1 and the first node capacitor electrode NCE1 to form a first node capacitor NC1 (reference Figure 2B ), and facing the second node capacitor electrode NCE2 with the second insulating layer 20 between the first common node capacitor electrode C_NCE1 and the second node capacitor electrode NCE2 to form the second node capacitor NC2 (reference Figure 2B ). The second common node capacitor electrode C_NCE2 may overlap the third node capacitor electrode NCE3 and the fourth node capacitor electrode NCE4 collectively. The second common node capacitor electrode C_NCE2 faces the third node capacitor electrode NCE3 with the second insulating layer 20 between the second common node capacitor electrode C_NCE2 and the third node capacitor electrode NCE3 to form a third node capacitor NC3 (reference Figure 2B), and facing the fourth node capacitor electrode NCE4 with the second insulating layer 20 between the second common node capacitor electrode C_NCE2 and the fourth node capacitor electrode NCE4 to form a fourth node capacitor NC4 (reference Figure 2B ). According to some embodiments of the present disclosure, the first common node capacitor electrode C_NCE1 may have a floating state.

[0137] The second gate pattern layer 130 may further include a first horizontal initialization voltage line H_VIL extending in the first direction DR1. The first horizontal initialization voltage line H_VIL may be included in Figure 2A and Figure 2B . The first initialization voltage line VIL illustrated in FIG. The first initialization voltage VINT may be applied to the first horizontal initialization voltage line H_VIL. According to some embodiments of the present disclosure, the first horizontal initialization voltage line H_VIL may be integrally formed with the second common node capacitor electrode C_NCE2. A portion of the first horizontal initialization voltage line H_VIL may be used as the second common node capacitor electrode C_NCE2. Accordingly, one end of the first node capacitor NC1 and one end of the second node capacitor NC2 may be connected to the first horizontal initialization voltage line H_VIL and may receive the first initialization voltage VINT.

[0138] refer to Figure 4 and Figure 5D , the third insulating layer 30 may be located on the second insulating layer 20 to cover the second gate pattern layer 130. The additional pattern layer 135 may be located on the third insulating layer 30. The additional pattern layer 135 may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material.

[0139] The additional pattern layer 135 may include a third capacitor electrode CE3. The third capacitor electrode CE3 is arranged to overlap with the second capacitor electrode CE2 on a plane. The second capacitor C2 may be formed in each pixel circuit unit PXCa by the second capacitor electrode CE2 and the third capacitor electrode CE3. The first capacitor electrode CE1 to the third capacitor electrode CE3 may overlap with the first transistor T1 on a plane. Since the first transistor T1 occupying the largest area in each pixel circuit unit PXCa and the first capacitor C1 and the second capacitor C2 are arranged to overlap with each other on a plane, it is possible to reduce the total area of ​​each pixel circuit unit PXCa while ensuring that the capacitance of the first capacitor C1 and the capacitance of the second capacitor C2 are the largest. Accordingly, more pixel circuit units PXCa may be formed in a display panel DP having a given size, and therefore, the resolution of the display panel DP may be improved.

[0140] The additional pattern layer 135 may further include a plurality of repair lines RPL extending in the first direction DR1. The plurality of repair lines RPL may be provided to repair the display panel DP (refer to FIG. 1 ). Figure 1 ) provided in the non-display area NDA (reference area NDA). For example, when one of the scan line and the light emitting control line is disconnected, two parts of the disconnected line may be connected to an adjacent, corresponding repair line RPL. Accordingly, the two parts of the disconnected line may be electrically connected through the corresponding repair line RPL. According to some embodiments of the present disclosure, the corresponding repair line RPL and the disconnected line may be connected in the non-display area NDA (reference area NDA). Figure 1 ) are connected to each other.

[0141] refer to Figure 4 and Figure 5E , the fourth insulating layer 40 may be located on the third insulating layer 30 to cover the additional pattern layer 135. The first data pattern layer 140 may be located on the fourth insulating layer 40. The first data pattern layer 140 may be a layer formed by subjecting the first data metal layer to patterning. The first data pattern layer 140 may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material.

[0142] The first data pattern layer 140 may include Figure 2B The scan lines GWLj, GCLj, and GILj and the light emitting control line EMLj are illustrated in FIG. The scan lines GWLj, GCLj, and GILj and the light emitting control line EMLj may extend in the first direction DR1 and may be spaced apart from each other in the second direction DR2.

[0143] The first data pattern layer 140 may further include a second-first horizontal initialization voltage line H_AVIL1, a second-second horizontal initialization voltage line H_AVIL2, and a horizontal bias voltage line H_VBL. The second-first horizontal initialization voltage line H_AVIL1, the second-second horizontal initialization voltage line H_AVIL2, and the horizontal bias voltage line H_VBL may extend in the first direction DR1 and may be spaced apart from each other in the second direction DR2.

[0144] The second-first horizontal initialization voltage line H_AVIL1 may be connected to Figure 1 At least one pixel (e.g., the second pixel) among the plurality of pixels PX illustrated in the figure, and the second-second horizontal initialization voltage line H_AVIL2 may be connected to at least one pixel (e.g., the first pixel and the third pixel) among the plurality of pixels PX. According to some embodiments of the present disclosure, the first pixel includes a first light emitting element that outputs a first color light (e.g., red light), the second pixel includes a second light emitting element that outputs a second color light (e.g., green light), and the third pixel includes a third light emitting element that outputs a third color light (e.g., blue light).

[0145] The second-first horizontal initialization voltage line H_AVIL1 and the second-second horizontal initialization voltage line H_AVIL2 may be referred to as second horizontal initialization voltage lines, and may be included in Figure 2A and Figure 2B . The second-first initialization voltage is applied to the second-first horizontal initialization voltage line H_AVIL1 as the second initialization voltage AINT, and the second-second initialization voltage is applied to the second-second horizontal initialization voltage line H_AVIL2 as the second initialization voltage AINT. The second-first initialization voltage may have a voltage level that is the same as or different from the voltage level of the second-second initialization voltage. Alternatively, the second initialization voltage line AVIL may include a second horizontal initialization voltage line. In this case, the second horizontal initialization voltage lines may be commonly connected to the first pixel to the third pixel.

[0146] The horizontal bias voltage line H_VBL may be included in Figure 2A and Figure 2B The bias voltage Vbias (reference Figure 2A ) may be applied to the horizontal bias voltage line H_VBL.

[0147] The first data pattern layer 140 may further include Figure 4 The first and second bridge electrodes BE1 and BE2 and the first and second connection electrodes CNE1 and CNE2 are shown in FIG.

[0148] The first bridge electrode BE1 may be an electrode connecting the third electrode G1 (or the first capacitor electrode CE1) of the first transistor T1 and the second electrode D3 of the third transistor T3. The first bridge electrode BE1 is connected to the third electrode G1 (or the first capacitor electrode CE1) of the first transistor T1 through a contact hole penetrating the second insulating layer to the fourth insulating layer 20, 30, and 40. In addition, the first bridge electrode BE1 is connected to the second electrode D3 of the third transistor T3 through a contact hole penetrating the first insulating layer to the fourth insulating layer 10, 20, 30, and 40.

[0149] The second bridge electrode BE2 may be an electrode connecting the second capacitor electrode CE2 and the second electrode D2 of the second transistor T2. The second bridge electrode BE2 is connected to the second capacitor electrode CE2 through a contact hole penetrating the third insulating layer 30 and the fourth insulating layer 40, and is connected to the second electrode D2 of the second transistor T2 through a contact hole penetrating the first insulating layer to the fourth insulating layer 10, 20, 30 and 40.

[0150] refer to Figure 4 , Figure 5Eand Fig. 5F , the fifth insulating layer 50 may be located on the fourth insulating layer 40 to cover the first data pattern layer 140. The second data pattern layer 150 may be located on the fifth insulating layer 50. The second data pattern layer 150 may be a layer formed by subjecting the second data metal layer to patterning. The second data pattern layer 150 may include, for example, a metal, an alloy, a conductive metal oxide, or a transparent conductive material.

[0151] The second data pattern layer 150 may include data lines DLi-1, DLi and DLi+1, a first driving voltage line VL1 and a vertical voltage line V_VL. The data lines DLi-1, DLi and DLi+1, the first driving voltage line VL1 and the vertical voltage line V_VL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1. The first driving voltage line VL1 may include a portion overlapping the third capacitor electrode CE3 on a plane. Each of the vertical voltage lines V_VL may be located between the data line DLi+1 and the first driving voltage line VL1 on a plane.

[0152] One of the vertical voltage lines V_VL may be electrically connected to the first horizontal initialization voltage line H_VIL, the second-first horizontal initialization voltage line H_AVIL1, the second-second horizontal initialization voltage line H_AVIL2, and the horizontal bias voltage line H_VBL, and may be used as the first initialization voltage line VIL (refer to Figure 2A ), the second initialization voltage line AVIL (reference Figure 2A ) and the bias voltage line VBL (reference Figure 2A ). Accordingly, each of the first initialization voltage line VIL, the second initialization voltage line AVIL, and the bias voltage line VBL may be provided in a grid shape on the display panel DP. One of the vertical voltage lines V_VL may be used as the second driving voltage line VL2 (reference Figure 2A ). The following will refer to Figure 6 and Figure 7 The vertical voltage line V_VL is described in detail.

[0153] The second data pattern layer 150 may further include an element connection electrode P_CNE. The element connection electrode P_CNE may be provided in an island shape in each pixel PX and may be connected to the anode AE ​​of the light emitting element ED included in each pixel.

[0154] refer to Figure 4 , Fig. 5F and Figure 5G, the sixth insulating layer 60 may be located on the fifth insulating layer 50 to cover the second data pattern layer 150. The anode electrode layer 160 may be located on the sixth insulating layer 60. The anode electrode layer 160 may include, for example, a metal, an alloy, a conductive metal oxide, or a transparent conductive material.

[0155] The anode electrode layer 160 may include a first anode R_AE of a first light emitting element, a second anode G_AE of a second light emitting element, and a third anode B_AE of a third light emitting element. The first light emitting element outputs a first color light (e.g., red light), the second light emitting element outputs a second color light (e.g., green light), and the third light emitting element outputs a third color light (e.g., blue light). Figure 2B The light emitting element ED illustrated in the figure may be one of the first to third light emitting elements. Each of the first to third anodes R_AE, G_AE, and B_AE may be arranged to overlap with the corresponding element connection electrode P_CNE on a plane. Each of the first to third anodes R_AE, G_AE, and B_AE may be connected to the corresponding pixel circuit unit PXCa (in Figure 2B (see figure in the figure).

[0156] The first light emitting element further includes a first emission layer R_EL on the first anode R_AE, the second light emitting element further includes a second emission layer G_EL on the second anode G_AE, and the third light emitting element further includes a third emission layer B_EL on the third anode B_AE.

[0157] Figure 6 is a plan view illustrating the arrangement of voltage lines and pixel circuit units according to some embodiments of the present disclosure, and Figure 7 is a plan view illustrating the layout of voltage lines according to some embodiments of the present disclosure.

[0158] refer to Figure 6 and Figure 7 , display panel DP (reference Figure 1) includes a plurality of circuit areas CA repeatedly arranged in a first direction DR1 and a plurality of wiring areas WA respectively defined on first sides of the plurality of circuit areas CA. At least one pixel circuit unit may be located in each of the plurality of circuit areas CA. According to some embodiments of the present disclosure, three pixel circuit units (hereinafter referred to as first to third pixel circuit units R_PD, G_PD, and B_PD) sequentially arranged in the first direction DR1 may be located in each circuit area CA. The first pixel circuit unit R_PD is included in a first pixel outputting a first color light, the second pixel circuit unit G_PD is included in a second pixel outputting a second color light, and the third pixel circuit unit B_PD is included in a third pixel outputting a third color light.

[0159] Each of the first to third pixel circuit units R_PD, G_PD, and B_PD may cross a horizontal voltage line extending in the first direction DR1. According to some embodiments of the present disclosure, the horizontal voltage line may include a first horizontal initialization voltage line H_VIL, a second-first horizontal initialization voltage line H_AVIL1, a second-second horizontal initialization voltage line H_AVIL2, and a horizontal bias voltage line H_VBL.

[0160] The first horizontal initialization voltage line H_VIL and the horizontal bias voltage line H_VBL are connected to the first to third pixel circuit units R_PD, G_PD, and B_PD. The second-first horizontal initialization voltage line H_AVIL1 is connected to the second pixel circuit unit G_PD among the first to third pixel circuit units R_PD, G_PD, and B_PD, and the second-second horizontal initialization voltage line H_AVIL2 is connected to the first pixel circuit unit R_PD and the third pixel circuit unit B_PD among the first to third pixel circuit units R_PD, G_PD, and B_PD.

[0161] A plurality of vertical voltage lines V_VL extending in a second direction DR2 intersecting the first direction DR1 are located in a plurality of wiring areas WA. One of the vertical voltage lines V_VL may be electrically connected to the first horizontal initialization voltage line H_VIL, the second-first horizontal initialization voltage line H_AVIL1, the second-second horizontal initialization voltage line H_AVIL2, and the horizontal bias voltage line H_VBL. According to some embodiments of the present disclosure, the vertical voltage line V_VL may include a first vertical initialization voltage line V_VIL, a second-first vertical initialization voltage line V_AVIL1, a second-second vertical initialization voltage line V_AVIL2, and a vertical bias voltage line V_VBL. The first vertical initialization voltage line V_VIL is connected to the first horizontal initialization voltage line H_VIL at a first contact portion VCH1, and the second-first vertical initialization voltage line V_AVIL1 is connected to the second-first horizontal initialization voltage line H_AVIL1 at a second contact portion VCH2. The second-second vertical initialization voltage line V_AVIL2 is connected to the second-second horizontal initialization voltage line H_AVIL2 at the third contact portion VCH3, and the vertical bias voltage line V_VBL is connected to the horizontal bias voltage line H_VBL at the fourth contact portion VCH4. The first to fourth contact portions VCH1, VCH2, VCH3, and VCH4 may be located in the wiring area WA.

[0162] Accordingly, the first initialization voltage line VIL may be provided in a grid shape through the first vertical initialization voltage line V_VIL and the first horizontal initialization voltage line H_VIL, and the second-first initialization voltage line AVIL1 may be provided in a grid shape through the second-first vertical initialization voltage line V_AVIL1 and the second-first horizontal initialization voltage line H_AVIL1. The second-second initialization voltage line AVIL2 may be provided in a grid shape through the second-second vertical initialization voltage line V_AVIL2 and the second-second horizontal initialization voltage line H_AVIL2. The bias voltage line VBL may be provided in a grid shape through the vertical bias voltage line V_VBL and the horizontal bias voltage line H_VBL.

[0163] One of the vertical voltage lines V_VL (hereinafter, referred to as a vertical driving voltage line V_VL2) may be used as a second driving voltage line VL2 (refer to Figure 2A ). The vertical driving voltage line V_VL2 can be connected to the non-display area NDA (reference Figure 1 Alternatively, when the second driving voltage line VL2 further includes a horizontal driving voltage line, the vertical driving voltage line V_VL2 may be connected to the horizontal driving voltage line in the wiring area WA.

[0164] According to some embodiments of the present disclosure, the vertical bias voltage line V_VBL, the second-second vertical initialization voltage line V_AVIL2, the vertical drive voltage line V_VL2, the second-first vertical initialization voltage line V_AVIL1 and the vertical initialization voltage line V_VIL may be arranged sequentially in the first direction DR1. However, the order in which the voltage lines are arranged is not particularly limited. Alternatively, the vertical bias voltage line V_VBL, the second-second vertical initialization voltage line V_AVIL2, the vertical drive voltage line V_VL2, the second-first vertical initialization voltage line V_AVIL1, the vertical initialization voltage line V_VIL and the second-second vertical initialization voltage line V_AVIL2 may be arranged in this order. In this case, in the display panel DP, the number of the second-second vertical initialization voltage lines V_AVIL2 may be greater than the number of the second-first vertical initialization voltage lines V_AVIL1.

[0165] As described above, since the voltage lines VIL, AVIL and VBL connected to the pixel circuit units R_PD, G_PD and B_PD are provided in a grid shape on the display panel DP, the brightness difference between pixels caused by the drop in the voltage applied to the voltage lines VIL, AVIL and VBL can be reduced, and therefore, the overall picture quality of the display panel DP can be improved.

[0166] According to the present disclosure, a circuit structure capable of fully ensuring the compensation time of the first transistor in a display device operating in a variable frequency mode can be provided. In addition, even if each pixel circuit unit includes ten transistors and two capacitors according to some embodiments, the resolution of the display panel can be relatively improved by effectively reducing the area occupied by each pixel circuit unit.

[0167] In addition, the voltage line connected to each pixel circuit unit can be provided in a grid shape on the display panel. Accordingly, the brightness difference between pixels caused by the drop of the voltage applied to the voltage line can be reduced, and thus, the picture quality of the display panel can be improved.

[0168] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the claims and their equivalents.

Claims

1. A display panel, comprising: A component layer, including a light-emitting component; as well as a circuit layer including a pixel circuit connected to the light emitting element, Characterized in that the circuit layer comprises: a first transistor connected between a first driving voltage line and the light emitting element and configured to operate according to a potential of a first node; a second transistor connected between the data line and the second node; a third transistor connected between the first transistor and the first node; a first capacitor electrode connected to the first node; a second capacitor electrode connected to the second node and facing the first capacitor electrode to form a first capacitor; a third capacitor electrode facing the second capacitor electrode to form a second capacitor and connected to the first driving voltage line; a first bridge electrode electrically connecting the first capacitor electrode and the third transistor; and The second bridge electrode electrically connects the second capacitor electrode and the second transistor.

2. The display panel according to claim 1, wherein: The first capacitor electrode is on the first insulating layer, wherein the second capacitor electrode is on a second insulating layer covering the first capacitor electrode, wherein the third capacitor electrode is on a third insulating layer covering the second capacitor electrode, and The first bridge electrode and the second bridge electrode are on a fourth insulating layer covering the third capacitor electrode.

3. The display panel according to claim 2, wherein: In a plan view, the first capacitor electrode, the second capacitor electrode, and the third capacitor electrode overlap with the first transistor, and Wherein, in the cross-sectional view, the first capacitor is located between the second capacitor and the first transistor.

4. The display panel according to claim 2, wherein: The circuit layer further includes a connection electrode configured to connect the third capacitor electrode and the first driving voltage line.

5. The display panel according to claim 4, wherein: The connecting electrode is on the fourth insulating layer, and The first driving voltage line is on a fifth insulating layer configured to cover the connecting electrode and the first bridge electrode and the second bridge electrode.

6. The display panel according to any one of claims 1 to 5, wherein: The circuit layer further comprises: a fourth transistor connected between the first node and a first initialization voltage line and configured to operate in response to a first scan signal; and A fifth transistor is connected between the second node and the first driving voltage line and is configured to operate in response to a second scan signal.

7. The display panel according to claim 6, wherein: The third transistor is configured to operate in response to the second scan signal, and The activation period of the first scanning signal does not overlap with the activation period of the second scanning signal.

8. The display panel according to claim 6, wherein: The fifth transistor comprises: A fifth-first transistor connected between the first driving voltage line and a first intermediate node; and a fifth-second transistor connected between the first intermediate node and the second node, and Wherein, the third transistor comprises: A third-first transistor connected between the output electrode of the first transistor and the second intermediate node; and A third-second transistor is connected between the second intermediate node and the first node.

9. The display panel according to claim 8, wherein: The circuit layer further comprises: a first node capacitor electrode configured to extend from the first intermediate node; a second node capacitor electrode configured to extend from the second intermediate node; and A first common node capacitor electrode is configured to face the first node capacitor electrode to form a first node capacitor, and is configured to face the second node capacitor electrode to form a second node capacitor.

10. The display panel according to claim 9, wherein: The first node capacitor electrode and the second node capacitor electrode are in the same layer as the first capacitor electrode, and The first common node capacitor electrode and the second capacitor electrode are in the same layer.

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