MOS abnormality detection circuit and battery management system

Abstract

The utility model discloses an MOS anomaly detection circuit and a battery management system, the MOS anomaly detection circuit comprises a current sampling circuit (1), a voltage sampling circuit (2), a current comparison circuit (3) and a voltage comparison circuit (4), the MOS anomaly detection circuit samples input current of a grid electrode of an MOS tube in a mirror image mode, and when the sampled current exceeds reference current, an anomaly detection signal is output; meanwhile, the voltage drop between the grid electrode and the source electrode of the MOS tube is sampled and compared with the reference voltage, and when the voltage drop exceeds the reference voltage, an abnormal detection signal is output; thus, whether the MOS state is abnormal or not is monitored from the two aspects of the gate current and the gate source voltage, when the MOS state is abnormal, the control circuit is triggered to close the system in time by sending the abnormal detection signal, and therefore it is guaranteed that the circuit is in a normal and safe working state.

Description

Technical Field

[0001] The utility model relates to the field of charging and discharging, in particular to a MOS abnormality detection circuit and a battery management system. Background Art

[0002] The battery management system is commonly known as the battery nanny or battery butler. It is mainly used to intelligently manage and maintain each battery unit, monitor the battery status, prevent the battery from overcharging, over-discharging, over-temperature and over-current, so as to extend the battery life. The battery management system's battery pack is equipped with a MOS tube for controlling charging and a MOS tube for controlling discharging in the external charging and discharging path of the battery pack. The MOS tube will be turned on when charging or discharging is required, and the corresponding MOS tube will be disconnected when the battery voltage, current, and temperature are detected to be abnormal. If the MOS tube is turned on or off abnormally, it is very easy to affect the safety of the system. Utility Model Content

[0003] The technical problem to be solved by the utility model is to provide a MOS abnormality detection circuit and a battery management system in view of the above-mentioned defects of the prior art.

[0004] The technical solution adopted by the utility model to solve the technical problem is: construct a MOS abnormality detection circuit, which can be applied to the battery management system to detect the abnormality of the MOS tube that controls charging or discharging in the system to be turned on or off. The MOS abnormality detection circuit includes:

[0005] A current sampling circuit is connected to the gate of the target MOS tube and is used to sample the current of the gate of the target MOS tube in a mirroring manner and output it;

[0006] A voltage sampling circuit is connected between the gate and source of the target MOS tube, and is used to sample the voltage between the gate and source of the target MOS tube and output it;

[0007] a current comparison circuit connected to the output end of the current sampling circuit, used to compare the current sampled by the current sampling circuit with a reference current, and output an abnormality detection signal to the control circuit of the battery management system when the current sampled by the current sampling circuit exceeds the reference current, so as to trigger the control circuit to shut down the system;

[0008] A voltage comparison circuit is connected to the output end of the voltage sampling circuit, and is used to compare the voltage sampled by the voltage sampling circuit with a reference voltage, and when the sampled voltage exceeds the reference voltage, output an abnormality detection signal to the control circuit of the battery management system to trigger the control circuit to shut down the system.

[0009] Furthermore, in the MOS abnormality detection circuit described in the present utility model, the voltage comparison circuit includes a first comparator and a second comparator, the same-direction input end of the first comparator and the reverse input end of the second comparator are both connected to the output end of the voltage sampling circuit, the reverse input end of the first comparator is connected to a first reference voltage corresponding to a first voltage threshold according to a voltage division ratio of the voltage sampling circuit, the same-direction input end of the second comparator is connected to a second reference voltage corresponding to a second voltage threshold according to a voltage division ratio of the voltage sampling circuit, the output end of the first comparator and the output end of the second comparator are connected to the control circuit, the control circuit responds to the output end signal of the first comparator when the target MOS tube is turned on, and responds to the output end signal of the second comparator when the target MOS tube is turned off, the first voltage threshold is greater than the turn-on threshold of the target MOS tube, and the second voltage threshold is less than the turn-on threshold of the target MOS tube.

[0010] Furthermore, in the MOS abnormality detection circuit described in the utility model, the current comparison circuit includes a trigger and a reference current source, the output end of the current sampling circuit is connected to the trigger input end of the trigger, the trigger input end of the trigger is also grounded via a current source corresponding to the reference current, and the output end of the trigger is connected to the control circuit;

[0011] The reference current is Wherein: V is the stable voltage value output by the analog front-end chip of the battery management system, and V is greater than the first voltage threshold; R0 represents the equivalent resistance of the bias resistor between the gate and source of the target MOS tube and the voltage sampling circuit in parallel, and K is a constant.

[0012] Furthermore, in the MOS abnormality detection circuit described in the present invention, a bias resistor is connected between the gate and source of the target MOS tube, and the current sampling circuit is connected to the gate of the target MOS tube and the common point of the bias resistor and the voltage sampling circuit.

[0013] Furthermore, in the MOS abnormality detection circuit described in the present utility model, the current sampling circuit includes a reference end transistor and an output end transistor, the gate of the reference end transistor and the gate of the output end transistor are connected to each other, the gate of the reference end transistor is connected to the drain of the reference end transistor, the source of the reference end transistor and the source of the output end transistor are both connected to the power supply potential, the drain of the reference end transistor is connected to the gate of the target MOS tube and the common point of the bias resistor and the voltage sampling circuit as the input end of the current sampling circuit, and the drain of the output end transistor is connected to the current comparison circuit as the output end of the current sampling circuit.

[0014] Furthermore, in the MOS abnormality detection circuit described in the present invention, the voltage sampling circuit includes an upper voltage-dividing resistor and a lower voltage-dividing resistor, the upper voltage-dividing resistor and the lower voltage-dividing resistor are connected in series between the gate and the source of the target MOS tube, and the connection node of the upper voltage-dividing resistor and the lower voltage-dividing resistor is connected to the voltage comparison circuit as the output end of the voltage sampling circuit.

[0015] In a second aspect, a battery management system is constructed, including a MOS tube for controlling charging and a MOS tube for controlling discharging, wherein the two MOS tubes are respectively configured as target MOS tubes with the MOS abnormality detection circuit as described above.

[0016] Furthermore, in the battery management system described in the utility model, the system also includes a battery pack, the control circuit, and an analog front-end chip controlled by the control circuit. The gates of the two MOS tubes are respectively connected to the two output ports of the analog front-end chip, and the two MOS tubes are connected in series in the negative output path of the battery pack.

[0017] The MOS abnormality detection circuit and battery management system of the utility model have the following beneficial effects: the utility model samples the gate input current of the charging and discharging MOS tube in a mirroring manner, and outputs an abnormality detection signal when the sampled current exceeds the reference current; at the same time, the voltage drop between the gate and the source of the MOS tube is sampled, and the voltage drop is compared with the reference voltage, and an abnormality detection signal is output when the voltage exceeds the reference voltage; in this way, the MOS state is monitored from two aspects of the gate current and the gate-source voltage to see if it is abnormal. When the MOS state is abnormal, an abnormality detection signal is generated to trigger the control circuit to shut down the system in time, thereby ensuring that the circuit is in a normal and safe working state. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below. Obviously, the drawings in the following description are only embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without creative work:

[0019] Figure 1 It is a circuit schematic diagram of the MOS abnormality detection circuit of the utility model;

[0020] Figure 2 This is a circuit schematic diagram of the battery management system of the utility model. DETAILED DESCRIPTION

[0021] In order to facilitate the understanding of the present invention, the present invention will be described more comprehensively with reference to the relevant drawings below. Typical embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solutions of the present application, rather than limitations on the technical solutions of the present application. In the absence of conflict, the embodiments of the present invention and the technical features in the embodiments can be combined with each other.

[0022] refer to Figure 1 , the MOS abnormality detection circuit of the utility model comprises:

[0023] The voltage sampling circuit 2 is connected between the gate and source of the target MOS tube, and is used to sample the voltage between the gate and source of the target MOS tube and output it;

[0024] The current sampling circuit 1 is connected to the gate of the target MOS tube and is used to sample the current of the gate of the target MOS tube in a mirroring manner and output it; specifically, a bias resistor R and a voltage sampling circuit 2 are connected between the gate and the source of the target MOS tube, and the current sampling circuit 1 is connected to the gate of the target MOS tube and the common point of the bias resistor R and the voltage sampling circuit 2.

[0025] A current comparison circuit 3 is connected to the output end of the current sampling circuit 1, and is used to compare the current sampled by the current sampling circuit 1 with a reference current, and when the current sampled by the current sampling circuit 1 exceeds the reference current, output an abnormality detection signal to the control circuit 5 of the battery management system, so as to trigger the control circuit 5 to shut down the system;

[0026] The voltage comparison circuit 4 is connected to the output end of the voltage sampling circuit 2, and is used to compare the voltage sampled by the voltage sampling circuit 2 with a reference voltage, and when the sampled voltage exceeds the reference voltage, output an abnormal detection signal to the control circuit 5 of the battery management system to trigger the control circuit 5 to shut down the system.

[0027] Specifically, the voltage sampling circuit 2 includes an upper voltage-dividing resistor R1 and a lower voltage-dividing resistor R2, the upper voltage-dividing resistor R1 and the lower voltage-dividing resistor R2 are connected in series between the gate and the source of the target MOS tube, and the connection node of the upper voltage-dividing resistor R1 and the lower voltage-dividing resistor R2 is connected to the voltage comparison circuit 4 as the output end of the voltage sampling circuit 2, so that the voltage-dividing ratio of the voltage sampling circuit 2 is R1 / (R1+R2), that is, if the voltage drop between the gate and the source of the target MOS tube is U, the sampled voltage output by the voltage sampling circuit 2 will be U*R1 / (R1+R2).

[0028] Specifically, the voltage comparison circuit 4 includes a first comparator and a second comparator, wherein the same-direction input terminal of the first comparator and the reverse input terminal of the second comparator are both connected to the connection node of the upper voltage-dividing resistor R1 and the lower voltage-dividing resistor R2, and the reverse input terminal of the first comparator is connected to the first reference voltage Vref1 corresponding to the first voltage threshold according to the voltage-dividing ratio of the voltage sampling circuit 2, that is, the first reference voltage Vref1 = the first voltage threshold * voltage-dividing ratio = the first voltage threshold * R1 / (R1+R2). The same-direction input terminal of the second comparator is connected to the second reference voltage Vref2 corresponding to the voltage-dividing ratio of the voltage sampling circuit 2 and the second voltage threshold, that is, the second reference voltage Vref2 = the second voltage threshold * voltage-dividing ratio = the second voltage threshold * R1 / (R1+R2). The output terminal of the first comparator and the output terminal of the second comparator are connected to different ports of the control circuit 5.

[0029] The control circuit 5 responds to the signal at the output end of the first comparator when the target MOS tube is turned on, and responds to the signal at the output end of the second comparator when the target MOS tube is turned off. For example, when the signal sent by the system to the gate of the target MOS tube is a signal for turning on the target MOS tube, the control circuit 5 will process the output signal of the first comparator. At this time, if the voltage between the gate and the source of the target MOS tube is less than the first voltage threshold, the first comparator outputs a low level (this low level is an abnormal detection signal), and the control circuit 5 receives this low level to know that the target MOS tube is abnormally turned on; when the signal sent by the system to the gate of the target MOS tube is a signal for turning off the target MOS tube, the control circuit 5 will process the output signal of the second comparator. At this time, if the voltage between the gate and the source of the target MOS tube is greater than the second voltage threshold, the second comparator outputs a low level (this low level is an abnormal detection signal), and the control circuit 5 receives this low level to know that the target MOS tube is abnormally turned off.

[0030] In order to reduce the on-resistance of MOS and reduce power consumption, it is necessary to ensure that MOS is fully turned on or off, the ratio of the first voltage threshold to the turn-on threshold of the target MOS tube is M, and the ratio of the second voltage threshold to the turn-on threshold of the target MOS tube is N; M is a constant, and its value range is >1, and N is a constant, and its value range is <1. For example, in a specific implementation, M is 2 and N is 0.5, which means that when the target MOS tube is turned on (turned on), it is necessary to ensure that the voltage between the gate and the source is greater than twice the turn-on threshold of the MOS tube, and when the target MOS tube is turned off, it is necessary to ensure that the voltage between the gate and the source is less than 0.5 times the turn-on threshold of the MOS tube.

[0031] It is understandable that in other embodiments, the first comparator and the second comparator may be combined, and only one comparator may be used, and the voltage given to the reference terminal of the comparator may be switched to the first reference voltage or the second reference voltage through other logic circuits.

[0032] The current sampling circuit 1 in this embodiment is a 1:1 mirror image, including a reference end transistor and an output end transistor. The gate of the reference end transistor and the gate of the output end transistor are connected to each other, the gate of the reference end transistor is connected to the drain of the reference end transistor, the source of the reference end transistor and the source of the output end transistor are both connected to the power supply potential VCC, the drain of the reference end transistor is connected to the gate of the target MOS tube and the common point of the bias resistor R and the voltage sampling circuit 2 as the input end of the current sampling circuit 1, and the drain of the output end transistor is connected to the current comparison circuit 3 as the output end of the current sampling circuit 1.

[0033] Specifically, the current comparison circuit 3 includes a trigger and a reference current source. The output end of the current sampling circuit 1 is connected to the trigger input end of the trigger. The trigger input end of the trigger is also grounded via a current source corresponding to the reference current. The output end of the trigger is connected to the control circuit 5. The reference current is Wherein: V is the stable voltage value output by the analog front-end chip, which is a voltage value that can theoretically be applied to the gate of the MOS tube to turn it on. This value varies depending on the MOS tube used. For example, in this embodiment, it is 12V, and V is greater than the first voltage threshold; R0 represents the equivalent resistance of the bias resistor R between the gate and source of the target MOS tube and the voltage sampling circuit 2 in parallel, that is, R0 = R / / (R1+R2), R1 and R2 represent the resistance values ​​of the two voltage-dividing resistors in the voltage sampling circuit 2; K is a constant. When the sampling current is greater than the reference current, the input end of the trigger is pulled high, and the trigger outputs a low level (this low level is an abnormal detection signal) to the control circuit 5, and the control circuit 5 can know that the MOS tube state is abnormal; otherwise, if the sampling current is less than the reference current, the input end of the trigger is pulled low, and the trigger will output a high level to the control circuit 5, and the control circuit 5 can know that the gate current of the MOS tube is normal.

[0034] It is understandable that in other embodiments, if the mirror ratio of the current sampling circuit 1 changes, the current of the current source also needs to be adjusted accordingly, in order to ensure that the comparison result between the mirrored current and the current source actually reflects the comparison result between the gate current of the target MOS tube and the reference current.

[0035] refer to Figure 2The MOS abnormality detection circuit of this embodiment can be applied to a battery management system to detect abnormalities in the on or off state of a MOS tube that controls charging or discharging of the system. The battery management system includes a battery pack, a control circuit 5, an analog front-end chip AFE 6 controlled by the control circuit 5, a MOS tube for controlling charging, and a MOS tube for controlling discharging. The gates of the two MOS tubes are respectively connected to the two output ports of the analog front-end chip 6. The two MOS tubes that control charging and discharging are respectively configured with a MOS abnormality detection circuit 100 as target MOS tubes. The two MOS tubes are connected in series in the negative output path of the battery pack. Specifically, the battery management system has a simulated battery positive electrode Pack+ and a simulated battery negative electrode Pack-. The positive electrode of the battery pack is directly connected to the simulated battery positive electrode Pack+, and the negative electrode of the battery pack is connected to the simulated battery negative electrode Pack- via a resistor and the two MOS tubes.

[0036] Combination Figure 1 , 2 The working principle of the embodiment of the utility model is as follows: when the MOS is required to be turned on, the voltage sampling value of the voltage sampling circuit 2 is compared with the first voltage threshold. When the voltage sampling value is higher than the first voltage threshold (2 times the MOS turn-on threshold), the MOS state is considered normal, otherwise it is abnormal; when the MOS is required to be turned off, the voltage sampling value of the voltage sampling circuit 2 is compared with the second voltage threshold. When the voltage sampling value is lower than the second voltage threshold (0.5 times the MOS turn-on threshold), the MOS turn-off state is considered normal, otherwise it is abnormal. The sampling current of the current sampling circuit 1 is compared with the reference current If the voltage is lower than the reference current, the MOS is considered to be in a normal state, otherwise it is considered to be in an abnormal state. The above voltage detection and current detection can be used to determine whether the MOS state is abnormal. When the MOS state is abnormal, the control circuit 5 can send an interrupt signal to the AFE system to shut down the system in time, thereby ensuring that the circuit is in a normal and safe working state.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0038] Terms containing ordinal numbers such as "first" and "second" used in this specification can be used to describe various constituent elements, but these constituent elements are not limited by these terms. The purpose of using these terms is only to distinguish one constituent element from other constituent elements. For example, without departing from the scope of the present invention, the first constituent element can be named as the second constituent element, and similarly, the second constituent element can also be named as the first constituent element. The "connected" or "connected" not only includes directly connecting two entities, but also indirectly connecting through other entities with beneficial improvement effects.

[0039] The embodiments of the utility model are described above in conjunction with the accompanying drawings, but the utility model is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the enlightenment of the utility model, ordinary technicians in this field can also make many forms without departing from the scope of protection of the utility model and the claims, which all fall within the protection of the utility model.

Claims

1. A MOS abnormality detection circuit can be used in a battery management system to detect abnormalities in the on or off state of a MOS tube that controls charging or discharging in the system, characterized in that: The MOS abnormality detection circuit comprises: A current sampling circuit (1), connected to the gate of the target MOS tube, for sampling the gate current of the target MOS tube in a mirroring manner and outputting the same; A voltage sampling circuit (2) is connected between the gate and source of the target MOS tube and is used to sample the voltage between the gate and source of the target MOS tube and output it; A current comparison circuit (3) connected to the output end of the current sampling circuit (1) and used to compare the current sampled by the current sampling circuit (1) with a reference current, and when the sampled current exceeds the reference current, output an abnormality detection signal to the control circuit (5) of the battery management system, so as to trigger the control circuit (5) to shut down the system; A voltage comparison circuit (4) is connected to the output end of the voltage sampling circuit (2) and is used to compare the voltage sampled by the voltage sampling circuit (2) with a reference voltage, and when the sampled voltage exceeds the reference voltage, output an abnormality detection signal to the control circuit (5) of the battery management system, so as to trigger the control circuit (5) to shut down the system.

2. The MOS abnormality detection circuit according to claim 1, characterized in that: The voltage comparison circuit (4) comprises a first comparator and a second comparator, wherein the non-inverting input end of the first comparator and the reverse input end of the second comparator are both connected to the output end of the voltage sampling circuit (2), the reverse input end of the first comparator is connected to a first reference voltage corresponding to a first voltage threshold according to a voltage division ratio of the voltage sampling circuit (2), the non-inverting input end of the second comparator is connected to a second reference voltage corresponding to a second voltage threshold according to a voltage division ratio of the voltage sampling circuit (2), the output end of the first comparator and the output end of the second comparator are connected to the control circuit (5), the control circuit (5) responds to a signal at the output end of the first comparator when the target MOS tube is turned on, and responds to a signal at the output end of the second comparator when the target MOS tube is turned off, the first voltage threshold is greater than a turn-on threshold of the target MOS tube, and the second voltage threshold is less than a turn-on threshold of the target MOS tube.

3. The MOS abnormality detection circuit according to claim 2, characterized in that: The current comparison circuit (3) comprises a trigger and a reference current source, the output end of the current sampling circuit (1) is connected to the trigger input end of the trigger, the trigger input end of the trigger is also grounded via a current source corresponding to the reference current, and the output end of the trigger is connected to the control circuit (5); The reference current is Wherein: V is the stable voltage value output by the analog front-end chip of the battery management system, and V is greater than the first voltage threshold; R0 represents the equivalent resistance value of the bias resistor (R) between the gate and source of the target MOS tube and the voltage sampling circuit (2) connected in parallel; K is a constant.

4. The MOS abnormality detection circuit according to claim 1, characterized in that: A bias resistor (R) is connected between the gate and source of the target MOS tube, and the current sampling circuit (1) is connected to the common connection point of the gate of the target MOS tube, the bias resistor (R) and the voltage sampling circuit (2).

5. The MOS abnormality detection circuit according to claim 4, characterized in that: The current sampling circuit (1) comprises a reference end transistor and an output end transistor, the gate of the reference end transistor and the gate of the output end transistor are connected to each other, the gate of the reference end transistor is connected to the drain of the reference end transistor, the source of the reference end transistor and the source of the output end transistor are both connected to a power supply potential, the drain of the reference end transistor is connected to the gate of the target MOS tube and the common point of the bias resistor (R) and the voltage sampling circuit (2) as the input end of the current sampling circuit (1), and the drain of the output end transistor is connected to the current comparison circuit (3) as the output end of the current sampling circuit (1).

6. The MOS abnormality detection circuit according to claim 1, characterized in that: The voltage sampling circuit (2) comprises an upper voltage dividing resistor (R1) and a lower voltage dividing resistor (R2), wherein the upper voltage dividing resistor (R1) and the lower voltage dividing resistor (R2) are connected in series between the gate and the source of the target MOS tube, and a connection node between the upper voltage dividing resistor (R1) and the lower voltage dividing resistor (R2) is connected to the voltage comparison circuit (4) as an output end of the voltage sampling circuit (2).

7. A battery management system, characterized in that: It comprises a MOS tube for controlling charging and a MOS tube for controlling discharging, and the two MOS tubes are respectively used as target MOS tubes and are configured with a MOS abnormality detection circuit as described in any one of claims 1 to 6.

8. The battery management system according to claim 7, characterized in that: The system further comprises a battery pack, the control circuit (5), and an analog front-end chip (6) controlled by the control circuit (5); the gate electrodes of the two MOS tubes are respectively connected to two output ports of the analog front-end chip (6); and the two MOS tubes are connected in series in a negative electrode output path of the battery pack.

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