SIP transceiver module

Abstract

The utility model provides an SIP (Session Initiation Protocol) transceiver module, which relates to the technical field of chip packaging and comprises a multilayer circuit board, at least one first tube shell and at least one second tube shell, and a plurality of circuit layers are arranged in the multilayer circuit board; the first tube shell is arranged on one side of the multi-layer circuit board, and a first chip is arranged on the first tube shell; the second tube shell is arranged on the other side of the multi-layer circuit board, and a second chip is arranged on the second tube shell; wherein the first chip is electrically connected to part of the circuit layer through the first conductive column, the second chip is electrically connected to part of the circuit layer through the second conductive column, and the first chip and the second chip are electrically connected to different circuit layers. Compared with the prior art, due to the fact that the multi-layer circuit layer is adopted and the tube shells are arranged on the two sides, the multi-channel design can be achieved, the multi-channel radio frequency circuit can be connected to different circuit layers, and interference caused by radio frequency interconnection crossing in multi-channel transmission is effectively reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of chip packaging, in particular to a SIP transceiver module. Background Art

[0002] At present, the traditional SIP transceiver module is mainly designed with a 1-layer or 3-layer ceramic shell. A ceramic shell is mainly composed of a ceramic substrate with a metal dam, a chip is pasted on the ceramic substrate, and a metal cover is covered on the ceramic shell. The shell structure of this module is simple. When the shell size is determined, the size of the chip placement is limited.

[0003] Furthermore, a three-layer tube shell structure appeared. The three-layer ceramic tube shell is mainly composed of two layers of ceramic substrates with a metal dam, and chips are bonded to these two layers of ceramic substrates. A ceramic flat plate is designed in the middle to achieve upper and lower interconnection between the two tube shells.

[0004] The above two common modules have solved the design requirements of mass production and miniaturization of most modules. However, with the requirements of multi-channel and functional integration of TR modules, the increase in the number of module layers is an inevitable trend in future designs. At the same time, traditional transceiver modules are dual-channel and quad-channel modules. When the number of channels is small, the RF routing can still meet the design requirements. However, with the design requirements of eight-channel and sixteen-channel modules, the complexity of RF routing makes traditional modules unable to meet the established requirements. The increasing complexity of RF routing also makes RF routing cross-connected with each other. Therefore, the phenomenon of crosstalk and interference between RF signals is more serious, affecting the transmission of signals. Utility Model Content

[0005] The utility model aims to provide a SIP transceiver module, which can realize multi-channel design and reduce the interference caused by radio frequency interconnection crossover in multi-channel transmission.

[0006] The embodiment of the utility model is achieved as follows:

[0007] In a first aspect, the utility model provides a SIP transceiver module, comprising:

[0008] A multi-layer circuit board, wherein multiple circuit layers are arranged in the multi-layer circuit board;

[0009] at least one first tube shell, the first tube shell being arranged on one side of the multi-layer circuit board and having a first chip arranged on the first tube shell;

[0010] at least one second tube shell, the second tube shell being arranged on the other side of the multi-layer circuit board, and a second chip being arranged on the second tube shell;

[0011] Among them, a first conductive column is arranged in the first tube shell, and the first chip is electrically connected to part of the circuit layer through the first conductive column; a second conductive column is arranged in the second tube shell, and the second chip is electrically connected to part of the circuit layer through the second conductive column, and the first chip and the second chip are electrically connected to different circuit layers.

[0012] In an optional embodiment, the first tube shell includes a first ceramic substrate and a first metal dam, the first metal dam is arranged around the first ceramic substrate and connected to the edge of the multilayer circuit board, the first chip is attached to the side surface of the first ceramic substrate close to the multilayer circuit board, the first ceramic substrate is also provided with the first conductive column, the first chip is electrically connected to the first conductive column, and the first conductive column is correspondingly bonded to the surface of the multilayer circuit board.

[0013] In an optional embodiment, a first wiring layer is provided on a surface of the first ceramic substrate close to the multilayer circuit board, the first chip is electrically connected to the first wiring layer, and the first wiring layer is electrically connected to the first conductive column.

[0014] In an optional embodiment, a first pad is disposed on a surface of the first ceramic substrate away from the multilayer circuit board, the first pad is electrically connected to the first wiring layer, and a solder ball is disposed on the first pad.

[0015] In an optional embodiment, the back side of the first chip is bonded and fixed to the surface of the first ceramic substrate, and a plurality of first pins are provided on the front side of the first chip, each of the first pins is provided with a first wire, and the first wire is connected to the first wiring layer, so that the first chip is electrically connected to the first wiring layer through the first wire.

[0016] In an optional embodiment, there are multiple second tube shells, and the multiple second tube shells are stacked. Each second tube shell is provided with a second chip, and each second tube shell is provided with multiple second conductive pillars, and each second conductive pillar is correspondingly bonded to an adjacent second tube shell.

[0017] In an optional embodiment, each of the second tube shells includes a second ceramic substrate and a second metal dam, the second ceramic substrate is spaced apart from the multilayer circuit board, the second metal dam is arranged around the second ceramic substrate and connected to the edge of the multilayer circuit board or an adjacent second ceramic substrate, the second chip is correspondingly attached to a side surface of the second ceramic substrate close to the multilayer circuit board, a plurality of second conductive pillars are also arranged on the second ceramic substrate, the second chip is electrically connected to at least one of the second conductive pillars, and the plurality of second conductive pillars are correspondingly bonded to the surface of the multilayer circuit board or an adjacent second ceramic substrate.

[0018] In an optional embodiment, a second wiring layer is provided on a side of each second ceramic substrate close to the multilayer circuit board, the second chip is electrically connected to the corresponding second wiring layer, and the second wiring layer is electrically connected to the corresponding second conductive column.

[0019] In an optional embodiment, a second pad is provided on a side of each second ceramic substrate away from the multilayer circuit board, the second pad is electrically connected to the second wiring layer, and the second conductive column is correspondingly bonded to the second pad.

[0020] In an optional embodiment, the back side of the second chip is bonded and fixed to the surface of the second ceramic substrate, and a plurality of second pins are provided on the front side of the second chip, each of the second pins is provided with a second wire, and the second wire is connected to the second wiring layer or the second conductive column, so that the second chip is electrically connected to the second wiring layer through the second wire.

[0021] The beneficial effects of the embodiments of the utility model include:

[0022] The SIP transceiver module provided by the embodiment of the utility model uses a multi-layer circuit board provided with multiple circuit layers, a first tube shell is provided on one side of the multi-layer circuit board, and a second tube shell is provided on the other side, a first chip is provided on the first tube shell, and a second chip is provided on the second tube shell, the first chip is connected to part of the circuit layer through the first conductive column in the first tube shell, and the second chip is connected to part of the circuit layer through the second conductive column in the second tube shell, and because the multi-layer circuit board is designed with a multi-layer circuit board, the first chip and the second chip can be electrically connected to different circuit layers, thereby avoiding mutual crosstalk and interference between different radio frequency lines. Compared with the prior art, the utility model adopts a multi-layer circuit layer and designs tube shells on both sides, so that a multi-channel design can be realized, and the radio frequency lines of multiple channels can be connected to different circuit layers, effectively reducing the interference caused by the crossover of radio frequency interconnection in multi-channel transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the utility model, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the utility model and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 It is a structural diagram of a SIP transceiver module in the prior art;

[0025] Figure 2 A schematic diagram of the structure of a SIP transceiver module provided in an embodiment of the utility model;

[0026] Figure 3 A schematic diagram of the exploded structure of a SIP transceiver module provided in an embodiment of the utility model;

[0027] Figure 4 for Figure 2 A schematic diagram of the structure of the first tube shell;

[0028] Figure 5 for Figure 2 Schematic diagram of the structure of the second tube shell.

[0029] icon:

[0030] 100-SIP transceiver module; 110-multilayer circuit board; 130-first tube shell; 131-first ceramic substrate; 133-first metal dam; 135-first wiring layer; 137-first pad; 139-solder ball; 140-first chip; 141-first pin; 143-first wire; 150-second tube shell; 151-second ceramic substrate; 153-second metal dam; 155-second wiring layer; 157-second pad; 160-second chip; 161-second pin; 163-second wire; 170-first conductive column; 190-second conductive column. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical scheme and advantages of the embodiments of the utility model clearer, the technical scheme in the embodiments of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiments of the utility model. Obviously, the described embodiments are part of the embodiments of the utility model, not all of the embodiments. Generally, the components of the embodiments of the utility model described and shown in the drawings here can be arranged and designed in various different configurations.

[0032] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the present invention to be protected, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0033] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0034] In the description of the present utility model, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside", etc. indicate the orientation or position relationship based on the orientation or position relationship shown in the accompanying drawings, or the orientation or position relationship in which the utility model product is usually placed when in use, which is only for the convenience of describing the utility model and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present utility model. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0035] In addition, the terms "horizontal", "vertical" and the like do not mean that the components are required to be absolutely horizontal or suspended, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0036] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0037] As disclosed in the background art, the SIP module designs in the prior art generally include one-layer and three-layer designs.

[0038] Early SIP transceiver modules, such as Figure 1As shown in the figure, the module is in the form of a ceramic shell + cover plate. The chip is bonded to the ceramic shell by conductive glue and connected to the microstrip line on the ceramic surface by gold wire bonding to achieve the transmission of RF and electrical signals. The module shell structure is simple. When the shell size is determined, the size of the chip placement is limited. Due to the limited size of the single-layer shell, the design of the three-layer shell is easy to come by, including the bottom and top ceramic shells + the middle ceramic plate. This form solves the problem of Figure 1 The problem of insufficient chip placement in a single-layer ceramic shell is that the chip placement area is theoretically doubled under the same area. However, in actual design, in order to ensure the interconnection of the upper and lower shell chips, there must be connecting columns, so the chip placement area is not actually doubled. Therefore, the design of the traditional SIP transceiver module generally contains at most three layers of ceramic shells, of which the upper and lower layers of ceramic shells contain Al2O3 ceramic substrates and metal dams, and the middle ceramic shell is only an Al2O3 ceramic flat plate. In actual assembly, due to the height of the dam, the chip can generally only be placed in the upper and lower layers. The traditional TR module generally contains four channels, such as Figure 2 As shown, the number of chips it can accommodate is limited.

[0039] With the requirement of component miniaturization, the design of 16-channel TR module is imminent. As the number of channels increases, the area reserved for chip placement in each channel will be reduced exponentially. Taking 16 channels as an example, under the condition of the same SIP module size, the actual usable area of ​​​​each channel is 1 / 4 of the original area, and the simple stacking of conventional multi-layer ceramic tube shells obviously cannot meet the design requirements.

[0040] In order to solve the above problems, an embodiment of the present utility model provides a novel SIP transceiver module, which is described in detail below.

[0041] Please refer to Figure 2 and Figure 3 This embodiment provides a SIP transceiver module 100, which can realize multi-channel design, greatly increase the number of channels in a single product, meet the requirements of component miniaturization and channel number, and effectively reduce the interference caused by RF interconnection in multi-channel transmission.

[0042] The present embodiment provides a SIP transceiver module 100, including a multi-layer circuit board 110, at least one first tube shell 130 and at least one second tube shell 150, wherein the multi-layer circuit board 110 is provided with multiple circuit layers; the first tube shell 130 is arranged on one side of the multi-layer circuit board 110, and a first chip 140 is arranged on the first tube shell 130; the second tube shell 150 is arranged on the other side of the multi-layer circuit board 110, and a second chip 160 is arranged on the second tube shell 150; wherein a first conductive column 170 is arranged in the first tube shell 130, and the first chip 140 is electrically connected to a part of the circuit layer through the first conductive column 170, a second conductive column 190 is arranged in the second tube shell 150, and the second chip 160 is electrically connected to a part of the circuit layer through the second conductive column 190, and the first chip 140 and the second chip 160 are electrically connected to different circuit layers.

[0043] It is worth noting that the multi-layer circuit board is a multi-layer PCB structure, which can realize the design of any number of layers, and is made by pressing the RF substrate. Its specific manufacturing process can refer to the production of existing PCB multi-layer boards. Among them, the multi-layer RF substrate in the multi-layer circuit board can constitute a multi-layer circuit layer, each circuit layer is independent of each other, and the RF signal routing is a strip line. Since the upper and lower layers of the strip line are ground structures, the interference between the RF signal transmission can be minimized, which is convenient for the first chip 140 and the second chip 160 to be connected to different circuit layers without mutual interference. At the same time, no chip is placed on the multi-layer PCB board, only the transmission of signals between the tube shells is provided, and the upper and lower tube shells are bonded to achieve interconnection.

[0044] See also Figure 4 In this embodiment, the first tube shell 130 is arranged on the bottom side of the multi-layer circuit board, and the first tube shell 130 can be one, the first tube shell 130 includes a first ceramic substrate 131 and a first metal dam 133, the first metal dam 133 is arranged around the first ceramic substrate 131 and connected to the edge of the multi-layer circuit board 110, the first chip 140 is attached to the side surface of the first ceramic substrate 131 close to the multi-layer circuit board 110, and the first ceramic substrate 131 is also provided with a first conductive column 170, the first chip 140 is electrically connected to the first conductive column 170, and the first conductive column 170 is correspondingly bonded to the surface of the multi-layer circuit board.

[0045] Of course, in other preferred embodiments of the present invention, the first tube shell 130 may also adopt a multi-layer stacking structure. When the first tube shell 130 adopts a multi-layer structure, its stacking structure may refer to the stacking structure of the subsequent second tube shell 150 .

[0046] In this embodiment, a first wiring layer 135 is provided on a surface of one side of the first ceramic substrate 131 close to the multi-layer circuit board 110, the first chip 140 is electrically connected to the first wiring layer 135, and the first wiring layer 135 is electrically connected to the first conductive column 170. Specifically, the first ceramic substrate 131 can be an AL2O3 substrate, and wiring is performed on the surface to form the first wiring layer 135, and its wiring process can refer to the existing ceramic substrate. After the first chip 140 is mounted, it can be electrically connected to the first conductive column 170 through the first wiring layer 135, wherein the first metal dam 133 is surrounded by the edge of the first ceramic substrate 131, and the first chip 140 is mounted at the center of the first ceramic substrate 131. Among them, the height of the first conductive column 170 is the same as the height of the first metal dam 133, and the first metal dam 133 can be bonded and fixed at the edge of the multi-layer circuit board 110, and the first conductive column 170 can directly abut on the pad on the surface of the multi-layer circuit board 110, and different pads on the multi-layer circuit board 110 can be connected to different circuit layers.

[0047] In the present embodiment, a first pad 137 is disposed on a surface of the first ceramic substrate 131 on one side away from the multilayer circuit board 110. The first pad 137 is electrically connected to the first wiring layer 135, and a solder ball 139 is disposed on the first pad 137. Specifically, the first pad 137 can be electrically connected to the first wiring layer 135 through a TSV through-hole process, and there can be multiple first pads 137. Multiple solder balls 139 are formed on the multiple first pads 137 by ball planting, so as to facilitate welding with an external substrate.

[0048] In this embodiment, the back side of the first chip 140 is bonded and fixed to the surface of the first ceramic substrate 131, and a plurality of first pins 141 are arranged on the front side of the first chip 140, each of which is provided with a first wire 143, and the first wire 143 is connected to the first wiring layer 135, so that the first chip 140 is electrically connected to the first wiring layer 135 through the first wire 143. Specifically, after the first chip 140 is mounted by surface mounting technology (SMT), the plurality of first pins 141 of the first chip 140 can be bonded to the first wiring layer 135 through the first wire 143 by wire bonding technology to achieve electrical interconnection. Of course, in other preferred embodiments of the utility model, the flip chip technology can also be adopted to mount the front side of the first chip 140 on the surface of the first ceramic substrate 131 with the front side facing downward, so that the first pins 141 are directly connected to the first wiring layer 135. The mounting method of the first chip 140 is not specifically limited here.

[0049] See also Figure 3 and Figure 5In this embodiment, there are multiple second tube shells 150, and multiple second tube shells 150 are stacked. Each second tube shell 150 is provided with a second chip 160, and each second tube shell 150 is provided with multiple second conductive pillars 190, and each second conductive pillar 190 is correspondingly bonded to an adjacent second tube shell 150. Specifically, multiple second tube shells 150 are stacked in sequence, and the second tube shells 150 located at the bottom are stacked on the upper surface of the multi-layer circuit board 110 to realize a multi-layer tube shell structure, which can greatly increase the number of chips and channels. Among them, the number of second tube shells 150 can be set according to the number of channels required. In this embodiment, the second tube shells 150 are 3 as an example for explanation, and it can realize a 16-channel structural design in combination with the first tube shell 130. It should be noted that the traditional SIP module requires 4-16 products, while in this embodiment, only one product is needed to realize its function, which provides a more high-quality and reliable miniaturized design for components that cannot be arranged in traditional modules.

[0050] Each second tube shell 150 includes a second ceramic substrate 151 and a second metal dam 153. The second ceramic substrate 151 is spaced apart from the multi-layer circuit board 110. The second metal dam 153 is arranged around the second ceramic substrate 151 and connected to the edge of the multi-layer circuit board 110 or the adjacent second ceramic substrate 151. The second chip 160 is correspondingly attached to the surface of the second ceramic substrate 151 close to the multi-layer circuit board. A plurality of second conductive pillars 190 are also arranged on the second ceramic substrate 151. The second chip 160 is electrically connected to at least one second conductive pillar 190. The plurality of second conductive pillars 190 are correspondingly bonded to the surface of the multi-layer circuit board or the adjacent second ceramic substrate 151. Specifically, the structures of the plurality of second tube shells 150 are basically the same, except for the distribution positions of the second conductive pillars 190. The distribution positions of the second conductive pillars 190 in the second tube shells 150 of adjacent layers are not one-to-one corresponding, but are staggered, so as to facilitate the longitudinal line connection. Meanwhile, when each second tube shell 150 is stacked, the second metal dam 153 is located at the lower edge of the second ceramic substrate 151 , and the second metal dam 153 at the bottom layer is bonded and fixed to the upper edge of the multilayer circuit board 110 .

[0051] In this embodiment, a second wiring layer 155 is provided on one side of each second ceramic substrate 151 close to the multilayer circuit board 110, the second chip 160 is electrically connected to the corresponding second wiring layer 155, and the second wiring layer 155 is electrically connected to the corresponding second conductive column 190. Specifically, the second ceramic substrate 151 may also be an AL2O3 substrate, and wiring is performed on the surface to form the second wiring layer 155. After the second chip 160 is mounted, it can be electrically connected to the second conductive column 190 through the second wiring layer 155, wherein the second metal dam 153 is arranged at the edge of the second ceramic substrate 151, and the second chip 160 is mounted at the center of the second ceramic substrate 151. Among them, the height of the second conductive column 190 is the same as the height of the second metal dam 153. The second metal dam 153 located at the bottom layer can be bonded and fixed to the edge position of the multi-layer circuit board 110, and the second conductive column 190 can directly abut against the pad on the surface of the multi-layer circuit board 110. Different pads on the multi-layer circuit board 110 can be connected to different circuit layers; and the second metal dams 153 of the remaining layers can be bonded and fixed to the upper edge of the adjacent second ceramic substrate 151, and the second conductive column 190 can directly abut against the top surface of the second ceramic substrate 151.

[0052] It should be noted that in this embodiment, there are multiple second conductive pillars 190 in each layer of the tube shell, and the second chip 160 can be electrically connected to the multi-layer circuit board 110 through one or part of the second conductive pillars 190, while the second conductive pillars 190 electrically connected to different second chips 160 are isolated from each other, thereby avoiding crosstalk.

[0053] In this embodiment, a second pad 157 is disposed on a side of each second ceramic substrate 151 away from the multilayer circuit board 110, the second pad 157 is electrically connected to the second wiring layer 155, and the second conductive pillar 190 is correspondingly bonded to the second pad 157. Specifically, the second pad 157 and the second wiring layer 155 can be electrically connected through a TSV through hole.

[0054] In this embodiment, the back side of the second chip 160 is bonded and fixed to the surface of the second ceramic substrate 151, and a plurality of second pins 161 are arranged on the front side of the second chip 160, and a second wire 163 is arranged on each second pin 161, and the second wire 163 is connected to the second wiring layer 155 or the second conductive column 190, so that the second chip 160 is electrically connected to the second wiring layer 155 through the second wire 163. Specifically, after the second chip 160 is mounted by surface mounting technology (SMT), the plurality of second pins 161 of the second chip 160 can be bonded to the second wiring layer 155 through the second wire 163 by wire bonding technology to achieve electrical interconnection. Of course, in other preferred embodiments of the utility model, the flip chip technology can also be adopted to mount the front side of the second chip 160 on the surface of the second ceramic substrate 151 upward, so that the second pins 161 are directly connected to the second wiring layer 155. The mounting method of the second chip 160 is not specifically limited here.

[0055] In summary, the SIP transceiver module 100 provided in this embodiment uses a multi-layer circuit board 110 provided with multiple circuit layers, a first tube shell 130 is provided on one side of the multi-layer circuit board 110, and a second tube shell 150 is provided on the other side, a first chip 140 is provided on the first tube shell 130, and a second chip 160 is provided on the second tube shell 150, the first chip 140 is connected to part of the circuit layer through the first conductive column 170 in the first tube shell 130, and the second chip 160 is connected to part of the circuit layer through the second conductive column 190 in the second tube shell 150, and because the multi-layer circuit board is designed with a multi-layer circuit board 110, the first chip 140 and the second chip 160 can be electrically connected to different circuit layers, thereby avoiding mutual crosstalk and interference between different radio frequency lines. Compared with the prior art, in this embodiment, a chip is placed on each layer of the ceramic tube shell, and the longitudinal interconnection of the radio frequency line can be achieved through the first conductive column 170 and the second conductive column 190, while the lateral connection is achieved through the inner strip line in the multi-layer circuit board 110. Due to the use of multiple layers of circuit layers and the design of tube shells on both sides, multi-channel design can be achieved, and multi-channel RF lines can be connected to different circuit layers, effectively reducing the interference caused by RF interconnection and cross-connection in multi-channel transmission.

[0056] The above description is only the preferred embodiment of the utility model, and is not intended to limit the utility model. For those skilled in the art, the utility model can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the utility model shall be included in the protection scope of the utility model.

Claims

1. A SIP transceiver module, characterized in that: include: A multi-layer circuit board (110), wherein a plurality of circuit layers are arranged in the multi-layer circuit board (110); at least one first tube shell (130), the first tube shell (130) being arranged on one side of the multilayer circuit board (110), and a first chip (140) being arranged on the first tube shell (130); at least one second tube shell (150), the second tube shell (150) being arranged on the other side of the multilayer circuit board (110), and a second chip (160) being arranged on the second tube shell (150); A first conductive column (170) is disposed in the first tube shell (130), and the first chip (140) is electrically connected to a portion of the circuit layer through the first conductive column (170); a second conductive column (190) is disposed in the second tube shell (150), and the second chip (160) is electrically connected to a portion of the circuit layer through the second conductive column (190); and the first chip (140) and the second chip (160) are electrically connected to different circuit layers.

2. The SIP transceiver module according to claim 1, characterized in that: The first tube shell (130) comprises a first ceramic substrate (131) and a first metal dam (133); the first metal dam (133) is arranged around the first ceramic substrate (131) and connected to the edge of the multi-layer circuit board (110); the first chip (140) is attached to a surface of the first ceramic substrate (131) on one side close to the multi-layer circuit board (110); the first ceramic substrate (131) is also provided with the first conductive column (170); the first chip (140) is electrically connected to the first conductive column (170); and the first conductive column (170) is correspondingly bonded to the surface of the multi-layer circuit board.

3. The SIP transceiver module according to claim 2, characterized in that: A first wiring layer (135) is provided on a surface of the first ceramic substrate (131) close to the multilayer circuit board (110); the first chip (140) is electrically connected to the first wiring layer (135); and the first wiring layer (135) is electrically connected to the first conductive column (170).

4. The SIP transceiver module according to claim 3, characterized in that: A first solder pad (137) is provided on a surface of the first ceramic substrate (131) away from the multilayer circuit board (110); the first solder pad (137) is electrically connected to the first wiring layer (135); and a solder ball (139) is provided on the first solder pad (137).

5. The SIP transceiver module according to claim 3, characterized in that: The back side of the first chip (140) is bonded and fixed to the surface of the first ceramic substrate (131), and the front side of the first chip (140) is provided with a plurality of first pins (141), each of the first pins (141) is provided with a first wire (143), and the first wire (143) is connected to the first wiring layer (135), so that the first chip (140) is electrically connected to the first wiring layer (135) through the first wire (143).

6. The SIP transceiver module according to claim 1 or 2, characterized in that: There are a plurality of second tube shells (150), and the plurality of second tube shells (150) are stacked and arranged, each of the second tube shells (150) is provided with a second chip (160), and each of the second tube shells (150) is provided with a plurality of second conductive pillars (190), and each of the second conductive pillars (190) is correspondingly bonded to an adjacent second tube shell (150).

7. The SIP transceiver module according to claim 6, characterized in that: Each second tube shell (150) comprises a second ceramic substrate (151) and a second metal dam (153); the second ceramic substrate (151) is spaced apart from the multi-layer circuit board (110); the second metal dam (153) is arranged around the second ceramic substrate (151) and connected to the edge of the multi-layer circuit board (110) or an adjacent second ceramic substrate (151); the second chip (160) is correspondingly attached to a surface of one side of the second ceramic substrate (151) close to the multi-layer circuit board; a plurality of second conductive pillars (190) are also arranged on the second ceramic substrate (151); the second chip (160) is electrically connected to at least one of the second conductive pillars (190); and a plurality of second conductive pillars (190) are correspondingly bonded to the surface of the multi-layer circuit board or an adjacent second ceramic substrate (151).

8. The SIP transceiver module according to claim 7, characterized in that: A second wiring layer (155) is provided on a side of each second ceramic substrate (151) close to the multilayer circuit board (110); the second chip (160) is electrically connected to the corresponding second wiring layer (155); and the second wiring layer (155) is electrically connected to the corresponding second conductive column (190).

9. The SIP transceiver module according to claim 8, characterized in that: A second soldering pad (157) is provided on a side of each second ceramic substrate (151) away from the multilayer circuit board (110); the second soldering pad (157) is electrically connected to the second wiring layer (155); and the second conductive column (190) is correspondingly bonded to the second soldering pad (157).

10. The SIP transceiver module according to claim 8, characterized in that: The back side of the second chip (160) is bonded and fixed to the surface of the second ceramic substrate (151), and the front side of the second chip (160) is provided with a plurality of second pins (161), each of the second pins (161) is provided with a second wire (163), and the second wire (163) is connected to the second wiring layer (155) or the second conductive column (190), so that the second chip (160) is electrically connected to the second wiring layer (155) through the second wire (163).

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