Solar cell

Abstract

The present application provides a solar cell comprising: a silicon substrate having a front surface and a back surface opposite to each other, the back surface having a first region and a second region adjacent to each other; a first passivation layer on the front surface; the tunneling oxide layer and the first doping layer are sequentially arranged on the first area in a stacked mode, the thickness of the tunneling oxide layer is equal to or larger than 2 nm, and the tunneling oxide layer is provided with pinholes; a second passivation layer on the second region; the second doping layer is located on the surface, away from the silicon substrate, of the second passivation layer, and the doping type of the first doping layer is opposite to that of the second doping layer; the first electrode is electrically connected with the first doping layer; and the second electrode is electrically connected with the second doped layer. According to the solar cell, pyramid suede morphology can be formed on the front surface and the back surface at the same time in the same process step, and the process complexity of manufacturing the solar cell is reduced.

Description

Technical Field

[0001] The present application mainly relates to the field of photovoltaic technology, and in particular to a solar cell. Background Art

[0002] The types of crystalline silicon solar cells mainly include Passivated Emitter and Rear Contact (PERC), Tunnel Oxide Passivated Contact (TOPcon), Heterojunction with Intrinsic Thin-layer (HJT) and Interdigitated Back Contact (IBC). HJT cells have been a hot topic in the field of photovoltaic technology due to their simple process, high efficiency, low temperature coefficient, good weak light response, low temperature throughout the process, and energy saving. However, the amorphous silicon film in HJT cells has light absorption characteristics, which leads to lower current density than other cells (such as PERC and TOPcon). The back contact heterojunction cell (HBC) developed based on the HJT process has both positive and negative electrodes located on the back of the cell, and there is no metal grid line blocking the front of the cell. While retaining the high opening voltage characteristics of the HJT cell, it can effectively reduce the shading of the front surface electrode and improve the short-circuit current density. However, the current preparation process of HBC batteries is relatively complicated, and how to reduce the complexity of the preparation process is one of the important research directions in this field. Utility Model Content

[0003] The technical problem to be solved by the present application is to provide a solar cell which can reduce the complexity of the preparation process.

[0004] To solve the above technical problems, the present application provides a solar cell, comprising: a silicon substrate having a relative front side and a back side, the back side having a first region and a second region adjacent to each other; a first passivation layer located on the front side; a tunneling oxide layer and a first doping layer, which are sequentially stacked on the first region, the thickness of the tunneling oxide layer is equal to or greater than 2 nm, and the tunneling oxide layer has pinholes; a second passivation layer located on the second region; a second doping layer located on a surface of the second passivation layer away from the silicon substrate, the doping type of the first doping layer being opposite to the doping type of the second doping layer; a first electrode electrically connected to the first doping layer; and a second electrode electrically connected to the second doping layer.

[0005] In an implementation of the present application, the second passivation layer extends to above the first region and covers at least a portion of the surface of the first doped layer away from the silicon substrate.

[0006] In an implementation of the present application, the solar cell further includes a first insulating layer, where the first insulating layer is located on a surface of the first doped layer away from the silicon substrate.

[0007] In one embodiment of the present application, the solar cell also includes a second insulating layer, which extends along the thickness direction of the silicon substrate and is located between the second passivation layer, the first doping layer and the tunneling oxide layer in a first direction, and the second insulating layer is in contact with the first insulating layer on the side away from the silicon substrate, wherein the first direction intersects with the thickness direction.

[0008] In one embodiment of the present application, the first region and / or the second region has a pyramid velvet morphology.

[0009] In an implementation of the present application, a height difference between the first region and the second region is 0 μm to 20 μm.

[0010] In an implementation of the present application, the second passivation layer includes intrinsic silicon, and the first doped layer includes doped polysilicon.

[0011] In an implementation of the present application, the solar cell further includes an anti-reflection layer, and the anti-reflection layer is located on the first passivation layer.

[0012] In an implementation of the present application, the solar cell further includes a transparent conductive layer, and the transparent conductive layer is located on the second doped layer.

[0013] In one implementation of the present application, an isolation trench is further included, wherein the isolation trench is located between the first electrode and the second electrode and penetrates the second doping layer and the second passivation layer.

[0014] Compared with the prior art, this application has the following advantages:

[0015] (1) When the front surface, the first region, and the second region all have pyramid velvet morphology, the pyramid velvet morphology is formed simultaneously in the same process step, thereby reducing the process complexity of manufacturing solar cells.

[0016] (2) The thickness of the tunneling oxide layer of the present application is equal to or greater than 2 nm. The thicker thickness requires a lower flatness of the surface where the tunneling oxide layer is located, so that the surface where the tunneling oxide layer is located can be processed into a pyramid velvet morphology, which is beneficial to improving the utilization rate of incident light by the solar cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings are included to provide a further understanding of the present application. They are included and constitute a part of the present application. The accompanying drawings illustrate embodiments of the present application and together with the present specification serve to explain the principles of the present application. In the accompanying drawings:

[0018] Figure 1 is a cross-sectional schematic diagram of a solar cell in one embodiment of the present application;

[0019] Figure 2 is a cross-sectional schematic diagram of a solar cell in one embodiment of the present application;

[0020] Figure 3 is a cross-sectional schematic diagram of a solar cell in one embodiment of the present application;

[0021] Figure 4 is a cross-sectional schematic diagram of a solar cell in one embodiment of the present application;

[0022] Figure 5 It is a cross-sectional schematic diagram of a solar cell in one embodiment of the present application.

[0023] Reference numerals

[0024] Silicon substrate 110 Pinhole 131 Diffusion layer 210

[0025] Front surface 111 First doping layer 140 First insulating layer 220

[0026] Back surface 112 Second passivation layer 150 Transparent conductive layer 230

[0027] First region 112a Second doping layer 160 Isolation trench 240

[0028] Second region 112b First electrode 170 Second insulating layer 250

[0029] First passivation layer 120 Second electrode 180

[0030] Tunneling oxide layer 130 Anti-reflection layer 190 DETAILED DESCRIPTION

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for the description of the embodiments. Obviously, the drawings described below are only some examples or embodiments of the present application. For ordinary technicians in this field, the present application can also be applied to other similar scenarios based on these drawings without creative work. Unless it is obvious from the language environment or otherwise explained, the same reference numerals in the figures represent the same structure or operation.

[0032] As shown in this application and claims, unless the context clearly indicates an exception, the words "a", "an", "an" and / or "the" do not refer to the singular and may also include the plural. Generally speaking, the terms "include" and "comprise" only indicate the inclusion of the steps and elements that have been clearly identified, and these steps and elements do not constitute an exclusive list. The method or device may also include other steps or elements.

[0033] Unless otherwise specifically stated, the relative arrangement, numerical expressions and numerical values ​​of the parts and steps set forth in these embodiments do not limit the scope of the present application. At the same time, it should be understood that, for ease of description, the sizes of the various parts shown in the accompanying drawings are not drawn according to the actual proportional relationship. The technology, method and equipment known to those of ordinary skill in the relevant field may not be discussed in detail, but in appropriate cases, the technology, method and equipment should be considered as a part of the authorization specification. In all examples shown and discussed here, any specific value should be interpreted as being merely exemplary, rather than as a limitation. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters represent similar items in the following drawings, so that once a certain item is defined in an accompanying drawing, it does not need to be further discussed in subsequent drawings.

[0034] In the description of the present application, it should be understood that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the device or element referred to must have a specific direction or be constructed and operated in a specific direction, and therefore cannot be understood as limiting the scope of protection of the present application; the directional words "inside and outside" refer to the inside and outside relative to the contours of each component itself.

[0035] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used here to describe the spatial positional relationship between a device or feature and other devices or features as shown in the figure. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" can include both "above" and "below". The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used here are interpreted accordingly.

[0036] In addition, it should be noted that the use of words such as "first" and "second" to define components is only for the convenience of distinguishing the corresponding components. If not otherwise stated, the above words have no special meaning and cannot be understood as limiting the scope of protection of this application. In addition, although the terms used in this application are selected from well-known and commonly used terms, some terms mentioned in the specification of this application may be selected by the applicant at his or her discretion, and their detailed meanings are explained in the relevant parts of the description of this article. In addition, it is required to understand this application not only by the actual terms used, but also by the meaning implied by each term.

[0037] Next, the solar cell of the present application is described by way of examples.

[0038] refer to Figure 1 The cross-sectional schematic diagram of a solar cell in an embodiment shown in the figure includes a silicon substrate 110, a first passivation layer 120, a tunneling oxide layer 130, a first doping layer 140, a second passivation layer 150, a second doping layer 160, a first electrode 170 and a second electrode 180.

[0039] Specifically, the silicon substrate 110 has a front side 111 and a back side 112 opposite to each other, and the back side 112 has a first region 112a and a second region 112b adjacent to each other. The first passivation layer 120 is located on the front side 111. The tunneling oxide layer 130 and the first doping layer 140 are sequentially stacked on the first region 112a, and the thickness of the tunneling oxide layer 130 is equal to or greater than 2nm, for example, the thickness is 2.2nm, 2.4nm, 2.6nm, 2.8nm, 3.0nm, 3.2nm, 3.4nm, 3.4nm, 3.6nm, 3.8nm or 4.0nm, and the tunneling oxide layer 130 has a pinhole 131. The second passivation layer 150 is located on the second region 112b. The second doping layer 160 is located on the surface of the second passivation layer 150 away from the silicon substrate 110. The doping type of the first doping layer 140 is opposite to the doping type of the second doping layer 160. For example, the first doping layer 140 is N-type doped and the second doping layer 160 is P-type doped, or the first doping layer 140 is P-type doped and the second doping layer 160 is N-type doped. The first electrode 170 is electrically connected to the first doping layer 140, and the second electrode 180 is electrically connected to the second doping layer 160.

[0040] The silicon substrate 110 is doped, and the silicon substrate 110 may be N-type (or P) type single crystal silicon, N-type (or P) polycrystalline silicon or N-type (or P) type cast single crystal. When the silicon substrate 110 is N-type doped, the doping element may be phosphorus (P) and / or arsenic (As); when the silicon substrate 110 is P-type doped, the doping element may be boron (B) and / or gallium (Ga). The present application does not limit the doping method and doping concentration of the silicon substrate 110. The thickness of the silicon substrate 110 may be any value within a range of 60 μm to 200 μm, for example, 100 μm or 150 μm.

[0041] In one embodiment, the solar cell further comprises an anti-reflection layer 190, which is located on the surface of the first passivation layer 120 away from the silicon substrate 110. The first passivation layer 120 can be selected from intrinsic amorphous silicon, a composite layer of intrinsic amorphous silicon and doped thin film silicon, silicon oxide (SiO2), silicon oxynitride (SiO x N y ) and aluminum oxide (Al2O3), wherein the intrinsic amorphous silicon may contain one or more elements of oxygen (O), carbon (C), and nitrogen (N), and the doped thin film silicon may be phosphorus (P) doped or boron (B) doped, and the doped thin film silicon may contain one or more elements of oxygen (O), carbon (C), and nitrogen (N).

[0042] When the first passivation layer 120 is selected from the above-mentioned multiple materials, the first passivation layer 120 can be a stacked structure formed by the above-mentioned multiple materials. For example, the stacked structure can be formed by stacking an aluminum oxide layer and a silicon oxynitride layer, or can be formed by stacking an aluminum oxide layer and a silicon oxide layer. The first passivation layer 120 with a stacked structure has a stacked passivation effect.

[0043] According to different passivation mechanisms, the first passivation layer 120 can be a chemical passivation layer or a field passivation layer, or can be formed by stacking a chemical passivation layer and a field passivation layer. When the first passivation layer 120 is formed by stacking a chemical passivation layer and a field passivation layer, the chemical passivation layer is arranged on the front surface 111, the field passivation layer is arranged on the surface of the chemical passivation layer away from the silicon substrate 110, and the anti-reflection layer 190 is arranged on the surface of the field passivation layer away from the silicon substrate 110. The chemical passivation layer can saturate the defects at the front surface 111, reduce the defect concentration, thereby reducing the recombination center in the forbidden band, and thus improve the efficiency of the solar cell. The field passivation layer can form an electrostatic field at the interface through charge accumulation, thereby reducing the minority carrier concentration, and thus improve the efficiency of the solar cell.

[0044] The thickness of the first passivation layer 120 is equal to or greater than 1.5 nm, for example, the thickness is 2 nm, 3 nm, 4 nm or 5 nm. The thickness of the anti-reflection layer 190 is equal to or greater than 40 nm, for example, the thickness is 45 nm, 50 nm, 55 nm or 60 nm. The anti-reflection layer 190 can increase the absorption of incident light by the solar cell, thereby improving the utilization rate of the incident light by the solar cell. The anti-reflection layer 190 can be silicon oxide and / or silicon oxynitride.

[0045] The front surface 111 may have a pyramid suede morphology. The first passivation layer 120 and the anti-reflection layer 190 sequentially formed on the front surface 111 also have a pyramid suede morphology. When the solar cell is working, the pyramid suede morphology can trap light and reduce the reflection of incident light, thereby improving the utilization rate of light by the solar cell.

[0046] In one embodiment, the solar cell has a diffusion layer 210, the diffusion layer 210 is located on the first region 112a, and the tunneling oxide layer 130 and the first doping layer 140 are sequentially arranged on the surface of the diffusion layer 210 away from the silicon substrate 110. The diffusion layer 210 can be crystalline silicon (single crystal silicon and / or polycrystalline silicon), and the doping type of the diffusion layer 210 is the same as or opposite to that of the silicon substrate 110. The doping concentration of the diffusion layer 210 is not limited here, and its doping concentration can be equal to or less than the doping concentration of the first doping layer 140, can also be greater than the doping concentration of the first doping layer 140, and can also be greater than the doping concentration of the silicon substrate 110.

[0047] The diffusion depth of the doping elements in the diffusion layer 210 is equal to or greater than 10 nm and equal to or less than 1500 nm, for example, the diffusion depth is 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 1000 nm, 1100 nm, 1200 nm, 1300 nm or 1400 nm.

[0048] The tunneling oxide layer 130 and the first doping layer 140 are polysilicon oxide passivation contact structures (Poly-Si onoxide, POLO). The tunneling oxide layer 130 can be silicon oxide, which has a passivation effect and improves the open circuit voltage (Voc) of the battery. The first doping layer 140 has a pinhole (Pin-hole) 131 formed by high temperature annealing (≥900°C). After the silicon substrate 110 generates carriers through light, the carriers can be transmitted to the first doping layer 140 through the pinhole 131, effectively reducing the tunneling resistance and improving the battery fill factor (FF). This application does not limit the number of pinholes 131 per unit area.

[0049] The first doping layer 140 has the same or opposite doping type as the silicon substrate 110. The silicon substrate 110 may be P-type doped (or N-type doped) polysilicon or P-type doped (or N-type doped) silicon carbide. The thickness of the first doping layer 140 is equal to or greater than 30 nm and equal to or less than 300 nm, for example, the thickness is 50 nm, 100 nm, 150 nm, 200 nm or 250 nm.

[0050] In one embodiment, the second passivation layer 150 extends to above the first region 112a and covers at least a portion of the surface of the first doped layer 140 away from the silicon substrate 110. Figure 1 In the solar cell, the first insulating layer 220 is located on the surface of the first doping layer 140 away from the silicon substrate 110, and the second passivation layer 150 covers the entire surface of the first doping layer 140 away from the silicon substrate 110, wherein the first insulating layer 220 is located between the first doping layer 140 and the second passivation layer 150; Figure 2 In the embodiment, the solar cell does not include the first insulating layer 220, and the second passivation layer 150 covers the entire surface of the first doping layer 140 away from the silicon substrate 110, and directly contacts the first doping layer 140. Figure 1 and Figure 2 In the embodiment, the second passivation layer 150 may also only cover a portion of the surface of the first doped layer 140 away from the silicon substrate 110 .

[0051] The first insulating layer 220 may be one or more of silicon oxide, silicon nitride and silicon oxynitride. The first insulating layer 220 may contain the doping elements in the first doping layer 140. The doping elements in the first insulating layer 220 may be intentionally doped through a specific process, or may be self-diffused into the first insulating layer 220 by the doping elements in the first doping layer 140. For example, the doping elements in the first doping layer 140 may be self-diffused into the portion of the first insulating layer 220 away from the silicon substrate 110.

[0052] The second passivation layer 150 may be intrinsic amorphous silicon, which may contain one or more of oxygen, carbon and nitrogen, which are beneficial to improving the passivation effect of the second passivation layer 150 and reducing optical absorption loss. The thickness of the second passivation layer 150 may be any thickness within the range of 3nm to 15nm, for example, 5nm or 10nm. The thickness of the portion of the second passivation layer 150 located on the first region 112a, the thickness of the portion located on the second region 112b, and the thickness of the portion located at the junction of the first region 112a and the second region 112b may be equal or different.

[0053] exist Figure 1 In the embodiment, the second region 112b has a pyramid velvet structure, and the second passivation layer 150 and the second doping layer 160 located on the second region 112b also have a pyramid velvet structure. In some other embodiments, the first region 112a may also have a pyramid velvet structure, and the film layer located on the first region 112a also has a pyramid velvet structure. The first region 112a and the second region 112b may both be polished surfaces, or the first region 112a is a polished surface, and the second region 112b is a pyramid base. When the front side 111, the first region 112a and the second region 112b all have a pyramid velvet morphology, the pyramid velvet morphology is formed simultaneously in the same process step, which can reduce the process complexity of manufacturing solar cells.

[0054] The thickness of the tunneling oxide layer 130 of the present application is equal to or greater than 2 nm. A thicker thickness is beneficial to passivation, and a thicker thickness has lower requirements on the flatness of the surface where the tunneling oxide layer 130 is located. In this way, the surface where the tunneling oxide layer 130 is located can be processed into a pyramid velvet morphology, which is beneficial to improving the utilization rate of incident light by solar cells.

[0055] The second doping layer 160 may be one or more of doped amorphous silicon, nanocrystalline silicon, and microcrystalline silicon, and the second doping layer 160 may contain one or more of oxygen, carbon, and nitrogen. The thickness of the second doping layer 160 may be any value within the range of 3nm to 50nm, for example, the thickness is 10nm, 20nm, 30nm, or 40nm, and the thickness of the portion of the second doping layer 160 located on the first region 112a, the thickness of the portion located on the second region 112b, and the thickness of the portion located at the junction of the first region 112a and the second region 112b may be equal or different.

[0056] refer to Figure 1 As shown, in one embodiment, the solar cell further includes a transparent conductive layer 230, which is located on the second doping layer 160 and extends to the top of the first region 112a. The transparent conductive layer 230 may be one or more of zinc oxide (ZnO), indium oxide (InO) and tin oxide (SnO), and the transparent conductive layer 230 may be doped with one or more of titanium (Ti), zirconium (Zr), gallium (Ga), tin (Sn), molybdenum (Mo), cerium (Ce), fluorine (F), tungsten (W) and aluminum (Al). The thickness of the transparent conductive layer 230 is equal to or greater than 20nm and equal to or less than 200nm, for example, the thickness is 50nm, 100nm or 150nm, and the thickness of the portion of the transparent conductive layer 230 located on the first region 112a, the thickness of the portion located on the second region 112b, and the thickness of the portion located at the junction of the first region 112a and the second region 112b may be equal or different.

[0057] Continue to refer Figure 1 As shown, in one embodiment, the solar cell further includes an isolation groove 240, which is located between the first electrode 170 and the second electrode 180, and sequentially penetrates the transparent conductive layer 230, the second doping layer 160 and the second passivation layer 150, and the isolation groove 240 separates the P region and the N region to prevent short circuit. The isolation groove 240 can also be deep into the first insulating layer 220 or penetrate the first insulating layer 220, for example, the depth of the portion of the isolation groove 240 in the first insulating layer 220 can be any percentage within the range of 5% to 95% of the thickness of the first insulating layer 220 (such as 5%, 25%, 50% or 95%), the width of the isolation groove 240 can be any value within the range of 15μm to 300μm, for example, 15μm, 50μm, 100μm, 200μm or 300μm, and the isolation groove 240 can be formed by laser grooving or wet etching.

[0058] refer to Figure 3As shown, in one embodiment, the first insulating layer 220 covers a portion of the surface of the first doped layer 140 away from the silicon substrate 110, the transparent conductive layer 230 extends from the second region 112b to the first region 112a, the transparent conductive layer 230 located above the first doped layer 140 contacts the surface of the first doped layer 140 away from the silicon substrate 110, and the first electrode 170 contacts the transparent conductive layer 230 located above the first doped layer 140.

[0059] refer to Figure 4 As shown, in one embodiment, the solar cell also includes a second insulating layer 250, which extends along the thickness direction D2 of the silicon substrate 110, and is located between the second passivation layer 150 and the first doping layer 140 in the first direction D1, and is located between the second passivation layer 150 and the tunneling oxide layer 130, and the side of the second insulating layer 250 away from the silicon substrate 110 is in contact with the first insulating layer 220, wherein the first direction D1 intersects with the thickness direction D2.

[0060] refer to Figure 5 As shown, the solar cell has a first insulating layer 220 and a second insulating layer 250, the first insulating layer 220 covers a portion of the surface of the first doped layer 140 away from the silicon substrate 110, the transparent conductive layer 230 extends from the second region 112b to the first region 112a, the transparent conductive layer 230 located above the first doped layer 140 contacts the surface of the first doped layer 140 away from the silicon substrate 110, and the first electrode 170 contacts the transparent conductive layer 230 located above the first doped layer 140.

[0061] refer to Figure 1 As shown, the height difference between the first region 112a and the second region 112b in the thickness direction D2 is 0 μm to 20 μm, for example, the height difference is 2 μm, 4 μm, 6 μm, 8 μm, 10 μm, 12 μm, 14 μm, 16 μm or 18 μm.

[0062] In one embodiment, the tunneling oxide layer 130 and the first doping layer 140 are formed first, and then the second passivation layer 150 and the second doping layer 160 are formed. The process temperature for forming the tunneling oxide layer 130 and the first doping layer 140 is higher than the process temperature for forming the second passivation layer 150 and the second doping layer 160. Forming the tunneling oxide layer 130 and the first doping layer 140 first can avoid the influence of high temperature on the second passivation layer 150 and the second doping layer 160.

[0063] In one embodiment, the first electrode 170 and the second electrode 180 may be any of a silver electrode, a copper electrode, an aluminum electrode, a tin-coated copper electrode, a silver-coated copper electrode, or a composite electrode composed of metals such as nickel, copper, aluminum, and tin. The method of forming the electrodes may be screen printing, electroplating, physical vapor deposition, evaporation, etc. The first electrode 170 may contact the first doping layer 140, and the second electrode 180 may contact the transparent conductive layer 230.

[0064] The basic concepts have been described above. Obviously, for those skilled in the art, the above application disclosure is only an example and does not constitute a limitation of the present application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements and amendments to the present application. Such modifications, improvements and amendments are suggested in the present application, so such modifications, improvements and amendments still belong to the spirit and scope of the exemplary embodiments of the present application.

[0065] At the same time, the present application uses specific words to describe the embodiments of the present application. For example, "one embodiment", "an embodiment", and / or "some embodiments" refer to a certain feature, structure or characteristic related to at least one embodiment of the present application. Therefore, it should be emphasized and noted that "one embodiment" or "an embodiment" or "an alternative embodiment" mentioned twice or more in different positions in this specification does not necessarily refer to the same embodiment. In addition, some features, structures or characteristics in one or more embodiments of the present application can be appropriately combined.

[0066] Similarly, it should be noted that in order to simplify the description of the disclosure of this application and thus help understand one or more application embodiments, in the above description of the embodiments of this application, multiple features are sometimes merged into one embodiment, figure or description thereof. However, this disclosure method does not mean that the features required by the object of this application are more than the features mentioned in the claims. In fact, the features of the embodiments are less than all the features of the single embodiment disclosed above.

[0067] In some embodiments, numbers describing the number of components and attributes are used. It should be understood that such numbers used in the description of the embodiments are modified by the modifiers "about", "approximately" or "substantially" in some examples. Unless otherwise specified, "about", "approximately" or "substantially" indicate that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, which may change according to the required features of individual embodiments. In some embodiments, the numerical parameters should take into account the specified significant digits and adopt the general method of retaining digits. Although the numerical domains and parameters used to confirm the breadth of their range in some embodiments of the present application are approximate values, in specific embodiments, the setting of such numerical values ​​is as accurate as possible within the feasible range.

[0068] Although the present application has been described with reference to the current specific embodiments, ordinary technicians in this technical field should recognize that the above embodiments are only used to illustrate the present application, and various equivalent changes or substitutions may be made without departing from the spirit of the present application. Therefore, as long as the changes and modifications to the above embodiments are within the essential spirit of the present application, they will fall within the scope of the claims of the present application.

Claims

1. A solar cell, characterized in that: include: A silicon substrate having an opposite front side and a back side, the back side having adjacent first and second regions; A first passivation layer, located on the front surface; A tunneling oxide layer and a first doping layer are sequentially stacked on the first region, the thickness of the tunneling oxide layer is equal to or greater than 2 nm, and the tunneling oxide layer has pinholes; a second passivation layer, located on the second region; A second doping layer is located on a surface of the second passivation layer away from the silicon substrate, and the doping type of the first doping layer is opposite to the doping type of the second doping layer; a first electrode, electrically connected to the first doped layer; as well as The second electrode is electrically connected to the second doping layer.

2. The solar cell according to claim 1, wherein: The second passivation layer extends above the first region and covers at least a portion of the surface of the first doped layer away from the silicon substrate.

3. The solar cell according to claim 1 or 2, characterized in that: The invention also includes a first insulating layer, wherein the first insulating layer is located on a surface of the first doping layer away from the silicon substrate.

4. The solar cell according to claim 3, characterized in that It also includes a second insulating layer, which extends along the thickness direction of the silicon substrate and is located between the second passivation layer, the first doping layer and the tunneling oxide layer in a first direction, and the second insulating layer is in contact with the first insulating layer away from the side of the silicon substrate, wherein the first direction intersects with the thickness direction.

5. The solar cell according to claim 1, wherein: The first region and / or the second region has a pyramid velvet morphology.

6. The solar cell according to claim 1, wherein: A height difference between the first region and the second region is 0 μm to 20 μm.

7. The solar cell according to claim 1, wherein: The second passivation layer includes intrinsic silicon, and the first doped layer includes doped polysilicon.

8. The solar cell according to claim 1, wherein: The invention also includes an anti-reflection layer, wherein the anti-reflection layer is located on the first passivation layer.

9. The solar cell according to claim 1, wherein: The invention also includes a transparent conductive layer, wherein the transparent conductive layer is located on the second doping layer.

10. The solar cell according to claim 1, wherein: The device also includes an isolation trench, which is located between the first electrode and the second electrode and penetrates the second doping layer and the second passivation layer.

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