A single-socket CPU server

Abstract

The utility model belongs to the technical field of computer equipment, and specifically relates to a single-channel CPU server. The utility model includes a chassis, a storage module, a mainboard, a PSU redundant power supply module and multiple PCIE expansion modules, the mainboard includes a CPU controller module and multiple mainboard MCIO connectors, the storage module includes multiple backplane modules, each backplane module includes multiple backplane MCIO connectors and multiple U.2 interfaces, the PCIE expansion module includes multiple extension MCIO connectors and multiple PCIE SLOT slots, the mainboard MCIO connector can be connected to the backplane MCIO connector and the extension MCIO connector, and the PSU redundant power supply module is connected to the storage module and the CPU controller module. The utility model can meet a variety of scenarios without increasing additional board modification time, and the cost is low.

Description

Technical Field

[0001] The utility model belongs to the technical field of computer equipment, and in particular relates to a single-channel CPU server. Background Art

[0002] At present, in the research of high-performance single-channel rack servers, it is often encountered that different usage scenarios are switched for single-channel rack servers on the same motherboard. In the current existing technology, the PCIE signal is generally expanded in the form of onboard PCIE SLOT through the CPU direct output PCIE signal or the CPU under the bridge chip, that is, for single-channel rack servers, the onboard PCIE SLOT is still used to expand the number of PCIE cards. When there is a need for PCIE cards, the PCIE card is inserted into the PCIE SLOT, and the usage scenario is relatively simple. At the same time, the current PCIE signal is generally only GEN4.0. For example, if there is a layout that meets 3 PCIE GEN5.0 X16 double-width cards plus 8 PCIE GEN5.0 NVMe U.2SSD disks, then it can no longer meet 3 PCIE GEN5.0 X8 double-width cards plus 17 PCIE GEN5.0 NVMe U.2SSD disks. If you want to meet it, you need to change the board, that is, one version corresponds to one scenario. Therefore, the current technical layout has certain limitations on the changing application scenarios, cannot flexibly switch between different scenarios, and has functional obstacles in the PCIE rate.

[0003] When multiple PCIE GEN5.0 NVMe U.2SSD disks are needed, the onboard PCIE SLOT cannot take into account the flexible configuration between the PCIE expansion card and the number of disks. It has many limitations for different application scenarios and is not convenient for flexible switching of multiple application scenarios. If multiple scenarios are required for the same motherboard, the motherboard needs to be modified, which increases the design and development cycle and development costs. The existing technology requires additional cost for the PCIE expansion card, and the card is not domestically produced and has a high cost. Utility Model Content

[0004] The purpose of the utility model is to solve the problems of the prior art and to provide a single-channel CPU server that can meet many scenarios without increasing additional board modification time.

[0005] In order to achieve the above purpose, the technical solution provided by the utility model is:

[0006] A single-channel CPU server comprises a chassis, a storage module, a mainboard, a PSU redundant power supply module and a plurality of PCIE expansion modules, wherein the mainboard comprises a CPU controller module and a plurality of mainboard MCIO connectors, the CPU controller module comprises a CPU, the CPU controller module is connected to a plurality of mainboard MCIO connectors through in-board wiring, the storage module, the mainboard, the PSU redundant power supply module and a plurality of PCIE expansion modules are mounted on the chassis, the storage module comprises a plurality of backplane modules, each backplane module comprises a plurality of backplane MCIO connectors and a plurality of U.2 interfaces, the backplane MCIO connector is connected to the U.2 interface, the PCIE expansion module comprises a plurality of extended MCIO connectors and a plurality of PCIE SLOT slots, the extended MCIO connector is connected to the PCIE SLOT slots, the mainboard MCIO connector is connected to the backplane MCIO connector and / or the extended MCIO connector, and the PSU redundant power supply module is connected to the storage module and the CPU controller module.

[0007] Furthermore, the backplane module also includes a power connector, the PCIE expansion module also includes a power connector, and the mainboard also includes multiple mainboard power connectors and two PSU power connectors. The mainboard power connector is used to connect to the power connectors of the backplane module and the PCIE expansion module, and the two PSU power connectors are connected to the PSU redundant power module.

[0008] Furthermore, it also includes a heat dissipation fan module, which includes a plurality of fans and is installed on the chassis.

[0009] Furthermore, the PSU redundant power supply module adopts a 1+1 redundant structure, including a first PSU power supply module and a second PSU power supply module, and the first PSU power supply module and the second PSU power supply module are respectively connected to two PSU power supply connectors.

[0010] Furthermore, the mainboard MCIO connector is connected to the backplane MCIO connector and the extended MCIO connector through a high-speed cable.

[0011] Furthermore, the PCIE expansion module is mounted on the chassis via buckles and fixed via screws.

[0012] Compared with the prior art, the utility model has the following significant advantages: the PCIE GEN5.0 signal directly output from the CPU controller module is connected to the mainboard MCIO connector through the internal wiring, and then the PCIE GEN5.0 signal directly output from the CPU controller module can be connected to the PCIE expansion module or the backplane module through the form of a high-speed cable, and the number of PCIE GEN5.0 NVMe U.2SSD disks carried on the backplane module and the number of cards extended on the PCIE expansion module can be flexibly switched, so that the same mainboard has different or even multiple usage scenarios, and by moving the connection between the high-speed cable and the backplane MCIO connector and the extended MCIO connector, multiple application scenarios can be met, and many scenarios can be met without increasing the extra board modification time. The utility model has a high localization rate and low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a schematic diagram of a single-channel CPU server of the utility model;

[0014] Figure 2 It is a schematic diagram of the back panel module of the utility model;

[0015] Figure 3 This is the architecture diagram of the CPU controller module of the utility model;

[0016] Figure 4 This is an architectural diagram of the first PCIE expansion module of the present invention;

[0017] Figure 5 This is a schematic diagram of the second PCIE expansion module of the present invention;

[0018] Figure 6 This is an architectural diagram of the third PCIE expansion module of the present utility model;

[0019] Figure 7 The figure is an architectural diagram of a CPU controller module in the prior art.

[0020] Explanation of the accompanying drawings: 1. Storage module; 2. First backplane module; 3. Cooling fan module; 4. CPU controller module; 5. First PCIE extension module; 6. PSU redundant power supply module; 7. Third PCIE extension module; 8. Second PCIE extension module; 9. Second backplane module; 10. Third backplane module; 11. First PSU power connector; 12. First PSU power module; 13. Second PSU power module; 14. Second PSU power connector. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the utility model more clear, the utility model is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the utility model and are not used to limit the utility model.

[0022] The utility model provides a single-channel CPU server, such as Figure 1 As shown, it includes a chassis, a storage module 1, a mainboard, a PSU redundant power module 6, a cooling fan module 3 and multiple PCIE expansion modules, and the storage module 1, the mainboard, the PSU redundant power module 6, the cooling fan module 3 and the multiple PCIE expansion modules are installed on the chassis. The storage module 1 includes three backplane modules, namely the first backplane module 2, the second backplane module 9 and the third backplane module 10, each backplane module includes a power connector, four backplane MCIO connectors and four U.2 interfaces, the backplane MCIO connector is connected to the U.2 interface, and the U.2 interface is used to plug the SSD disk. The backplane module is mainly used to connect with the high-speed signal extended from the mainboard, and a 2.5 / 3.5-inch SSD or HDD disk can be installed for data storage or system disk. Multiple PCIE expansion modules include a first PCIE expansion module 5, a second PCIE expansion module 8 and a third PCIE expansion module 7. The first PCIE expansion module 5, the second PCIE expansion module 8 and the third PCIE expansion module 7 are installed on the chassis by buckles and reinforced by screws. The extended MCIO connector on the PCIE expansion module is connected to the standard PCIE SLOT slot, and then the standard RAID card, network card, graphics card, double-width card, etc. can be expanded through the PCIE SLOT slot. The motherboard includes a CPU controller module 4, twelve motherboard MCIO connectors, six motherboard power connectors and two PSU power connectors. The CPU controller module 4 includes a CPU, and the CPU controller module 4 is connected to the twelve motherboard MCIO connectors through the on-board wiring. The CPU controller module 4 can directly output the PCIE high-speed signal to the motherboard MCIO connector, and then connect the external device through the motherboard MCIO connector. The motherboard MCIO connector can be connected to the backplane MCIO connector and the extended MCIO connector through a high-speed cable. The PSU power connector is used to connect to the PSU redundant power module 6. The two PSU power connectors include a first PSU power connector 11 and a second PSU power connector 14. The PSU redundant power supply module 6 is connected to the storage module 1, the CPU controller module 4 and the cooling fan module 3, and is used to supply power to the storage module 1, the CPU controller module 4 and the cooling fan module 3. The PSU redundant power supply module 6 adopts a 1+1 redundant structure, including a first PSU power supply module 12 and a second PSU power supply module 13. The cooling fan module 3 includes five high-power fans, which are used to support the cooling system of the whole machine.

[0023] like Figure 2 As shown, the first backplane module 2, the second backplane module 9 and the third backplane module 10 are of the same form, and all include four backplane MCIO connectors and a power connector. The backplane MCIO connector is used to connect to the mainboard MCIO connector, and the power connector is used to connect to the mainboard power connector. Each backplane MCIO connector can support 2 PCIEGEN5.0 X4 SSD disks. Therefore, when the mainboard PCIE resources are sufficient, the three backplane modules can connect the mainboard MCIO connector to the backplane MCIO connector of the backplane module through a high-speed cable, and can support up to 24 NVMe SSD disks.

[0024] like Figure 3 As shown, it is a schematic diagram of the chip architecture layout of a PCB. The single-channel CPU server is directly powered by the first PSU power module 12 and the first PSU power connector 11, and the second PSU power module 13 and the second PSU power connector 14. The core system CPU controller module 4 works through level conversion. The CPLD (Complex Programmable Logic Device) is connected to the CPU controller module 4 through IO, and is mainly responsible for level conversion and timing control, signal transmission, and signal connection with the BMC controller.

[0025] It is important that the CPU controller module 4 itself contains four PCIE GEN5.0 X16 signals and four PCIE GEN5.0 X8 signals, which are led out to twelve motherboard MCIO connectors in the motherboard through on-board wiring. In this embodiment, the twelve motherboard MCIO connectors in the motherboard are connected to the backplane module or PCIE expansion module through high-speed cables.

[0026] like Figures 4-5As shown, the first PCIE expansion module 5 is a left PCIE expansion module, including a power connector, three extended MCIO connectors and two PCIE SLOT slots, and the three extended MCIO connectors all support PCIE GEN5.0 X8 signals. From the signal perspective, two of the extended MCIO connectors are connected to a PCIE SLOT slot, and the respective PCIE GEN5.0 X8 signals are connected to the PCIE SLOT slot, and the PCIE GEN5.0 X16 signal is synthesized, so the PCIE SLOT slot can support a card with a PCIE GEN5.0 X16 signal. Another extended MCIO connector is connected to a PCIE SLOT slot, and the PCIE SLOT slot can support a card with a PCIE GEN5.0 X8 signal. From the perspective of quantity, the first PCIE expansion module 5 can support a single double-width PCIE card and a single single-width PCIE card. The second PCIE expansion module 8 is a left PCIE expansion module, and its structure is the same as that of the first PCIE expansion module 5.

[0027] like Figure 6 As shown, the third PCIE expansion module 7 is a right PCIE expansion module, including a power connector, two expansion MCIO connectors and two PCIE SLOT slots, and the two expansion MCIO connectors are respectively connected to the two PCIE SLOT slots. Both expansion MCIO connectors support PCIE GEN5.0 X8 signals. From a signal perspective, the PCIE GEN5.0 X8 signal of an expansion MCIO connector is connected to a PCIE SLOT slot, so a PCIE SLOT slot can support a card with a PCIE GEN5.0 X8 signal. From a quantity perspective, the third PCIE expansion module 7 can support a single double-width PCIE card and a single single-width PCIE card.

[0028] like Figure 7 As shown in the figure, the existing design layout is basically to directly output the PCIE signal from the CPU and then connect it to the PCIE SLOT slot through the internal wiring of the board. According to the PCIE resources of the CPU, 8 PCIE SLOT slots can be derived. When the scenario 1: 3 double-width cards and 9 SSD disks are required, the requirements can be met, that is, 3 double-width cards will occupy 6 PCIE SLOT slots; 9 SSD disks need to be inserted into Figure 7The remaining two PCIE SLOT slots are connected to storage module 1 through high-speed cables. Although this layout can meet the needs, it also indirectly increases the cost of two PCIE expansion cards. Since the PCIE expansion cards are not domestically produced, they also bring negative impacts. When scenario 2: 3 double-width cards and 17 SSD disks are required, the requirements cannot be met.

[0029] This example is aimed at scenario 1: requiring 3 double-width cards and 9 SSD disks. Figure 3 The five motherboard MCIO connectors are connected in sequence through high-speed cables Figure 2 The five backplane MCIO connectors on the first backplane module 2 and the second backplane module 9 in the embodiment of the present invention are connected. Figure 3 The two motherboard power connectors in the Figure 2 The two power connectors on the first backplane module 2 and the second backplane module 9 can meet the needs of 9 SSD disks. Figure 3 The two motherboard MCIO connectors in the Figure 4 The two expansion MCIO connectors connected to the same PCIE SLOT slot; Figure 3 The two motherboard MCIO connectors in the Figure 5 The two expansion MCIO connectors connected to the same PCIE SLOT slot; Figure 3 A motherboard MCIO connector is connected to the Figure 6 An expansion MCIO connector in Figure 3 The three motherboard power connectors are connected to the Figures 4 to 6 This approach can meet the needs of three double-width cards.

[0030] For scenario 2: 3 double-width cards and 17 SSDs are required. Figure 3 The nine mainboard MCIO connectors are connected in sequence through high-speed cables Figure 2 The nine backplane MCIO connectors on the first backplane module 2, the second backplane module 9 and the third backplane module 10. Figure 3 The three motherboard power connectors are connected to the Figure 2 This method can meet the needs of 17 SSDs. Figure 3 The three motherboard MCIO connectors are connected to the Figure 4 One of the expansion MCIO connectors in Figure 5 One of the expansion MCIO connectors in Figure 6 One of the expansion MCIO connectors in Figure 3 The three motherboard power connectors are connected to the Figures 4 to 6 This method can meet the scenario of 3 PCIE GEN5.0 X8 double-width cards.

[0031] The hardware architecture layout for single-channel CPU rack-mounted services uses the PCIE GEN5.0 signal directly output from the CPU, which is directly connected to the mainboard MCIO connector through the internal wiring, and then connected to the mainboard MCIO connector led out from the mainboard through an external high-speed cable, connecting the high-speed PCEI GEN5.0 signal to the PCIE expansion module or storage module 1, and flexibly switching according to different needs.

[0032] The above-mentioned embodiments only express one or several implementation methods of the utility model, and the description is relatively specific and detailed, but it cannot be understood as limiting the scope of the utility model patent. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the utility model, which all belong to the protection scope of the utility model. Therefore, the protection scope of the utility model patent shall be based on the attached claims.

Claims

1. A single-channel CPU server, characterized in that: The invention comprises a chassis, a storage module, a mainboard, a PSU redundant power supply module and a plurality of PCIE extension modules, wherein the mainboard comprises a CPU controller module and a plurality of mainboard MCIO connectors, the CPU controller module comprises a CPU, the CPU controller module is connected to a plurality of mainboard MCIO connectors through on-board wiring, the storage module, the mainboard, the PSU redundant power supply module and a plurality of PCIE extension modules are installed on the chassis, the storage module comprises a plurality of backplane modules, each backplane module comprises a plurality of backplane MCIO connectors and a plurality of U.2 interfaces, the backplane MCIO connector is connected to the U.2 interface, the PCIE extension module comprises a plurality of extended MCIO connectors and a plurality of PCIE SLOT slots, the extended MCIO connector is connected to the PCIE SLOT slots, the mainboard MCIO connector is connected to the backplane MCIO connector and / or the extended MCIO connector, and the PSU redundant power supply module is connected to the storage module and the CPU controller module.

2. The single-channel CPU server according to claim 1, characterized in that: The backplane module also includes a power connector, the PCIE expansion module also includes a power connector, and the mainboard also includes multiple mainboard power connectors and two PSU power connectors. The mainboard power connector is used to connect to the power connectors of the backplane module and the PCIE expansion module, and the two PSU power connectors are connected to the PSU redundant power module.

3. The single-socket CPU server according to claim 1, characterized in that: It also includes a heat dissipation fan module, which includes a plurality of fans and is installed on the chassis.

4. The single-channel CPU server according to claim 2, characterized in that: The PSU redundant power supply module adopts a 1+1 redundant structure, and includes a first PSU power supply module and a second PSU power supply module, wherein the first PSU power supply module and the second PSU power supply module are respectively connected to two PSU power supply connectors.

5. The single-socket CPU server according to claim 1, characterized in that: The mainboard MCIO connector is connected to the backplane MCIO connector and the extended MCIO connector through a high-speed cable.

6. The single-socket CPU server according to claim 1, characterized in that: The PCIE expansion module is mounted on the chassis via buckles and fixed via screws.

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