Multi-redundancy architecture test system based on time-triggered protocol bus
By designing a multi-redundant architecture test system based on time-triggered protocol bus, the shortcomings of TTP bus in the prior art test and verification in terms of security and multi-redundant applications are solved, and more efficient and effective TTP application test and verification effects are achieved.
Patent Information
- Application Number
- CN202420752100.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-12
- Publication Date
- 2025-04-01
- Estimated Expiration
- 2034-04-12
AI Technical Summary
There is a lack of effective trial and verification schemes in the prior art to improve the performance of Time Trigger Protocol Bus (TTP) in terms of security level and multi-redundant channel system applications.
A multi-redundant architecture test system based on the time-triggered protocol bus is designed. The system includes multiple single-limit test subsystems, each subsystem includes a communication node and a simulation node. The communication node supports the TTP bus protocol. The simulation node and the communication node form a daisy-chain bus topology, which is used to provide multi-faceted tests and verifications.
The system provides a multi-redundancy TTP bus test solution, which can effectively improve the effectiveness and efficiency of TTP application testing and verification, and ensure the performance improvement of TTP bus in security and multi-redundancy applications.
Smart Images
Figure CN222706522U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of communication technology, and in particular to a multi-redundancy architecture test system based on a time-triggered protocol bus. Background Art
[0002] In the existing technology, bus communication has received increasing attention in many fields of production and life. For example, with the continuous development of aircraft research and development, the overall performance improvement of aircraft has put forward higher requirements for airborne systems. Among them, airborne data bus technology has become one of the key technologies in aircraft design due to its rapid development. Accordingly, how to achieve stable and efficient support of airborne systems such as engines, power supplies, flight control, and environmental control by the airborne data bus, and how to achieve more timely, accurate, and reliable processing of bus communication requirements in aircraft work have become topics that urgently need to be weighed in aircraft design.
[0003] Traditional event-triggered buses, such as the CAN bus, have the defects of low data communication efficiency, small bus bandwidth, and poor real-time performance, which can easily cause bus congestion and other problems.
[0004] The time triggered protocol (TTP) is a high-determinism and high-security communication bus protocol based on time triggering. The TTP bus has strict determinism based on time triggering, and the delay can be controlled within 20us and the jitter can be controlled within 5us. The dual redundant channels, node guardian, CNI architecture, etc. of the TTP bus can provide high security for key systems that use the TTP bus. Therefore, the TTP bus provides a superior performance and distinctive feature selection solution for data communication needs with high security requirements, especially airborne system data communication needs. At present, the TTP bus has been widely used in safety-critical systems in the aerospace field, including cabin pressure control systems, electrical systems and environmental control systems.
[0005] Although the TTP bus has high application value, there is still a lack of effective testing and verification solutions in terms of how to improve its security level and how to apply multi-redundant channel systems. Utility Model Content
[0006] The embodiments of this specification provide a multi-redundant architecture test system based on a time-triggered protocol bus to solve the technical problem of how to conduct TTP application testing and verification more effectively and efficiently.
[0007] To solve the above technical problems, the embodiments of this specification provide the following technical solutions:
[0008] The embodiment of the present specification provides a multi-redundancy architecture test system based on a time-triggered protocol bus, the system comprising a plurality of single redundancy test subsystems; the single redundancy test subsystem comprises:
[0009] Communication nodes, each communication node supports the TTP bus protocol, is used to form a message description table for TTP communication, and is managed by the host computer;
[0010] A simulation node, wherein the simulation node has a protocol layer and a physical layer interface consistent with each of the communication nodes, is used to provide simulation of the communication node, and is managed by a host computer;
[0011] The simulation node and each of the communication nodes form a daisy chain bus topology.
[0012] Optionally, the communication node accepting management from the host computer includes: the host computer performing network configuration and / or application information loading and / or working status monitoring on the communication node.
[0013] Optionally, the simulation node accepting management from the host computer includes: the host computer developing and / or configuring and / or monitoring node device applications or network communications for the simulation node.
[0014] Optionally, the single redundancy test subsystem also includes a monitoring node supporting the TTP bus protocol.
[0015] Optionally, the simulation node and each communication node of a single redundancy test subsystem are led out to a distribution board through an interface.
[0016] Optionally, the simulation node and each communication node of each single redundancy test subsystem are integrated in a cabinet.
[0017] Optionally, the cabinet is provided with a spare patch panel for accessing communication nodes and / or simulation nodes and / or airborne system real equipment supporting TTP communication and / or TTP bus fault injection equipment and / or TTP bus monitoring equipment and bypass equipment.
[0018] Optionally, the cabinet is provided with a spare patch panel interface for realizing a physical connection with other cabinets in the TTP network.
[0019] Optionally, the cabinet uses a PDU module to power the components therein.
[0020] Optionally, a single single redundancy test subsystem includes four communication nodes and one simulation node.
[0021] At least one of the above technical solutions adopted in the embodiments of this specification can achieve the following beneficial effects:
[0022] A multi-redundancy TTP bus test solution is provided, which can conduct multi-faceted tests and verifications on the TPP bus, effectively improving the effect and efficiency of TTP application tests and verifications. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] In order to more clearly illustrate the technical solutions in the embodiments of this specification or the prior art, the drawings required for use in the embodiments of this specification or the prior art description are briefly described below. Obviously, the following only describes the drawings required for use in some embodiments of this application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor.
[0024] Figure 1 It is a schematic diagram of the architecture of the single redundancy test subsystem in the first embodiment of this specification.
[0025] Figure 2 This is a schematic diagram of node integration in the first embodiment of this specification.
[0026] Figure 3 This is a schematic diagram of the daisy chain topology in the first embodiment of this specification.
[0027] Figure 4 It is a schematic diagram of a multi-redundant architecture in the first embodiment of this specification. DETAILED DESCRIPTION
[0028] In order to enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments involved in the specific implementation methods are only part of the embodiments of this application, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the specific implementation methods without making creative work should belong to the scope of protection of this application.
[0029] The first embodiment of this specification (hereinafter referred to as "embodiment 1") provides a multi-redundancy architecture test system based on a time-triggered protocol bus, the system comprising a plurality of single redundancy test subsystems; the single redundancy test subsystem comprises:
[0030] Communication nodes, each communication node supports the TTP bus protocol, is used to form a message description table for TTP communication, and is managed by the host computer;
[0031] A simulation node, wherein the simulation node has a protocol layer and a physical layer interface consistent with each of the communication nodes, is used to provide simulation of the communication node, and is managed by a host computer;
[0032] The simulation node and each of the communication nodes form a daisy chain bus topology.
[0033] The following is a further description of the single redundancy test subsystem:
[0034] like Figure 1 As shown, each single redundancy test subsystem may include a communication node (also referred to as a computing node or a TTP computing node or a TTP processing device or a TTP communication node) and a simulation node (also referred to as a TTP simulation node or a TTP simulation device). Each single redundancy test subsystem may include multiple communication nodes.
[0035] For a single single redundancy test subsystem, each communication node includes it supports the TTP bus protocol, each communication node is used to form a message description table for TTP communication, and accepts the management of the host computer (also referred to as the host computer workstation, the same below). Specifically, the communication node is a device that supports the TTP bus protocol (including but not limited to a computer or server or control device), and each communication node, as a node unit in the bus communication network, forms a message description table for TTP communication together with other communication nodes in the same single redundancy test subsystem. Each communication node can represent a computer or server in reality or a distributed control device with communication requirements. For example, the communication node can represent a distributed control device such as FCM / ACE or a flight control computer or a similar distributed control device with communication requirements in the work of a real aircraft system.
[0036] Exemplarily, when applied in aircraft-related fields, the communication node has the following characteristics:
[0037] The communication node supports the SAE AS6003 standard protocol and has a chip or FPGA device that complies with AS8202 as a TTP node controller for flight control electronic equipment. The communication node has a CPU that can implement embedded application information processing to achieve a development environment similar to that of the flight control electronic processor. The communication node has interfaces such as RJ45 to implement physical layer cable communication based on the RS485 protocol. The communication node has a memory composed of RAM, SRAM and FLASH to realize the storage and operation of messages and application data. The communication node has a suitable power module to power the components.
[0038] For a single single redundancy test subsystem, the simulation node includes a TTP bus protocol, and has a protocol layer and physical layer interface consistent with the communication node, which is used to provide simulation of the communication node, including but not limited to providing simulation at the same TTP protocol communication mechanism level as the communication node, and accepting the management of the host computer. Among them, a single simulation node can simulate multiple communication nodes at the same time, and usually a single simulation node is used to simulate each communication node in the same single redundancy test subsystem.
[0039] In the first embodiment, a single redundancy test subsystem may include multiple communication nodes and one simulation node (but not limited to), for example, four communication nodes and one simulation node. Figure 1 The simulation node can simulate multiple communication nodes of the same single redundancy test subsystem.
[0040] Specifically, the simulation node is a device that supports the TTP bus protocol (including but not limited to a computer or a server or a control device), and the simulation node can represent a distributed control device such as FCM / ACE.
[0041] For example, when applied in the field of aircraft, the simulation node does not need to have a real CPU and cache components similar to flight control electronics, but directly simulates the behavior and configuration method of the TTP node (including the communication node) through the host workstation. In addition, the simulation node has a physical layer interface that supports RS485 based on Manchester encoding.
[0042] In the first embodiment, a single single redundancy test subsystem may be equipped with or include a host computer, and the communication nodes and / or simulation nodes of the same single redundancy test subsystem are managed by the host computer of the same single redundancy test subsystem. Wherein, the communication node being managed by the host computer may include: the host computer performing network configuration and / or application information loading and / or working status monitoring on the communication node; and / or the simulation node being managed by the host computer may include: the host computer performing node device (including the simulation node itself) application program or network communication development and / or configuration and / or monitoring on the simulation node.
[0043] like Figure 1 As shown, the single redundancy test subsystem may also include a monitoring node supporting the TTP bus protocol (also referred to as a TTP monitoring node). The monitoring node is used to read the signals transmitted on the bus in real time, so that relevant personnel can understand the communication transmission characteristics and function realization of the tested bus architecture scheme, including the single redundancy test subsystem, in real time. The monitoring node can be selected from suitable devices, including but not limited to computers or servers or other devices with data processing functions.
[0044] A specific installation or architecture example is provided below (not intended to limit the first embodiment):
[0045] For a single redundancy test subsystem, its multiple communication nodes can be integrated on an integrated rack or other suitable components, and integrated in a cabinet (a standard cabinet can be used, such as a 42U laboratory cabinet or similar device), and the simulation node, monitoring node and host computer of the single redundancy test subsystem can also be integrated in the same cabinet. Figure 2In the present invention, each communication node of a single redundancy test subsystem is integrated in the chassis. In addition, the monitoring node of the same single redundancy test subsystem can also be integrated in the chassis.
[0046] In the cabinet, the simulation node and each communication node of a single single redundancy test subsystem are led out to the distribution board through an interface. Specifically, the simulation node and each communication node may be led out to the RJ45 distribution board through an RJ45 interface.
[0047] The simulation node and each communication node of a single redundancy test subsystem can form a daisy chain bus topology. For example, the simulation node and each communication node form a daisy chain bus topology through a Category 5e Ethernet cable, that is, each communication node on a bus is connected in sequence, and a certain communication node is connected to the simulation node. Each node has a physical input interface and a physical output interface. The physical output interface of the previous node is connected to the physical input interface of the next node. For example Figure 3 As shown. The monitoring node of the same single redundancy test subsystem can be installed at the end of the bus in a daisy chain connection mode. It has a physical input interface in the form of RJ45 and a physical output interface in the form of RJ45. The physical input interface of the monitoring node is connected to a TTP communication node (which can be an installed integrated structure, the previous TTP communication node of the monitoring node, the same below) through a transmission cable, and the physical output interface of the monitoring node is connected to the 120Ω impedance terminal at the end of the bus. When multiple single redundancy test subsystems are interconnected to form a multi-redundant physical bus network (described below), the physical input interface of the monitoring node of one of the single redundancy test subsystems is connected to the previous TTP communication node through a transmission cable, and the physical output interface of the monitoring node is connected to the 120Ω impedance terminal at the end of the bus. In each of the remaining single redundancy test subsystems, the physical input interface of the monitoring node is connected to a TTP communication node through a transmission cable, and the physical output interface of the monitoring node is connected to the simulation node, as shown in FIG. Figure 3 shown.
[0048] Each communication node of a single single redundancy test subsystem can communicate with the host computer. For example, each communication node is connected to the Ethernet network through an N-port and a multi-port switch device, and communicates with the host computer (also referred to as a host computer workstation). The host computer can deploy and support related software, and the functions of the software include but are not limited to TTP development, configuration, loading and monitoring. In this way, the network layer communication between the underlying hardware device (communication node) and the host computer software supporting TTP is realized, and the host computer (host computer software) can perform network configuration and / or application information loading and / or work status monitoring on the communication node.
[0049] Similarly, the simulation node of a single single redundancy test subsystem can communicate with the host computer. For example, the simulation node communicates directly with the host computer through a PCIe bridge, so that the host computer can be used to develop and / or configure and / or monitor node device applications or network communications for the simulation node.
[0050] Through the above-mentioned single-redundancy test subsystem, a single-redundancy multi-node communication network (maximum topology network) can be formed. For example, if the single-redundancy test subsystem includes four communication nodes and one simulation node, a semi-physical simulation of a single-redundancy 8-node communication network (four communication nodes + four communication nodes that can be simulated by the simulation node, these 8 nodes can represent a flight control electronic communication network consisting of more than three main flight control computers and four actuator control electronic computers) can be formed, and the formed single-redundancy 8-node topology network can meet or be applied to the configuration of various OEM flight control electronics. For example Figure 1 , Figure 3 and Figure 4 As shown, each single redundancy test subsystem forms a network of 8 nodes. Of course, the number of communication nodes and simulation nodes included in the single redundancy test subsystem can vary, the number of communication nodes that can be simulated by the simulation node can vary, and thus the number of communication network nodes can vary.
[0051] In the first embodiment, the cabinet can be provided with a spare patch panel (e.g., an RJ45 patch panel) for accessing other communication nodes and / or simulation nodes and / or devices supporting TTP communication (e.g., various airborne system real equipment, such as a main flight control computer and other airborne system real equipment) and / or TTP bus fault injection equipment and / or TTP bus monitoring equipment and bypass equipment. The connected components or equipment may have or additionally have an interface corresponding to the patch panel (e.g., an RJ45 interface).
[0052] Of course, the cabinet may also include other devices, which are not specifically limited in the first embodiment.
[0053] In the first embodiment, there may be multiple (for example, three) single redundancy test subsystems, a single redundancy test subsystem is integrated in a cabinet, the communication nodes and simulation nodes of the single redundancy test subsystem form a TTP node network, and the single redundancy test subsystems can be connected or communicated with each other to form a multi-redundant physical bus network. Figure 3 In FIG. 3 , three groups of communication nodes and three groups of simulation nodes are shown, which can form three single-redundancy test subsystems; Figure 4The specific connection architecture examples of each node of the three single redundancy test subsystems are given. For example, each cabinet can be provided with a spare patch panel interface (such as an RJ45 patch panel interface, and can be provided with a suitable cable, such as a Category 5e network cable supporting RS485), so that the physical connection of the TTP network with other cabinets can be realized (specifically, it can be connected with the communication nodes and / or simulation nodes of other cabinets), thus realizing the connection and communication between the single redundancy test subsystems.
[0054] The cabinet can use PDU modules to power its internal components, including communication nodes, simulation nodes, host computers, switches and other devices, and can use UPS power to ensure stable and continuous power quality. Standard power cables can also be used to power the components in the cabinet through the mains. The three bottom lines of the cabinet are equipotential bottom lines and are independently grounded.
[0055] In addition, the cabinet can be moved and fixed using cabinet universal wheels with locking devices.
[0056] The following is a specific application example of Embodiment 1 (not intended to limit Embodiment 1):
[0057] For example, during the development of a certain type of aircraft, a bus communication scheme for the node equipment of the flight control system consisting of the main flight control computer (PFC) and the actuator control electronic computer (ACE) was proposed. On this basis, the communication nodes and simulation nodes of a single single redundancy test subsystem are connected according to the above content (each communication node or simulation node represents a PFC or ACE), and the application program that the PFC or ACE should execute is burned into the memory of each communication node or simulation node through the host computer, such as control law solution, actuation instruction settlement, etc. In this way, through the single redundancy test subsystem, the effect of TTP bus communication can be simulated to verify whether the proposed bus communication scheme meets the bandwidth requirements of the flight control system, whether it meets the real-time requirements and instruction integrity requirements of the flight control system, and verify the reliability and safety performance of the bus communication scheme when dealing with faults.
[0058] Embodiment 1 can achieve the following beneficial effects:
[0059] In the first embodiment, each single redundancy test subsystem provides a redundancy, and a multi-redundancy TTP bus test scheme and test configuration are formed through multiple single redundancy test subsystems, which can perform multi-faceted tests and verifications on the TPP bus, effectively improving the effect and efficiency of TTP application tests and verifications.
[0060] In the first embodiment, the single redundancy test subsystem has an independent and complete hardware architecture and working closed loop, and can independently realize the TTP bus development and simulation test functions, including but not limited to judging the working status of each node under the TTP bus network, testing the information exchanged between each avionics system, detecting bus conflicts, data loss and other errors and situations that do not comply with protocol specifications.
[0061] Embodiment 1 can be applied to TTP bus development and simulation testing in various fields. For example, in the process of airborne system bus solution development, design and verification, the time-triggered protocol (TTP) bus-related experimental work can be applied to realize the TTP bus development and simulation testing of airborne systems, including the functions / effects of simulation development and function / performance verification of single / dual / triple redundant architecture solutions of TTP-based flight control system buses.
[0062] Among them, the first embodiment can make full use of simulation nodes and TTP controller nodes (i.e., communication nodes), and through embedded real-time TTP node devices (i.e., communication nodes) and TTP simulation devices (i.e., simulation nodes, which can simulate multiple communication nodes at the same time), the maximum network topology that meets the flight control electronic architecture of various civil aircraft is formed with as few resources as possible. Each single redundancy test subsystem can provide the test task requirements of 8 nodes, which can simultaneously meet the maximum topology requirements of flight control electronics, and can meet the needs of node and redundancy simulation verification contained in the architecture of flight control electronics of various fly-by-wire flight control systems. In addition, the first embodiment provides multiple single redundancy test subsystems, which can perform multi-redundant TTP bus network tests, including a trade-off test of a flight control bus architecture solution with no less than three redundancies. In addition, the first embodiment can be used as a semi-physical simulation tool for an airborne system architecture solution to test and verify the communication function, signal integrity, bus utilization, fault shielding capability, and countermeasure strategy of the airborne system architecture solution.
[0063] In Example 1, an embedded processor node (communication node) supporting TTP, a monitoring node supporting TTP, and a simulation node supporting TTP are used as computing hardware carriers for the test simulation. Physical layer communication or connection between nodes is achieved through RJ45 patch panels and Category 5e network cables, and network layer communication between underlying hardware devices and upper computer software supporting TTP is achieved through Nports, switch devices, etc., effectively ensuring the stability of the test.
[0064] In the first embodiment, the hardware device of the RJ45 patch panel and the switch and the topological configuration of the daisy chain provide a reconstruction space for the subsequent test configuration reorganization and the access of the test equipment.
[0065] The above installation or connection structures are examples and are not intended to limit the first embodiment.
[0066] The above is only an embodiment of this specification and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims
1. A multi-redundant architecture test system based on a time-triggered protocol bus, characterized in that: The system includes a plurality of single redundancy test subsystems; the single redundancy test subsystem includes: Communication nodes, each communication node supports the TTP bus protocol, is used to form a message description table for TTP communication, and is managed by the host computer; A simulation node, wherein the simulation node has a protocol layer and a physical layer interface consistent with each of the communication nodes, is used to provide simulation of the communication node, and is managed by a host computer; The simulation node and each of the communication nodes form a daisy chain bus topology.
2. The system according to claim 1, characterized in that The communication node accepting management from the host computer includes: the host computer performing network configuration and / or application information loading and / or working status monitoring on the communication node.
3. The system according to claim 1 or 2, characterized in that: The simulation node accepts management of the host computer including: the host computer develops and / or configures and / or monitors the node device application or network communication of the simulation node.
4. The system according to claim 1, characterized in that The single redundancy test subsystem also includes a monitoring node supporting the TTP bus protocol.
5. The system according to claim 1, characterized in that The simulation node and each communication node of the single redundancy test subsystem are led out to the distribution board through an interface.
6. The system according to claim 1, wherein: The simulation node and each communication node of each single redundancy test subsystem are integrated in a cabinet.
7. The system according to claim 6, characterized in that The cabinet is provided with a spare patch panel for accessing communication nodes and / or simulation nodes and / or airborne system real equipment supporting TTP communication and / or TTP bus fault injection equipment and / or TTP bus monitoring equipment and bypass equipment.
8. The system according to claim 6 or 7, characterized in that The cabinet is provided with a spare patch panel interface for realizing a physical connection with other cabinets in a TTP network.
9. The system according to claim 6 or 7, characterized in that The cabinet uses a PDU module to power the components therein.
10. The system according to claim 1, wherein: A single single redundancy test subsystem includes four communication nodes and one simulation node.