Current limiting drive circuit and electronic equipment

Abstract

A current limiting driving circuit and electronic equipment belong to the field of electronic technology. A sampling circuit samples the output current of a power supply circuit to output the sampled current; a comparison circuit compares the sampled current with a preset current and outputs a comparison signal according to the comparison result; a logic circuit accesses a first control signal and responds to the rising edge of the first control signal to convert the first control signal into a second control signal according to the comparison signal; a driving circuit outputs a driving signal according to the second control signal to drive the power supply circuit; because the logic circuit outputs the second control signal in response to the rising edge of the first control signal, the possibility of the driving circuit directly outputting a narrow pulse driving signal when the current limiting is released is reduced, the possibility of the narrow pulse affecting the device stress in the power supply circuit is effectively reduced, and the reliability of the circuit is improved.

Description

Technical Field

[0001] The present application belongs to the field of electronic technology, and in particular relates to a current limiting driving circuit and an electronic device. Background Art

[0002] For the software current limiting method of clearing the current limiting signal through the input / output port (IO), if the number of current limiting signals is greater than the current limiting resources of the control chip, if the excess current limiting signals continue to use software current limiting, the program will need to actively clear the fault signal. The action time of this behavior will cause the current to drop too much, and the uninterruptible power supply equipment based on average current control cannot achieve the ideal control effect. When the equipment is loaded, it will cause the equipment to absorb insufficient energy from the power grid, resulting in state switching failure, forced power-off and other problems of the working equipment. For this reason, the control chip with more current limiting resources must be replaced, but the replacement control chip is expensive, which increases the cost.

[0003] In order to solve the above technical problems, the existing technical solution realizes current limiting through the traditional external hardware current limiting circuit. Specifically, the current limiting purpose can be achieved by turning off the driving signal. However, after the current limiting signal disappears in the relevant external hardware current limiting circuit, the driving signal will be turned on immediately, which will cause a narrow pulse drive when the current limiting is released, and the current will rise sharply, resulting in excessive stress on electronic components, thereby damaging the electronic equipment. Utility Model Content

[0004] The purpose of the present application is to provide a current limiting drive circuit and an electronic device, aiming to solve the problem that when the related current limiting drive circuit stops limiting current, there is a narrow pulse drive, which causes excessive stress on electronic components and further damages the electronic device.

[0005] The embodiment of the present application provides a current limiting driving circuit connected to a power supply circuit, wherein the current limiting driving circuit comprises:

[0006] a sampling circuit, connected to the power circuit, and configured to sample the output current of the power circuit to output a sampled current;

[0007] A comparison circuit, connected to the sampling circuit, configured to compare the sampled current with a preset current and output a comparison signal according to a comparison result;

[0008] a logic circuit connected to the comparison circuit, configured to receive a first control signal, and in response to a rising edge of the first control signal, convert the first control signal into a second control signal according to the comparison signal; wherein both the first control signal and the second control signal are periodic signals;

[0009] The driving circuit is connected to the logic circuit and the power circuit, and is configured to output a driving signal according to the second control signal to drive the power circuit.

[0010] In one embodiment, the logic circuit comprises:

[0011] a logic module, configured to receive the first control signal, and output a first logic signal according to the comparison signal in response to a rising edge of the first control signal;

[0012] The NAND gate module is connected to the logic module and is configured to perform a NAND operation on the first control signal and the first logic signal to output the second control signal.

[0013] In one embodiment, the logic module includes a D flip-flop or a JK flip-flop.

[0014] In one embodiment, the logic module includes the D flip-flop, a fifth resistor and a sixth resistor;

[0015] The first end of the sixth resistor serves as the first control signal input end of the logic module to input the first control signal; the reset end of the D flip-flop serves as the comparison signal input end of the logic module and is connected to the comparison circuit to input the comparison signal; the second end of the sixth resistor is connected to the clock input end of the D flip-flop, the data input end of the D flip-flop is connected to the set end of the D flip-flop and the first end of the fifth resistor, the in-phase output end of the D flip-flop serves as the first logic signal output end of the logic module and is connected to the NAND gate module to output the first logic signal; the second end of the fifth resistor is connected to the first power supply; or

[0016] The logic module includes the JK trigger, a fifth resistor and a sixth resistor;

[0017] The first end of the sixth resistor serves as the first control signal input end of the logic module to input the first control signal; the reset end of the JK trigger serves as the comparison signal input end of the logic module and is connected to the comparison circuit to input the comparison signal; the second end of the sixth resistor is connected to the clock input end of the JK trigger, the first input control end of the JK trigger is connected to the set end of the JK trigger and the first end of the fifth resistor, the in-phase output end of the JK trigger serves as the first logic signal output end of the logic module and is connected to the NAND gate module to output the first logic signal; the second end of the fifth resistor is connected to the first power supply; and the second input control end of the JK trigger is connected to the power ground.

[0018] In one embodiment, the current limiting driving circuit further includes:

[0019] A unidirectional conduction circuit, connected to the comparison circuit, configured to conduct unidirectional conduction to the comparison signal;

[0020] The control circuit is connected to the one-way conduction circuit and is configured to execute a corresponding action in response to the comparison signal after the one-way conduction lasting for a preset time period.

[0021] In one embodiment, the comparison circuit and the control circuit are integrated in the same microprocessor.

[0022] In one embodiment, the current limiting driving circuit further includes:

[0023] an amplifier circuit, connected to the logic circuit and configured to amplify the first control signal;

[0024] The logic circuit is specifically configured to receive the amplified first control signal, and in response to a rising edge of the amplified first control signal, convert the amplified first control signal into a second control signal according to the comparison signal.

[0025] In one embodiment, the amplifying circuit includes a second NAND gate, a first transistor, a first resistor, a second resistor and a third resistor;

[0026] The first end of the first resistor serves as the first control signal input end of the amplifier circuit to input the first control signal; the second end of the first resistor is connected to the first end of the second resistor and the base of the first transistor, the collector of the first transistor is connected to the first end of the third resistor, the first input end of the second NAND gate and the second input end of the second NAND gate, the output end of the second NAND gate serves as the amplified first control signal output end of the amplifier circuit, and is connected to the logic circuit to output the amplified first control signal; the second end of the second resistor and the emitter of the first transistor are commonly connected to the power ground.

[0027] In one embodiment, the comparison circuit includes a comparator, a first diode, a second diode, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, and a capacitor;

[0028] The first end of the eleventh resistor is used as a sampling current input end of the comparison circuit, and is connected to the sampling circuit to input the sampling current; the first end of the tenth resistor is used as a preset current input end of the comparison circuit to input the preset current; the second end of the tenth resistor is connected to the first end of the twelfth resistor and the non-inverting input end of the comparator, the second end of the eleventh resistor is connected to the first end of the capacitor and the inverting input end of the comparator, the second end of the twelfth resistor is connected to the first end of the thirteenth resistor, the output end of the comparator and the positive electrode of the first diode, the cathode of the first diode, the anode of the second diode and the first end of the fourteenth resistor are used together as a comparison signal output end of the comparison circuit, and are connected to the logic circuit to output the comparison signal; the cathode of the second diode and the second end of the thirteenth resistor are connected together to the first power supply, and the second end of the capacitor and the second end of the fourteenth resistor are connected together to the power ground.

[0029] An embodiment of the present application further provides an electronic device, which includes the above-mentioned current limiting driving circuit.

[0030] The beneficial effect of the embodiments of the present application compared with the prior art is: since the logic circuit outputs the second control signal in response to the rising edge of the first control signal, when the current limiting is stopped, even if the first control signal is in the middle of an output cycle, the logic circuit will not immediately output the second control signal corresponding to the cycle, thereby reducing the possibility of the driving circuit directly outputting a narrow pulse driving signal when the current limiting is stopped, effectively reducing the possibility of the narrow pulse affecting the device stress in the power supply circuit, and improving the reliability of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical application in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0032] Figure 1 A schematic diagram of a structure of a current limiting driving circuit provided in an embodiment of the present application;

[0033] Figure 2 Another structural schematic diagram of a current limiting driving circuit provided in an embodiment of the present application;

[0034] Figure 3 Another structural schematic diagram of a current limiting driving circuit provided in an embodiment of the present application;

[0035] Figure 4Another structural schematic diagram of a current limiting driving circuit provided in an embodiment of the present application;

[0036] Figure 5 A partial exemplary circuit schematic diagram of a current limiting driving circuit provided in an embodiment of the present application;

[0037] Figure 6 Another partial exemplary circuit schematic diagram of a current limiting drive circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0039] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0040] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0041] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0042] Figure 1 The structure diagram of the current limiting driving circuit provided by an embodiment of the present application is shown. For the convenience of explanation, only the part related to the present embodiment is shown, which is described in detail as follows:

[0043] The above-mentioned current limiting driving circuit is connected to the power supply circuit 500 , and the power supply circuit 500 is used to convert the input voltage VIN to output the output current; the current limiting driving circuit includes a sampling circuit 100 , a comparison circuit 200 , a logic circuit 300 and a driving circuit 400 .

[0044] The sampling circuit 100 is connected to the power circuit 500 and is configured to sample the output current of the power circuit to output the sampled current.

[0045] The comparison circuit 200 is connected to the sampling circuit 100 and is configured to compare the sampled current with a preset current and output a comparison signal according to the comparison result.

[0046] The logic circuit 300 is connected to the comparison circuit 200 and is configured to receive the first control signal control and, in response to the rising edge of the first control signal control, convert the first control signal control into a second control signal according to the comparison signal; wherein both the first control signal and the second control signal are periodic signals. The periodic signal may be a PWM signal.

[0047] The driving circuit 400 is connected to the logic circuit 300 and the power circuit 500 , and is configured to output a driving signal according to the second control signal to drive the power circuit 500 .

[0048] In a specific implementation, the comparison circuit 200 is specifically configured to output a comparison signal in response to the sampling current being less than or equal to the preset current.

[0049] In actual use, the power supply circuit 500 can be a rectifier circuit, which is used to rectify the input voltage VIN to output the output current; the power supply circuit 500 can also be an inverter circuit, which is used to invert the input voltage VIN to output the output current.

[0050] It should be noted that the preset current can be set according to actual needs. For example, the voltage corresponding to the preset current can be output by the control circuit 800. By adjusting the voltage, different current limiting points can be adjusted to adapt to devices with different power, thereby improving the versatility of the circuit.

[0051] Since the logic circuit 300 outputs the second control signal in response to the rising edge of the first control signal control, the possibility of the drive circuit 400 directly outputting a narrow pulse drive signal when the current limiting is released is reduced, thereby effectively reducing the possibility of the narrow pulse affecting the device stress in the power supply circuit 500 and improving the reliability of the circuit.

[0052] By way of example and not limitation, Figure 2 As shown, the logic circuit 300 includes a logic module 310 and a NAND gate module 320 .

[0053] The logic module 310 is configured to receive the first control signal control, and output a first logic signal according to the comparison signal in response to a rising edge of the first control signal control.

[0054] The NAND gate module 320 is connected to the logic module 310 and is configured to perform a NAND operation on the first control signal control and the first logic signal to output a second control signal.

[0055] It should be noted that the logic module 310 can respond to the rising edge of the first control signal control by a trigger having a rising edge trigger function, for example, the logic module can include a D trigger or a JK trigger. The present application does not limit the specific trigger type.

[0056] In the specific implementation, the first logic signal is at a high level. In the case of current limiting, the logic module 310 stops outputting the first logic signal. At this time, the NAND gate module 320 realizes that no matter what state the first control signal control is in, the output of the second control signal can be directly disconnected according to the stop of the first logic signal to achieve current limiting; in the case of stopping current limiting, the logic module 310 responds to the rising edge of the first control signal control and outputs the first logic signal of a high level, so that the NAND gate module 320 outputs the second control signal to resume driving, with fast response speed and simple structure.

[0057] By way of example and not limitation, Figure 3 As shown, the current limiting driving circuit further includes an amplifier circuit 600 .

[0058] The amplifier circuit 600 is connected to the logic circuit 300 and is configured to amplify the first control signal control.

[0059] The logic circuit 300 is specifically configured to receive the amplified first control signal control, and in response to a rising edge of the amplified first control signal control, convert the amplified first control signal control into a second control signal according to the comparison signal.

[0060] Since the first control signal control is a signal provided by the control chip in the control circuit 800, and the control chip is powered by a low voltage, the current that can be output by the IO port is limited, and the driving ability of the control chip is low, the amplifier circuit 600 is used to amplify the first control signal control to increase the driving voltage and driving current, thereby improving the practicality of the circuit.

[0061] By way of example and not limitation, Figure 4 As shown, the current limiting driving circuit further includes a unidirectional conduction circuit 700 and a control circuit 800 .

[0062] The unidirectional conduction circuit 700 is connected to the comparison circuit 200 and is configured to unidirectionally conduct the comparison signal.

[0063] The control circuit 800 is connected to the unidirectional conduction circuit 700, and is configured to execute a corresponding action in response to the comparison signal after the unidirectional conduction lasting for a preset time period.

[0064] The control circuit 800 may also output a first control signal control.

[0065] It should be noted that the corresponding action can be to switch to bypass (backup circuit). If the current limiting time of the main circuit (current circuit) exceeds the preset time, it means that the load is too large, the output power is too large, and the temperature rises due to long-term overload, which affects the life of the device and further damages the main circuit. Therefore, it is necessary to switch to bypass (backup circuit). This improves circuit safety and extends the life of the equipment.

[0066] As an example but not a limitation, the comparison circuit 200 and the control circuit 800 are integrated in the same microprocessor.

[0067] The microprocessor can directly output a comparison signal to the logic circuit 300, so that when the current limiting point needs to be changed, there is no need to change the parameters of the hardware circuit, which improves the convenience of use and broadens the application scope of the circuit.

[0068] Figure 5 A partial exemplary circuit structure of a current limiting driving circuit provided in an embodiment of the present application is shown. Figure 6 Another partial exemplary circuit structure of the current limiting driving circuit provided in the embodiment of the present application is shown. For the convenience of description, only the part related to the embodiment of the present application is shown, which is described in detail as follows:

[0069] like Figure 5 and Figure 6 As shown, the amplifier circuit 600 includes a second NAND gate M2, a first transistor Q1, a first resistor R1, a second resistor R2 and a third resistor R3.

[0070] The first end of the first resistor R1 serves as the first control signal control input end of the amplifier circuit 600 to input the first control signal control; the second end of the first resistor R1 is connected to the first end of the second resistor R2 and the base of the first transistor Q1, the collector of the first transistor Q1 is connected to the first end of the third resistor R3, the first input end of the second NAND gate M2 and the second input end of the second NAND gate M2, the output end of the second NAND gate M2 serves as the amplified first control signal control output end of the amplifier circuit 600, and is connected to the logic circuit 300 to output the amplified first control signal control; the second end of the second resistor R2 and the emitter of the first transistor Q1 are commonly connected to the power ground.

[0071] The first resistor R1 is a current limiting resistor, the second resistor R2 can prevent the first transistor Q1 from malfunctioning, and the third resistor R3 is a pull-up resistor.

[0072] The first control signal control which is inverted due to flowing through the first transistor Q1 is inverted again through the second NAND gate M2 and the output level is pulled up, thereby outputting a second control signal which is in phase with the first control signal control.

[0073] It should be noted that the second NAND gate M2 is used here to implement the NOT logic in order to use the same logic gate as the first NAND gate M1 in the logic circuit 300, thereby reducing the types of logic gate circuits used and reducing the cost of building the circuit.

[0074] like Figure 5 As shown, the logic module 310 includes a D flip-flop N1 , a fifth resistor R5 , and a sixth resistor R6 .

[0075] The first end of the sixth resistor R6 serves as the first control signal control input end of the logic module 310 to input the first control signal control; the reset end R of the D flip-flop N1 serves as the comparison signal input end of the logic module 310 and is connected to the comparison circuit 200 to input the comparison signal; the second end of the sixth resistor R6 is connected to the clock input end of the D flip-flop N1, the data input end D of the D flip-flop N1 is connected to the set end S of the D flip-flop N1 and the first end of the fifth resistor R5, the in-phase output end Q of the D flip-flop N1 serves as the first logic signal output end of the logic module 310 and is connected to the NAND gate module 320 to output the first logic signal; the second end of the fifth resistor R5 is connected to the first power supply.

[0076] The fifth resistor R5 and the sixth resistor R6 have an impedance matching function.

[0077] The following table is the truth table of a D flip-flop.

[0078] S R D Clock Q \Q 0 1 × × 1 0 1 0 × × 0 1 0 0 × × 0 0 1 1 0 ↑ 0 1 1 1 1 ↑ 1 0

[0079] Among them, the working state corresponding to the second row is the current limiting state, and the working state corresponding to the fifth row is the stop current limiting state.

[0080] It can be seen from the above table that under the current limiting condition, the in-phase output terminal Q of the D flip-flop N1 stops outputting the first logic signal; when the current limiting stops, the D flip-flop N1 will output the first logic signal of a high level according to the rising edge of the next driving cycle of the first control signal control and resume driving.

[0081] The D flip-flop N1 has a fast response speed, thereby ensuring that a high-level first logic signal can be output according to the rising edge of the next driving cycle of the first control signal control, without delaying the recovery time, thereby improving the reliability of the circuit.

[0082] like Figure 6 As shown, the logic module 310 includes a JK flip-flop N2 , a fifth resistor R5 , and a sixth resistor R6 .

[0083] The first end of the sixth resistor R6 serves as the first control signal control input end of the logic module 310 to input the first control signal control; the reset end R of the JK trigger N2 serves as the comparison signal input end of the logic module 310 and is connected to the comparison circuit 200 to input the comparison signal; the second end of the sixth resistor R6 is connected to the clock input end of the JK trigger N2, the first input control end J of the JK trigger N2 is connected to the set end S of the JK trigger N2 and the first end of the fifth resistor R5, the in-phase output end Q of the JK trigger N2 serves as the first logic signal output end of the logic module 310 and is connected to the NAND gate module 320 to output the first logic signal; the second end of the fifth resistor R5 is connected to the first power supply; the second input control end K of the JK trigger N2 is connected to the power ground.

[0084] The fifth resistor R5 and the sixth resistor R6 have an impedance matching function.

[0085] The following table is the truth table of the JK flip-flop.

[0086]

[0087] Among them, the working state corresponding to the second row is the current limiting state, and the working state corresponding to the sixth row is the stop current limiting state.

[0088] It can be seen from the above table that, in the case of current limiting, the in-phase output terminal Q of the JK flip-flop N2 stops outputting the first logic signal of a high level; in the case of stopping current limiting, the JK flip-flop N2 will output the first logic signal of a high level according to the rising edge of the next driving cycle of the first control signal control to resume driving.

[0089] The JK trigger N2 has a fast response speed, thereby ensuring that a high-level first logic signal can be output according to the rising edge of the next driving cycle of the first control signal control, without delaying the recovery time, thereby improving the reliability of the circuit.

[0090] like Figure 5 and Figure 6As shown, the comparison circuit 200 includes a comparator U1 , a first diode D1 , a second diode D2 , a tenth resistor R10 , an eleventh resistor R11 , a twelfth resistor R12 , a thirteenth resistor R13 , a fourteenth resistor R14 and a capacitor C1 .

[0091] The first end of the eleventh resistor R11 is used as a sampling current input end of the comparison circuit 200, and is connected to the sampling circuit 100 to input the sampling current; the first end of the tenth resistor R10 is used as a preset current input end of the comparison circuit 200 to input the preset current; the second end of the tenth resistor R10 is connected to the first end of the twelfth resistor R12 and the non-inverting input end of the comparator U1, the second end of the eleventh resistor R11 is connected to the first end of the capacitor C1 and the inverting input end of the comparator U1, the second end of the twelfth resistor R12 is connected to the first end of the thirteenth resistor R13, the output end of the comparator U1 and the anode of the first diode D1, the cathode of the first diode D1, the anode of the second diode D2 and the first end of the fourteenth resistor R14 are used together as a comparison signal output end of the comparison circuit 200, and are connected to the logic circuit 300 to output the comparison signal; the cathode of the second diode D2 and the second end of the thirteenth resistor R13 are connected to the first power supply, and the second end of the capacitor C1 and the second end of the fourteenth resistor R14 are connected to the power ground.

[0092] The second diode D2 may be a Schottky diode, which has a clamping effect; the thirteenth resistor R13 is a pull-up resistor, and the capacitor C1 has a phase compensation effect for the comparator U1.

[0093] The circuit components are easily available and have low cost.

[0094] like Figure 5 and Figure 6 As shown, the driving circuit 400 includes a second transistor Q2, a third transistor Q3, a third diode D3, a fourth diode D4, an eighth resistor R8, a ninth resistor R9, a fifteenth resistor R15, a sixteenth resistor R16 and a seventeenth resistor R17.

[0095] The first end of the eighth resistor R8 is used as the second control signal input end of the driving circuit 400 and is connected to the logic circuit 300 to input the second control signal; the second end of the eighth resistor R8 is connected to the first end of the ninth resistor R9 and the base of the second transistor Q2, the collector of the second transistor Q2 is connected to the first end of the fifteenth resistor R15, the second end of the fifteenth resistor R15 is connected to the first end of the sixteenth resistor R16, the base of the third diode D3 and the cathode of the third diode D3, the emitter of the third transistor Q3 is connected to the first end of the seventeenth resistor R17, the second end of the seventeenth resistor R17, the anode of the third diode D3 and the anode of the fourth diode D4 are used together as the driving signal output end of the driving circuit 400, and are connected to the power supply circuit 500 to output the driving signal; the second end of the sixteenth resistor R16 is connected to the cathode of the fourth diode D4, the collector of the third transistor Q3 and the first power supply; the second end of the ninth resistor R9 and the emitter of the second transistor Q2 are connected to the power ground.

[0096] The third diode D3 and the fourth diode D4 can both be Schottky diodes, which play a clamping role and clamp the level of the drive signal to the first power supply voltage; the eighth resistor R8 and the fifteenth resistor R15 are current limiting resistors; the sixteenth resistor R16 is a pull-up resistor; and the ninth resistor R9 is used to prevent the second transistor Q2 from malfunctioning.

[0097] The transistor switch has low loss and fast action, and can be used in the driving circuit 400 to reduce circuit loss and improve response speed.

[0098] like Figure 5 and Figure 6 As shown, the NAND gate module 320 includes a first NAND gate M1 , a fourth resistor R4 , and a seventh resistor R7 .

[0099] The first end of the seventh resistor R7 serves as the first control signal control input end of the NAND gate module 320 to input the first control signal control; the first end of the fourth resistor R4 serves as the first logic signal input end of the NAND gate module 320 and is connected to the logic module 310 to input the first logic signal; the second end of the seventh resistor R7 is connected to the first input end of the first NAND gate M1, the second end of the fourth resistor R4 is connected to the second input end of the first NAND gate M1, and the output end of the first NAND gate M1 serves as the second control signal output end of the NAND gate module 320 and is connected to the drive circuit 400 to output the second control signal.

[0100] The fourth resistor R4 and the seventh resistor R7 have an impedance matching function.

[0101] like Figure 5 and Figure 6 As shown, the unidirectional conducting circuit 700 includes a fifth diode D5 and an eighteenth resistor R18.

[0102] The anode of the fifth diode D5 serves as the comparison signal input terminal of the unidirectional conduction circuit 700, and is connected to the comparison circuit 200 to input the comparison signal; the cathode of the fifth diode D5 and the first end of the eighteenth resistor R18 serve together as the comparison signal output terminal of the unidirectional conduction circuit 700 after unidirectional conduction, and are connected to the control circuit 800 to output the comparison signal after unidirectional conduction; the second end of the eighteenth resistor R18 is connected to the second power supply.

[0103] The eighteenth resistor R18 is a pull-up resistor.

[0104] The following is a combination of working principles Figure 5 to Figure 6 As shown for further explanation:

[0105] like Figure 5 As shown, the first end of the first resistor R1 is connected to the first control signal control, the second end of the third resistor R3 is connected to the first power supply, the first resistor R1 limits the current of the first control signal control, and then outputs the third control signal to the base of the first transistor Q1, the first transistor Q1 inverts the third control signal, and then outputs the fourth control signal, the third resistor R3 pulls up the voltage of the fourth control signal, and outputs the fifth control signal from the first end of the third resistor R3 and the emitter of the first transistor Q1 to the first input end and the second input end of the second NAND gate M2, the second NAND gate M2 inverts the fifth control signal, and the fifth control signal is output from the first end of the third resistor R3 and the emitter of the first transistor Q1 to the first input end and the second input end of the second NAND gate M2. After the control signal is negated, the sixth control signal is output to the first end of the sixth resistor R6 and the first end of the seventh resistor R7. The sixth resistor R6 transmits the sixth control signal to the clock input end of the D flip-flop N1. The first end of the tenth resistor R10 is connected to the preset current. The sampling circuit 100 samples the output current and outputs the sampled current to the first end of the eleventh resistor R11. The comparator U1 compares the sampled current with the preset current and outputs a comparison signal according to the comparison result. In a specific implementation, the comparator U1 can output a high-level comparison signal when the sampled current is less than or equal to the preset current.

[0106] When the sampling current is greater than the preset current, the comparator U1 stops outputting a high-level comparison signal to the reset terminal R of the D flip-flop N1. It can be seen from the second row of the D flip-flop truth table that at this time, the in-phase output terminal Q of the D flip-flop N1 stops outputting a high-level first logic signal to the first end of the fourth resistor R4, so that the output end of the first NAND gate M1 outputs a high-level signal to the first end of the eighth resistor R8, the second transistor Q2 is turned on, and the base voltage of the third transistor Q3 is pulled down, the third transistor Q3 is turned off, and the second end of the seventeenth resistor R17 and the anode of the third diode D3 and the anode of the fourth diode D4 stop outputting a drive signal to the power supply circuit 500, thereby achieving current limiting.

[0107] When the sampling current is less than or equal to the preset current, the comparator U1 outputs a high-level comparison signal to the reset terminal R of the D flip-flop N1. It can be seen from the fifth row of the D flip-flop truth table that the D flip-flop N1 will respond to the next rising edge of the first control signal control, and output a high-level first logic signal from the in-phase output terminal Q of the D flip-flop N1. The first NAND gate M1 performs a NAND operation on the high-level first logic signal and the sixth control signal, and outputs a second control signal from the output terminal of the first NAND gate M1 to the first end of the eighth resistor R8. The second transistor Q2 inverts the second control signal and outputs it to the base of the third transistor Q3, thereby realizing the normal operation of the circuit after stopping the current limiting.

[0108] If the sampled current is greater than the preset current for a preset period of time, the control circuit 800 will turn off the main circuit and switch to a bypass circuit (not shown) to supply power to the load.

[0109] like Figure 6 As shown, the clock input terminal of the JK trigger N2 is connected to the sixth control signal. When the sampling current is greater than the preset current, the comparator U1 stops outputting a high-level comparison signal to the reset terminal R of the JK trigger N2. It can be seen from the second row of the JK trigger truth table that at this time, the in-phase output terminal Q of the JK trigger N2 stops outputting a high-level first logic signal to the first end of the fourth resistor R4; when the sampling current is less than or equal to the preset current, the comparator U1 outputs a high-level comparison signal to the reset terminal R of the JK trigger N2. It can be seen from the sixth row of the JK trigger truth table that at this time, the JK trigger N2 will respond to the next rising edge of the first control signal control and output a high-level first logic signal from the in-phase output terminal Q of the JK trigger N2. The working principles of the remaining circuits are the same as those of the embodiment of the present invention. Figure 5 The same is not repeated here.

[0110] An embodiment of the present application further provides an electronic device, which includes the above-mentioned current limiting driving circuit.

[0111] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0112] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A current limiting driving circuit, connected to a power supply circuit, characterized in that: The current limiting driving circuit comprises: a sampling circuit, connected to the power circuit, and configured to sample the output current of the power circuit to output a sampled current; A comparison circuit, connected to the sampling circuit, configured to compare the sampled current with a preset current and output a comparison signal according to a comparison result; a logic circuit connected to the comparison circuit, configured to receive a first control signal, and in response to a rising edge of the first control signal, convert the first control signal into a second control signal according to the comparison signal; wherein both the first control signal and the second control signal are periodic signals; The driving circuit is connected to the logic circuit and the power circuit, and is configured to output a driving signal according to the second control signal to drive the power circuit.

2. The current limiting driving circuit according to claim 1, characterized in that: The logic circuit comprises: a logic module, configured to receive the first control signal, and output a first logic signal according to the comparison signal in response to a rising edge of the first control signal; The NAND gate module is connected to the logic module and is configured to perform a NAND operation on the first control signal and the first logic signal to output the second control signal.

3. The current limiting driving circuit according to claim 2, characterized in that: The logic module includes a D flip-flop or a JK flip-flop.

4. The current limiting driving circuit according to claim 3, characterized in that: The logic module includes the D flip-flop, a fifth resistor and a sixth resistor; The first end of the sixth resistor serves as a first control signal input end of the logic module to input the first control signal; The reset end of the D flip-flop is used as the comparison signal input end of the logic module, and is connected to the comparison circuit to input the comparison signal; the second end of the sixth resistor is connected to the clock input end of the D flip-flop, the data input end of the D flip-flop is connected to the set end of the D flip-flop and the first end of the fifth resistor, the in-phase output end of the D flip-flop is used as the first logic signal output end of the logic module, and is connected to the NAND gate module to output the first logic signal; the second end of the fifth resistor is connected to the first power supply; or The logic module includes the JK trigger, a fifth resistor and a sixth resistor; The first end of the sixth resistor serves as a first control signal input end of the logic module to input the first control signal; The reset end of the JK trigger serves as the comparison signal input end of the logic module and is connected to the comparison circuit to input the comparison signal; the second end of the sixth resistor is connected to the clock input end of the JK trigger, the first input control end of the JK trigger is connected to the set end of the JK trigger and the first end of the fifth resistor, the in-phase output end of the JK trigger serves as the first logic signal output end of the logic module and is connected to the NAND gate module to output the first logic signal; the second end of the fifth resistor is connected to the first power supply; and the second input control end of the JK trigger is connected to the power ground.

5. The current limiting driving circuit according to claim 1, characterized in that: Also includes: A unidirectional conduction circuit, connected to the comparison circuit, configured to conduct unidirectional conduction to the comparison signal; The control circuit is connected to the one-way conduction circuit and is configured to execute a corresponding action in response to the comparison signal after the one-way conduction lasting for a preset time period.

6. The current limiting driving circuit according to claim 5, characterized in that: The comparison circuit and the control circuit are integrated in the same microprocessor.

7. The current limiting driving circuit according to any one of claims 1 to 6, characterized in that: Also includes: an amplifier circuit, connected to the logic circuit and configured to amplify the first control signal; The logic circuit is specifically configured to receive the amplified first control signal, and in response to a rising edge of the amplified first control signal, convert the amplified first control signal into a second control signal according to the comparison signal.

8. The current limiting driving circuit according to claim 7, characterized in that: The amplifying circuit includes a second NAND gate, a first transistor, a first resistor, a second resistor and a third resistor; The first end of the first resistor serves as the first control signal input end of the amplifier circuit to input the first control signal; the second end of the first resistor is connected to the first end of the second resistor and the base of the first transistor, the collector of the first transistor is connected to the first end of the third resistor, the first input end of the second NAND gate and the second input end of the second NAND gate, the output end of the second NAND gate serves as the amplified first control signal output end of the amplifier circuit, and is connected to the logic circuit to output the amplified first control signal; the second end of the second resistor and the emitter of the first transistor are commonly connected to the power ground.

9. The current limiting driving circuit according to any one of claims 1 to 6, characterized in that: The comparison circuit includes a comparator, a first diode, a second diode, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor and a capacitor; The first end of the eleventh resistor serves as a sampling current input end of the comparison circuit and is connected to the sampling circuit to input the sampling current; The first end of the tenth resistor serves as a preset current input end of the comparison circuit to input the preset current; The second end of the tenth resistor is connected to the first end of the twelfth resistor and the non-inverting input end of the comparator, the second end of the eleventh resistor is connected to the first end of the capacitor and the inverting input end of the comparator, the second end of the twelfth resistor is connected to the first end of the thirteenth resistor, the output end of the comparator and the anode of the first diode, the cathode of the first diode, the anode of the second diode and the first end of the fourteenth resistor are commonly used as the comparison signal output end of the comparison circuit, and are connected to the logic circuit to output the comparison signal; the cathode of the second diode and the second end of the thirteenth resistor are commonly connected to the first power supply, and the second end of the capacitor and the second end of the fourteenth resistor are commonly connected to the power ground.

10. An electronic device, characterized in that: It comprises the current limiting driving circuit as claimed in any one of claims 1 to 9.

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