Display panel and display device

Abstract

The utility model relates to the technical field of display, and provides a display panel and a display device.The display panel comprises a substrate, a plurality of pixel driving circuits, a first grid line and a fourth grid line, orthographic projections of the pixel driving circuits on the substrate are distributed in an array mode in the first direction and the second direction, and the first direction and the second direction intersect; the pixel driving circuit comprises a driving transistor, a second transistor and a ninth transistor, a first electrode of the ninth transistor is connected with a grid electrode of the driving transistor, a second electrode of the ninth transistor is connected with a first electrode of the second transistor, and a second electrode of the second transistor is connected with a second electrode of the driving transistor; orthographic projections of the first grid lines on the substrate extend along a first direction, and the first grid lines are used for providing grid driving signals for second transistors in a plurality of pixel driving circuits distributed in the first direction; the orthographic projection of the fourth grid line on the substrate extends in the second direction, and the fourth grid line is used for providing grid driving signals for ninth transistors in a plurality of pixel driving circuits distributed in the second direction. According to the display panel, the refreshing frequency of the local display area can be adjusted.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In the related art, in order to improve the display effect of the display panel, the display panel has a higher refresh frequency. However, if the refresh frequency of the display panel is too high, the power consumption of the display panel will be too high.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Utility Model Content

[0004] According to one aspect of the present disclosure, a display panel is provided, wherein the display panel includes:

[0005] substrate substrate;

[0006] A plurality of pixel driving circuits, wherein the orthographic projections of the plurality of pixel driving circuits on the substrate are distributed in an array along a first direction and a second direction, and the first direction and the second direction intersect;

[0007] The pixel driving circuit includes a driving transistor, a second transistor, and a ninth transistor, wherein a first electrode of the ninth transistor is connected to a gate of the driving transistor, a second electrode of the ninth transistor is connected to a first electrode of the second transistor, and a second electrode of the second transistor is connected to a second electrode of the driving transistor;

[0008] A first gate line, the orthographic projection of which on the substrate extends along the first direction, and the first gate line is used to provide a gate driving signal to second transistors in a plurality of pixel driving circuits distributed in the first direction;

[0009] A fourth gate line, an orthographic projection of which on the substrate extends along the second direction, and the fourth gate line is used to provide a gate driving signal to a ninth transistor in a plurality of pixel driving circuits distributed in the second direction.

[0010] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0011] a ninth active portion, the ninth active portion being used to form a channel region of the ninth transistor;

[0012] A sixth conductive part, the sixth conductive part is connected to a stable power supply terminal, the conductive layer where the sixth conductive part is located is located between the active layer where the ninth active part is located and the base substrate, and the orthographic projection of the sixth conductive part on the base substrate and the orthographic projection of the ninth active part on the base substrate at least partially overlap.

[0013] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0014] A shielding layer, located on one side of the base substrate, the shielding layer comprising a first shielding portion;

[0015] A first active layer is located on a side of the shielding layer away from the base substrate, the first active layer comprises a third active portion, the third active portion is used to form a channel region of the driving transistor, and an orthographic projection of the first shielding portion on the base substrate and an orthographic projection of the third active portion on the base substrate at least partially overlap;

[0016] Wherein, the sixth conductive portion is located on the shielding layer.

[0017] In an exemplary embodiment of the present disclosure, the shielding layer further includes:

[0018] a second connecting portion, the second connecting portion being connected between two adjacent first shielding portions in the second direction;

[0019] The sixth conductive portion is connected to the second connecting portion, and an orthographic projection of the sixth conductive portion on the base substrate is located on one side of an orthographic projection of the second connecting portion on the base substrate in the first direction.

[0020] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0021] a second active portion, the second active portion being used to form a channel region of the second transistor;

[0022] a ninth active portion, the ninth active portion being used to form a channel region of the ninth transistor;

[0023] The second active portion and the ninth active portion are located in the same active layer, and an area of ​​an orthographic projection of the ninth active portion on the base substrate is smaller than an area of ​​an orthographic projection of the second active portion on the base substrate.

[0024] In an exemplary embodiment of the present disclosure, the length of the channel region of the ninth transistor is smaller than the length of the channel region of the second transistor;

[0025] And / or, a width of a channel region of the ninth transistor is smaller than a width of a channel region of the second transistor.

[0026] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a first transistor, a first electrode of the first transistor is connected to a first initial signal line, a second electrode of the first transistor is connected to a second electrode of the driving transistor, and the display panel further includes:

[0027] a first active portion, the first active portion being used to form a channel region of the first transistor;

[0028] a ninth active portion, the ninth active portion being used to form a channel region of the ninth transistor;

[0029] The first active portion and the ninth active portion are located in the same active layer, and an area of ​​an orthographic projection of the ninth active portion on the base substrate is smaller than an area of ​​an orthographic projection of the first active portion on the base substrate.

[0030] In an exemplary embodiment of the present disclosure, the driving transistor and the ninth transistor are P-type transistors, and the display panel further includes:

[0031] The first active layer is located on one side of the base substrate, and the first active layer includes a third active portion and a ninth active portion. The third active portion is used to form a channel region of the driving transistor, and the ninth active portion is used to form a channel region of the ninth transistor.

[0032] In an exemplary embodiment of the present disclosure, the driving transistor is a P-type transistor, the ninth transistor is an N-type transistor, and the display panel further includes:

[0033] A first active layer, located on one side of the base substrate, the first active layer comprising a third active portion, the third active portion being used to form a channel region of the driving transistor;

[0034] The second active layer is located on a side of the first active layer away from the substrate, and the second active layer includes a ninth active portion, and the ninth active portion is used to form a channel region of the ninth transistor.

[0035] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a first transistor and a fourth transistor, wherein a first electrode of the first transistor is connected to a first initial signal line, a second electrode of the first transistor is connected to a second electrode of the driving transistor, a first electrode of the fourth transistor is connected to a data line, and a second electrode of the fourth transistor is connected to a first electrode of the driving transistor;

[0036] The display panel further includes:

[0037] A first reset signal line, located at one side of the base substrate, wherein an orthographic projection of the first reset signal line on the base substrate extends along a first direction, and a partial structure of the first reset signal line is used to form a gate of the first transistor;

[0038] A second gate line, located at one side of the base substrate, an orthographic projection of the second gate line on the base substrate extends along a first direction, and a partial structure of the second gate line is used to form a gate of the fourth transistor;

[0039] Wherein, in the same pixel driving circuit, the orthographic projection of the channel region of the ninth transistor on the base substrate is located between the orthographic projection of the second gate line on the base substrate and the orthographic projection of the first reset signal line on the base substrate.

[0040] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a fourth transistor, a first electrode of the fourth transistor is connected to the data line, and a second electrode of the fourth transistor is connected to the first electrode of the driving transistor;

[0041] Wherein, in the first direction of the same pixel driving circuit, the orthographic projection of the channel region of the ninth transistor on the substrate is located between the orthographic projection of the channel region of the fourth transistor on the substrate and the orthographic projection of the channel region of the second transistor on the substrate.

[0042] In an exemplary embodiment of the present disclosure, a length direction of the channel region of the second transistor is a second direction, and a length direction of the channel region of the ninth transistor is a first direction.

[0043] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0044] a first source-drain layer, located at one side of the base substrate, the first source-drain layer comprising a ninth bridge portion, the ninth bridge portion connecting the first electrode of the ninth transistor and the gate of the driving transistor through via holes;

[0045] a second source-drain layer, located on a side of the first source-drain layer away from the substrate, the second source-drain layer comprising a first power line, the first power line being used to provide a high-level power signal to the pixel driving circuit;

[0046] The third source-drain layer is located on a side of the second source-drain layer away from the substrate, and the third source-drain layer includes the fourth gate line.

[0047] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0048] A first power line, the first power line is used to provide a high-level power signal to the pixel driving circuit, and an orthographic projection of the first power line on the substrate extends along the second direction;

[0049] An orthographic projection of the fourth gate line on the base substrate and an orthographic projection of the first power line on the base substrate at least partially overlap.

[0050] In an exemplary embodiment of the present disclosure, the first power line includes: a first extension portion and a second extension portion, wherein a size of an orthographic projection of the first extension portion on the base substrate in the first direction is larger than a size of an orthographic projection of the second extension portion on the base substrate in the first direction;

[0051] An orthographic projection of the fourth gate line on the base substrate and an orthographic projection of the second extension portion on the base substrate at least partially overlap.

[0052] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0053] A first power line is located on one side of the substrate, and is used to provide a high-level power signal to the pixel driving circuit. The orthographic projection of the first power line on the substrate and the orthographic projection of the channel region of the ninth transistor on the substrate at least partially overlap.

[0054] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0055] a first source-drain layer, located at one side of the base substrate, the first source-drain layer comprising a second bridge portion and a ninth bridge portion, the second bridge portion respectively connecting the second electrode of the driving transistor and the second electrode of the second transistor through via holes, and the ninth bridge portion respectively connecting the first electrode of the ninth transistor and the gate of the driving transistor through via holes;

[0056] A second source-drain layer is located on a side of the first source-drain layer away from the substrate, the second source-drain layer comprises a first power line, and the first power line is used to provide a high-level power signal to the pixel driving circuit;

[0057] The orthographic projection of the first power line on the base substrate and the orthographic projection of the second bridge portion on the base substrate at least partially overlap, and / or the orthographic projection of the first power line on the base substrate and the orthographic projection of the ninth bridge portion on the base substrate at least partially overlap.

[0058] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a first transistor, a first electrode of the first transistor is connected to a first initial signal line, and a second electrode of the first transistor is connected to a second electrode of the driving transistor;

[0059] The display panel further includes:

[0060] A second bridge portion, located at one side of the base substrate, the second bridge portion is connected to the second electrode of the driving transistor, the second electrode of the second transistor, and the second electrode of the first transistor through via holes respectively;

[0061] The first gate line includes a third extension portion and a fourth extension portion, the third extension portion is used to form the gate of the second transistor, and the size of the orthogonal projection of the third extension portion on the substrate in the second direction is greater than the size of the orthogonal projection of the fourth extension portion on the substrate in the second direction;

[0062] The second bridge portion and the first gate line are located in different conductive layers, the second bridge portion includes a first sub-bridge portion, the orthographic projection of the first sub-bridge portion on the base substrate extends along the second direction, and the orthographic projection of the first sub-bridge portion on the base substrate intersects with the orthographic projection of the fourth extension portion on the base substrate.

[0063] In an exemplary embodiment of the present disclosure, the second bridging portion further includes:

[0064] a second sub-bridge portion, wherein the second sub-bridge portion is connected to a second electrode of the first transistor through a via hole;

[0065] a third sub-bridge portion, wherein the third sub-bridge portion is connected to the second electrode of the second transistor and the second electrode of the driving transistor through a via hole;

[0066] Among them, the first sub-bridge portion is connected between the second sub-bridge portion and the third sub-bridge portion, the angle between the orthographic projection of the first sub-bridge portion on the substrate and the orthographic projection of the second sub-bridge portion on the substrate is less than 180°, and the angle between the orthographic projection of the first sub-bridge portion on the substrate and the orthographic projection of the third sub-bridge portion on the substrate is less than 180°.

[0067] In an exemplary embodiment of the present disclosure, the display panel further includes a light-emitting unit, the pixel driving circuit is used to drive the light-emitting unit to emit light, and the pixel driving circuit further includes:

[0068] a first transistor, wherein a first electrode of the first transistor is connected to a first initial signal line, and a second electrode of the first transistor is connected to a second electrode of the driving transistor;

[0069] a fourth transistor, a first electrode of which is connected to the data line, and a second electrode of which is connected to the first electrode of the driving transistor;

[0070] a fifth transistor, a first electrode of which is connected to the first power line, and a second electrode of which is connected to the first electrode of the driving transistor;

[0071] a sixth transistor, a first electrode of which is connected to the second electrode of the driving transistor, and a second electrode of which is connected to the light-emitting unit;

[0072] a seventh transistor, a first electrode connected to the second initial signal line, and a second electrode connected to the light emitting unit;

[0073] an eighth transistor, a first electrode of which is connected to the third initial signal line, and a second electrode of which is connected to the first electrode of the driving transistor;

[0074] a capacitor, a first electrode of which is connected to the gate of the driving transistor, and a second electrode of which is connected to the first power line;

[0075] Among them, the first transistor, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are P-type transistors, the second transistor is an N-type transistor, and the ninth transistor is an N-type transistor or a P-type transistor.

[0076] In an exemplary embodiment of the present disclosure, the pixel driving circuit includes a P-type transistor and an N-type transistor, and the display panel further includes:

[0077] A first active layer, located on one side of the substrate, wherein a portion of the first active layer is used to form a channel region of a P-type transistor in the pixel driving circuit;

[0078] A first gate layer, located on a side of the first active layer away from the substrate, wherein a portion of the first gate layer is used to form a gate of a P-type transistor in the pixel driving circuit;

[0079] A second gate layer, located on a side of the first gate layer away from the base substrate, a portion of the second gate layer being used to form a bottom gate of an N-type transistor in the pixel driving circuit;

[0080] A second active layer, located on a side of the second gate layer away from the substrate, wherein a portion of the second active layer is used to form a channel region of an N-type transistor in the pixel driving circuit;

[0081] A third gate layer, located on a side of the second active layer away from the substrate, wherein a portion of the third gate layer is used to form a top gate of an N-type transistor in the pixel driving circuit;

[0082] The first source-drain layer is located at a side of the third gate layer away from the substrate, and a part of the structure of the first source-drain layer is used to form a bridge portion connecting different transistors.

[0083] According to one aspect of the present disclosure, a display device is provided, wherein the display device includes the above-mentioned display panel.

[0084] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0085] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0086] Figure 1 A schematic structural diagram of an exemplary embodiment of a display panel in the related art;

[0087] Figure 2 A schematic structural diagram of an exemplary embodiment of a pixel driving circuit disclosed in the present invention;

[0088] Figure 3 for Figure 2 A timing diagram of some nodes in an exemplary embodiment of the pixel driving circuit shown;

[0089] Figure 4 A schematic structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0090] Figure 5 A timing diagram of some signal lines in an exemplary embodiment of the display panel disclosed herein;

[0091] Figure 6 A structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0092] Figure 7 for Figure 6 The structural layout of the middle occlusion layer;

[0093] Figure 8 for Figure 6 The structural layout of the first active layer in FIG.

[0094] Fig. 9 for Figure 6 The structural layout of the first gate layer;

[0095] Fig.10 for Figure 6The structural layout of the second gate layer;

[0096] Fig.11 for Figure 6 The structural layout of the second active layer;

[0097] Fig.12 for Figure 6 The structural layout of the third gate layer;

[0098] Fig.13 for Figure 6 The structural layout of the first source and drain layer;

[0099] Fig.14 for Figure 6 The structural layout of the second source and drain layer;

[0100] Fig.15 for Figure 6 The structural layout of the third source and drain layer;

[0101] Fig.16 for Figure 6 Structural layout of the middle shielding layer and the first active layer;

[0102] Fig.17 for Figure 6 The structural layout of the middle shielding layer, the first active layer, and the first gate layer;

[0103] Fig.18 for Figure 6 Structural layout of a middle shielding layer, a first active layer, a first gate layer, and a second gate layer;

[0104] Fig.19 for Figure 6 A structural layout of a middle shielding layer, a first active layer, a first gate layer, a second gate layer, and a second active layer;

[0105] Fig. 20 for Figure 6 Structural layout of a middle shielding layer, a first active layer, a first gate layer, a second gate layer, a second active layer, and a third gate layer;

[0106] Fig.21 for Figure 6 A structural layout of a middle shielding layer, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, and a first source and drain layer;

[0107] Fig. 22 for Figure 6 A structural layout of a middle shielding layer, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first source-drain layer, and a second source-drain layer;

[0108] Fig.23 for Figure 6The display panel is shown as a partial cross-sectional view taken along the dotted line BB;

[0109] Fig.24 A structural layout of a shielding layer, a first active layer, a first gate layer, a second gate layer, and a third gate layer in an exemplary embodiment of a display panel disclosed herein;

[0110] Fig.25 for Fig.24 The structural layout of the shielding layer in the display panel shown;

[0111] Fig.26 for Fig.24 The structural layout of the second gate layer in the display panel shown;

[0112] Fig. 27 for Fig.24 The structural layout of the shielding layer, the first active layer, the first gate layer and the second gate layer in the display panel shown;

[0113] Fig.28 is a structural schematic diagram of another exemplary embodiment of the pixel driving circuit disclosed in the present invention;

[0114] Fig.29 A structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0115] Fig.30 for Fig.29 The structural layout of the middle occlusion layer;

[0116] Fig.31 for Fig.29 The structural layout of the first active layer in FIG.

[0117] Fig.32 for Fig.29 The structural layout of the first gate layer;

[0118] Fig.33 for Fig.29 The structural layout of the second gate layer;

[0119] Fig.34 for Fig.29 The structural layout of the second active layer;

[0120] Fig.35 for Fig.29 The structural layout of the third gate layer;

[0121] Fig.36 for Fig.29 The structural layout of the first source and drain layer;

[0122] Fig.37 for Fig.29 The structural layout of the second source and drain layer;

[0123] Fig.38 for Fig.29 The structural layout of the third source and drain layer;

[0124] Fig.39 for Fig.29 Structural layout of the middle shielding layer and the first active layer;

[0125] Fig.40 for Fig.29 The structural layout of the middle shielding layer, the first active layer, and the first gate layer;

[0126] Fig.41 for Fig.29 Structural layout of a middle shielding layer, a first active layer, a first gate layer, and a second gate layer;

[0127] Fig.42 for Fig.29 A structural layout of a middle shielding layer, a first active layer, a first gate layer, a second gate layer, and a second active layer;

[0128] Fig.43 for Fig.29 Structural layout of a middle shielding layer, a first active layer, a first gate layer, a second gate layer, a second active layer, and a third gate layer;

[0129] Fig.44 for Fig.29 A structural layout of a middle shielding layer, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, and a first source and drain layer;

[0130] Fig.45 for Fig.29 A structural layout of a middle shielding layer, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first source-drain layer, and a second source-drain layer;

[0131] Fig.46 for Fig.29 The display panel is shown as a partial cross-sectional view taken along the dotted line CC;

[0132] Fig.47 is a cross-sectional view of another exemplary embodiment of a display panel disclosed herein;

[0133] Fig.48 is a cross-sectional view of another exemplary embodiment of a display panel disclosed herein;

[0134] Fig.49 FIG. 4 is a structural diagram of another exemplary embodiment of a display panel disclosed herein. DETAILED DESCRIPTION

[0135] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the present disclosure will be more comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted.

[0136] The terms "a", "an", and "said" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to indicate an open-ended inclusive meaning and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.

[0137] like Figure 1As shown, it is a schematic diagram of the structure of an exemplary embodiment of a display panel in the related art. The display panel may include a timing controller, a source driving circuit, a gate driving circuit and a pixel array. The timing controller is respectively connected to the source driving circuit and the gate driving circuit, and the source driving circuit is respectively connected to a plurality of data lines (Da1 to Dan). The gate driving circuit includes: a scanning driving circuit and a light-emitting driving circuit. The scanning driving circuit is respectively connected to a plurality of scanning signal lines (S1 to Sm), and the light-emitting driving circuit is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, and the sub-pixel Pxij may include a pixel driving circuit and a light-emitting device connected to the pixel driving circuit, and the pixel driving circuit may be respectively connected to the scanning signal line, the light-emitting signal line and the data line. The data line can be used for providing the above-mentioned data signal terminal, and the light-emitting signal line can be used for providing the above-mentioned enable signal terminal. This exemplary embodiment only exemplarily draws a scanning signal line connected to the pixel driving circuit. Each row of pixel driving circuits can be connected to multiple scanning signal lines, and multiple scanning signal lines can be used to provide the above-mentioned first gate driving signal terminal, second gate driving signal terminal, first reset signal terminal, and second reset signal terminal, respectively. In an exemplary embodiment, the timing controller can provide the grayscale value and control signal suitable for the specification of the source driving circuit to the source driving circuit, and can provide the clock signal, scanning start signal, etc. suitable for the specification of the scanning driving circuit to the scanning driving circuit, and can provide the clock signal, emission stop signal, etc. suitable for the specification of the light-emitting driving circuit to the light-emitting driving circuit. The source driving circuit can use the grayscale value and control signal received from the timing controller to generate the data signal to be provided to the data lines Da1, Da2, Da3, ... and Dan. For example, the source driving circuit can sample the grayscale value using a clock signal, and apply the data signal corresponding to the grayscale value to the data lines Da1 to Dan in units of pixel rows, and n can be a natural number. The scanning driving circuit can generate a scanning signal to be provided to the scanning signal lines S1, S2, S3, ... and Sm by receiving a clock signal, a scanning start signal, etc. from a timing controller. For example, the scanning driving circuit can sequentially provide a scanning signal with a conduction level pulse to the scanning signal lines S1 to Sm. For example, the scanning driving circuit can be constructed in the form of a shift register, and can sequentially transmit the scanning start signal provided in the form of a conduction level pulse to the next level circuit under the control of the clock signal to generate a scanning signal, and m can be a natural number. The light-emitting driving circuit can generate an emission signal to be provided to the light-emitting signal lines E1, E2, E3, ... and Eo by receiving a clock signal, an emission stop signal, etc. from a timing controller. For example, the light-emitting driving circuit can sequentially provide an emission signal with a cut-off level pulse to the light-emitting signal lines E1 to Eo.For example, the light-emitting driving circuit can be constructed in the form of a shift register, and can generate an emission signal by sequentially transmitting an emission stop signal provided in the form of a cut-off level pulse to a next-level circuit under the control of a clock signal, and o can be a natural number. Thus, the display panel can realize line-by-line scanning and driving.

[0138] This exemplary embodiment provides a pixel driving circuit such as Figure 2 , 3 As shown, Figure 2 is a schematic structural diagram of an exemplary embodiment of a pixel driving circuit disclosed in the present invention. Figure 3 for Figure 2 A timing diagram of some nodes in an exemplary embodiment of a pixel driving circuit is shown.

[0139] The pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a capacitor C. Among them, a first electrode of the fourth transistor T4 is connected to a data signal terminal Da, a second electrode of the fourth transistor T4 is connected to a first electrode of the driving transistor T3, and a gate of the fourth transistor T4 is connected to a second gate driving signal terminal G2; a first electrode of the fifth transistor T5 is connected to a first power supply terminal VDD, a second electrode of the fifth transistor T5 is connected to a first electrode of the driving transistor T3, and a gate of the fifth transistor T5 is connected to an enable signal terminal EM; a gate of the driving transistor T3 is connected to a node N; a second electrode of the second transistor T2 is connected to a second electrode of the driving transistor T3, and a gate of the second transistor T2 is connected to a first gate driving signal terminal G1; a first electrode of the sixth transistor T6 is connected to a second electrode of the driving transistor T3, a second electrode of the sixth transistor T6 is connected to a second electrode of the seventh transistor T7, a gate of the sixth transistor T6 is connected to an enable signal terminal EM, and a first electrode of the seventh transistor T7 is connected to a second initial The first electrode of the first transistor T1 is connected to the first initial signal terminal Vinit2, the gate of the seventh transistor T7 is connected to the second reset signal terminal Re2; the first electrode of the first transistor T1 is connected to the first initial signal terminal Vinit1, the second electrode of the first transistor T1 is connected to the second electrode of the driving transistor T3, and the gate of the first transistor T1 is connected to the first reset signal terminal Re1; the first electrode of the eighth transistor T8 is connected to the third initial signal terminal Vinit3, the second electrode of the eighth transistor T8 is connected to the first electrode of the driving transistor T3, and the gate of the eighth transistor T8 is connected to the second reset signal terminal Re2; the first electrode of the ninth transistor T9 is connected to the gate of the driving transistor T3, the second electrode of the ninth transistor T9 is connected to the first electrode of the second transistor T2, and the gate of the ninth transistor T9 is connected to the fourth gate driving signal terminal G4; the first electrode of the capacitor C is connected to the node N, and the second electrode of the capacitor C is connected to the first power supply terminal VDD. The pixel driving circuit can be used to drive a light-emitting unit L, the first electrode of the light-emitting unit L can be connected to the second electrode of the sixth transistor T6, the second electrode of the light-emitting unit can be connected to the second power supply terminal VSS, the first electrode of the light-emitting unit can be the anode of the light-emitting unit, and the second electrode of the light-emitting unit can be the cathode of the light-emitting unit. Among them, the second transistor T2 and the ninth transistor T9 can be N-type transistors, for example, the second transistor T2 and the ninth transistor T9 can be N-type metal oxide transistors, and the N-type transistor has a smaller leakage current, thereby reducing the leakage current of the node N through the ninth transistor T9 and the second transistor T2 during the light-emitting stage.At the same time, the first transistor T1, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be P-type transistors. For example, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be P-type low-temperature polycrystalline silicon transistors. P-type transistors have higher carrier mobility, which is conducive to realizing a display panel with high resolution, high response speed, high pixel density, and high aperture ratio. The first initial signal terminal, the second initial signal terminal, and the third initial signal terminal can output the same or different voltage signals according to actual conditions.

[0140] like Figure 3 As shown, G1 represents the timing of the first gate drive signal terminal G1, G2 represents the timing of the second gate drive signal terminal G2, Re2 represents the timing of the second reset signal terminal Re2, Re1 represents the timing of the first reset signal terminal Re1, and EM represents the timing of the enable signal terminal EM. A driving cycle of the pixel drive circuit may include a first reset phase t1, a data writing phase t2, a second reset phase t3, and a light emitting phase t4.

[0141] When the fourth gate drive signal terminal G4 turns on the ninth transistor T9:

[0142] In the first reset stage t1: the first gate drive signal terminal G1 outputs a high level, the first reset signal terminal Re1 outputs a low level signal, the first transistor T1 and the second transistor T2 are turned on, and the first initial signal terminal Vinit1 inputs the first initial signal to the node N through the first transistor T1 and the second transistor T2. In the data writing stage t2: the second gate drive signal terminal G2 outputs a low level signal, the first gate drive signal terminal G1 outputs a high level signal, the fourth transistor T4 and the second transistor T2 are turned on, and the data signal terminal Da writes the compensation voltage Vdata+Vth to the node N through the fourth transistor T4 and the second transistor T2, wherein Vdata is the voltage of the data signal on the data signal terminal, and Vth is the threshold voltage of the driving transistor T3. In the second reset stage t3: the second reset signal terminal Re2 outputs a low level signal, the seventh transistor T7 and the eighth transistor T8 are turned on, the second initial signal terminal Vinit2 inputs the second initial signal to the first electrode of the light emitting unit L, and the third initial signal terminal Vinit3 inputs the third initial signal to the first electrode of the driving transistor T3. In the light-emitting stage t4: the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light-emitting unit to emit light under the action of the compensation voltage Vdata+Vth stored in the capacitor C. The output current formula of the driving transistor is as follows:

[0143] I=(μWCox / 2L)(Vgs-Vth)2

[0144] Where, I is the output current of the driving transistor; μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driving transistor channel, L is the length of the driving transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor. The output current of the driving transistor in the above pixel driving circuit is I = (μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2 The pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.

[0145] When the fourth gate driving signal terminal G4 turns off the ninth transistor T9: the pixel driving circuit will not write the initial signal and the new data signal to the driving transistor T3 during the scanning phase, and the gate of the driving transistor will maintain the voltage of the previous frame.

[0146] like Figure 4 As shown, it is a schematic diagram of the structure of an exemplary embodiment of the display panel of the present disclosure. The display panel includes: a substrate, a plurality of pixel driving circuits P1-P9, a plurality of first gate lines G11-G13, and a plurality of fourth gate lines G41-G43, the orthographic projections of the plurality of pixel driving circuits on the substrate are distributed in an array along a first direction X and a second direction Y, the first direction X and the second direction Y intersect, for example, the first direction X can be a row direction, and the second direction Y can be a column direction; the orthographic projection of the first gate line on the substrate extends along the first direction, and the first gate line is used to provide a gate driving signal to the second transistors in the plurality of pixel driving circuits distributed in the first direction X; the orthographic projection of the fourth gate line on the substrate extends along the second direction Y, and the fourth gate line is used to provide a gate driving signal to the ninth transistor in the plurality of pixel driving circuits distributed in the second direction.

[0147] It should be noted that Figure 4 The display panel shown is described by taking nine pixel driving circuits as an example. It should be understood that the display panel may include other numbers of pixel driving circuits, and correspondingly, the display panel may include other numbers of first gate lines and fourth gate lines.

[0148] like Figure 4As shown, the fourth gate line G41 controls the on-off of the ninth transistor T9 in the pixel driving circuits P1, P4, and P7 distributed along the second direction Y, the fourth gate line G42 controls the on-off of the ninth transistor T9 in the pixel driving circuits P2, P5, and P8 distributed along the second direction Y, and the fourth gate line G43 controls the on-off of the ninth transistor T9 in the pixel driving circuits P3, P6, and P9 distributed along the second direction Y. If the fourth gate lines G41 and G43 control the ninth transistor T9 in the pixel driving circuits P1, P4, P7, P3, P6, and P9 to be turned off, the pixel driving circuits P1, P4, P7, P3, P6, and P9 will not write the initial signal and the new data signal to their driving transistors T3, the gate of the driving transistor will maintain the voltage of the previous frame, and the corresponding pixel driving circuits P1, P4, P7, P3, P6, and P9 can achieve low-frequency display. If the fourth gate line G42 controls the ninth transistor T9 in the pixel driving circuit P2, P5, and P8 to be turned on, the pixel driving circuit P2, P5, and P8 can normally write the compensation voltage to the gate of the driving transistor. At this time, the refresh frequency of the pixel driving circuit P2, P5, and P8 can be controlled by controlling the frequency of the first gate line G11, G12, and G13 outputting the gate drive signal. For example, the first gate line G11 outputs a conduction signal per frame, and the pixel driving circuit P2 is refreshed per frame, and the first gate line G12 outputs a conduction signal once every 3 frames, and the pixel driving circuit P5 is refreshed once every 3 frames. The method can control the refresh frequencies of different pixel driving circuits by controlling the frequency of the fourth gate line and the first gate line outputting the conduction signal.

[0149] The display panel can also control the refresh frequency of the local area by other driving methods. For example, the frequency of the conduction signal output by each first gate line can be the same, and when the display panel scans each row of pixel driving circuits, different fourth gate lines can control the on and off of the ninth transistor T9 connected thereto to control whether the pixel driving circuits in different areas write data signals. For example, when the pixel driving circuits P1, P2, and P3 are scanned, the fourth gate line G41 can control the ninth transistor in the pixel driving circuit P1 to be turned on, the fourth gate line G42 can control the ninth transistor in the pixel driving circuit P2 to be turned on, and the fourth gate line G43 can control the ninth transistor in the pixel driving circuit P3 to be turned off, thereby controlling the pixel driving circuits P1 and P2 to be refreshed, while the pixel driving circuit P3 is not refreshed; when the pixel driving circuits P4, P5, and P6 are scanned, the fourth gate line G41 can control the ninth transistor in the pixel driving circuit P4 to be turned off, the fourth gate line G42 can control the ninth transistor in the pixel driving circuit P5 to be turned on, and the fourth gate line G43 can control the ninth transistor in the pixel driving circuit P6 to be turned off, thereby controlling the pixel driving circuit P5 to be refreshed, while the pixel driving circuits P4 and P6 are not refreshed.

[0150] It should be understood that in other exemplary embodiments, the pixel driving circuit can also be other structures, as long as the pixel driving circuit includes a driving transistor T3, a second transistor T2, and a ninth transistor T9, the first electrode of the ninth transistor is connected to the gate of the driving transistor T3, the second electrode of the ninth transistor T9 is connected to the first electrode of the second transistor T2, and the second electrode of the second transistor T2 is connected to the second electrode of the driving transistor T3. This exemplary embodiment can control the refresh frequency of the display panel in different areas by turning the ninth transistor T9 on and off. Among them, the second transistor T2 and the ninth transistor T9 can be either P-type transistors or N-type transistors.

[0151] In addition, in other exemplary embodiments, one or more of the first transistor T1 , the fourth transistor T4 , the fifth transistor T5 , the sixth transistor T6 , the seventh transistor T7 , and the eighth transistor T8 may also be an N-type transistor.

[0152] like Figure 5 As shown, it is a timing diagram of some signal lines in an exemplary embodiment of the display panel disclosed in the present invention. Among them, G4x is a timing diagram of the fourth gate line in the low refresh area, and G4y is a timing diagram of the fourth gate line in the high refresh area. In the low refresh area, the fourth gate line outputs an off signal in some frames and outputs an on signal in some frames; in the high refresh area, the fourth gate line continuously outputs an on signal. When the ninth transistor T9 changes from an on state to an off state, since the signal on the fourth gate line will change from a high level to a low level, under the gate-source coupling of the ninth transistor T9, the gate of the driving transistor will be pulled down, resulting in a split screen phenomenon with high brightness in the low refresh area and low brightness in the high refresh area.

[0153] Of course, when the ninth transistor T9 is a P-type transistor, when the ninth transistor T9 changes from an on state to an off state, since the signal on the fourth gate line will change from a low level to a high level, under the gate-source coupling of the ninth transistor T9, the gate of the driving transistor will be pulled up, resulting in the same split-screen phenomenon with low brightness in the low refresh area and high brightness in the high refresh area.

[0154] It should be noted that the shutdown signal is a signal for shutting down the target circuit, for example, the shutdown signal of a P-type transistor is a high-level signal, and the shutdown signal of an N-type transistor is a low-level signal. The on signal is a signal for turning on the target circuit, for example, the on signal of a P-type transistor is a low-level signal, and the on signal of an N-type transistor is a high-level signal.

[0155] Based on this, the present exemplary embodiment further provides a display panel, which may include a base substrate, a shielding layer, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first source-drain layer, a second source-drain layer, and a third source-drain layer stacked in sequence. An insulating layer may be provided between the adjacent layers. Figure 6-22As shown, Figure 6 This is a structural diagram of an exemplary embodiment of the display panel disclosed herein. Figure 7 for Figure 6 The structural layout of the middle occlusion layer, Figure 8 for Figure 6 The structural layout of the first active layer in Fig. 9 for Figure 6 The structural layout of the first gate layer in Fig.10 for Figure 6 The structural layout of the second gate layer in Fig.11 for Figure 6 The structural layout of the second active layer, Fig.12 for Figure 6 The structural layout of the third gate layer, Fig.13 for Figure 6 The structural layout of the first source and drain layer in the figure. Fig.14 for Figure 6 The structural layout of the second source and drain layer in the figure. Fig.15 for Figure 6 The structural layout of the third source and drain layer. Fig.16 for Figure 6 The structural layout of the middle shielding layer and the first active layer. Fig.17 for Figure 6 The structural layout of the middle shielding layer, the first active layer, and the first gate layer. Fig.18 for Figure 6 The structural layout of the middle shielding layer, the first active layer, the first gate layer, and the second gate layer. Fig.19 for Figure 6 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer, Fig. 20 for Figure 6 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer, Fig.21 for Figure 6 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source and drain layer, Fig. 22 for Figure 6 The display panel may include a plurality of Figure 2 In the pixel driving circuit shown, a plurality of pixel driving circuits are arranged in an array in a first direction X and a second direction Y.

[0156] like Figure 6As shown, the plurality of pixel driving circuits may include a first pixel driving circuit P1 and a second pixel driving circuit P2 adjacently distributed in a first direction X, and at least part of the structure of the first pixel driving circuit P1 and the second pixel driving circuit P2 may be arranged in mirror symmetry with the mirror symmetry plane AA. Wherein, the mirror symmetry plane AA may be perpendicular to the substrate. And the orthographic projection of the first pixel driving circuit P1 on the substrate substrate and the orthographic projection of the second pixel driving circuit P2 on the substrate substrate may at least partially be arranged symmetrically with the intersection line of the mirror symmetry plane AA and the substrate substrate as the symmetry axis. The first pixel driving circuit P1 and the second pixel driving circuit P2 may form a repeating unit, and the display panel may include a plurality of repeating units distributed in an array in the first direction X and the second direction Y. Wherein, the second direction Y and the first direction X may intersect, for example, the first direction X may be a row direction, and the second direction Y may be a column direction. In addition, in this exemplary embodiment, the display panel may have design errors and process errors, and the first pixel driving circuit P1 and the second pixel driving circuit P2 may be roughly mirror symmetric with the mirror symmetry plane AA.

[0157] like Figure 6 , 7 As shown in FIG. 16 , the shielding layer includes a plurality of first shielding portions 81 distributed in an array along the first direction X and the second direction Y, and the first shielding portions 81 are connected to each other through second connecting portions 82 .

[0158] like Figure 6 , 8As shown in FIGS. 16 and 17, the first active layer may include a first active portion 71, a third active portion 73, a fourth active portion 74, a fifth active portion 75, a sixth active portion 76, a seventh active portion 77, an eighth active portion 78, a twenty-first active portion 721, a tenth active portion 710, an eleventh active portion 711, a twelfth active portion 712, a thirteenth active portion 713, a fourteenth active portion 714, a fifteenth active portion 715, a sixteenth active portion 716, a seventeenth active portion 717 and an eighteenth active portion 718. The first active portion 71 is used to form the channel region of the first transistor T1; the third active portion 73 can be used to form the channel region of the driving transistor T3; the fourth active portion 74 can be used to form the channel region of the fourth transistor T4; the fifth active portion 75 can be used to form the channel region of the fifth transistor T5; the sixth active portion 76 can be used to form the channel region of the sixth transistor T6; the seventh active portion 77 can be used to form the channel region of the seventh transistor T7; the eighth active portion 78 can be used to form the channel region of the eighth transistor T8; the twenty-first active portion 721 is connected between the third active portion 73 and the sixth active portion 76; the tenth active portion 710 is connected to the third active portion 73 and the sixth active portion 76; The twelfth active portion 712 is connected to both ends of the eighth active portion 78; the eleventh active portion 711 is connected between the fourth active portion 74 and the third active portion 73; the thirteenth active portion 713 is connected to the side of the fourth active portion 74 away from the third active portion 73; the fourteenth active portion 714 is connected to the side of the seventh active portion 77 away from the sixth active portion 76; the fifteenth active portion 715 is connected to the side of the fifth active portion 75 away from the third active portion 73; the sixteenth active portion 716 is connected between the seventh active portion 77 and the sixth active portion 76, and the seventeenth active portion 717 and the eighteenth active portion 718 are connected to both ends of the first active portion 71. The first active layer may be formed of polysilicon material, and accordingly, the first transistor T1, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be P-type low temperature polysilicon thin film transistors.

[0159] The orthographic projection of the first shielding portion 81 on the substrate can at least partially overlap with the orthographic projection of the third active portion 73 on the substrate, and the first shielding portion 81 can shield the third active portion 73 to improve the stability of the output characteristics of the driving transistor. The shielding layer can be a conductive structure, the shielding layer can be connected to a stable voltage source, and the shielding layer can play a signal shielding role for the pixel driving circuit.

[0160] like Figure 6 , 9 As shown in FIG. 16 and FIG. 17 , the first gate layer may include: a first conductive portion 11, a second gate line G2, an enable signal line EM, a first reset signal line Re1, and a second reset signal line Re2. The second gate line G2 may be used to provide Figure 2The second gate drive signal terminal; the enable signal line EM can be used to provide Figure 2 The first reset signal line Re1 can be used to provide Figure 2 The first reset signal terminal in; the second reset signal line Re2 can be used to provide Figure 2 The second reset signal terminal in. The orthographic projection of the second gate line G2 on the substrate, the orthographic projection of the enable signal line EM on the substrate, the orthographic projection of the first reset signal line Re1 on the substrate, and the orthographic projection of the second reset signal line Re2 on the substrate can all extend along the first direction X. The orthographic projection of the second gate line G2 on the substrate covers the orthographic projection of the fourth active portion 74 on the substrate, and a partial structure of the second gate line G2 is used to form the gate of the fourth transistor. The orthographic projection of the enable signal line EM on the substrate covers the orthographic projection of the fifth active portion 75 on the substrate, and the orthographic projection of the sixth active portion 76 on the substrate, and a partial structure of the enable signal line EM can be used to form the gates of the fifth transistor T5 and the sixth transistor T6, respectively. The orthographic projection of the first reset signal line Re1 on the substrate can cover the orthographic projection of the first active portion 71 on the substrate, and a partial structure of the first reset signal line Re1 is used to form the gate of the first transistor T1. The orthographic projection of the second reset signal line Re2 on the substrate can cover the orthographic projection of the seventh active portion 77 on the substrate and the orthographic projection of the eighth active portion 78 on the substrate, and the partial structure of the second reset signal line Re2 can be used to form the gates of the seventh transistor T7 and the eighth transistor T8, respectively. The orthographic projection of the first conductive portion 11 on the substrate covers the orthographic projection of the third active portion 73 on the substrate, and the first conductive portion 11 can be used to form the gate of the driving transistor T3 and the first electrode of the capacitor C. The display panel can use the first gate layer as a mask to perform conductor processing on the first active layer, that is, the area of ​​the first active layer covered by the first gate layer can form the channel region of the transistor, and the area of ​​the first active layer not covered by the first gate layer forms a conductor structure.

[0161] like Figure 6 , 10 As shown in FIG. 18 , the second gate layer may include: a third gate line 2G1, a second conductive portion 22, a first connecting portion 23, a fourth conductive portion 24, and a first initial signal line Vinit1. The orthographic projection of the third gate line 2G1 on the substrate extends along the first direction X. The third gate line 2G1 may be used to provide Figure 2 The first gate drive signal terminal in the first direction X can be connected by the first connecting portion 23. The first initial signal line Vinit1 is used to provide Figure 2The first initial signal terminal in.

[0162] like Figure 6 , 11 , 19, the second active layer may include an active portion 9, and the active portion 9 may include: a second active portion 92, a ninth active portion 99, a nineteenth active portion 919, and a twentieth active portion 920, wherein the nineteenth active portion 919 is connected to an end of the second active portion 92 away from the ninth active portion 99, and the twentieth active portion 920 is connected to an end of the ninth active portion 99 away from the second active portion 92. The second active portion 92 is used to form a channel region of the second transistor T2, and the ninth active portion 99 is used to form a channel region of the ninth transistor T9. The orthographic projection of the third gate line 2G1 on the substrate may cover the orthographic projection of the second active portion 92 on the substrate, and a partial structure of the third gate line 2G1 may be used to form the bottom gate of the second transistor T2. The orthographic projection of the fourth conductive portion 24 on the substrate may cover the orthographic projection of the ninth active portion 99 on the substrate, and at least a partial structure of the fourth conductive portion 24 is used to form the bottom gate of the ninth transistor T9. The second active layer may be formed of indium gallium zinc oxide, and accordingly, the second transistor T2 and the ninth transistor T9 may be N-type metal oxide thin film transistors.

[0163] like Figure 6 , 12 As shown in FIG. 20 , the third gate layer may include a first gate line 3G1, a second initial signal line Vinit2, a third initial signal line Vinit3, and a fifth conductive portion 35. The orthographic projection of the first gate line 3G1 on the substrate, the orthographic projection of the second initial signal line Vinit2 on the substrate, and the orthographic projection of the third initial signal line Vinit3 on the substrate may all extend along the first direction X. The first gate line 3G1 may be used to provide Figure 2 The first gate driving signal terminal in the display panel, the positive projection of the first gate line 3G1 on the substrate can cover the positive projection of the second active portion 92 on the substrate, and a part of the structure of the first gate line 3G1 can be used to form the top gate of the second transistor T2. At the same time, the first gate line 3G1 can be connected to the third gate line 2G1 through a via located in the frame area of ​​the display panel. The second initial signal line Vinit2 can be used to provide Figure 2 The second initial signal terminal, the third initial signal line Vinit3 can be used to provide Figure 2The third initial signal terminal in. The orthographic projection of the fifth conductive portion 35 on the substrate covers the orthographic projection of the ninth active portion 99 on the substrate, and at least part of the structure of the fifth conductive portion 35 is used to form the top gate of the ninth transistor. The orthographic projection of the second initial signal line Vinit2 on the substrate can at least partially overlap with the orthographic projection of the second reset signal line Re2 in the pixel driving circuit of this row on the substrate, and the orthographic projection of the third initial signal line Vinit3 on the substrate can at least partially overlap with the orthographic projection of the enable signal line EM in the pixel driving circuit of this row on the substrate. This arrangement can improve the transmittance and integration of the display panel. In addition, the display panel can use the third gate layer as a mask to perform conductor processing on the second active layer, that is, the area covered by the third gate layer in the second active layer can form a channel region of the transistor, and the area not covered by the third gate layer in the second active layer forms a conductor structure.

[0164] It should be noted that in other exemplary embodiments, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 can also be located in other conductive layers. For example, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 can also be located in the second gate layer, the first source and drain layer, etc.

[0165] like Figure 6 , 13, 21, the first source-drain layer may include a first bridge portion 41, a second bridge portion 42, a third bridge portion 43, a fourth bridge portion 44, a fifth bridge portion 45, a sixth bridge portion 46, a seventh bridge portion 47, an eighth bridge portion 48, a ninth bridge portion 49, and a tenth bridge portion 410. The first bridge portion 41 may be connected to the fourth conductive portion 24 and the fifth conductive portion 35 through vias, respectively, to connect the bottom gate and the top gate of the ninth transistor T9. The second bridge portion 42 may be connected to the twenty-first active portion 721, the nineteenth active portion 919, and the seventeenth active portion 717 through vias, respectively, to connect the second electrode of the first transistor T1, the second electrode of the second transistor T2, and the second electrode of the driving transistor T3. The third bridge portion 43 is connected to the eighteenth active portion 718 and the first initial signal line Vinit1 through vias, respectively, to connect the first electrode of the first transistor T1 and the first initial signal terminal. The fourth bridge portion 44 is connected to the fourteenth active portion 714 and the second initial signal line Vinit2 through vias, respectively, to connect the first electrode of the seventh transistor T7 and the second initial signal line. The fifth bridge portion 45 is connected to the thirteenth active portion 713 through vias, to connect the first electrode of the fourth transistor T4. The sixth bridge portion 46 is connected to the eleventh active portion 711 and the tenth active portion 710 through vias, respectively, to connect the second electrode of the eighth transistor T8 and the first electrode of the driving transistor T3. The seventh bridge portion 47 is connected to the first connection portion 23 and the fifteenth active portion 715 through vias, respectively, to connect the second electrode of the capacitor C and the first electrode of the fifth transistor T5. In the same repeating unit, the two fifth active portions 75 can be connected through the fifteenth active portion 715, and the two pixel driving circuits in the same repeating unit can share the same seventh bridge portion 47. The eighth bridge portion 48 is connected to the sixteenth active portion 716 through vias, to connect the second electrode of the seventh transistor T7 and the second electrode of the sixth transistor T6. The ninth bridge portion 49 is connected to the twentieth active portion 920 and the first conductive portion 11 through vias, respectively, to connect the gate of the driving transistor T3 and the first electrode of the second transistor T2, wherein an opening 221 may be formed on the second conductive portion 22, and a via connected between the ninth bridge portion 49 and the first conductive portion 11 is provided through the opening 221. The tenth bridge portion 410 may be connected to the third initial signal line Vinit3 and the twelfth active portion 712 through vias, respectively, to connect the first electrode of the eighth transistor and the third initial signal line Vinit3, and two eighth active portions 78 in the same repeating unit may be connected through the twelfth active portion 712, and two pixel driving circuits in the same repeating unit may share the same tenth bridge portion 410.

[0166] like Figure 6 , 13As shown in , 21, the first source-drain layer may also include a column-oriented initial signal line Vinitx, and the orthographic projection of the column-oriented initial signal line Vinitx on the substrate extends along the second direction Y. There may be multiple column-oriented initial connection lines Vinitx, and the column-oriented initial connection lines Vinitx may be connected to the same type of row-oriented initial signal lines intersecting with their orthographic projections on the substrate through vias, so as to form a grid structure of the row-oriented initial signal lines, and this arrangement may reduce the voltage difference of the initial signal ends at different positions of the display panel. Among them, the row-oriented initial signal lines may include one or more of the above-mentioned first initial signal lines, second initial signal lines, and third initial signal lines. For example, three adjacent columns of pixel driving circuits may be respectively provided with initial connection lines Vinitx, wherein one initial connection line Vinitx is connected to the first initial signal line, one initial connection line Vinitx is connected to the second initial signal line, and one initial connection line Vinitx is connected to the third initial signal line.

[0167] like Figure 6 , 14 As shown in FIG. 22, the second source-drain layer may include: an eleventh bridge portion 511, a twelfth bridge portion 512, a thirteenth bridge portion 513, and a first power line VDD. The eleventh bridge portion 511 may be connected to the first bridge portion 41 through a via hole. The twelfth bridge portion 512 may be connected to the fifth bridge portion 45 through a via hole. The thirteenth bridge portion 513 may be connected to the eighth bridge portion 48 through a via hole. The first power line VDD may be used to provide Figure 2 The first power supply end in the first power supply line VDD, the orthographic projection of the first power supply line VDD on the substrate can extend along the second direction Y, and the first power supply line VDD can be connected to the seventh bridge portion 47 through a via hole.

[0168] like Figure 6 , 15 As shown, the third source-drain layer may include: a data line Da, a fourth gate line G4, and a fourteenth bridge portion 614. The orthographic projections of the data line Da and the fourth gate line G4 on the substrate may extend along the second direction Y. The data line Da is used to provide Figure 2 The fourth gate line G4 is used to provide a data signal terminal. Figure 2 The data line Da can be connected to the twelfth bridge portion 512 through a via hole to connect the data signal terminal and the first electrode of the fourth transistor. The fourth gate line G4 can be connected to the eleventh bridge portion 511 through a via hole to connect the gate of the ninth transistor T9. The fourteenth bridge portion 614 can be connected to the thirteenth bridge portion 513 through a via hole, and the fourteenth bridge portion 614 can be used to connect the first electrode of the light-emitting unit.

[0169] It should be noted that if Figure 6 , 21As shown in 22, the black squares drawn on the side of the first source-drain layer away from the substrate substrate represent the via holes of other layers connected to the first source-drain layer facing the substrate substrate side; the black squares drawn on the side of the second source-drain layer away from the substrate substrate represent the via holes of other layers connected to the second source-drain layer facing the substrate substrate side; the black squares drawn on the side of the third source-drain layer away from the substrate substrate represent the via holes of other layers connected to the third source-drain layer facing the substrate substrate side; the black squares drawn on the side of the electrode layer away from the substrate substrate represent the via holes of other layers connected to the electrode layer facing the substrate substrate side. Different via holes represented by black squares at different positions can pass through different insulating layers.

[0170] like Fig.23 As shown, Figure 6The display panel is shown in a partial cross-sectional view taken along the dotted line BB. The display panel may further include a buffer layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104, a fifth insulating layer 105, a first dielectric layer 106, a passivation layer 107, a first flat layer 108, and a second flat layer 109. The substrate 100, the shielding layer, the buffer layer 101, the first active layer, the second insulating layer 102, the first gate layer, the third insulating layer 103, the second gate layer, the fourth insulating layer 104, the second active layer, the fifth insulating layer 105, the third gate layer, the first dielectric layer 106, the first source-drain layer, the passivation layer 107, the first flat layer 108, the second source-drain layer, the second flat layer 109, and the third source-drain layer are stacked in sequence. The buffer layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 may be a single-layer structure or a multi-layer structure, and the materials of the buffer layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 may be at least one of silicon nitride, silicon oxide, and silicon oxynitride; the first dielectric layer 106 may be a silicon nitride layer; the materials of the first flat layer 108 and the second flat layer 109 may be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG), etc. The passivation layer 107 may be a silicon oxide layer. The substrate 100 may include a glass substrate, a barrier layer, and a polyimide layer stacked in sequence, and the barrier layer may be an inorganic material. The material of the first gate layer, the second gate layer, and the third gate layer may be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy, or a molybdenum / titanium alloy or a laminated conductive layer. The material of the first source-drain layer, the second source-drain layer, and the third source-drain layer may include a metal material, for example, one of molybdenum, aluminum, copper, titanium, niobium, or an alloy, or a molybdenum / titanium alloy or a laminated layer, or a titanium / aluminum / titanium laminated conductive layer. The square resistance of any one of the first source-drain layer, the second source-drain layer, and the third source-drain layer may be less than the square resistance of any one of the first gate layer, the second gate layer, and the third gate layer.

[0171] This exemplary embodiment also provides another display panel, which may also include a base substrate, a shielding layer, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first source-drain layer, a second source-drain layer, and a third source-drain layer stacked in sequence. An insulating layer may be provided between the adjacent layers. Figure 24-27 As shown, Fig.24 This is a structural layout of a shielding layer, a first active layer, a first gate layer, a second gate layer, and a third gate layer in an exemplary embodiment of a display panel disclosed in the present invention. Fig.25 for Fig.24 The structural layout of the shielding layer in the display panel is shown. Fig.26 for Fig.24 The structural layout of the second gate layer in the display panel is shown. Fig. 27 for Fig.24 The structural layout of the shielding layer, the first active layer, the first gate layer and the second gate layer in the display panel is shown.

[0172] Compared to Figure 6 The embodiment shown, Fig.24 The shielding layer and the second gate layer in the display panel shown are different.

[0173] like Figure 24-27 As shown, compared to Figure 6 In the embodiment shown, the shielding layer also includes a sixth conductive portion 86, and the conductive layer where the sixth conductive portion 86 is located is located between the active layer where the ninth active portion 99 is located and the base substrate, and the orthographic projection of the sixth conductive portion 86 on the base substrate and the orthographic projection of the ninth active portion 99 on the base substrate at least partially overlap, and optionally, the orthographic projection of the sixth conductive portion 86 on the base substrate can cover the orthographic projection of the ninth active portion 99 on the base substrate. The sixth conductive portion 86 can be connected to a stable power supply terminal, and the sixth conductive portion 86 can stabilize the sixth conductive portion 86, thereby reducing the gate-source capacitance of the ninth transistor, and further improving the above-mentioned split-screen problem. Figure 24-27 As shown, the shielding layer itself includes a first shielding portion 81 and a second connecting portion 82 connected between two adjacent first shielding portions 81 in the second direction Y, and the sixth conductive portion 86 can be connected to the first shielding portion 81 and the second connecting portion 82. For example, the sixth conductive portion 86 can be a protrusion connected to the second connecting portion 82, and the orthographic projection of the sixth conductive portion 86 on the base substrate is located on one side of the orthographic projection of the second connecting portion 82 on the base substrate in the first direction X. Figure 24-27 As shown, compared to Figure 6 In the illustrated embodiment, the second gate layer is not provided with the fourth conductive portion.

[0174] It should be understood that in other exemplary embodiments, the sixth conductive portion connected to the stable power supply terminal may also be located in other conductive layers, and the sixth conductive portion may be located in any conductive layer on the side of the second active layer facing the substrate, for example, the sixth conductive portion may be located in the first gate layer, the second gate layer, etc. In addition, the sixth conductive portion may also be located in other additional conductive layers. Fig.47, is a cross-sectional view of another exemplary embodiment of the display panel of the present disclosure, wherein the sixth conductive portion 86 is located in the second gate layer, and the sixth conductive portion 86 can be connected to the shielding layer through a via. In other exemplary embodiments, the sixth conductive portion 86 can also be connected to the first power line VDD in the second source and drain layer through a via. The sixth conductive portion located in the second gate layer and the ninth active portion 99 located in the second active layer are close to each other, so that the sixth conductive portion can have a better voltage stabilizing effect on the ninth active portion 99. For another example, Fig.48 As shown, it is a cross-sectional view of another exemplary embodiment of the display panel of the present disclosure, wherein the sixth conductive portion 86 can be located in the first gate layer, and the sixth conductive portion 86 can be connected to the shielding layer through a via. In other exemplary embodiments, the sixth conductive portion 86 can also be connected to the first power line VDD in the second source and drain layer through a via. The sixth conductive portion located in other conductive layers can be connected to the shielding layer through a via to connect to a stable power supply terminal, and the sixth conductive portion located in other conductive layers can also be connected to the first power line VDD located in the second source and drain layer through a via to connect to a stable power supply terminal. In addition, the sixth conductive portion located in other conductive layers can also be connected to other stable power supply terminals in the display panel.

[0175] It should be noted that Fig.24 Other structures of the display panel shown can be Figure 6 The display panels shown are identical.

[0176] like Fig.28 FIG. 1 is a schematic diagram of another exemplary embodiment of a pixel driving circuit disclosed in the present invention. Figure 2 Compared with the pixel driving circuit shown in Fig.28 The ninth transistor T9 in the pixel driving circuit is a P-type transistor.

[0177] This exemplary embodiment also provides another display panel, which may also include a base substrate, a shielding layer, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first source-drain layer, a second source-drain layer, and a third source-drain layer stacked in sequence. An insulating layer may be provided between the adjacent layers. Figure 29-45 As shown, Fig.29 This is a structural diagram of an exemplary embodiment of the display panel disclosed herein. Fig.30 for Fig.29 The structural layout of the middle occlusion layer, Fig.31 for Fig.29 The structural layout of the first active layer in Fig.32 for Fig.29 The structural layout of the first gate layer in Fig.33 for Fig.29 The structural layout of the second gate layer in Fig.34 for Fig.29The structural layout of the second active layer, Fig.35 for Fig.29 The structural layout of the third gate layer, Fig.36 for Fig.29 The structural layout of the first source and drain layer in the figure. Fig.37 for Fig.29 The structural layout of the second source and drain layer in the figure. Fig.38 for Fig.29 The structural layout of the third source and drain layer. Fig.39 for Fig.29 The structural layout of the middle shielding layer and the first active layer. Fig.40 for Fig.29 The structural layout of the middle shielding layer, the first active layer, and the first gate layer. Fig.41 for Fig.29 The structural layout of the middle shielding layer, the first active layer, the first gate layer, and the second gate layer. Fig.42 for Fig.29 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer, Fig.43 for Fig.29 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer, Fig.44 for Fig.29 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source and drain layer, Fig.45 for Fig.29 Structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source and drain layer, and the second source and drain layer.

[0178] The display panel may include multiple Fig.28 In the pixel driving circuit shown, a plurality of pixel driving circuits are arranged in an array in a first direction X and a second direction Y.

[0179] like Fig.29As shown, the plurality of pixel driving circuits may include a first pixel driving circuit P1 and a second pixel driving circuit P2 adjacently distributed in a first direction X, and at least part of the structure of the first pixel driving circuit P1 and the second pixel driving circuit P2 may be arranged in mirror symmetry with the mirror symmetry plane AA. Wherein, the mirror symmetry plane AA may be perpendicular to the substrate. And the orthographic projection of the first pixel driving circuit P1 on the substrate substrate and the orthographic projection of the second pixel driving circuit P2 on the substrate substrate may at least partially be arranged symmetrically with the intersection line of the mirror symmetry plane AA and the substrate substrate as the symmetry axis. The first pixel driving circuit P1 and the second pixel driving circuit P2 may form a repeating unit, and the display panel may include a plurality of repeating units distributed in an array in the first direction X and the second direction Y. Wherein, the second direction Y and the first direction X may intersect, for example, the first direction X may be a row direction, and the second direction Y may be a column direction. In addition, in this exemplary embodiment, the display panel may have design errors and process errors, and the first pixel driving circuit P1 and the second pixel driving circuit P2 may be roughly mirror symmetric with the mirror symmetry plane AA.

[0180] like Fig.29 , 30 As shown in Figure 39, the shielding layer includes a plurality of first shielding portions 81 and second connecting portions 82 distributed in an array along the first direction X and the second direction Y, and the first shielding portions 81 are connected to each other through the second connecting portions 82.

[0181] like Fig.29 , 31, 39, and 40, the first active layer may include: a first active portion 71, a third active portion 73, a fourth active portion 74, a fifth active portion 75, a sixth active portion 76, a seventh active portion 77, an eighth active portion 78, a ninth active portion 79, a twentieth active portion 720, a twenty-first active portion 721, a tenth active portion 710, an eleventh active portion 711, a twelfth active portion 712, a thirteenth active portion 713, a fourteenth active portion 714, a fifteenth active portion 715, a sixteenth active portion 716, a seventeenth active portion 717, and an eighteenth active portion 718. The first active portion 71 is used to form the channel region of the first transistor T1; the third active portion 73 can be used to form the channel region of the driving transistor T3; the fourth active portion 74 can be used to form the channel region of the fourth transistor T4; the fifth active portion 75 can be used to form the channel region of the fifth transistor T5; the sixth active portion 76 can be used to form the channel region of the sixth transistor T6; the seventh active portion 77 can be used to form the channel region of the seventh transistor T7; the eighth active portion 78 can be used to form the channel region of the eighth transistor T8; the ninth active portion 79 can be used to form the channel region of the ninth transistor T9; the twenty-first active portion 721 is connected between the third active portion 73 and the sixth active portion 76; the tenth active portion 710 and the twelfth active portion 711 are connected to each other; The source portion 712 is connected to both ends of the eighth active portion 78; the eleventh active portion 711 is connected between the fourth active portion 74 and the third active portion 73; the thirteenth active portion 713 is connected to the side of the fourth active portion 74 away from the third active portion 73; the fourteenth active portion 714 is connected to the side of the seventh active portion 77 away from the sixth active portion 76; the fifteenth active portion 715 is connected to the side of the fifth active portion 75 away from the third active portion 73; the sixteenth active portion 716 is connected between the seventh active portion 77 and the sixth active portion 76; the seventeenth active portion 717 and the eighteenth active portion 718 are connected to both ends of the first active portion 71; the twentieth active portion 720 and the twenty-second active portion 722 are connected to both ends of the ninth active portion 79. The first active layer may be formed of polysilicon material, and accordingly, the first transistor T1, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 may be P-type low-temperature polysilicon thin film transistors.

[0182] The orthographic projection of the first shielding portion 81 on the substrate can at least partially overlap with the orthographic projection of the third active portion 73 on the substrate, and the first shielding portion 81 can shield the third active portion 73 to improve the stability of the output characteristics of the driving transistor. The shielding layer can be a conductive structure, the shielding layer can be connected to a stable voltage source, and the shielding layer can play a signal shielding role for the pixel driving circuit.

[0183] like Fig.29 , 30As shown in Figures 39, the shielding layer also includes a sixth conductive portion 86, and the conductive layer where the sixth conductive portion 86 is located is located between the active layer where the ninth active portion 79 is located and the base substrate. The orthographic projection of the sixth conductive portion 86 on the base substrate and the orthographic projection of the ninth active portion 79 on the base substrate at least partially overlap. Optionally, the orthographic projection of the sixth conductive portion on the base substrate can cover the orthographic projection of the ninth active portion 79 on the base substrate. The sixth conductive portion 86 can be connected to a stable power supply terminal, and the sixth conductive portion 86 can stabilize the voltage of the sixth conductive portion 86, thereby reducing the gate-source capacitance of the ninth transistor, and further improving the above-mentioned split screen problem. The shielding layer itself includes a first shielding portion 81 and a second connecting portion 82 connected between two adjacent first shielding portions 81 in the second direction Y. The sixth conductive portion 86 can be connected to the first shielding portion 81 and the second connecting portion 82. For example, the sixth conductive portion 86 may be a protrusion connected to the second connecting portion 82 , and the orthographic projection of the sixth conductive portion 86 on the base substrate may be located on one side of the orthographic projection of the second connecting portion 82 on the base substrate in the first direction X.

[0184] like Fig.29 , 32 As shown in FIG. 40 , the first gate layer may include: a first conductive portion 11, a fifth conductive portion 15, a second gate line G2, an enable signal line EM, a first reset signal line Re1, and a second reset signal line Re2. The second gate line G2 may be used to provide Figure 2 The second gate drive signal terminal; the enable signal line EM can be used to provide Figure 2 The first reset signal line Re1 can be used to provide Figure 2 The first reset signal terminal in; the second reset signal line Re2 can be used to provide Figure 2The second reset signal terminal in. The orthographic projection of the second gate line G2 on the substrate, the orthographic projection of the enable signal line EM on the substrate, the orthographic projection of the first reset signal line Re1 on the substrate, and the orthographic projection of the second reset signal line Re2 on the substrate can all extend along the first direction X. The orthographic projection of the second gate line G2 on the substrate covers the orthographic projection of the fourth active portion 74 on the substrate, and a partial structure of the second gate line G2 is used to form the gate of the fourth transistor. The orthographic projection of the enable signal line EM on the substrate covers the orthographic projection of the fifth active portion 75 on the substrate, and the orthographic projection of the sixth active portion 76 on the substrate, and a partial structure of the enable signal line EM can be used to form the gates of the fifth transistor T5 and the sixth transistor T6, respectively. The orthographic projection of the first reset signal line Re1 on the substrate can cover the orthographic projection of the first active portion 71 on the substrate, and a partial structure of the first reset signal line Re1 is used to form the gate of the first transistor T1. The orthographic projection of the second reset signal line Re2 on the substrate can cover the orthographic projection of the seventh active portion 77 on the substrate and the orthographic projection of the eighth active portion 78 on the substrate, and a partial structure of the second reset signal line Re2 can be used to form the gates of the seventh transistor T7 and the eighth transistor T8, respectively. The orthographic projection of the first conductive portion 11 on the substrate covers the orthographic projection of the third active portion 73 on the substrate, and the first conductive portion 11 can be used to form the gate of the driving transistor T3 and the first electrode of the capacitor C. The orthographic projection of the fifth conductive portion 15 on the substrate covers the orthographic projection of the ninth active portion 79 on the substrate, and at least a partial structure of the fifth conductive portion 15 is used to form the gate of the ninth transistor T9.

[0185] The display panel can use the first gate layer as a mask to conduct the first active layer, that is, the area of ​​the first active layer covered by the first gate layer can form a channel region of the transistor, and the area of ​​the first active layer not covered by the first gate layer forms a conductor structure.

[0186] like Fig.29 , 33 As shown in FIG. 41 , the second gate layer may include: a third gate line 2G1, a second conductive portion 22, a first connecting portion 23, and a first initial signal line Vinit1. The orthographic projection of the third gate line 2G1 on the substrate extends along the first direction X. The third gate line 2G1 may be used to provide Fig.28 The first gate drive signal terminal in the first direction X can be connected by the first connecting portion 23. The first initial signal line Vinit1 is used to provide Figure 2 The first initial signal terminal in.

[0187] like Fig.29 , 34 42, the second active layer may include an active portion 9, and the active portion 9 may include: a second active portion 92, a nineteenth active portion 919, and a twenty-third active portion 923, wherein the nineteenth active portion 919 and the twenty-third active portion 923 are connected to both ends of the second active portion 92. The second active portion 92 is used to form a channel region of the second transistor T2. The orthographic projection of the third gate line 2G1 on the substrate may cover the orthographic projection of the second active portion 92 on the substrate, and a partial structure of the third gate line 2G1 may be used to form a bottom gate of the second transistor T2. The second active layer may be formed of indium gallium zinc oxide, and accordingly, the second transistor T2 may be an N-type metal oxide thin film transistor.

[0188] like Fig.29 , 35 43, the third gate layer may include a first gate line 3G1, a second initial signal line Vinit2, and a third initial signal line Vinit3. The orthographic projection of the first gate line 3G1 on the substrate, the orthographic projection of the second initial signal line Vinit2 on the substrate, and the orthographic projection of the third initial signal line Vinit3 on the substrate may all extend along the first direction X. The first gate line 3G1 may be used to provide Fig.28 The first gate driving signal terminal in the display panel, the positive projection of the first gate line 3G1 on the substrate can cover the positive projection of the second active portion 92 on the substrate, and a part of the structure of the first gate line 3G1 can be used to form the top gate of the second transistor T2. At the same time, the first gate line 3G1 can be connected to the third gate line 2G1 through a via located in the frame area of ​​the display panel. The second initial signal line Vinit2 can be used to provide Fig.28 The second initial signal terminal, the third initial signal line Vinit3 can be used to provide Fig.28 The third initial signal terminal in the display panel. The orthographic projection of the second initial signal line Vinit2 on the substrate substrate can at least partially overlap with the orthographic projection of the second reset signal line Re2 in the pixel driving circuit of this row on the substrate substrate, and the orthographic projection of the third initial signal line Vinit3 on the substrate substrate can at least partially overlap with the orthographic projection of the enable signal line EM in the pixel driving circuit of this row on the substrate substrate. This setting can improve the light transmittance and integration of the display panel. In addition, the display panel can use the third gate layer as a mask to conduct the second active layer, that is, the area of ​​the second active layer covered by the third gate layer can form the channel area of ​​the transistor, and the area of ​​the second active layer not covered by the third gate layer forms a conductor structure.

[0189] It should be noted that in other exemplary embodiments, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 can also be located in other conductive layers. For example, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 can also be located in the second gate layer, the first source and drain layer, etc.

[0190] like Fig.29 , 36, 44 show that the first source-drain layer may include a first bridge portion 41, a second bridge portion 42, a third bridge portion 43, a fourth bridge portion 44, a fifth bridge portion 45, a sixth bridge portion 46, a seventh bridge portion 47, an eighth bridge portion 48, a ninth bridge portion 49, a tenth bridge portion 410, and a fifteenth bridge portion 415. The first bridge portion 41 may be connected to the fifth conductive portion 15 through a via hole to connect the gate of the ninth transistor T9. The second bridge portion 42 may be connected to the twenty-first active portion 721, the nineteenth active portion 919, and the seventeenth active portion 717 through via holes to connect the second electrode of the first transistor T1, the second electrode of the second transistor T2, and the second electrode of the driving transistor T3. The third bridge portion 43 is connected to the eighteenth active portion 718 and the first initial signal line Vinit1 through via holes to connect the first electrode of the first transistor T1 and the first initial signal terminal. The fourth bridge portion 44 is connected to the fourteenth active portion 714 and the second initial signal line Vinit2 through vias, respectively, to connect the first electrode of the seventh transistor T7 and the second initial signal line. The fifth bridge portion 45 is connected to the thirteenth active portion 713 through vias, to connect the first electrode of the fourth transistor T4. The sixth bridge portion 46 is connected to the eleventh active portion 711 and the tenth active portion 710 through vias, respectively, to connect the second electrode of the eighth transistor T8 and the first electrode of the driving transistor T3. The seventh bridge portion 47 is connected to the first connection portion 23 and the fifteenth active portion 715 through vias, respectively, to connect the second electrode of the capacitor C and the first electrode of the fifth transistor T5. In the same repeating unit, the two fifth active portions 75 can be connected through the fifteenth active portion 715, and the two pixel driving circuits in the same repeating unit can share the same seventh bridge portion 47. The eighth bridge portion 48 is connected to the sixteenth active portion 716 through vias, to connect the second electrode of the seventh transistor T7 and the second electrode of the sixth transistor T6. The ninth bridge portion 49 is connected to the twentieth active portion 920 and the first conductive portion 11 through vias, respectively, to connect the gate of the driving transistor T3 and the first electrode of the second transistor T2, wherein an opening 221 may be formed on the second conductive portion 22, and a via connected between the ninth bridge portion 49 and the first conductive portion 11 is provided through the opening 221. The tenth bridge portion 410 may be connected to the third initial signal line Vinit3 and the twelfth active portion 712 through vias, respectively, to connect the first electrode of the eighth transistor and the third initial signal line Vinit3, and the two eighth active portions 78 in the same repeating unit may be connected through the twelfth active portion 712, and the two pixel driving circuits in the same repeating unit may share the same tenth bridge portion 410. The fifteenth bridge portion 415 is connected to the twenty-third active portion 923 and the twenty-second active portion 722 through vias, respectively, to connect the second electrode of the ninth transistor T9 and the first electrode of the second transistor T2.

[0191] like Fig.29 , 3644 shows that the first source-drain layer may also include a column-oriented initial signal line Vinitx, and the orthographic projection of the column-oriented initial signal line Vinitx on the substrate extends along the second direction Y. There may be multiple column-oriented initial connection lines Vinitx, and the column-oriented initial connection lines Vinitx may be connected to the same type of row-oriented initial signal lines intersecting with their orthographic projections on the substrate through vias, so as to form a grid structure of the row-oriented initial signal lines. This arrangement may reduce the voltage difference of the initial signal ends at different positions of the display panel. Among them, the row-oriented initial signal lines may include one or more of the above-mentioned first initial signal lines, second initial signal lines, and third initial signal lines. For example, three adjacent columns of pixel driving circuits may be respectively provided with initial connection lines Vinitx, wherein one initial connection line Vinitx is connected to the first initial signal line, one initial connection line Vinitx is connected to the second initial signal line, and one initial connection line Vinitx is connected to the third initial signal line.

[0192] like Fig.29 , 37 , 45, the second source-drain layer may include: an eleventh bridge portion 511, a twelfth bridge portion 512, a thirteenth bridge portion 513, and a first power line VDD. The eleventh bridge portion 511 may be connected to the first bridge portion 41 through a via hole. The twelfth bridge portion 512 may be connected to the fifth bridge portion 45 through a via hole. The thirteenth bridge portion 513 may be connected to the eighth bridge portion 48 through a via hole. The first power line VDD may be used to provide Figure 2 The first power supply end in the first power supply line VDD, the orthographic projection of the first power supply line VDD on the substrate can extend along the second direction Y, and the first power supply line VDD can be connected to the seventh bridge portion 47 through a via hole.

[0193] like Fig.29 , 38 As shown, the third source-drain layer may include: a data line Da, a fourth gate line G4, and a fourteenth bridge portion 614. The orthographic projections of the data line Da and the fourth gate line G4 on the substrate may extend along the second direction Y. The data line Da is used to provide Figure 2 The fourth gate line G4 is used to provide a data signal terminal. Figure 2 The data line Da can be connected to the twelfth bridge portion 512 through a via hole to connect the data signal terminal and the first electrode of the fourth transistor. The fourth gate line G4 can be connected to the eleventh bridge portion 511 through a via hole to connect the gate of the ninth transistor T9. The fourteenth bridge portion 614 can be connected to the thirteenth bridge portion 513 through a via hole, and the fourteenth bridge portion 614 can be used to connect the first electrode of the light-emitting unit.

[0194] It should be noted that if Fig.29 , 44As shown in 45, the black squares drawn on the side of the first source-drain layer away from the substrate substrate represent the via holes of other layers connected to the first source-drain layer facing the substrate substrate side; the black squares drawn on the side of the second source-drain layer away from the substrate substrate represent the via holes of other layers connected to the second source-drain layer facing the substrate substrate side; the black squares drawn on the side of the third source-drain layer away from the substrate substrate represent the via holes of other layers connected to the third source-drain layer facing the substrate substrate side; the black squares drawn on the side of the electrode layer away from the substrate substrate represent the via holes of other layers connected to the electrode layer facing the substrate substrate side. Different via holes represented by black squares at different positions can pass through different insulating layers.

[0195] like Fig.46 As shown, Fig.29The display panel is shown in a partial cross-sectional view taken along the dotted line CC. The display panel may also include a buffer layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104, a fifth insulating layer 105, a first dielectric layer 106, a passivation layer 107, a first flat layer 108, and a second flat layer 109. The substrate 100, the shielding layer, the buffer layer 101, the first active layer, the second insulating layer 102, the first gate layer, the third insulating layer 103, the second gate layer, the fourth insulating layer 104, the second active layer, the fifth insulating layer 105, the third gate layer, the first dielectric layer 106, the first source-drain layer, the passivation layer 107, the first flat layer 108, the second source-drain layer, the second flat layer 109, and the third source-drain layer are stacked in sequence. The buffer layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 may be a single-layer structure or a multi-layer structure, and the materials of the buffer layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 may be at least one of silicon nitride, silicon oxide, and silicon oxynitride; the first dielectric layer 106 may be a silicon nitride layer; the materials of the first flat layer 108 and the second flat layer 109 may be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG), etc. The passivation layer 107 may be a silicon oxide layer. The substrate 100 may include a glass substrate, a barrier layer, and a polyimide layer stacked in sequence, and the barrier layer may be an inorganic material. The material of the first gate layer, the second gate layer, and the third gate layer may be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy, or a molybdenum / titanium alloy or a laminated conductive layer. The material of the first source-drain layer, the second source-drain layer, and the third source-drain layer may include a metal material, for example, one of molybdenum, aluminum, copper, titanium, niobium, or an alloy, or a molybdenum / titanium alloy or a laminated layer, or a titanium / aluminum / titanium laminated conductive layer. The square resistance of any one of the first source-drain layer, the second source-drain layer, and the third source-drain layer may be less than the square resistance of any one of the first gate layer, the second gate layer, and the third gate layer.

[0196] like Figure 6 As shown, the area of ​​the orthographic projection of the ninth active portion 99 on the substrate substrate is smaller than the area of ​​the orthographic projection of the second active portion 92 on the substrate substrate. This exemplary embodiment can reduce the gate-source parasitic capacitance of the ninth transistor T9 by reducing the area of ​​the orthographic projection of the ninth active portion 99 on the substrate substrate, thereby improving the above-mentioned split screen problem.

[0197] Optionally, the length of the channel region of the ninth transistor T9 is smaller than the length of the channel region of the second transistor T2; and / or the width of the channel region of the ninth transistor T9 is smaller than the width of the channel region of the second transistor T2.

[0198] It should be understood that the solution of reducing the area of ​​the channel region of the ninth transistor can also be applied to Fig.24 That is, the solution of reducing the area of ​​the positive projection of the ninth active portion 99 on the substrate to improve the split screen problem and the solution of stabilizing the ninth active portion 99 by the sixth conductive portion to improve the split screen problem can be applied to the same display panel. Similarly, the solution of reducing the area of ​​the ninth transistor channel region can also be applied to Fig.29 The display panel shown, accordingly, Fig.29 In the embodiment, an area of ​​an orthographic projection of the ninth active portion on the base substrate may be smaller than an area of ​​an orthographic projection of the first active portion on the base substrate.

[0199] In this exemplary embodiment, Figure 6 , 24 As shown in FIG. 29 , in the same pixel driving circuit, the orthographic projection of the channel region of the ninth transistor T9 on the base substrate is located between the orthographic projection of the second gate line G2 on the base substrate and the orthographic projection of the first reset signal line Re1 on the base substrate.

[0200] In this exemplary embodiment, Figure 6 , 24 As shown in FIG. 29 , in the first direction X of the same pixel driving circuit, the orthographic projection of the channel region of the ninth transistor T9 on the substrate is located between the orthographic projection of the channel region of the fourth transistor T4 on the substrate and the orthographic projection of the channel region of the second transistor T2 on the substrate.

[0201] In this exemplary embodiment, Figure 6 , 24 As shown in FIG. 29 , the length direction of the channel region of the second transistor is the second direction, and the length direction of the channel region of the ninth transistor is the first direction.

[0202] In this exemplary embodiment, Figure 6 , 24 As shown in FIG. 29 , the fourth gate line G4 is located in the third source-drain layer. It should be understood that in other exemplary embodiments, the fourth gate line G4 may also be located in other conductive layers such as the second source-drain layer and the first source-drain layer.

[0203] In this exemplary embodiment, Figure 6 , 24 As shown in FIG. 29 , the orthographic projection of the fourth gate line G4 on the base substrate and the orthographic projection of the first power line VDD on the base substrate at least partially overlap. The first power line VDD can shield the interference between the fourth gate line G4 and other signal terminals.

[0204] In this exemplary embodiment, Figure 6 , 24 As shown in , 29, the first power line VDD includes: a first extension portion VDD1 and a second extension portion VDD2, the size of the orthographic projection of the first extension portion VDD1 on the base substrate in the first direction X is larger than the size of the orthographic projection of the second extension portion VDD2 on the base substrate in the first direction; the orthographic projection of the fourth gate line G4 on the base substrate and the orthographic projection of the second extension portion VDD2 on the base substrate at least partially overlap.

[0205] In this exemplary embodiment, Figure 6 , 24 As shown in FIG. 29 , the orthographic projection of the first power line VDD on the substrate and the orthographic projection of the channel region of the ninth transistor T9 on the substrate at least partially overlap. The first power line VDD can shield and shield the ninth transistor T9.

[0206] In this exemplary embodiment, Figure 6 , 24 29, the orthographic projection of the first power line VDD on the substrate substrate and the orthographic projection of the second bridge portion 42 on the substrate substrate at least partially overlap, and / or the orthographic projection of the first power line VDD on the substrate substrate and the orthographic projection of the ninth bridge portion 49 on the substrate substrate at least partially overlap. The first power line VDD can shield and stabilize the second bridge portion 42 and the ninth bridge portion 49.

[0207] In this exemplary embodiment, Figure 6 , 24 As shown in , the first gate line 3G1 includes a third extension portion 3G13 and a fourth extension portion 3G14, the third extension portion 3G13 is used to form the gate of the second transistor T2, and the size of the orthogonal projection of the third extension portion 3G13 on the substrate in the second direction Y is greater than the size of the orthogonal projection of the fourth extension portion 3G14 on the substrate in the second direction Y; the second bridge portion 42 and the first gate line 3G1 are located in different conductive layers, the second bridge portion 42 includes a first sub-bridge portion 421, the orthogonal projection of the first sub-bridge portion 421 on the substrate extends along the second direction Y, and the orthogonal projection of the first sub-bridge portion 421 on the substrate intersects with the orthogonal projection of the fourth extension portion 3G14 on the substrate. This arrangement can reduce the parasitic capacitance between the second bridge portion 42 and the first gate line 3G1.

[0208] In this exemplary embodiment, Figure 6 , 24As shown in , 29, the second bridge portion 42 also includes: a second sub-bridge portion 422 and a third sub-bridge portion 423, the second sub-bridge portion 422 is connected to the second electrode of the first transistor through a via; the third sub-bridge portion 423 is connected to the second electrode of the second transistor and the second electrode of the driving transistor through a via; wherein the first sub-bridge portion 421 is connected between the second sub-bridge portion 422 and the third sub-bridge portion 423, the angle b between the orthographic projection of the first sub-bridge portion 421 on the substrate and the orthographic projection of the second sub-bridge portion 422 on the substrate is less than 180°, and the angle a between the orthographic projection of the first sub-bridge portion 421 on the substrate and the orthographic projection of the third sub-bridge portion 423 on the substrate is less than 180°.

[0209] like Fig.24 , 29 As shown, the shielding layer may further include a seventh conductive portion 87, and the orthographic projection of the seventh conductive portion 87 on the substrate covers the orthographic projection of the via hole between the ninth bridge portion 49 and the twentieth active portion 720 on the substrate. There is a position error when the via hole between the ninth bridge portion 49 and the twentieth active portion 720 is formed, which will lead to different light shielding degrees of the via hole in different pixel driving circuits, and further lead to inconsistent exposure sizes of the via hole. The seventh conductive portion 87 can make the exposure degree of the via hole consistent and the via hole size consistent in the exposure process.

[0210] In this exemplary embodiment, Fig.49 FIG. 2 is a structural layout diagram of another exemplary embodiment of the display panel disclosed in the present invention. The orthographic projection of the fourth gate line G4 on the substrate can be bent along the second direction Y, which can increase the overlapping area of ​​the orthographic projection of the fourth gate line G4 on the substrate and the orthographic projection of the first power line VDD on the substrate, thereby further improving the shielding effect of the first power line VDD on the fourth gate line G4.

[0211] This exemplary embodiment also provides a display device, which includes the above-mentioned display panel. The display device can be a display device such as a mobile phone, a tablet computer, a television, etc.

[0212] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The specification and embodiments are to be considered merely as exemplary, and the true scope and spirit of the present disclosure are indicated by the claims.

[0213] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The specification and embodiments are to be considered merely as exemplary, and the true scope and spirit of the present disclosure are indicated by the claims.

[0214] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A display panel, wherein: The display panel comprises: substrate substrate; A plurality of pixel driving circuits, wherein the orthographic projections of the plurality of pixel driving circuits on the substrate are distributed in an array along a first direction and a second direction, and the first direction and the second direction intersect; The pixel driving circuit includes a driving transistor, a second transistor, and a ninth transistor, wherein a first electrode of the ninth transistor is connected to a gate of the driving transistor, a second electrode of the ninth transistor is connected to a first electrode of the second transistor, and a second electrode of the second transistor is connected to a second electrode of the driving transistor; A first gate line, the orthographic projection of which on the substrate extends along the first direction, and the first gate line is used to provide a gate driving signal to second transistors in a plurality of pixel driving circuits distributed in the first direction; A fourth gate line, an orthographic projection of which on the substrate extends along the second direction, and the fourth gate line is used to provide a gate driving signal to a ninth transistor in a plurality of pixel driving circuits distributed in the second direction.

2. The display panel according to claim 1, wherein: The display panel further includes: a ninth active portion, the ninth active portion being used to form a channel region of the ninth transistor; A sixth conductive part, the sixth conductive part is connected to a stable power supply terminal, the conductive layer where the sixth conductive part is located is located between the active layer where the ninth active part is located and the base substrate, and the orthographic projection of the sixth conductive part on the base substrate and the orthographic projection of the ninth active part on the base substrate at least partially overlap.

3. The display panel according to claim 2, wherein: The display panel further includes: A shielding layer, located on one side of the base substrate, the shielding layer comprising a first shielding portion; A first active layer is located on a side of the shielding layer away from the base substrate, the first active layer comprises a third active portion, the third active portion is used to form a channel region of the driving transistor, and an orthographic projection of the first shielding portion on the base substrate and an orthographic projection of the third active portion on the base substrate at least partially overlap; Wherein, the sixth conductive portion is located on the shielding layer.

4. The display panel according to claim 3, wherein: The shielding layer also includes: a second connecting portion, the second connecting portion being connected between two adjacent first shielding portions in the second direction; The sixth conductive portion is connected to the second connecting portion, and an orthographic projection of the sixth conductive portion on the base substrate is located on one side of an orthographic projection of the second connecting portion on the base substrate in the first direction.

5. The display panel according to claim 1, wherein: The display panel further includes: a second active portion, the second active portion being used to form a channel region of the second transistor; a ninth active portion, the ninth active portion being used to form a channel region of the ninth transistor; The second active portion and the ninth active portion are located in the same active layer, and an area of ​​an orthographic projection of the ninth active portion on the base substrate is smaller than an area of ​​an orthographic projection of the second active portion on the base substrate.

6. The display panel according to claim 5, wherein: The length of the channel region of the ninth transistor is smaller than the length of the channel region of the second transistor; And / or, a width of a channel region of the ninth transistor is smaller than a width of a channel region of the second transistor.

7. The display panel according to claim 1, wherein: The pixel driving circuit further includes a first transistor, a first electrode of the first transistor is connected to a first initial signal line, a second electrode of the first transistor is connected to a second electrode of the driving transistor, and the display panel further includes: a first active portion, the first active portion being used to form a channel region of the first transistor; a ninth active portion, the ninth active portion being used to form a channel region of the ninth transistor; The first active portion and the ninth active portion are located in the same active layer, and an area of ​​an orthographic projection of the ninth active portion on the base substrate is smaller than an area of ​​an orthographic projection of the first active portion on the base substrate.

8. The display panel according to any one of claims 1 to 7, wherein: The driving transistor and the ninth transistor are P-type transistors, and the display panel further includes: The first active layer is located on one side of the base substrate, and the first active layer includes a third active portion and a ninth active portion. The third active portion is used to form a channel region of the driving transistor, and the ninth active portion is used to form a channel region of the ninth transistor.

9. The display panel according to any one of claims 1 to 7, wherein: The driving transistor is a P-type transistor, the ninth transistor is an N-type transistor, and the display panel further includes: A first active layer, located on one side of the base substrate, the first active layer comprising a third active portion, the third active portion being used to form a channel region of the driving transistor; The second active layer is located on a side of the first active layer away from the substrate, and the second active layer includes a ninth active portion, and the ninth active portion is used to form a channel region of the ninth transistor.

10. The display panel according to any one of claims 1 to 7, wherein: The pixel driving circuit further includes a first transistor and a fourth transistor, wherein a first electrode of the first transistor is connected to a first initial signal line, a second electrode of the first transistor is connected to a second electrode of the driving transistor, a first electrode of the fourth transistor is connected to a data line, and a second electrode of the fourth transistor is connected to a first electrode of the driving transistor; The display panel further includes: A first reset signal line, located at one side of the base substrate, wherein an orthographic projection of the first reset signal line on the base substrate extends along a first direction, and a partial structure of the first reset signal line is used to form a gate of the first transistor; A second gate line, located at one side of the base substrate, an orthographic projection of the second gate line on the base substrate extends along a first direction, and a partial structure of the second gate line is used to form a gate of the fourth transistor; Wherein, in the same pixel driving circuit, the orthographic projection of the channel region of the ninth transistor on the base substrate is located between the orthographic projection of the second gate line on the base substrate and the orthographic projection of the first reset signal line on the base substrate.

11. The display panel according to any one of claims 1 to 7, wherein: The pixel driving circuit further includes a fourth transistor, a first electrode of the fourth transistor is connected to the data line, and a second electrode of the fourth transistor is connected to the first electrode of the driving transistor; Wherein, in the first direction of the same pixel driving circuit, the orthographic projection of the channel region of the ninth transistor on the substrate is located between the orthographic projection of the channel region of the fourth transistor on the substrate and the orthographic projection of the channel region of the second transistor on the substrate.

12. The display panel according to any one of claims 1 to 7, wherein: The length direction of the channel region of the second transistor is the second direction, and the length direction of the channel region of the ninth transistor is the first direction.

13. The display panel according to any one of claims 1 to 7, wherein: The display panel further includes: a first source-drain layer, located at one side of the base substrate, the first source-drain layer comprising a ninth bridge portion, the ninth bridge portion connecting the first electrode of the ninth transistor and the gate of the driving transistor through via holes; a second source-drain layer, located on a side of the first source-drain layer away from the substrate, the second source-drain layer comprising a first power line, the first power line being used to provide a high-level power signal to the pixel driving circuit; The third source-drain layer is located on a side of the second source-drain layer away from the substrate, and the third source-drain layer includes the fourth gate line.

14. The display panel according to any one of claims 1 to 7, wherein: The display panel further includes: A first power line, the first power line is used to provide a high-level power signal to the pixel driving circuit, and an orthographic projection of the first power line on the substrate extends along the second direction; An orthographic projection of the fourth gate line on the base substrate and an orthographic projection of the first power line on the base substrate at least partially overlap.

15. The display panel according to claim 14, wherein: The first power line comprises: a first extension portion and a second extension portion, wherein a size of an orthographic projection of the first extension portion on the base substrate in the first direction is larger than a size of an orthographic projection of the second extension portion on the base substrate in the first direction; An orthographic projection of the fourth gate line on the base substrate and an orthographic projection of the second extension portion on the base substrate at least partially overlap.

16. The display panel according to any one of claims 1 to 7, wherein: The display panel further includes: A first power line is located on one side of the substrate, and is used to provide a high-level power signal to the pixel driving circuit. The orthographic projection of the first power line on the substrate and the orthographic projection of the channel region of the ninth transistor on the substrate at least partially overlap.

17. The display panel according to any one of claims 1 to 7, wherein: The display panel further includes: a first source-drain layer, located at one side of the base substrate, the first source-drain layer comprising a second bridge portion and a ninth bridge portion, the second bridge portion respectively connecting the second electrode of the driving transistor and the second electrode of the second transistor through via holes, and the ninth bridge portion respectively connecting the first electrode of the ninth transistor and the gate of the driving transistor through via holes; A second source-drain layer is located on a side of the first source-drain layer away from the substrate, the second source-drain layer comprises a first power line, and the first power line is used to provide a high-level power signal to the pixel driving circuit; The orthographic projection of the first power line on the base substrate and the orthographic projection of the second bridge portion on the base substrate at least partially overlap, and / or the orthographic projection of the first power line on the base substrate and the orthographic projection of the ninth bridge portion on the base substrate at least partially overlap.

18. The display panel according to any one of claims 1 to 7, wherein: The pixel driving circuit further comprises a first transistor, a first electrode of the first transistor is connected to a first initial signal line, and a second electrode of the first transistor is connected to a second electrode of the driving transistor; The display panel further includes: A second bridge portion, located at one side of the base substrate, the second bridge portion is connected to the second electrode of the driving transistor, the second electrode of the second transistor, and the second electrode of the first transistor through via holes respectively; The first gate line includes a third extension portion and a fourth extension portion, the third extension portion is used to form the gate of the second transistor, and the size of the orthogonal projection of the third extension portion on the substrate in the second direction is greater than the size of the orthogonal projection of the fourth extension portion on the substrate in the second direction; The second bridge portion and the first gate line are located in different conductive layers, the second bridge portion includes a first sub-bridge portion, the orthographic projection of the first sub-bridge portion on the base substrate extends along the second direction, and the orthographic projection of the first sub-bridge portion on the base substrate intersects with the orthographic projection of the fourth extension portion on the base substrate.

19. The display panel according to claim 18, wherein: The second bridging portion further includes: a second sub-bridge portion, wherein the second sub-bridge portion is connected to a second electrode of the first transistor through a via hole; a third sub-bridge portion, wherein the third sub-bridge portion is connected to the second electrode of the second transistor and the second electrode of the driving transistor through a via hole; Among them, the first sub-bridge portion is connected between the second sub-bridge portion and the third sub-bridge portion, the angle between the orthographic projection of the first sub-bridge portion on the substrate and the orthographic projection of the second sub-bridge portion on the substrate is less than 180°, and the angle between the orthographic projection of the first sub-bridge portion on the substrate and the orthographic projection of the third sub-bridge portion on the substrate is less than 180°.

20. The display panel according to any one of claims 1 to 7, wherein: The display panel further includes a light emitting unit, the pixel driving circuit is used to drive the light emitting unit to emit light, and the pixel driving circuit further includes: a first transistor, wherein a first electrode of the first transistor is connected to a first initial signal line, and a second electrode of the first transistor is connected to a second electrode of the driving transistor; a fourth transistor, a first electrode of which is connected to the data line, and a second electrode of which is connected to the first electrode of the driving transistor; a fifth transistor, a first electrode of which is connected to the first power line, and a second electrode of which is connected to the first electrode of the driving transistor; a sixth transistor, a first electrode of which is connected to the second electrode of the driving transistor, and a second electrode of which is connected to the light-emitting unit; a seventh transistor, a first electrode connected to the second initial signal line, and a second electrode connected to the light emitting unit; an eighth transistor, a first electrode of which is connected to the third initial signal line, and a second electrode of which is connected to the first electrode of the driving transistor; a capacitor, a first electrode of which is connected to the gate of the driving transistor, and a second electrode of which is connected to the first power line; Among them, the first transistor, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are P-type transistors, the second transistor is an N-type transistor, and the ninth transistor is an N-type transistor or a P-type transistor.

21. The display panel according to claim 1, wherein: The pixel driving circuit includes a P-type transistor and an N-type transistor, and the display panel further includes: A first active layer, located on one side of the substrate, wherein a portion of the first active layer is used to form a channel region of a P-type transistor in the pixel driving circuit; A first gate layer, located on a side of the first active layer away from the substrate, wherein a portion of the first gate layer is used to form a gate of a P-type transistor in the pixel driving circuit; A second gate layer, located on a side of the first gate layer away from the base substrate, a portion of the second gate layer being used to form a bottom gate of an N-type transistor in the pixel driving circuit; A second active layer, located on a side of the second gate layer away from the substrate, wherein a portion of the second active layer is used to form a channel region of an N-type transistor in the pixel driving circuit; A third gate layer, located on a side of the second active layer away from the substrate, wherein a portion of the third gate layer is used to form a top gate of an N-type transistor in the pixel driving circuit; The first source-drain layer is located at a side of the third gate layer away from the substrate, and a part of the structure of the first source-drain layer is used to form a bridge portion connecting different transistors.

22. A display device, wherein: The display device comprises the display panel according to any one of claims 1-21.

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