Shift register unit, display substrate and display device

Abstract

The utility model discloses a shift register unit, a display substrate and a display device. The shift register unit comprises a first control circuit, a second control circuit and an output control circuit. The first control circuit is connected with a starting signal end, a first reference signal end, a second reference signal end and a clock signal end, and is configured to control the potential of the first node under the control of the starting signal end and the clock signal end. And the second control circuit is connected with an initial signal end and a clock signal end, and is configured to control the potential of the third node under the control of the clock signal end. And the output control circuit is connected with the first node, the third node, the first reference signal end, the second reference signal end and the output signal end, and is configured to control an output signal of the output signal end under the control of the first node and the third node. The shift register unit is simple in structure and small in occupied space, and the narrow frame design of the display device can be achieved easily.

Description

Technical Field

[0001] The utility model relates to the field of display technology, and in particular to a shift register unit, a display substrate and a display device. Background Art

[0002] Nowadays, pixels are generally driven by pixel driving circuits. A light-emitting control transistor is generally provided in the pixel driving circuit to control whether the driving transistor outputs a driving current. The light-emitting control transistor is generally controlled by a light-emitting control signal line. The light-emitting control signal line needs to be configured with a corresponding light-emitting control gate driving circuit.

[0003] In the prior art, the gate driver circuit usually adopts the array substrate row drive (Gate Driver on Array, GOA) technology. The transistors in the gate driver circuit for light control are integrated on the array substrate to scan and drive the light control signal lines in the display panel, thereby eliminating the gate driver IC part, which is conducive to the realization of a narrow frame.

[0004] However, in actual applications, it is found that the circuit structure of the shift register in the existing gate driving circuit for light emitting control is complex and occupies a large space. Utility Model Content

[0005] The purpose of the present application is to provide a shift register unit, a display substrate and a display device with a simple structure.

[0006] The present application discloses a shift register unit, the shift register unit comprising:

[0007] a first control circuit, the first control circuit being connected to a start signal terminal, a first reference signal terminal, a second reference signal terminal and a clock signal terminal; the first control circuit being configured to control a potential of a first node under control of the start signal terminal and the clock signal terminal;

[0008] a second control circuit, the second control circuit being connected to the start signal terminal and the clock signal terminal; the second control circuit being configured to control the potential of the third node under the control of the clock signal terminal;

[0009] An output control circuit, wherein the output control circuit is connected to the first node, the third node, the first reference signal terminal, the second reference signal terminal and the output signal terminal; the output control circuit is configured to control the output signal of the output signal terminal under the control of the first node and the third node.

[0010] Optionally, the first control circuit includes:

[0011] A first control subcircuit, the first control subcircuit is connected to the first node, the start signal terminal, the first reference signal terminal and the clock signal terminal; the first control subcircuit is configured to control the connection between the first reference signal terminal and the first node under the control of the start signal terminal and the clock signal terminal.

[0012] Optionally, the first control subcircuit includes:

[0013] a first transistor, wherein a first electrode of the first transistor is connected to a second node, a second electrode of the first transistor is connected to the first node, and a control electrode of the first transistor is connected to the clock signal terminal;

[0014] A second transistor, wherein a first electrode of the second transistor is connected to the first reference signal terminal, a second electrode of the second transistor is connected to the second node, and a control electrode of the second transistor is connected to the start signal terminal.

[0015] Optionally, the first control circuit includes:

[0016] A second control subcircuit, the second control subcircuit is connected to the first node, the start signal terminal and the second reference signal terminal; the second control subcircuit is configured to control the connection between the second reference signal terminal and the first node under the control of the start signal terminal.

[0017] Optionally, the second control subcircuit includes:

[0018] A third transistor, wherein a first electrode of the third transistor is connected to the second reference signal terminal, a second electrode of the third transistor is connected to the first node, and a control electrode of the third transistor is connected to the start signal terminal.

[0019] Optionally, the output control circuit includes:

[0020] a sixth transistor, wherein a first electrode of the sixth transistor is connected to the second reference signal terminal, a second electrode of the sixth transistor is connected to the output signal terminal, and a control electrode of the sixth transistor is connected to the first node;

[0021] A seventh transistor, wherein a first electrode of the seventh transistor is connected to the first reference signal terminal, a second electrode of the seventh transistor is connected to the output signal terminal, and a control electrode of the seventh transistor is connected to the third node.

[0022] Optionally, the output control circuit further includes:

[0023] A first capacitor, wherein a first end of the first capacitor is connected to the third node, and a second end of the first capacitor is connected to the output signal end.

[0024] Optionally, the output control circuit further includes:

[0025] A second capacitor, wherein a first end of the second capacitor is connected to the second reference signal end, and a second end of the second capacitor is connected to the first node.

[0026] Optionally, a third control circuit and a fourth node are arranged between the third node and the output control circuit; the third control circuit is connected to the third node, the first reference signal terminal and the fourth node; the third control circuit is configured to selectively turn on the third node and the fourth node according to the potential conditions of the third node, the fourth node and the first reference signal terminal; the first end of the first capacitor is connected to the third node through the fourth node and the third control circuit.

[0027] Optionally, the third control circuit includes:

[0028] A fifth transistor, wherein a first electrode of the fifth transistor is connected to the third node, a second electrode of the fifth transistor is connected to the fourth node, and a control electrode of the fifth transistor is connected to the first reference signal terminal.

[0029] Optionally, the second control circuit includes:

[0030] A fourth transistor, wherein a first electrode of the fourth transistor is connected to the start signal terminal, a second electrode of the fourth transistor is connected to the third node, and a control electrode of the fourth transistor is connected to the clock signal terminal.

[0031] Optionally, the first transistor is a P-type transistor, and the second transistor is an N-type transistor.

[0032] The present application also discloses a display substrate, which includes the above-mentioned shift register unit, and a plurality of the shift register units are cascaded.

[0033] The present application also discloses a display device, which includes the above-mentioned display substrate.

[0034] Compared with the related art, the shift register unit of the present application has a simple structure and occupies a small space, which is conducive to realizing a narrow frame design of the display device.

[0035] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the specification and, together with the description, serve to explain the principles of the specification.

[0037] Figure 1 This is a schematic diagram of a circuit module in an embodiment of the present application.

[0038] Figure 2 This is a schematic diagram of a circuit module in an embodiment of the present application.

[0039] Figure 3 This is a schematic diagram of a circuit module in an embodiment of the present application.

[0040] Figure 4 This is a schematic diagram of a circuit structure in an embodiment of the present application.

[0041] Figure 5 This is a schematic diagram of a circuit structure in an embodiment of the present application.

[0042] Figure 6 In one embodiment Figure 4 as well as Figure 5 Timing diagram of the circuit structure in .

[0043] Figure 7 This is a schematic diagram of a circuit structure in an embodiment of the present application.

[0044] Figure 8 In one embodiment Figure 7 Timing diagram of the circuit structure in .

[0045] Fig. 9 This is a schematic diagram of a circuit structure in an embodiment of the present application.

[0046] Fig.10 This is a schematic diagram of a circuit structure in an embodiment of the present application.

[0047] Fig.11 In one embodiment Fig. 9 as well as Fig.10 Timing diagram of the circuit structure in .

[0048] Fig.12 FIG. 1 is a schematic diagram showing the structure of a substrate in an embodiment of the present application.

[0049] Fig.13 In one embodiment Fig.12 The cascade relationship timing diagram of the substrate is shown in FIG. DETAILED DESCRIPTION

[0050] When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0051] The words "first", "second" and similar words used in this specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "an" do not indicate a quantitative limitation, but rather indicate the presence of at least one. "Multiple" or "several" means two or more. Unless otherwise indicated, words such as "front", "rear", "lower" and / or "upper" are used for ease of description and are not limited to one position or one spatial orientation. Words such as "include" or "comprises" and similar words mean that the elements or objects appearing before "include" or "comprises" include the elements or objects listed after "include" or "comprises" and their equivalents, and do not exclude other elements or objects. Words such as "connected" or "connected" and similar words are not limited to physical or mechanical connections, and may include electrical connections, whether direct or indirect.

[0052] As used in this specification and the appended claims, the singular forms "a", "an", "said", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0053] like Figure 1 As shown, the present application provides a shift register unit, which includes:

[0054] The first control circuit 10 is connected to the start signal terminal STV, the first reference signal terminal VREF1, the second reference signal terminal VREF2 and the clock signal terminal. The first control circuit 10 is configured to control the potential of the first node N1 under the control of the start signal terminal STV and the clock signal terminal.

[0055] The second control circuit 20 is connected to the start signal terminal STV and the clock signal terminal. The second control circuit 20 is configured to control the potential of the third node N3 under the control of the clock signal terminal.

[0056] The output control circuit 40 is connected to the first node N1, the third node N3, the first reference signal terminal VREF1, the second reference signal terminal VREF2 and the output signal terminal OUT. The output control circuit 40 is configured to control the output signal of the output signal terminal OUT under the control of the first node N1 and the third node N3.

[0057] The shift register unit of the present application has a simple structure and occupies a small space, which is conducive to realizing a narrow frame design of the display device.

[0058] The transistors used in the present application may be triodes, thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present disclosure, in order to distinguish the two electrodes of the transistor except the control electrode, one of the electrodes is called the first electrode and the other is called the second electrode. The energy storage unit used in the present disclosure may be a capacitor.

[0059] In actual operation, when the transistor is a triode, the control electrode may be the base electrode, the first electrode may be the collector electrode, and the second electrode may be the emitter electrode. Alternatively, the control electrode may be the base electrode, the first electrode may be the emitter electrode, and the second electrode may be the collector electrode.

[0060] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode can be a gate electrode, the first electrode can be a drain electrode, and the second electrode can be a source electrode. Alternatively, the control electrode can be a gate electrode, the first electrode can be a source electrode, and the second electrode can be a drain electrode.

[0061] In actual operation, when the transistor is a thin film transistor, some transistors may be an N-type transistor or a P-type transistor or a combination of an N-type transistor and a P-type transistor. When the transistor is an N-type transistor, it may be a metal oxide transistor, whose on-potential is a high potential and whose off-potential is a low potential. When the transistor is a P-type transistor, it may be a low temperature polysilicon transistor, whose on-potential is a low potential and whose off-potential is a high potential.

[0062] In the present application, the signal written to the first reference signal terminal VREF1 is the first reference signal vref1 of a fixed potential. The signal written to the second reference signal terminal VREF2 is the second reference signal vref2 of a fixed potential. The signal written to the start signal terminal STV is the start signal stv. The clock signal terminal includes a first clock signal terminal CK and a second clock signal terminal CB. The signal written to the first clock signal terminal CK is the first clock signal ck. The signal written to the second clock signal terminal CB is the second clock signal cb. The phases of the first clock signal ck and the second clock signal cb are roughly opposite, and roughly opposite means that although the high potential segment of the first clock signal ck is in phase with the low potential segment of the second clock signal cb, the length of the high potential segment of the first clock signal ck and the length of the low potential segment of the second clock signal cb may be different, for example, the length of the high potential segment of the first clock signal ck may be greater than the length of the low potential segment of the second clock signal cb, or the length of the high potential segment of the first clock signal ck may be less than the length of the low potential segment of the second clock signal cb, or the length of the high potential segment of the first clock signal ck may be equal to the length of the low potential segment of the second clock signal cb. Similarly, the length of the low potential segment of the first clock signal ck and the length of the high potential segment of the second clock signal cb are also as above. The shift register unit of the present application can be connected to any one of the first clock signal terminal CK or the second clock signal terminal CB. Of course, the first clock signal terminal CK and the second clock signal terminal CB can also be connected at the same time according to actual needs. The signal output by the output signal terminal OUT is the output signal out.

[0063] The following will describe in detail various embodiments of the present application that are consistent with the above-mentioned creative concepts.

[0064] like Figure 1 As shown, the present application provides a shift register unit. The shift register unit includes a first control circuit 10, a second control circuit 20, and an output control circuit 40.

[0065] The first control circuit 10 is connected to the start signal terminal STV, the first reference signal terminal VREF1, the second reference signal terminal VREF2 and the clock signal terminal. The first control circuit 10 is configured to control the connection between the first reference signal terminal VREF1 and the first node N1 under the control of the start signal terminal STV and the clock signal terminal. And it is configured to control the connection between the second reference signal terminal VREF2 and the first node N1 under the control of the start signal terminal STV. That is, the first control circuit 10 controls whether the first reference signal vref1 and / or the second reference signal vref2 are written to the first node N1 under the control of the start signal stv and the clock signal. And the first control circuit 10 controls whether the second reference signal vref2 is written to the first node N1 under the control of the start signal stv.

[0066] The second control circuit 20 is connected to the start signal terminal STV and the clock signal terminal. The second control circuit 20 is configured to control the connection between the start signal terminal STV and the third node N3 under the control of the clock signal terminal. That is, the second control circuit 20 is configured to control whether the start signal stv is written into the third node N3 under the control of the clock signal.

[0067] The output control circuit 40 is connected to the first node N1, the third node N3, the first reference signal terminal VREF1, the second reference signal terminal VREF2 and the output signal terminal OUT. The output control circuit 40 is configured to control the connection between the first reference signal terminal VREF1 and / or the second reference signal terminal VREF2 and the output signal terminal OUT under the control of the first node N1 and the third node N3. That is, the output control circuit 40 controls whether the first reference signal vref1 and / or the second reference signal vref2 are written to the output signal terminal OUT under the control of the potential of the first node N1 and the potential of the third node N3.

[0068] The clock signal terminal may be the first clock signal terminal CK or the second clock signal terminal CB.

[0069] like Figure 2 As shown, in some optional embodiments, the first control circuit 10 includes a first control subcircuit 11 and a second control subcircuit 12.

[0070] The first control subcircuit 11 is connected to the first node N1, the start signal terminal STV, the first reference signal terminal VREF1 and the clock signal terminal. The first control subcircuit 11 is configured to control the connection between the first reference signal terminal VREF1 and the first node N1 under the control of the start signal terminal STV and the clock signal terminal. That is, the first control subcircuit 11 controls whether the first reference signal vref1 is written into the first node N1 under the control of the start signal stv and the clock signal.

[0071] The second control subcircuit 12 is connected to the first node N1, the start signal terminal STV and the second reference signal terminal VREF2. The second control subcircuit 12 is configured to control the connection between the second reference signal terminal VREF2 and the first node N1 under the control of the start signal terminal STV. That is, the second control subcircuit 12 controls whether the second reference signal vref2 is written into the first node N1 under the control of the start signal stv.

[0072] like Figure 3As shown, in some optional embodiments, a third control circuit 30 and a fourth node N4 are provided between the third node N3 and the output control circuit 40. The third control circuit 30 is connected to the third node N3, the first reference signal terminal VREF1 and the fourth node N4. The third control circuit 30 is configured to selectively conduct the third node N3 and the fourth node N4 according to the potential conditions of the third node N3, the fourth node N4 and the first reference signal terminal VREF1.

[0073] like Figure 4 As shown, Figure 4 for Figure 2 A specific circuit structure of the schematic diagram shown.

[0074] In some embodiments, the first control subcircuit 11 includes a first transistor T1 and a second transistor T2. The first electrode of the first transistor T1 is connected to the second node N2, the second electrode of the first transistor T1 is connected to the first node N1, and the control electrode of the first transistor T1 is connected to the clock signal terminal. The first electrode of the second transistor T2 is connected to the first reference signal terminal VREF1, the second electrode of the second transistor T2 is connected to the second node N2, and the control electrode of the second transistor T2 is connected to the start signal terminal STV.

[0075] The second control subcircuit 12 includes a third transistor T3. A first electrode of the third transistor T3 is connected to the second reference signal terminal VREF2, a second electrode of the third transistor T3 is connected to the first node N1, and a control electrode of the third transistor T3 is connected to the start signal terminal STV.

[0076] The second control circuit 20 includes a fourth transistor T4. A first electrode of the fourth transistor T4 is connected to the start signal terminal STV, a second electrode of the fourth transistor T4 is connected to the third node N3, and a control electrode of the fourth transistor T4 is connected to the clock signal terminal.

[0077] The output control circuit 40 includes a sixth transistor T6 and a seventh transistor T7. A first electrode of the sixth transistor T6 is connected to the second reference signal terminal VREF2, a second electrode of the sixth transistor T6 is connected to the output signal terminal OUT, and a control electrode of the sixth transistor T6 is connected to the first node N1. A first electrode of the seventh transistor T7 is connected to the first reference signal terminal VREF1, a second electrode of the seventh transistor T7 is connected to the output signal terminal OUT, and a control electrode of the seventh transistor T7 is connected to the third node N3.

[0078] like Figure 6As shown, the first starting rising edge x of the start signal stv emitted by the start signal terminal STV falls into the first high potential segment H1 of the clock signal emitted by the clock signal terminal. The first starting falling edge y of the start signal stv falls into the nth high potential segment H2 of the clock signal, where n is greater than or equal to 2. The first and nth here do not represent specific positions, but only represent the sequential relationship. For example, the second high potential segment is located after the first high potential segment, and the third high potential segment is located after the second high potential segment. Among them, the first high potential segment H1 does not represent the first high potential segment, and the first high potential segment H1 can be the first, second, third, fourth or fifth high potential segment, for example Figure 6 The first high potential segment H1 is the fourth high potential segment.

[0079] The following will be combined Figure 6 right Figure 4 The circuit diagram shown is used to illustrate, Figure 6 In one embodiment Figure 4 The timing diagram of the circuit structure shown in FIG. Figure 4 The second transistor T2 in the shift register unit shown is an N-type transistor, and the other transistors are P-type transistors. The first reference signal vref1 is fixed to a low potential signal, and the second reference signal vref2 is fixed to a high potential signal. The clock signal terminals are all first clock signal terminals CK. Of course, the embodiments of the present application are not limited to this setting, and the setting can be changed according to actual needs.

[0080] Before the first period t1, since the start signal stv is always at a low potential, the first clock signal ck switches between a high potential and a low potential. Therefore, the third transistor T3 always remains in an on state, the second reference signal terminal VREF2 is always connected to the first node N1, and the second reference signal vref2 is always written to the first node N1. That is, the first node N1 maintains a high potential. The sixth transistor T6 remains in an off state. The fourth transistor T4 switches between an on state and an off state, and the start signal stv is written to the third node N3. That is, the third node N3 maintains a low potential. The seventh transistor T7 remains in an on state, and the first reference signal terminal VREF1 remains connected to the output signal terminal OUT. The output signal terminal OUT outputs a low potential signal.

[0081] In the first time period t1, the start signal stv changes to a high potential, but at this time the first clock signal ck is a high potential. At this time, the first transistor T1 and the third transistor T3 are both in the off state, and the first node N1 maintains the potential before the T1 period, that is, maintains a high potential. The sixth transistor T6 remains in the off state. The fourth transistor T4 is in the off state, and the third node N3 maintains the state before the t1 period, that is, maintains a low potential. The seventh transistor T7 remains in the on state, the first reference signal terminal VREF1 remains connected to the output signal terminal OUT, and the output signal terminal OUT outputs a low potential signal.

[0082] In the second period t2, the start signal stv is at a high potential, and the first clock signal ck is at a low potential. The fourth transistor T4 is in a conducting state, and the start signal stv is written to the third node N3. That is, the third node N3 is changed to a high potential. The seventh transistor T7 is changed to a disconnected state. The third transistor T3 is turned off, the first transistor T1 and the second transistor T2 are turned on, and the first reference signal vref1 is written to the first node N1, that is, the first node N1 is changed to a low potential. The sixth transistor T6 is changed to a conducting state, the second reference signal terminal VREF2 is connected to the output signal terminal OUT, and the output signal terminal OUT outputs a high potential signal.

[0083] In the third time period t3, the start signal stv is at a high potential, and the first clock signal ck is at a high potential. At this time, the first transistor T1 and the third transistor T3 are both in the off state, and the first node N1 maintains the potential of the time period T2, that is, maintains a low potential. The sixth transistor T6 remains in the on state. The fourth transistor T4 is in the off state, and the third node N3 maintains the potential of the time period t2, that is, maintains a high potential. The seventh transistor T7 remains in the off state. The second reference signal terminal VREF2 remains connected to the output signal terminal OUT, and the output signal terminal OUT outputs a high potential signal.

[0084] During the period between the third period t3 and the fourth period t4, the circuit continuously repeats the process of the second period t2 and the third period t3, so it will not be described in detail here.

[0085] In the fourth time period t4, the start signal stv is at a low potential, and the first clock signal ck is at a high potential. At this time, the first transistor T1 and the second transistor T2 are in an off state, and the third transistor T3 is in an on state. The second reference signal vref2 is written into the first node N1, and the first node N1 is changed to a high potential. The sixth transistor T6 is changed to an off state. The fourth transistor T4 is in an off state, and the third node N3 maintains the potential of the previous stage, that is, maintains a high potential. The seventh transistor T7 remains in an off state. The output signal terminal OUT maintains the output of the previous stage, and the output signal terminal OUT outputs a high potential signal.

[0086] In the fifth period t5, the start signal stv is at a low potential, and the first clock signal ck is at a low potential. At this time, the second transistor T2 is in an off state, and the first transistor T1 and the third transistor T3 are in an on state. The second reference signal vref2 is written into the first node N1, and the first node N1 remains at a high potential. The sixth transistor T6 remains in an off state. The fourth transistor T4 is turned into an on state, the start signal stv is written into the third node N3, and the third node N3 is turned into a low potential. The seventh transistor T7 is turned into an on state. The first reference signal terminal VREF1 is connected to the output signal terminal OUT, and the signal output by the output signal terminal OUT is turned into a low potential signal.

[0087] In the sixth period t6, the start signal stv is at a low potential, and the first clock signal ck is at a high potential. At this time, the first transistor T1 and the second transistor T2 are in an off state, and the third transistor T3 is in an on state. The second reference signal vref2 is written into the first node N1, and the first node N1 remains at a high potential. The sixth transistor T6 remains in an off state. The fourth transistor T4 is turned into an off state, and the third node N3 maintains the potential of the period t5, that is, maintains a low potential. The seventh transistor T7 remains in an on state. The first reference signal terminal VREF1 is connected to the output signal terminal OUT, and the signal output by the output signal terminal OUT remains a low potential signal.

[0088] In the subsequent time periods, the circuit continuously repeats the processes of the fifth time period t5 and the sixth time period t6, so they are not described in detail here.

[0089] The present application realizes the function of the shift register unit by only six transistors: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a sixth transistor T6 and a seventh transistor T7. Compared with the existing shift register unit, the shift register unit of the present application is more streamlined, has a simple circuit structure, and occupies a small size, which is conducive to the design of a narrow frame of the screen.

[0090] like Figure 5 As shown, in some optional embodiments, the output control circuit 40 further includes a second capacitor C2. The first end of the second capacitor C2 is connected to the second reference signal terminal VREF2, and the second end of the second capacitor C2 is connected to the first node N1. The second capacitor C2 can store the potential of the first node N1, so that the potential of the previous stage can be effectively maintained when the first node N1 is in a floating state. For example, Figure 6 In the third period t3 shown, the second capacitor C2 can effectively store the low potential of the first node N1 in the second period t2, so that the first node N1 can effectively maintain a low potential in the third period t3.

[0091] like Figure 4 As shown, the potential of the third node N3 controls the conduction and cutoff of the seventh transistor T7. In the period t5 and the period thereafter, the third node N3 needs to maintain a sufficiently low potential to ensure the normal conduction of the seventh transistor T7. However, in practical applications, considering factors such as IR Drop (voltage drop), it is found that the actual potential of the third node N3 of the shift register in the period t5 and the period thereafter is higher than the expected potential. The actual potential of the third node N3 is higher than the expected potential, which will cause the output signal terminal OUT to fail to output the expected low potential signal in the period t5 and the period thereafter. In order to solve the above problems, the present application also discloses a method as follows Figure 7 The shift register unit shown. Figure 7The shift register unit shown in Figure 4 The output control circuit 40 is improved on the basis of the shift register unit shown in FIG. The output control circuit 40 further includes a first capacitor C1, a first end of the first capacitor C1 is connected to the third node N3, and a second end of the first capacitor C1 is connected to the output signal terminal OUT.

[0092] The following will be combined Figure 8 right Figure 7 The circuit diagram shown is used to illustrate, Figure 8 In one embodiment Figure 7 Timing diagram of the circuit structure shown. Figure 8 The timing diagram shown is similar to Figure 6 The processes in the timing diagram shown in the figure are roughly the same in the time periods t1, t3, t4 and t6, and the only difference is the potential of the low potential signal segment of the start signal terminal STV. Figure 8 The start signal terminal STV in the circuit changes from a high potential to a low potential, at which time the third node N3 first changes from a high potential to a first low potential V1, the seventh transistor T7 is turned on, and the first reference signal terminal VREF1 is connected to the output signal terminal OUT. At this time, due to the existence of the first capacitor C1, when the output signal out changes from a high potential to a low potential, the potential of the third node N3 will be coupled to a lower second low potential V2, so that the seventh transistor T7 is turned on more fully, so that the output signal terminal OUT outputs an output signal out that is more in line with the expected output signal.

[0093] like Figure 7 as well as Figure 8 As shown, the potential of the third node N3 will be coupled to the lower second low potential V2 in some periods. At this time, there will be a large voltage difference between the first end and the second end of the fourth transistor T4, which will affect the service life of the fourth transistor T4. In order to solve the above problem, the present application also discloses a method as follows Fig. 9 The shift register unit shown. Fig. 9 The shift register unit shown in Figure 7On the basis of the shift register unit shown in the figure, a third control circuit 30 and a fourth node N4 are arranged between the third node N3 and the output control circuit 40. Among them, the third control circuit 30 is connected to the third node N3, the first reference signal terminal VREF1 and the fourth node N4. The third control circuit 30 is configured to selectively conduct the third node N3 and the fourth node N4 according to the potential of the third node N3, the fourth node N4 and the first reference signal terminal VREF1. The first end of the first capacitor C1 is connected to the third node N3 through the fourth node N4 and the third control circuit 30. That is, the first end of the first capacitor C1 is connected to the fourth node N4. The third control circuit 30 includes a fifth transistor T5, the first electrode of the fifth transistor T5 is connected to the third node N3, the second electrode of the fifth transistor T5 is connected to the fourth node N4, and the control electrode of the fifth transistor T5 is connected to the first reference signal terminal VREF1.

[0094] The following will be combined Fig.11 right Fig. 9 The circuit diagram shown is used to illustrate, Fig.11 In one embodiment Fig. 9 Timing diagram of the circuit structure shown. Fig.11 The timing diagram shown is similar to Figure 8 Compared with the timing diagram shown in FIG. 1 , the only difference is the potential of the third node N3 and the fourth node N4, so the other parts are not described in detail here. Fig.11 As shown, taking the t4 period as an example, when the potential of the third node N3 changes from a high potential to a first low potential V1, the fifth transistor T5 is in a conducting state, and the potential of the fourth node N4 also changes to the first low potential V1. Afterwards, when the potential of the fourth node N4 is coupled to the second low potential V2, the gate-source voltage of the fifth transistor T5 will be greater than its own threshold voltage, and the fifth transistor T5 will be turned into a cut-off state, and the second low potential V2 of the fourth node N4 will not affect the third node N3, and the third node N3 will always maintain the first low potential V1. At this time, there will be no large voltage difference between the first end and the second end of the fourth transistor T4, which significantly improves the service life of the fourth transistor T4.

[0095] like Fig.10 As shown, Fig.10 for Figure 3 A specific circuit structure of the schematic diagram shown. Fig.10 The circuit structure shown in Figure 4 Based on the circuit structure shown, a first capacitor C1, a second capacitor C2 and a third control circuit 30 are added. Since the functions of the first capacitor C1, the second capacitor C2 and the third control circuit 30 are the same as those of the above embodiment, they will not be described in detail here.

[0096] like Fig.12 and Fig.13As shown, the present application also discloses a display substrate, which includes a plurality of the above-mentioned shift register units, and a plurality of shift register units are cascaded. The display substrate shown in the figure is only an example, and display substrates of different specifications can be selected according to different situations. For example, two shift registers can control the same row of pixels, or one shift register can control two rows of pixels, and so on.

[0097] The first shift register unit GOA1 is connected to the start signal terminal STV. The output signal out1 of the output signal terminal OUT1 of the first shift register unit GOA1 is used as the start signal stv of the second shift register unit GOA2, and the output signal out2 of the output signal terminal OUT2 of the second shift register unit GOA2 is used as the start signal stv of the third shift register unit GOA3... The subsequent shift register units are analogous to each other, thereby realizing cascading. Of course, the first, third, fifth... and other odd-numbered shift register units can also be cascaded, and the second, fourth, sixth... and other even-numbered shift register units can be cascaded, or other cascading methods can be selected.

[0098] In some optional embodiments, the clock signal terminal includes a first clock signal terminal CK and a second clock signal terminal CB with opposite phases, and the shift register units of odd bits in a plurality of cascaded shift register units are connected to the first clock signal terminal CK, and the shift register units of even bits are connected to the second clock signal terminal CB. In this way, the first starting rising edge x of the start signal stv emitted by the start signal terminal STV of each stage of the shift register unit can fall into the first high potential segment H1 of the clock signal emitted by the clock signal terminal. The first starting falling edge y of the start signal stv of each stage of the shift register unit can fall into the nth high potential segment H2 of the clock signal, where n is greater than or equal to 2. Of course, the present application can also select other clock signal combinations according to actual needs, for example, the third, fourth or fifth clock signal terminals can be set according to actual needs.

[0099] The present application also discloses a display device, which includes the above-mentioned display substrate.

Claims

1. A shift register unit, characterized in that: The shift register unit comprises: a first control circuit, the first control circuit being connected to a start signal terminal, a first reference signal terminal, a second reference signal terminal and a clock signal terminal; the first control circuit being configured to control a potential of a first node under control of the start signal terminal and the clock signal terminal; a second control circuit, the second control circuit being connected to the start signal terminal and the clock signal terminal; the second control circuit being configured to control the potential of the third node under the control of the clock signal terminal; An output control circuit, wherein the output control circuit is connected to the first node, the third node, the first reference signal terminal, the second reference signal terminal and the output signal terminal; the output control circuit is configured to control the output signal of the output signal terminal under the control of the first node and the third node.

2. The shift register unit according to claim 1, characterized in that: The first control circuit comprises: A first control subcircuit, the first control subcircuit is connected to the first node, the start signal terminal, the first reference signal terminal and the clock signal terminal; the first control subcircuit is configured to control the connection between the first reference signal terminal and the first node under the control of the start signal terminal and the clock signal terminal.

3. The shift register unit according to claim 2, characterized in that: The first control subcircuit comprises: a first transistor, wherein a first electrode of the first transistor is connected to a second node, a second electrode of the first transistor is connected to the first node, and a control electrode of the first transistor is connected to the clock signal terminal; A second transistor, wherein a first electrode of the second transistor is connected to the first reference signal terminal, a second electrode of the second transistor is connected to the second node, and a control electrode of the second transistor is connected to the start signal terminal.

4. The shift register unit according to claim 1, characterized in that: The first control circuit comprises: A second control subcircuit, the second control subcircuit is connected to the first node, the start signal terminal and the second reference signal terminal; the second control subcircuit is configured to control the connection between the second reference signal terminal and the first node under the control of the start signal terminal.

5. The shift register unit according to claim 4, characterized in that: The second control subcircuit comprises: A third transistor, wherein a first electrode of the third transistor is connected to the second reference signal terminal, a second electrode of the third transistor is connected to the first node, and a control electrode of the third transistor is connected to the start signal terminal.

6. The shift register unit according to claim 1, characterized in that: The output control circuit comprises: a sixth transistor, wherein a first electrode of the sixth transistor is connected to the second reference signal terminal, a second electrode of the sixth transistor is connected to the output signal terminal, and a control electrode of the sixth transistor is connected to the first node; A seventh transistor, wherein a first electrode of the seventh transistor is connected to the first reference signal terminal, a second electrode of the seventh transistor is connected to the output signal terminal, and a control electrode of the seventh transistor is connected to the third node.

7. The shift register unit according to claim 6, characterized in that: The output control circuit further includes: A first capacitor, wherein a first end of the first capacitor is connected to the third node, and a second end of the first capacitor is connected to the output signal end.

8. The shift register unit according to claim 6, characterized in that: The output control circuit further includes: A second capacitor, wherein a first end of the second capacitor is connected to the second reference signal end, and a second end of the second capacitor is connected to the first node.

9. The shift register unit according to claim 7, characterized in that: A third control circuit and a fourth node are arranged between the third node and the output control circuit; the third control circuit is connected to the third node, the first reference signal terminal and the fourth node; the third control circuit is configured to selectively turn on the third node and the fourth node according to the potential conditions of the third node, the fourth node and the first reference signal terminal; the first end of the first capacitor is connected to the third node through the fourth node and the third control circuit.

10. The shift register unit according to claim 9, characterized in that: The third control circuit comprises: A fifth transistor, wherein a first electrode of the fifth transistor is connected to the third node, a second electrode of the fifth transistor is connected to the fourth node, and a control electrode of the fifth transistor is connected to the first reference signal terminal.

11. The shift register unit according to claim 1, characterized in that: The second control circuit comprises: A fourth transistor, wherein a first electrode of the fourth transistor is connected to the start signal terminal, a second electrode of the fourth transistor is connected to the third node, and a control electrode of the fourth transistor is connected to the clock signal terminal.

12. The shift register unit according to claim 3, characterized in that: The first transistor is a P-type transistor, and the second transistor is an N-type transistor.

13. A display substrate, characterized in that: The display substrate comprises the shift register unit according to any one of claims 1 to 12, and a plurality of the shift register units are cascaded.

14. A display device, characterized in that: The display device comprises the display substrate as claimed in claim 13.

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